1 /** 2 * \file 3 * 4 * \brief Component description for EFC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_EFC_COMPONENT_H_ 32 #define _SAMV71_EFC_COMPONENT_H_ 33 #define _SAMV71_EFC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Embedded Flash Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR EFC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define EFC_6450 /**< (EFC) Module ID */ 46 #define REV_EFC Y /**< (EFC) Module revision */ 47 48 /* -------- EEFC_FMR : (EFC Offset: 0x00) (R/W 32) EEFC Flash Mode Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t FRDY:1; /**< bit: 0 Flash Ready Interrupt Enable */ 54 uint32_t :7; /**< bit: 1..7 Reserved */ 55 uint32_t FWS:4; /**< bit: 8..11 Flash Wait State */ 56 uint32_t :4; /**< bit: 12..15 Reserved */ 57 uint32_t SCOD:1; /**< bit: 16 Sequential Code Optimization Disable */ 58 uint32_t :9; /**< bit: 17..25 Reserved */ 59 uint32_t CLOE:1; /**< bit: 26 Code Loop Optimization Enable */ 60 uint32_t :5; /**< bit: 27..31 Reserved */ 61 } bit; /**< Structure used for bit access */ 62 uint32_t reg; /**< Type used for register access */ 63 } EEFC_FMR_Type; 64 #endif 65 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 #define EEFC_FMR_OFFSET (0x00) /**< (EEFC_FMR) EEFC Flash Mode Register Offset */ 68 69 #define EEFC_FMR_FRDY_Pos 0 /**< (EEFC_FMR) Flash Ready Interrupt Enable Position */ 70 #define EEFC_FMR_FRDY_Msk (_U_(0x1) << EEFC_FMR_FRDY_Pos) /**< (EEFC_FMR) Flash Ready Interrupt Enable Mask */ 71 #define EEFC_FMR_FRDY EEFC_FMR_FRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FMR_FRDY_Msk instead */ 72 #define EEFC_FMR_FWS_Pos 8 /**< (EEFC_FMR) Flash Wait State Position */ 73 #define EEFC_FMR_FWS_Msk (_U_(0xF) << EEFC_FMR_FWS_Pos) /**< (EEFC_FMR) Flash Wait State Mask */ 74 #define EEFC_FMR_FWS(value) (EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos)) 75 #define EEFC_FMR_SCOD_Pos 16 /**< (EEFC_FMR) Sequential Code Optimization Disable Position */ 76 #define EEFC_FMR_SCOD_Msk (_U_(0x1) << EEFC_FMR_SCOD_Pos) /**< (EEFC_FMR) Sequential Code Optimization Disable Mask */ 77 #define EEFC_FMR_SCOD EEFC_FMR_SCOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FMR_SCOD_Msk instead */ 78 #define EEFC_FMR_CLOE_Pos 26 /**< (EEFC_FMR) Code Loop Optimization Enable Position */ 79 #define EEFC_FMR_CLOE_Msk (_U_(0x1) << EEFC_FMR_CLOE_Pos) /**< (EEFC_FMR) Code Loop Optimization Enable Mask */ 80 #define EEFC_FMR_CLOE EEFC_FMR_CLOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FMR_CLOE_Msk instead */ 81 #define EEFC_FMR_MASK _U_(0x4010F01) /**< \deprecated (EEFC_FMR) Register MASK (Use EEFC_FMR_Msk instead) */ 82 #define EEFC_FMR_Msk _U_(0x4010F01) /**< (EEFC_FMR) Register Mask */ 83 84 85 /* -------- EEFC_FCR : (EFC Offset: 0x04) (/W 32) EEFC Flash Command Register -------- */ 86 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 87 #if COMPONENT_TYPEDEF_STYLE == 'N' 88 typedef union { 89 struct { 90 uint32_t FCMD:8; /**< bit: 0..7 Flash Command */ 91 uint32_t FARG:16; /**< bit: 8..23 Flash Command Argument */ 92 uint32_t FKEY:8; /**< bit: 24..31 Flash Writing Protection Key */ 93 } bit; /**< Structure used for bit access */ 94 uint32_t reg; /**< Type used for register access */ 95 } EEFC_FCR_Type; 96 #endif 97 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 #define EEFC_FCR_OFFSET (0x04) /**< (EEFC_FCR) EEFC Flash Command Register Offset */ 100 101 #define EEFC_FCR_FCMD_Pos 0 /**< (EEFC_FCR) Flash Command Position */ 102 #define EEFC_FCR_FCMD_Msk (_U_(0xFF) << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Flash Command Mask */ 103 #define EEFC_FCR_FCMD(value) (EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos)) 104 #define EEFC_FCR_FCMD_GETD_Val _U_(0x0) /**< (EEFC_FCR) Get Flash descriptor */ 105 #define EEFC_FCR_FCMD_WP_Val _U_(0x1) /**< (EEFC_FCR) Write page */ 106 #define EEFC_FCR_FCMD_WPL_Val _U_(0x2) /**< (EEFC_FCR) Write page and lock */ 107 #define EEFC_FCR_FCMD_EWP_Val _U_(0x3) /**< (EEFC_FCR) Erase page and write page */ 108 #define EEFC_FCR_FCMD_EWPL_Val _U_(0x4) /**< (EEFC_FCR) Erase page and write page then lock */ 109 #define EEFC_FCR_FCMD_EA_Val _U_(0x5) /**< (EEFC_FCR) Erase all */ 110 #define EEFC_FCR_FCMD_EPA_Val _U_(0x7) /**< (EEFC_FCR) Erase pages */ 111 #define EEFC_FCR_FCMD_SLB_Val _U_(0x8) /**< (EEFC_FCR) Set lock bit */ 112 #define EEFC_FCR_FCMD_CLB_Val _U_(0x9) /**< (EEFC_FCR) Clear lock bit */ 113 #define EEFC_FCR_FCMD_GLB_Val _U_(0xA) /**< (EEFC_FCR) Get lock bit */ 114 #define EEFC_FCR_FCMD_SGPB_Val _U_(0xB) /**< (EEFC_FCR) Set GPNVM bit */ 115 #define EEFC_FCR_FCMD_CGPB_Val _U_(0xC) /**< (EEFC_FCR) Clear GPNVM bit */ 116 #define EEFC_FCR_FCMD_GGPB_Val _U_(0xD) /**< (EEFC_FCR) Get GPNVM bit */ 117 #define EEFC_FCR_FCMD_STUI_Val _U_(0xE) /**< (EEFC_FCR) Start read unique identifier */ 118 #define EEFC_FCR_FCMD_SPUI_Val _U_(0xF) /**< (EEFC_FCR) Stop read unique identifier */ 119 #define EEFC_FCR_FCMD_GCALB_Val _U_(0x10) /**< (EEFC_FCR) Get CALIB bit */ 120 #define EEFC_FCR_FCMD_ES_Val _U_(0x11) /**< (EEFC_FCR) Erase sector */ 121 #define EEFC_FCR_FCMD_WUS_Val _U_(0x12) /**< (EEFC_FCR) Write user signature */ 122 #define EEFC_FCR_FCMD_EUS_Val _U_(0x13) /**< (EEFC_FCR) Erase user signature */ 123 #define EEFC_FCR_FCMD_STUS_Val _U_(0x14) /**< (EEFC_FCR) Start read user signature */ 124 #define EEFC_FCR_FCMD_SPUS_Val _U_(0x15) /**< (EEFC_FCR) Stop read user signature */ 125 #define EEFC_FCR_FCMD_GETD (EEFC_FCR_FCMD_GETD_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get Flash descriptor Position */ 126 #define EEFC_FCR_FCMD_WP (EEFC_FCR_FCMD_WP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page Position */ 127 #define EEFC_FCR_FCMD_WPL (EEFC_FCR_FCMD_WPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write page and lock Position */ 128 #define EEFC_FCR_FCMD_EWP (EEFC_FCR_FCMD_EWP_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page Position */ 129 #define EEFC_FCR_FCMD_EWPL (EEFC_FCR_FCMD_EWPL_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase page and write page then lock Position */ 130 #define EEFC_FCR_FCMD_EA (EEFC_FCR_FCMD_EA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase all Position */ 131 #define EEFC_FCR_FCMD_EPA (EEFC_FCR_FCMD_EPA_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase pages Position */ 132 #define EEFC_FCR_FCMD_SLB (EEFC_FCR_FCMD_SLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set lock bit Position */ 133 #define EEFC_FCR_FCMD_CLB (EEFC_FCR_FCMD_CLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear lock bit Position */ 134 #define EEFC_FCR_FCMD_GLB (EEFC_FCR_FCMD_GLB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get lock bit Position */ 135 #define EEFC_FCR_FCMD_SGPB (EEFC_FCR_FCMD_SGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Set GPNVM bit Position */ 136 #define EEFC_FCR_FCMD_CGPB (EEFC_FCR_FCMD_CGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Clear GPNVM bit Position */ 137 #define EEFC_FCR_FCMD_GGPB (EEFC_FCR_FCMD_GGPB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get GPNVM bit Position */ 138 #define EEFC_FCR_FCMD_STUI (EEFC_FCR_FCMD_STUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read unique identifier Position */ 139 #define EEFC_FCR_FCMD_SPUI (EEFC_FCR_FCMD_SPUI_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read unique identifier Position */ 140 #define EEFC_FCR_FCMD_GCALB (EEFC_FCR_FCMD_GCALB_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Get CALIB bit Position */ 141 #define EEFC_FCR_FCMD_ES (EEFC_FCR_FCMD_ES_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase sector Position */ 142 #define EEFC_FCR_FCMD_WUS (EEFC_FCR_FCMD_WUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Write user signature Position */ 143 #define EEFC_FCR_FCMD_EUS (EEFC_FCR_FCMD_EUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Erase user signature Position */ 144 #define EEFC_FCR_FCMD_STUS (EEFC_FCR_FCMD_STUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Start read user signature Position */ 145 #define EEFC_FCR_FCMD_SPUS (EEFC_FCR_FCMD_SPUS_Val << EEFC_FCR_FCMD_Pos) /**< (EEFC_FCR) Stop read user signature Position */ 146 #define EEFC_FCR_FARG_Pos 8 /**< (EEFC_FCR) Flash Command Argument Position */ 147 #define EEFC_FCR_FARG_Msk (_U_(0xFFFF) << EEFC_FCR_FARG_Pos) /**< (EEFC_FCR) Flash Command Argument Mask */ 148 #define EEFC_FCR_FARG(value) (EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos)) 149 #define EEFC_FCR_FKEY_Pos 24 /**< (EEFC_FCR) Flash Writing Protection Key Position */ 150 #define EEFC_FCR_FKEY_Msk (_U_(0xFF) << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) Flash Writing Protection Key Mask */ 151 #define EEFC_FCR_FKEY(value) (EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos)) 152 #define EEFC_FCR_FKEY_PASSWD_Val _U_(0x5A) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ 153 #define EEFC_FCR_FKEY_PASSWD (EEFC_FCR_FKEY_PASSWD_Val << EEFC_FCR_FKEY_Pos) /**< (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. Position */ 154 #define EEFC_FCR_MASK _U_(0xFFFFFFFF) /**< \deprecated (EEFC_FCR) Register MASK (Use EEFC_FCR_Msk instead) */ 155 #define EEFC_FCR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FCR) Register Mask */ 156 157 158 /* -------- EEFC_FSR : (EFC Offset: 0x08) (R/ 32) EEFC Flash Status Register -------- */ 159 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 160 #if COMPONENT_TYPEDEF_STYLE == 'N' 161 typedef union { 162 struct { 163 uint32_t FRDY:1; /**< bit: 0 Flash Ready Status (cleared when Flash is busy) */ 164 uint32_t FCMDE:1; /**< bit: 1 Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ 165 uint32_t FLOCKE:1; /**< bit: 2 Flash Lock Error Status (cleared on read) */ 166 uint32_t FLERR:1; /**< bit: 3 Flash Error Status (cleared when a programming operation starts) */ 167 uint32_t :12; /**< bit: 4..15 Reserved */ 168 uint32_t UECCELSB:1; /**< bit: 16 Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ 169 uint32_t MECCELSB:1; /**< bit: 17 Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ 170 uint32_t UECCEMSB:1; /**< bit: 18 Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ 171 uint32_t MECCEMSB:1; /**< bit: 19 Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ 172 uint32_t :12; /**< bit: 20..31 Reserved */ 173 } bit; /**< Structure used for bit access */ 174 uint32_t reg; /**< Type used for register access */ 175 } EEFC_FSR_Type; 176 #endif 177 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 178 179 #define EEFC_FSR_OFFSET (0x08) /**< (EEFC_FSR) EEFC Flash Status Register Offset */ 180 181 #define EEFC_FSR_FRDY_Pos 0 /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Position */ 182 #define EEFC_FSR_FRDY_Msk (_U_(0x1) << EEFC_FSR_FRDY_Pos) /**< (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) Mask */ 183 #define EEFC_FSR_FRDY EEFC_FSR_FRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FRDY_Msk instead */ 184 #define EEFC_FSR_FCMDE_Pos 1 /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Position */ 185 #define EEFC_FSR_FCMDE_Msk (_U_(0x1) << EEFC_FSR_FCMDE_Pos) /**< (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) Mask */ 186 #define EEFC_FSR_FCMDE EEFC_FSR_FCMDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FCMDE_Msk instead */ 187 #define EEFC_FSR_FLOCKE_Pos 2 /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Position */ 188 #define EEFC_FSR_FLOCKE_Msk (_U_(0x1) << EEFC_FSR_FLOCKE_Pos) /**< (EEFC_FSR) Flash Lock Error Status (cleared on read) Mask */ 189 #define EEFC_FSR_FLOCKE EEFC_FSR_FLOCKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FLOCKE_Msk instead */ 190 #define EEFC_FSR_FLERR_Pos 3 /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Position */ 191 #define EEFC_FSR_FLERR_Msk (_U_(0x1) << EEFC_FSR_FLERR_Pos) /**< (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) Mask */ 192 #define EEFC_FSR_FLERR EEFC_FSR_FLERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_FLERR_Msk instead */ 193 #define EEFC_FSR_UECCELSB_Pos 16 /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */ 194 #define EEFC_FSR_UECCELSB_Msk (_U_(0x1) << EEFC_FSR_UECCELSB_Pos) /**< (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */ 195 #define EEFC_FSR_UECCELSB EEFC_FSR_UECCELSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_UECCELSB_Msk instead */ 196 #define EEFC_FSR_MECCELSB_Pos 17 /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Position */ 197 #define EEFC_FSR_MECCELSB_Msk (_U_(0x1) << EEFC_FSR_MECCELSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) Mask */ 198 #define EEFC_FSR_MECCELSB EEFC_FSR_MECCELSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_MECCELSB_Msk instead */ 199 #define EEFC_FSR_UECCEMSB_Pos 18 /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */ 200 #define EEFC_FSR_UECCEMSB_Msk (_U_(0x1) << EEFC_FSR_UECCEMSB_Pos) /**< (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */ 201 #define EEFC_FSR_UECCEMSB EEFC_FSR_UECCEMSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_UECCEMSB_Msk instead */ 202 #define EEFC_FSR_MECCEMSB_Pos 19 /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Position */ 203 #define EEFC_FSR_MECCEMSB_Msk (_U_(0x1) << EEFC_FSR_MECCEMSB_Pos) /**< (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) Mask */ 204 #define EEFC_FSR_MECCEMSB EEFC_FSR_MECCEMSB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_FSR_MECCEMSB_Msk instead */ 205 #define EEFC_FSR_MASK _U_(0xF000F) /**< \deprecated (EEFC_FSR) Register MASK (Use EEFC_FSR_Msk instead) */ 206 #define EEFC_FSR_Msk _U_(0xF000F) /**< (EEFC_FSR) Register Mask */ 207 208 209 /* -------- EEFC_FRR : (EFC Offset: 0x0c) (R/ 32) EEFC Flash Result Register -------- */ 210 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 211 #if COMPONENT_TYPEDEF_STYLE == 'N' 212 typedef union { 213 struct { 214 uint32_t FVALUE:32; /**< bit: 0..31 Flash Result Value */ 215 } bit; /**< Structure used for bit access */ 216 uint32_t reg; /**< Type used for register access */ 217 } EEFC_FRR_Type; 218 #endif 219 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 220 221 #define EEFC_FRR_OFFSET (0x0C) /**< (EEFC_FRR) EEFC Flash Result Register Offset */ 222 223 #define EEFC_FRR_FVALUE_Pos 0 /**< (EEFC_FRR) Flash Result Value Position */ 224 #define EEFC_FRR_FVALUE_Msk (_U_(0xFFFFFFFF) << EEFC_FRR_FVALUE_Pos) /**< (EEFC_FRR) Flash Result Value Mask */ 225 #define EEFC_FRR_FVALUE(value) (EEFC_FRR_FVALUE_Msk & ((value) << EEFC_FRR_FVALUE_Pos)) 226 #define EEFC_FRR_MASK _U_(0xFFFFFFFF) /**< \deprecated (EEFC_FRR) Register MASK (Use EEFC_FRR_Msk instead) */ 227 #define EEFC_FRR_Msk _U_(0xFFFFFFFF) /**< (EEFC_FRR) Register Mask */ 228 229 230 /* -------- EEFC_WPMR : (EFC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 231 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 232 #if COMPONENT_TYPEDEF_STYLE == 'N' 233 typedef union { 234 struct { 235 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 236 uint32_t :7; /**< bit: 1..7 Reserved */ 237 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 238 } bit; /**< Structure used for bit access */ 239 uint32_t reg; /**< Type used for register access */ 240 } EEFC_WPMR_Type; 241 #endif 242 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 243 244 #define EEFC_WPMR_OFFSET (0xE4) /**< (EEFC_WPMR) Write Protection Mode Register Offset */ 245 246 #define EEFC_WPMR_WPEN_Pos 0 /**< (EEFC_WPMR) Write Protection Enable Position */ 247 #define EEFC_WPMR_WPEN_Msk (_U_(0x1) << EEFC_WPMR_WPEN_Pos) /**< (EEFC_WPMR) Write Protection Enable Mask */ 248 #define EEFC_WPMR_WPEN EEFC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use EEFC_WPMR_WPEN_Msk instead */ 249 #define EEFC_WPMR_WPKEY_Pos 8 /**< (EEFC_WPMR) Write Protection Key Position */ 250 #define EEFC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Write Protection Key Mask */ 251 #define EEFC_WPMR_WPKEY(value) (EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos)) 252 #define EEFC_WPMR_WPKEY_PASSWD_Val _U_(0x454643) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ 253 #define EEFC_WPMR_WPKEY_PASSWD (EEFC_WPMR_WPKEY_PASSWD_Val << EEFC_WPMR_WPKEY_Pos) /**< (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ 254 #define EEFC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (EEFC_WPMR) Register MASK (Use EEFC_WPMR_Msk instead) */ 255 #define EEFC_WPMR_Msk _U_(0xFFFFFF01) /**< (EEFC_WPMR) Register Mask */ 256 257 258 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 259 #if COMPONENT_TYPEDEF_STYLE == 'R' 260 /** \brief EFC hardware registers */ 261 typedef struct { 262 __IO uint32_t EEFC_FMR; /**< (EFC Offset: 0x00) EEFC Flash Mode Register */ 263 __O uint32_t EEFC_FCR; /**< (EFC Offset: 0x04) EEFC Flash Command Register */ 264 __I uint32_t EEFC_FSR; /**< (EFC Offset: 0x08) EEFC Flash Status Register */ 265 __I uint32_t EEFC_FRR; /**< (EFC Offset: 0x0C) EEFC Flash Result Register */ 266 __I uint8_t Reserved1[212]; 267 __IO uint32_t EEFC_WPMR; /**< (EFC Offset: 0xE4) Write Protection Mode Register */ 268 } Efc; 269 270 #elif COMPONENT_TYPEDEF_STYLE == 'N' 271 /** \brief EFC hardware registers */ 272 typedef struct { 273 __IO EEFC_FMR_Type EEFC_FMR; /**< Offset: 0x00 (R/W 32) EEFC Flash Mode Register */ 274 __O EEFC_FCR_Type EEFC_FCR; /**< Offset: 0x04 ( /W 32) EEFC Flash Command Register */ 275 __I EEFC_FSR_Type EEFC_FSR; /**< Offset: 0x08 (R/ 32) EEFC Flash Status Register */ 276 __I EEFC_FRR_Type EEFC_FRR; /**< Offset: 0x0C (R/ 32) EEFC Flash Result Register */ 277 __I uint8_t Reserved1[212]; 278 __IO EEFC_WPMR_Type EEFC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 279 } Efc; 280 281 #else /* COMPONENT_TYPEDEF_STYLE */ 282 #error Unknown component typedef style 283 #endif /* COMPONENT_TYPEDEF_STYLE */ 284 285 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 286 /** @} end of Embedded Flash Controller */ 287 288 #endif /* _SAMV71_EFC_COMPONENT_H_ */ 289
