1 /** 2 * \file 3 * 4 * \brief Component description for AFEC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_AFEC_COMPONENT_H_ 32 #define _SAMV71_AFEC_COMPONENT_H_ 33 #define _SAMV71_AFEC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Analog Front-End Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR AFEC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define AFEC_11147 /**< (AFEC) Module ID */ 46 #define REV_AFEC S /**< (AFEC) Module revision */ 47 48 /* -------- AFEC_CR : (AFEC Offset: 0x00) (/W 32) AFEC Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t SWRST:1; /**< bit: 0 Software Reset */ 54 uint32_t START:1; /**< bit: 1 Start Conversion */ 55 uint32_t :30; /**< bit: 2..31 Reserved */ 56 } bit; /**< Structure used for bit access */ 57 uint32_t reg; /**< Type used for register access */ 58 } AFEC_CR_Type; 59 #endif 60 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 61 62 #define AFEC_CR_OFFSET (0x00) /**< (AFEC_CR) AFEC Control Register Offset */ 63 64 #define AFEC_CR_SWRST_Pos 0 /**< (AFEC_CR) Software Reset Position */ 65 #define AFEC_CR_SWRST_Msk (_U_(0x1) << AFEC_CR_SWRST_Pos) /**< (AFEC_CR) Software Reset Mask */ 66 #define AFEC_CR_SWRST AFEC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CR_SWRST_Msk instead */ 67 #define AFEC_CR_START_Pos 1 /**< (AFEC_CR) Start Conversion Position */ 68 #define AFEC_CR_START_Msk (_U_(0x1) << AFEC_CR_START_Pos) /**< (AFEC_CR) Start Conversion Mask */ 69 #define AFEC_CR_START AFEC_CR_START_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CR_START_Msk instead */ 70 #define AFEC_CR_MASK _U_(0x03) /**< \deprecated (AFEC_CR) Register MASK (Use AFEC_CR_Msk instead) */ 71 #define AFEC_CR_Msk _U_(0x03) /**< (AFEC_CR) Register Mask */ 72 73 74 /* -------- AFEC_MR : (AFEC Offset: 0x04) (R/W 32) AFEC Mode Register -------- */ 75 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 76 #if COMPONENT_TYPEDEF_STYLE == 'N' 77 typedef union { 78 struct { 79 uint32_t TRGEN:1; /**< bit: 0 Trigger Enable */ 80 uint32_t TRGSEL:3; /**< bit: 1..3 Trigger Selection */ 81 uint32_t :1; /**< bit: 4 Reserved */ 82 uint32_t SLEEP:1; /**< bit: 5 Sleep Mode */ 83 uint32_t FWUP:1; /**< bit: 6 Fast Wake-up */ 84 uint32_t FREERUN:1; /**< bit: 7 Free Run Mode */ 85 uint32_t PRESCAL:8; /**< bit: 8..15 Prescaler Rate Selection */ 86 uint32_t STARTUP:4; /**< bit: 16..19 Start-up Time */ 87 uint32_t :3; /**< bit: 20..22 Reserved */ 88 uint32_t ONE:1; /**< bit: 23 One */ 89 uint32_t TRACKTIM:4; /**< bit: 24..27 Tracking Time */ 90 uint32_t TRANSFER:2; /**< bit: 28..29 Transfer Period */ 91 uint32_t :1; /**< bit: 30 Reserved */ 92 uint32_t USEQ:1; /**< bit: 31 User Sequence Enable */ 93 } bit; /**< Structure used for bit access */ 94 uint32_t reg; /**< Type used for register access */ 95 } AFEC_MR_Type; 96 #endif 97 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 #define AFEC_MR_OFFSET (0x04) /**< (AFEC_MR) AFEC Mode Register Offset */ 100 101 #define AFEC_MR_TRGEN_Pos 0 /**< (AFEC_MR) Trigger Enable Position */ 102 #define AFEC_MR_TRGEN_Msk (_U_(0x1) << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Trigger Enable Mask */ 103 #define AFEC_MR_TRGEN AFEC_MR_TRGEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_TRGEN_Msk instead */ 104 #define AFEC_MR_TRGEN_DIS_Val _U_(0x0) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ 105 #define AFEC_MR_TRGEN_EN_Val _U_(0x1) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ 106 #define AFEC_MR_TRGEN_DIS (AFEC_MR_TRGEN_DIS_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. Position */ 107 #define AFEC_MR_TRGEN_EN (AFEC_MR_TRGEN_EN_Val << AFEC_MR_TRGEN_Pos) /**< (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. Position */ 108 #define AFEC_MR_TRGSEL_Pos 1 /**< (AFEC_MR) Trigger Selection Position */ 109 #define AFEC_MR_TRGSEL_Msk (_U_(0x7) << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Trigger Selection Mask */ 110 #define AFEC_MR_TRGSEL(value) (AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos)) 111 #define AFEC_MR_TRGSEL_AFEC_TRIG0_Val _U_(0x0) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ 112 #define AFEC_MR_TRGSEL_AFEC_TRIG1_Val _U_(0x1) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ 113 #define AFEC_MR_TRGSEL_AFEC_TRIG2_Val _U_(0x2) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ 114 #define AFEC_MR_TRGSEL_AFEC_TRIG3_Val _U_(0x3) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ 115 #define AFEC_MR_TRGSEL_AFEC_TRIG4_Val _U_(0x4) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ 116 #define AFEC_MR_TRGSEL_AFEC_TRIG5_Val _U_(0x5) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ 117 #define AFEC_MR_TRGSEL_AFEC_TRIG6_Val _U_(0x6) /**< (AFEC_MR) Analog Comparator */ 118 #define AFEC_MR_TRGSEL_AFEC_TRIG0 (AFEC_MR_TRGSEL_AFEC_TRIG0_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 Position */ 119 #define AFEC_MR_TRGSEL_AFEC_TRIG1 (AFEC_MR_TRGSEL_AFEC_TRIG1_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 Position */ 120 #define AFEC_MR_TRGSEL_AFEC_TRIG2 (AFEC_MR_TRGSEL_AFEC_TRIG2_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 Position */ 121 #define AFEC_MR_TRGSEL_AFEC_TRIG3 (AFEC_MR_TRGSEL_AFEC_TRIG3_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 Position */ 122 #define AFEC_MR_TRGSEL_AFEC_TRIG4 (AFEC_MR_TRGSEL_AFEC_TRIG4_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 Position */ 123 #define AFEC_MR_TRGSEL_AFEC_TRIG5 (AFEC_MR_TRGSEL_AFEC_TRIG5_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 Position */ 124 #define AFEC_MR_TRGSEL_AFEC_TRIG6 (AFEC_MR_TRGSEL_AFEC_TRIG6_Val << AFEC_MR_TRGSEL_Pos) /**< (AFEC_MR) Analog Comparator Position */ 125 #define AFEC_MR_SLEEP_Pos 5 /**< (AFEC_MR) Sleep Mode Position */ 126 #define AFEC_MR_SLEEP_Msk (_U_(0x1) << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep Mode Mask */ 127 #define AFEC_MR_SLEEP AFEC_MR_SLEEP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_SLEEP_Msk instead */ 128 #define AFEC_MR_SLEEP_NORMAL_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ 129 #define AFEC_MR_SLEEP_SLEEP_Val _U_(0x1) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ 130 #define AFEC_MR_SLEEP_NORMAL (AFEC_MR_SLEEP_NORMAL_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. Position */ 131 #define AFEC_MR_SLEEP_SLEEP (AFEC_MR_SLEEP_SLEEP_Val << AFEC_MR_SLEEP_Pos) /**< (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. Position */ 132 #define AFEC_MR_FWUP_Pos 6 /**< (AFEC_MR) Fast Wake-up Position */ 133 #define AFEC_MR_FWUP_Msk (_U_(0x1) << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast Wake-up Mask */ 134 #define AFEC_MR_FWUP AFEC_MR_FWUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_FWUP_Msk instead */ 135 #define AFEC_MR_FWUP_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ 136 #define AFEC_MR_FWUP_ON_Val _U_(0x1) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ 137 #define AFEC_MR_FWUP_OFF (AFEC_MR_FWUP_OFF_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. Position */ 138 #define AFEC_MR_FWUP_ON (AFEC_MR_FWUP_ON_Val << AFEC_MR_FWUP_Pos) /**< (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. Position */ 139 #define AFEC_MR_FREERUN_Pos 7 /**< (AFEC_MR) Free Run Mode Position */ 140 #define AFEC_MR_FREERUN_Msk (_U_(0x1) << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run Mode Mask */ 141 #define AFEC_MR_FREERUN AFEC_MR_FREERUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_FREERUN_Msk instead */ 142 #define AFEC_MR_FREERUN_OFF_Val _U_(0x0) /**< (AFEC_MR) Normal mode */ 143 #define AFEC_MR_FREERUN_ON_Val _U_(0x1) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. */ 144 #define AFEC_MR_FREERUN_OFF (AFEC_MR_FREERUN_OFF_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Normal mode Position */ 145 #define AFEC_MR_FREERUN_ON (AFEC_MR_FREERUN_ON_Val << AFEC_MR_FREERUN_Pos) /**< (AFEC_MR) Free Run mode: Never wait for any trigger. Position */ 146 #define AFEC_MR_PRESCAL_Pos 8 /**< (AFEC_MR) Prescaler Rate Selection Position */ 147 #define AFEC_MR_PRESCAL_Msk (_U_(0xFF) << AFEC_MR_PRESCAL_Pos) /**< (AFEC_MR) Prescaler Rate Selection Mask */ 148 #define AFEC_MR_PRESCAL(value) (AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos)) 149 #define AFEC_MR_STARTUP_Pos 16 /**< (AFEC_MR) Start-up Time Position */ 150 #define AFEC_MR_STARTUP_Msk (_U_(0xF) << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) Start-up Time Mask */ 151 #define AFEC_MR_STARTUP(value) (AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos)) 152 #define AFEC_MR_STARTUP_SUT0_Val _U_(0x0) /**< (AFEC_MR) 0 periods of AFE clock */ 153 #define AFEC_MR_STARTUP_SUT8_Val _U_(0x1) /**< (AFEC_MR) 8 periods of AFE clock */ 154 #define AFEC_MR_STARTUP_SUT16_Val _U_(0x2) /**< (AFEC_MR) 16 periods of AFE clock */ 155 #define AFEC_MR_STARTUP_SUT24_Val _U_(0x3) /**< (AFEC_MR) 24 periods of AFE clock */ 156 #define AFEC_MR_STARTUP_SUT64_Val _U_(0x4) /**< (AFEC_MR) 64 periods of AFE clock */ 157 #define AFEC_MR_STARTUP_SUT80_Val _U_(0x5) /**< (AFEC_MR) 80 periods of AFE clock */ 158 #define AFEC_MR_STARTUP_SUT96_Val _U_(0x6) /**< (AFEC_MR) 96 periods of AFE clock */ 159 #define AFEC_MR_STARTUP_SUT112_Val _U_(0x7) /**< (AFEC_MR) 112 periods of AFE clock */ 160 #define AFEC_MR_STARTUP_SUT512_Val _U_(0x8) /**< (AFEC_MR) 512 periods of AFE clock */ 161 #define AFEC_MR_STARTUP_SUT576_Val _U_(0x9) /**< (AFEC_MR) 576 periods of AFE clock */ 162 #define AFEC_MR_STARTUP_SUT640_Val _U_(0xA) /**< (AFEC_MR) 640 periods of AFE clock */ 163 #define AFEC_MR_STARTUP_SUT704_Val _U_(0xB) /**< (AFEC_MR) 704 periods of AFE clock */ 164 #define AFEC_MR_STARTUP_SUT768_Val _U_(0xC) /**< (AFEC_MR) 768 periods of AFE clock */ 165 #define AFEC_MR_STARTUP_SUT832_Val _U_(0xD) /**< (AFEC_MR) 832 periods of AFE clock */ 166 #define AFEC_MR_STARTUP_SUT896_Val _U_(0xE) /**< (AFEC_MR) 896 periods of AFE clock */ 167 #define AFEC_MR_STARTUP_SUT960_Val _U_(0xF) /**< (AFEC_MR) 960 periods of AFE clock */ 168 #define AFEC_MR_STARTUP_SUT0 (AFEC_MR_STARTUP_SUT0_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 0 periods of AFE clock Position */ 169 #define AFEC_MR_STARTUP_SUT8 (AFEC_MR_STARTUP_SUT8_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 8 periods of AFE clock Position */ 170 #define AFEC_MR_STARTUP_SUT16 (AFEC_MR_STARTUP_SUT16_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 16 periods of AFE clock Position */ 171 #define AFEC_MR_STARTUP_SUT24 (AFEC_MR_STARTUP_SUT24_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 24 periods of AFE clock Position */ 172 #define AFEC_MR_STARTUP_SUT64 (AFEC_MR_STARTUP_SUT64_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 64 periods of AFE clock Position */ 173 #define AFEC_MR_STARTUP_SUT80 (AFEC_MR_STARTUP_SUT80_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 80 periods of AFE clock Position */ 174 #define AFEC_MR_STARTUP_SUT96 (AFEC_MR_STARTUP_SUT96_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 96 periods of AFE clock Position */ 175 #define AFEC_MR_STARTUP_SUT112 (AFEC_MR_STARTUP_SUT112_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 112 periods of AFE clock Position */ 176 #define AFEC_MR_STARTUP_SUT512 (AFEC_MR_STARTUP_SUT512_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 512 periods of AFE clock Position */ 177 #define AFEC_MR_STARTUP_SUT576 (AFEC_MR_STARTUP_SUT576_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 576 periods of AFE clock Position */ 178 #define AFEC_MR_STARTUP_SUT640 (AFEC_MR_STARTUP_SUT640_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 640 periods of AFE clock Position */ 179 #define AFEC_MR_STARTUP_SUT704 (AFEC_MR_STARTUP_SUT704_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 704 periods of AFE clock Position */ 180 #define AFEC_MR_STARTUP_SUT768 (AFEC_MR_STARTUP_SUT768_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 768 periods of AFE clock Position */ 181 #define AFEC_MR_STARTUP_SUT832 (AFEC_MR_STARTUP_SUT832_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 832 periods of AFE clock Position */ 182 #define AFEC_MR_STARTUP_SUT896 (AFEC_MR_STARTUP_SUT896_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 896 periods of AFE clock Position */ 183 #define AFEC_MR_STARTUP_SUT960 (AFEC_MR_STARTUP_SUT960_Val << AFEC_MR_STARTUP_Pos) /**< (AFEC_MR) 960 periods of AFE clock Position */ 184 #define AFEC_MR_ONE_Pos 23 /**< (AFEC_MR) One Position */ 185 #define AFEC_MR_ONE_Msk (_U_(0x1) << AFEC_MR_ONE_Pos) /**< (AFEC_MR) One Mask */ 186 #define AFEC_MR_ONE AFEC_MR_ONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_ONE_Msk instead */ 187 #define AFEC_MR_TRACKTIM_Pos 24 /**< (AFEC_MR) Tracking Time Position */ 188 #define AFEC_MR_TRACKTIM_Msk (_U_(0xF) << AFEC_MR_TRACKTIM_Pos) /**< (AFEC_MR) Tracking Time Mask */ 189 #define AFEC_MR_TRACKTIM(value) (AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos)) 190 #define AFEC_MR_TRANSFER_Pos 28 /**< (AFEC_MR) Transfer Period Position */ 191 #define AFEC_MR_TRANSFER_Msk (_U_(0x3) << AFEC_MR_TRANSFER_Pos) /**< (AFEC_MR) Transfer Period Mask */ 192 #define AFEC_MR_TRANSFER(value) (AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos)) 193 #define AFEC_MR_USEQ_Pos 31 /**< (AFEC_MR) User Sequence Enable Position */ 194 #define AFEC_MR_USEQ_Msk (_U_(0x1) << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence Enable Mask */ 195 #define AFEC_MR_USEQ AFEC_MR_USEQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_MR_USEQ_Msk instead */ 196 #define AFEC_MR_USEQ_NUM_ORDER_Val _U_(0x0) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ 197 #define AFEC_MR_USEQ_REG_ORDER_Val _U_(0x1) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ 198 #define AFEC_MR_USEQ_NUM_ORDER (AFEC_MR_USEQ_NUM_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. Position */ 199 #define AFEC_MR_USEQ_REG_ORDER (AFEC_MR_USEQ_REG_ORDER_Val << AFEC_MR_USEQ_Pos) /**< (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. Position */ 200 #define AFEC_MR_MASK _U_(0xBF8FFFEF) /**< \deprecated (AFEC_MR) Register MASK (Use AFEC_MR_Msk instead) */ 201 #define AFEC_MR_Msk _U_(0xBF8FFFEF) /**< (AFEC_MR) Register Mask */ 202 203 204 /* -------- AFEC_EMR : (AFEC Offset: 0x08) (R/W 32) AFEC Extended Mode Register -------- */ 205 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 206 #if COMPONENT_TYPEDEF_STYLE == 'N' 207 typedef union { 208 struct { 209 uint32_t CMPMODE:2; /**< bit: 0..1 Comparison Mode */ 210 uint32_t :1; /**< bit: 2 Reserved */ 211 uint32_t CMPSEL:5; /**< bit: 3..7 Comparison Selected Channel */ 212 uint32_t :1; /**< bit: 8 Reserved */ 213 uint32_t CMPALL:1; /**< bit: 9 Compare All Channels */ 214 uint32_t :2; /**< bit: 10..11 Reserved */ 215 uint32_t CMPFILTER:2; /**< bit: 12..13 Compare Event Filtering */ 216 uint32_t :2; /**< bit: 14..15 Reserved */ 217 uint32_t RES:3; /**< bit: 16..18 Resolution */ 218 uint32_t :5; /**< bit: 19..23 Reserved */ 219 uint32_t TAG:1; /**< bit: 24 TAG of the AFEC_LDCR */ 220 uint32_t STM:1; /**< bit: 25 Single Trigger Mode */ 221 uint32_t :2; /**< bit: 26..27 Reserved */ 222 uint32_t SIGNMODE:2; /**< bit: 28..29 Sign Mode */ 223 uint32_t :2; /**< bit: 30..31 Reserved */ 224 } bit; /**< Structure used for bit access */ 225 uint32_t reg; /**< Type used for register access */ 226 } AFEC_EMR_Type; 227 #endif 228 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 229 230 #define AFEC_EMR_OFFSET (0x08) /**< (AFEC_EMR) AFEC Extended Mode Register Offset */ 231 232 #define AFEC_EMR_CMPMODE_Pos 0 /**< (AFEC_EMR) Comparison Mode Position */ 233 #define AFEC_EMR_CMPMODE_Msk (_U_(0x3) << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Comparison Mode Mask */ 234 #define AFEC_EMR_CMPMODE(value) (AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos)) 235 #define AFEC_EMR_CMPMODE_LOW_Val _U_(0x0) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ 236 #define AFEC_EMR_CMPMODE_HIGH_Val _U_(0x1) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ 237 #define AFEC_EMR_CMPMODE_IN_Val _U_(0x2) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ 238 #define AFEC_EMR_CMPMODE_OUT_Val _U_(0x3) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ 239 #define AFEC_EMR_CMPMODE_LOW (AFEC_EMR_CMPMODE_LOW_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. Position */ 240 #define AFEC_EMR_CMPMODE_HIGH (AFEC_EMR_CMPMODE_HIGH_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. Position */ 241 #define AFEC_EMR_CMPMODE_IN (AFEC_EMR_CMPMODE_IN_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is in the comparison window. Position */ 242 #define AFEC_EMR_CMPMODE_OUT (AFEC_EMR_CMPMODE_OUT_Val << AFEC_EMR_CMPMODE_Pos) /**< (AFEC_EMR) Generates an event when the converted data is out of the comparison window. Position */ 243 #define AFEC_EMR_CMPSEL_Pos 3 /**< (AFEC_EMR) Comparison Selected Channel Position */ 244 #define AFEC_EMR_CMPSEL_Msk (_U_(0x1F) << AFEC_EMR_CMPSEL_Pos) /**< (AFEC_EMR) Comparison Selected Channel Mask */ 245 #define AFEC_EMR_CMPSEL(value) (AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos)) 246 #define AFEC_EMR_CMPALL_Pos 9 /**< (AFEC_EMR) Compare All Channels Position */ 247 #define AFEC_EMR_CMPALL_Msk (_U_(0x1) << AFEC_EMR_CMPALL_Pos) /**< (AFEC_EMR) Compare All Channels Mask */ 248 #define AFEC_EMR_CMPALL AFEC_EMR_CMPALL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_EMR_CMPALL_Msk instead */ 249 #define AFEC_EMR_CMPFILTER_Pos 12 /**< (AFEC_EMR) Compare Event Filtering Position */ 250 #define AFEC_EMR_CMPFILTER_Msk (_U_(0x3) << AFEC_EMR_CMPFILTER_Pos) /**< (AFEC_EMR) Compare Event Filtering Mask */ 251 #define AFEC_EMR_CMPFILTER(value) (AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos)) 252 #define AFEC_EMR_RES_Pos 16 /**< (AFEC_EMR) Resolution Position */ 253 #define AFEC_EMR_RES_Msk (_U_(0x7) << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) Resolution Mask */ 254 #define AFEC_EMR_RES(value) (AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos)) 255 #define AFEC_EMR_RES_NO_AVERAGE_Val _U_(0x0) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ 256 #define AFEC_EMR_RES_OSR4_Val _U_(0x2) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ 257 #define AFEC_EMR_RES_OSR16_Val _U_(0x3) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ 258 #define AFEC_EMR_RES_OSR64_Val _U_(0x4) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ 259 #define AFEC_EMR_RES_OSR256_Val _U_(0x5) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ 260 #define AFEC_EMR_RES_NO_AVERAGE (AFEC_EMR_RES_NO_AVERAGE_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). Position */ 261 #define AFEC_EMR_RES_OSR4 (AFEC_EMR_RES_OSR4_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). Position */ 262 #define AFEC_EMR_RES_OSR16 (AFEC_EMR_RES_OSR16_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). Position */ 263 #define AFEC_EMR_RES_OSR64 (AFEC_EMR_RES_OSR64_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). Position */ 264 #define AFEC_EMR_RES_OSR256 (AFEC_EMR_RES_OSR256_Val << AFEC_EMR_RES_Pos) /**< (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). Position */ 265 #define AFEC_EMR_TAG_Pos 24 /**< (AFEC_EMR) TAG of the AFEC_LDCR Position */ 266 #define AFEC_EMR_TAG_Msk (_U_(0x1) << AFEC_EMR_TAG_Pos) /**< (AFEC_EMR) TAG of the AFEC_LDCR Mask */ 267 #define AFEC_EMR_TAG AFEC_EMR_TAG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_EMR_TAG_Msk instead */ 268 #define AFEC_EMR_STM_Pos 25 /**< (AFEC_EMR) Single Trigger Mode Position */ 269 #define AFEC_EMR_STM_Msk (_U_(0x1) << AFEC_EMR_STM_Pos) /**< (AFEC_EMR) Single Trigger Mode Mask */ 270 #define AFEC_EMR_STM AFEC_EMR_STM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_EMR_STM_Msk instead */ 271 #define AFEC_EMR_SIGNMODE_Pos 28 /**< (AFEC_EMR) Sign Mode Position */ 272 #define AFEC_EMR_SIGNMODE_Msk (_U_(0x3) << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Sign Mode Mask */ 273 #define AFEC_EMR_SIGNMODE(value) (AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos)) 274 #define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val _U_(0x0) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ 275 #define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val _U_(0x1) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ 276 #define AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val _U_(0x2) /**< (AFEC_EMR) All channels: Unsigned conversions. */ 277 #define AFEC_EMR_SIGNMODE_ALL_SIGNED_Val _U_(0x3) /**< (AFEC_EMR) All channels: Signed conversions. */ 278 #define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. Position */ 279 #define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. Position */ 280 #define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (AFEC_EMR_SIGNMODE_ALL_UNSIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Unsigned conversions. Position */ 281 #define AFEC_EMR_SIGNMODE_ALL_SIGNED (AFEC_EMR_SIGNMODE_ALL_SIGNED_Val << AFEC_EMR_SIGNMODE_Pos) /**< (AFEC_EMR) All channels: Signed conversions. Position */ 282 #define AFEC_EMR_MASK _U_(0x330732FB) /**< \deprecated (AFEC_EMR) Register MASK (Use AFEC_EMR_Msk instead) */ 283 #define AFEC_EMR_Msk _U_(0x330732FB) /**< (AFEC_EMR) Register Mask */ 284 285 286 /* -------- AFEC_SEQ1R : (AFEC Offset: 0x0c) (R/W 32) AFEC Channel Sequence 1 Register -------- */ 287 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 288 #if COMPONENT_TYPEDEF_STYLE == 'N' 289 typedef union { 290 struct { 291 uint32_t USCH0:4; /**< bit: 0..3 User Sequence Number 0 */ 292 uint32_t USCH1:4; /**< bit: 4..7 User Sequence Number 1 */ 293 uint32_t USCH2:4; /**< bit: 8..11 User Sequence Number 2 */ 294 uint32_t USCH3:4; /**< bit: 12..15 User Sequence Number 3 */ 295 uint32_t USCH4:4; /**< bit: 16..19 User Sequence Number 4 */ 296 uint32_t USCH5:4; /**< bit: 20..23 User Sequence Number 5 */ 297 uint32_t USCH6:4; /**< bit: 24..27 User Sequence Number 6 */ 298 uint32_t USCH7:4; /**< bit: 28..31 User Sequence Number 7 */ 299 } bit; /**< Structure used for bit access */ 300 uint32_t reg; /**< Type used for register access */ 301 } AFEC_SEQ1R_Type; 302 #endif 303 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 304 305 #define AFEC_SEQ1R_OFFSET (0x0C) /**< (AFEC_SEQ1R) AFEC Channel Sequence 1 Register Offset */ 306 307 #define AFEC_SEQ1R_USCH0_Pos 0 /**< (AFEC_SEQ1R) User Sequence Number 0 Position */ 308 #define AFEC_SEQ1R_USCH0_Msk (_U_(0xF) << AFEC_SEQ1R_USCH0_Pos) /**< (AFEC_SEQ1R) User Sequence Number 0 Mask */ 309 #define AFEC_SEQ1R_USCH0(value) (AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos)) 310 #define AFEC_SEQ1R_USCH1_Pos 4 /**< (AFEC_SEQ1R) User Sequence Number 1 Position */ 311 #define AFEC_SEQ1R_USCH1_Msk (_U_(0xF) << AFEC_SEQ1R_USCH1_Pos) /**< (AFEC_SEQ1R) User Sequence Number 1 Mask */ 312 #define AFEC_SEQ1R_USCH1(value) (AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos)) 313 #define AFEC_SEQ1R_USCH2_Pos 8 /**< (AFEC_SEQ1R) User Sequence Number 2 Position */ 314 #define AFEC_SEQ1R_USCH2_Msk (_U_(0xF) << AFEC_SEQ1R_USCH2_Pos) /**< (AFEC_SEQ1R) User Sequence Number 2 Mask */ 315 #define AFEC_SEQ1R_USCH2(value) (AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos)) 316 #define AFEC_SEQ1R_USCH3_Pos 12 /**< (AFEC_SEQ1R) User Sequence Number 3 Position */ 317 #define AFEC_SEQ1R_USCH3_Msk (_U_(0xF) << AFEC_SEQ1R_USCH3_Pos) /**< (AFEC_SEQ1R) User Sequence Number 3 Mask */ 318 #define AFEC_SEQ1R_USCH3(value) (AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos)) 319 #define AFEC_SEQ1R_USCH4_Pos 16 /**< (AFEC_SEQ1R) User Sequence Number 4 Position */ 320 #define AFEC_SEQ1R_USCH4_Msk (_U_(0xF) << AFEC_SEQ1R_USCH4_Pos) /**< (AFEC_SEQ1R) User Sequence Number 4 Mask */ 321 #define AFEC_SEQ1R_USCH4(value) (AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos)) 322 #define AFEC_SEQ1R_USCH5_Pos 20 /**< (AFEC_SEQ1R) User Sequence Number 5 Position */ 323 #define AFEC_SEQ1R_USCH5_Msk (_U_(0xF) << AFEC_SEQ1R_USCH5_Pos) /**< (AFEC_SEQ1R) User Sequence Number 5 Mask */ 324 #define AFEC_SEQ1R_USCH5(value) (AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos)) 325 #define AFEC_SEQ1R_USCH6_Pos 24 /**< (AFEC_SEQ1R) User Sequence Number 6 Position */ 326 #define AFEC_SEQ1R_USCH6_Msk (_U_(0xF) << AFEC_SEQ1R_USCH6_Pos) /**< (AFEC_SEQ1R) User Sequence Number 6 Mask */ 327 #define AFEC_SEQ1R_USCH6(value) (AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos)) 328 #define AFEC_SEQ1R_USCH7_Pos 28 /**< (AFEC_SEQ1R) User Sequence Number 7 Position */ 329 #define AFEC_SEQ1R_USCH7_Msk (_U_(0xF) << AFEC_SEQ1R_USCH7_Pos) /**< (AFEC_SEQ1R) User Sequence Number 7 Mask */ 330 #define AFEC_SEQ1R_USCH7(value) (AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos)) 331 #define AFEC_SEQ1R_MASK _U_(0xFFFFFFFF) /**< \deprecated (AFEC_SEQ1R) Register MASK (Use AFEC_SEQ1R_Msk instead) */ 332 #define AFEC_SEQ1R_Msk _U_(0xFFFFFFFF) /**< (AFEC_SEQ1R) Register Mask */ 333 334 335 /* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) (R/W 32) AFEC Channel Sequence 2 Register -------- */ 336 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 337 #if COMPONENT_TYPEDEF_STYLE == 'N' 338 typedef union { 339 struct { 340 uint32_t USCH8:4; /**< bit: 0..3 User Sequence Number 8 */ 341 uint32_t USCH9:4; /**< bit: 4..7 User Sequence Number 9 */ 342 uint32_t USCH10:4; /**< bit: 8..11 User Sequence Number 10 */ 343 uint32_t USCH11:4; /**< bit: 12..15 User Sequence Number 11 */ 344 uint32_t :16; /**< bit: 16..31 Reserved */ 345 } bit; /**< Structure used for bit access */ 346 uint32_t reg; /**< Type used for register access */ 347 } AFEC_SEQ2R_Type; 348 #endif 349 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 350 351 #define AFEC_SEQ2R_OFFSET (0x10) /**< (AFEC_SEQ2R) AFEC Channel Sequence 2 Register Offset */ 352 353 #define AFEC_SEQ2R_USCH8_Pos 0 /**< (AFEC_SEQ2R) User Sequence Number 8 Position */ 354 #define AFEC_SEQ2R_USCH8_Msk (_U_(0xF) << AFEC_SEQ2R_USCH8_Pos) /**< (AFEC_SEQ2R) User Sequence Number 8 Mask */ 355 #define AFEC_SEQ2R_USCH8(value) (AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos)) 356 #define AFEC_SEQ2R_USCH9_Pos 4 /**< (AFEC_SEQ2R) User Sequence Number 9 Position */ 357 #define AFEC_SEQ2R_USCH9_Msk (_U_(0xF) << AFEC_SEQ2R_USCH9_Pos) /**< (AFEC_SEQ2R) User Sequence Number 9 Mask */ 358 #define AFEC_SEQ2R_USCH9(value) (AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos)) 359 #define AFEC_SEQ2R_USCH10_Pos 8 /**< (AFEC_SEQ2R) User Sequence Number 10 Position */ 360 #define AFEC_SEQ2R_USCH10_Msk (_U_(0xF) << AFEC_SEQ2R_USCH10_Pos) /**< (AFEC_SEQ2R) User Sequence Number 10 Mask */ 361 #define AFEC_SEQ2R_USCH10(value) (AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos)) 362 #define AFEC_SEQ2R_USCH11_Pos 12 /**< (AFEC_SEQ2R) User Sequence Number 11 Position */ 363 #define AFEC_SEQ2R_USCH11_Msk (_U_(0xF) << AFEC_SEQ2R_USCH11_Pos) /**< (AFEC_SEQ2R) User Sequence Number 11 Mask */ 364 #define AFEC_SEQ2R_USCH11(value) (AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos)) 365 #define AFEC_SEQ2R_MASK _U_(0xFFFF) /**< \deprecated (AFEC_SEQ2R) Register MASK (Use AFEC_SEQ2R_Msk instead) */ 366 #define AFEC_SEQ2R_Msk _U_(0xFFFF) /**< (AFEC_SEQ2R) Register Mask */ 367 368 369 /* -------- AFEC_CHER : (AFEC Offset: 0x14) (/W 32) AFEC Channel Enable Register -------- */ 370 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 371 #if COMPONENT_TYPEDEF_STYLE == 'N' 372 typedef union { 373 struct { 374 uint32_t CH0:1; /**< bit: 0 Channel 0 Enable */ 375 uint32_t CH1:1; /**< bit: 1 Channel 1 Enable */ 376 uint32_t CH2:1; /**< bit: 2 Channel 2 Enable */ 377 uint32_t CH3:1; /**< bit: 3 Channel 3 Enable */ 378 uint32_t CH4:1; /**< bit: 4 Channel 4 Enable */ 379 uint32_t CH5:1; /**< bit: 5 Channel 5 Enable */ 380 uint32_t CH6:1; /**< bit: 6 Channel 6 Enable */ 381 uint32_t CH7:1; /**< bit: 7 Channel 7 Enable */ 382 uint32_t CH8:1; /**< bit: 8 Channel 8 Enable */ 383 uint32_t CH9:1; /**< bit: 9 Channel 9 Enable */ 384 uint32_t CH10:1; /**< bit: 10 Channel 10 Enable */ 385 uint32_t CH11:1; /**< bit: 11 Channel 11 Enable */ 386 uint32_t :20; /**< bit: 12..31 Reserved */ 387 } bit; /**< Structure used for bit access */ 388 struct { 389 uint32_t CH:12; /**< bit: 0..11 Channel xx Enable */ 390 uint32_t :20; /**< bit: 12..31 Reserved */ 391 } vec; /**< Structure used for vec access */ 392 uint32_t reg; /**< Type used for register access */ 393 } AFEC_CHER_Type; 394 #endif 395 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 396 397 #define AFEC_CHER_OFFSET (0x14) /**< (AFEC_CHER) AFEC Channel Enable Register Offset */ 398 399 #define AFEC_CHER_CH0_Pos 0 /**< (AFEC_CHER) Channel 0 Enable Position */ 400 #define AFEC_CHER_CH0_Msk (_U_(0x1) << AFEC_CHER_CH0_Pos) /**< (AFEC_CHER) Channel 0 Enable Mask */ 401 #define AFEC_CHER_CH0 AFEC_CHER_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH0_Msk instead */ 402 #define AFEC_CHER_CH1_Pos 1 /**< (AFEC_CHER) Channel 1 Enable Position */ 403 #define AFEC_CHER_CH1_Msk (_U_(0x1) << AFEC_CHER_CH1_Pos) /**< (AFEC_CHER) Channel 1 Enable Mask */ 404 #define AFEC_CHER_CH1 AFEC_CHER_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH1_Msk instead */ 405 #define AFEC_CHER_CH2_Pos 2 /**< (AFEC_CHER) Channel 2 Enable Position */ 406 #define AFEC_CHER_CH2_Msk (_U_(0x1) << AFEC_CHER_CH2_Pos) /**< (AFEC_CHER) Channel 2 Enable Mask */ 407 #define AFEC_CHER_CH2 AFEC_CHER_CH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH2_Msk instead */ 408 #define AFEC_CHER_CH3_Pos 3 /**< (AFEC_CHER) Channel 3 Enable Position */ 409 #define AFEC_CHER_CH3_Msk (_U_(0x1) << AFEC_CHER_CH3_Pos) /**< (AFEC_CHER) Channel 3 Enable Mask */ 410 #define AFEC_CHER_CH3 AFEC_CHER_CH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH3_Msk instead */ 411 #define AFEC_CHER_CH4_Pos 4 /**< (AFEC_CHER) Channel 4 Enable Position */ 412 #define AFEC_CHER_CH4_Msk (_U_(0x1) << AFEC_CHER_CH4_Pos) /**< (AFEC_CHER) Channel 4 Enable Mask */ 413 #define AFEC_CHER_CH4 AFEC_CHER_CH4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH4_Msk instead */ 414 #define AFEC_CHER_CH5_Pos 5 /**< (AFEC_CHER) Channel 5 Enable Position */ 415 #define AFEC_CHER_CH5_Msk (_U_(0x1) << AFEC_CHER_CH5_Pos) /**< (AFEC_CHER) Channel 5 Enable Mask */ 416 #define AFEC_CHER_CH5 AFEC_CHER_CH5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH5_Msk instead */ 417 #define AFEC_CHER_CH6_Pos 6 /**< (AFEC_CHER) Channel 6 Enable Position */ 418 #define AFEC_CHER_CH6_Msk (_U_(0x1) << AFEC_CHER_CH6_Pos) /**< (AFEC_CHER) Channel 6 Enable Mask */ 419 #define AFEC_CHER_CH6 AFEC_CHER_CH6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH6_Msk instead */ 420 #define AFEC_CHER_CH7_Pos 7 /**< (AFEC_CHER) Channel 7 Enable Position */ 421 #define AFEC_CHER_CH7_Msk (_U_(0x1) << AFEC_CHER_CH7_Pos) /**< (AFEC_CHER) Channel 7 Enable Mask */ 422 #define AFEC_CHER_CH7 AFEC_CHER_CH7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH7_Msk instead */ 423 #define AFEC_CHER_CH8_Pos 8 /**< (AFEC_CHER) Channel 8 Enable Position */ 424 #define AFEC_CHER_CH8_Msk (_U_(0x1) << AFEC_CHER_CH8_Pos) /**< (AFEC_CHER) Channel 8 Enable Mask */ 425 #define AFEC_CHER_CH8 AFEC_CHER_CH8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH8_Msk instead */ 426 #define AFEC_CHER_CH9_Pos 9 /**< (AFEC_CHER) Channel 9 Enable Position */ 427 #define AFEC_CHER_CH9_Msk (_U_(0x1) << AFEC_CHER_CH9_Pos) /**< (AFEC_CHER) Channel 9 Enable Mask */ 428 #define AFEC_CHER_CH9 AFEC_CHER_CH9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH9_Msk instead */ 429 #define AFEC_CHER_CH10_Pos 10 /**< (AFEC_CHER) Channel 10 Enable Position */ 430 #define AFEC_CHER_CH10_Msk (_U_(0x1) << AFEC_CHER_CH10_Pos) /**< (AFEC_CHER) Channel 10 Enable Mask */ 431 #define AFEC_CHER_CH10 AFEC_CHER_CH10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH10_Msk instead */ 432 #define AFEC_CHER_CH11_Pos 11 /**< (AFEC_CHER) Channel 11 Enable Position */ 433 #define AFEC_CHER_CH11_Msk (_U_(0x1) << AFEC_CHER_CH11_Pos) /**< (AFEC_CHER) Channel 11 Enable Mask */ 434 #define AFEC_CHER_CH11 AFEC_CHER_CH11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHER_CH11_Msk instead */ 435 #define AFEC_CHER_MASK _U_(0xFFF) /**< \deprecated (AFEC_CHER) Register MASK (Use AFEC_CHER_Msk instead) */ 436 #define AFEC_CHER_Msk _U_(0xFFF) /**< (AFEC_CHER) Register Mask */ 437 438 #define AFEC_CHER_CH_Pos 0 /**< (AFEC_CHER Position) Channel xx Enable */ 439 #define AFEC_CHER_CH_Msk (_U_(0xFFF) << AFEC_CHER_CH_Pos) /**< (AFEC_CHER Mask) CH */ 440 #define AFEC_CHER_CH(value) (AFEC_CHER_CH_Msk & ((value) << AFEC_CHER_CH_Pos)) 441 442 /* -------- AFEC_CHDR : (AFEC Offset: 0x18) (/W 32) AFEC Channel Disable Register -------- */ 443 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 444 #if COMPONENT_TYPEDEF_STYLE == 'N' 445 typedef union { 446 struct { 447 uint32_t CH0:1; /**< bit: 0 Channel 0 Disable */ 448 uint32_t CH1:1; /**< bit: 1 Channel 1 Disable */ 449 uint32_t CH2:1; /**< bit: 2 Channel 2 Disable */ 450 uint32_t CH3:1; /**< bit: 3 Channel 3 Disable */ 451 uint32_t CH4:1; /**< bit: 4 Channel 4 Disable */ 452 uint32_t CH5:1; /**< bit: 5 Channel 5 Disable */ 453 uint32_t CH6:1; /**< bit: 6 Channel 6 Disable */ 454 uint32_t CH7:1; /**< bit: 7 Channel 7 Disable */ 455 uint32_t CH8:1; /**< bit: 8 Channel 8 Disable */ 456 uint32_t CH9:1; /**< bit: 9 Channel 9 Disable */ 457 uint32_t CH10:1; /**< bit: 10 Channel 10 Disable */ 458 uint32_t CH11:1; /**< bit: 11 Channel 11 Disable */ 459 uint32_t :20; /**< bit: 12..31 Reserved */ 460 } bit; /**< Structure used for bit access */ 461 struct { 462 uint32_t CH:12; /**< bit: 0..11 Channel xx Disable */ 463 uint32_t :20; /**< bit: 12..31 Reserved */ 464 } vec; /**< Structure used for vec access */ 465 uint32_t reg; /**< Type used for register access */ 466 } AFEC_CHDR_Type; 467 #endif 468 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 469 470 #define AFEC_CHDR_OFFSET (0x18) /**< (AFEC_CHDR) AFEC Channel Disable Register Offset */ 471 472 #define AFEC_CHDR_CH0_Pos 0 /**< (AFEC_CHDR) Channel 0 Disable Position */ 473 #define AFEC_CHDR_CH0_Msk (_U_(0x1) << AFEC_CHDR_CH0_Pos) /**< (AFEC_CHDR) Channel 0 Disable Mask */ 474 #define AFEC_CHDR_CH0 AFEC_CHDR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH0_Msk instead */ 475 #define AFEC_CHDR_CH1_Pos 1 /**< (AFEC_CHDR) Channel 1 Disable Position */ 476 #define AFEC_CHDR_CH1_Msk (_U_(0x1) << AFEC_CHDR_CH1_Pos) /**< (AFEC_CHDR) Channel 1 Disable Mask */ 477 #define AFEC_CHDR_CH1 AFEC_CHDR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH1_Msk instead */ 478 #define AFEC_CHDR_CH2_Pos 2 /**< (AFEC_CHDR) Channel 2 Disable Position */ 479 #define AFEC_CHDR_CH2_Msk (_U_(0x1) << AFEC_CHDR_CH2_Pos) /**< (AFEC_CHDR) Channel 2 Disable Mask */ 480 #define AFEC_CHDR_CH2 AFEC_CHDR_CH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH2_Msk instead */ 481 #define AFEC_CHDR_CH3_Pos 3 /**< (AFEC_CHDR) Channel 3 Disable Position */ 482 #define AFEC_CHDR_CH3_Msk (_U_(0x1) << AFEC_CHDR_CH3_Pos) /**< (AFEC_CHDR) Channel 3 Disable Mask */ 483 #define AFEC_CHDR_CH3 AFEC_CHDR_CH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH3_Msk instead */ 484 #define AFEC_CHDR_CH4_Pos 4 /**< (AFEC_CHDR) Channel 4 Disable Position */ 485 #define AFEC_CHDR_CH4_Msk (_U_(0x1) << AFEC_CHDR_CH4_Pos) /**< (AFEC_CHDR) Channel 4 Disable Mask */ 486 #define AFEC_CHDR_CH4 AFEC_CHDR_CH4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH4_Msk instead */ 487 #define AFEC_CHDR_CH5_Pos 5 /**< (AFEC_CHDR) Channel 5 Disable Position */ 488 #define AFEC_CHDR_CH5_Msk (_U_(0x1) << AFEC_CHDR_CH5_Pos) /**< (AFEC_CHDR) Channel 5 Disable Mask */ 489 #define AFEC_CHDR_CH5 AFEC_CHDR_CH5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH5_Msk instead */ 490 #define AFEC_CHDR_CH6_Pos 6 /**< (AFEC_CHDR) Channel 6 Disable Position */ 491 #define AFEC_CHDR_CH6_Msk (_U_(0x1) << AFEC_CHDR_CH6_Pos) /**< (AFEC_CHDR) Channel 6 Disable Mask */ 492 #define AFEC_CHDR_CH6 AFEC_CHDR_CH6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH6_Msk instead */ 493 #define AFEC_CHDR_CH7_Pos 7 /**< (AFEC_CHDR) Channel 7 Disable Position */ 494 #define AFEC_CHDR_CH7_Msk (_U_(0x1) << AFEC_CHDR_CH7_Pos) /**< (AFEC_CHDR) Channel 7 Disable Mask */ 495 #define AFEC_CHDR_CH7 AFEC_CHDR_CH7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH7_Msk instead */ 496 #define AFEC_CHDR_CH8_Pos 8 /**< (AFEC_CHDR) Channel 8 Disable Position */ 497 #define AFEC_CHDR_CH8_Msk (_U_(0x1) << AFEC_CHDR_CH8_Pos) /**< (AFEC_CHDR) Channel 8 Disable Mask */ 498 #define AFEC_CHDR_CH8 AFEC_CHDR_CH8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH8_Msk instead */ 499 #define AFEC_CHDR_CH9_Pos 9 /**< (AFEC_CHDR) Channel 9 Disable Position */ 500 #define AFEC_CHDR_CH9_Msk (_U_(0x1) << AFEC_CHDR_CH9_Pos) /**< (AFEC_CHDR) Channel 9 Disable Mask */ 501 #define AFEC_CHDR_CH9 AFEC_CHDR_CH9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH9_Msk instead */ 502 #define AFEC_CHDR_CH10_Pos 10 /**< (AFEC_CHDR) Channel 10 Disable Position */ 503 #define AFEC_CHDR_CH10_Msk (_U_(0x1) << AFEC_CHDR_CH10_Pos) /**< (AFEC_CHDR) Channel 10 Disable Mask */ 504 #define AFEC_CHDR_CH10 AFEC_CHDR_CH10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH10_Msk instead */ 505 #define AFEC_CHDR_CH11_Pos 11 /**< (AFEC_CHDR) Channel 11 Disable Position */ 506 #define AFEC_CHDR_CH11_Msk (_U_(0x1) << AFEC_CHDR_CH11_Pos) /**< (AFEC_CHDR) Channel 11 Disable Mask */ 507 #define AFEC_CHDR_CH11 AFEC_CHDR_CH11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHDR_CH11_Msk instead */ 508 #define AFEC_CHDR_MASK _U_(0xFFF) /**< \deprecated (AFEC_CHDR) Register MASK (Use AFEC_CHDR_Msk instead) */ 509 #define AFEC_CHDR_Msk _U_(0xFFF) /**< (AFEC_CHDR) Register Mask */ 510 511 #define AFEC_CHDR_CH_Pos 0 /**< (AFEC_CHDR Position) Channel xx Disable */ 512 #define AFEC_CHDR_CH_Msk (_U_(0xFFF) << AFEC_CHDR_CH_Pos) /**< (AFEC_CHDR Mask) CH */ 513 #define AFEC_CHDR_CH(value) (AFEC_CHDR_CH_Msk & ((value) << AFEC_CHDR_CH_Pos)) 514 515 /* -------- AFEC_CHSR : (AFEC Offset: 0x1c) (R/ 32) AFEC Channel Status Register -------- */ 516 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 517 #if COMPONENT_TYPEDEF_STYLE == 'N' 518 typedef union { 519 struct { 520 uint32_t CH0:1; /**< bit: 0 Channel 0 Status */ 521 uint32_t CH1:1; /**< bit: 1 Channel 1 Status */ 522 uint32_t CH2:1; /**< bit: 2 Channel 2 Status */ 523 uint32_t CH3:1; /**< bit: 3 Channel 3 Status */ 524 uint32_t CH4:1; /**< bit: 4 Channel 4 Status */ 525 uint32_t CH5:1; /**< bit: 5 Channel 5 Status */ 526 uint32_t CH6:1; /**< bit: 6 Channel 6 Status */ 527 uint32_t CH7:1; /**< bit: 7 Channel 7 Status */ 528 uint32_t CH8:1; /**< bit: 8 Channel 8 Status */ 529 uint32_t CH9:1; /**< bit: 9 Channel 9 Status */ 530 uint32_t CH10:1; /**< bit: 10 Channel 10 Status */ 531 uint32_t CH11:1; /**< bit: 11 Channel 11 Status */ 532 uint32_t :20; /**< bit: 12..31 Reserved */ 533 } bit; /**< Structure used for bit access */ 534 struct { 535 uint32_t CH:12; /**< bit: 0..11 Channel xx Status */ 536 uint32_t :20; /**< bit: 12..31 Reserved */ 537 } vec; /**< Structure used for vec access */ 538 uint32_t reg; /**< Type used for register access */ 539 } AFEC_CHSR_Type; 540 #endif 541 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 542 543 #define AFEC_CHSR_OFFSET (0x1C) /**< (AFEC_CHSR) AFEC Channel Status Register Offset */ 544 545 #define AFEC_CHSR_CH0_Pos 0 /**< (AFEC_CHSR) Channel 0 Status Position */ 546 #define AFEC_CHSR_CH0_Msk (_U_(0x1) << AFEC_CHSR_CH0_Pos) /**< (AFEC_CHSR) Channel 0 Status Mask */ 547 #define AFEC_CHSR_CH0 AFEC_CHSR_CH0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH0_Msk instead */ 548 #define AFEC_CHSR_CH1_Pos 1 /**< (AFEC_CHSR) Channel 1 Status Position */ 549 #define AFEC_CHSR_CH1_Msk (_U_(0x1) << AFEC_CHSR_CH1_Pos) /**< (AFEC_CHSR) Channel 1 Status Mask */ 550 #define AFEC_CHSR_CH1 AFEC_CHSR_CH1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH1_Msk instead */ 551 #define AFEC_CHSR_CH2_Pos 2 /**< (AFEC_CHSR) Channel 2 Status Position */ 552 #define AFEC_CHSR_CH2_Msk (_U_(0x1) << AFEC_CHSR_CH2_Pos) /**< (AFEC_CHSR) Channel 2 Status Mask */ 553 #define AFEC_CHSR_CH2 AFEC_CHSR_CH2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH2_Msk instead */ 554 #define AFEC_CHSR_CH3_Pos 3 /**< (AFEC_CHSR) Channel 3 Status Position */ 555 #define AFEC_CHSR_CH3_Msk (_U_(0x1) << AFEC_CHSR_CH3_Pos) /**< (AFEC_CHSR) Channel 3 Status Mask */ 556 #define AFEC_CHSR_CH3 AFEC_CHSR_CH3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH3_Msk instead */ 557 #define AFEC_CHSR_CH4_Pos 4 /**< (AFEC_CHSR) Channel 4 Status Position */ 558 #define AFEC_CHSR_CH4_Msk (_U_(0x1) << AFEC_CHSR_CH4_Pos) /**< (AFEC_CHSR) Channel 4 Status Mask */ 559 #define AFEC_CHSR_CH4 AFEC_CHSR_CH4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH4_Msk instead */ 560 #define AFEC_CHSR_CH5_Pos 5 /**< (AFEC_CHSR) Channel 5 Status Position */ 561 #define AFEC_CHSR_CH5_Msk (_U_(0x1) << AFEC_CHSR_CH5_Pos) /**< (AFEC_CHSR) Channel 5 Status Mask */ 562 #define AFEC_CHSR_CH5 AFEC_CHSR_CH5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH5_Msk instead */ 563 #define AFEC_CHSR_CH6_Pos 6 /**< (AFEC_CHSR) Channel 6 Status Position */ 564 #define AFEC_CHSR_CH6_Msk (_U_(0x1) << AFEC_CHSR_CH6_Pos) /**< (AFEC_CHSR) Channel 6 Status Mask */ 565 #define AFEC_CHSR_CH6 AFEC_CHSR_CH6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH6_Msk instead */ 566 #define AFEC_CHSR_CH7_Pos 7 /**< (AFEC_CHSR) Channel 7 Status Position */ 567 #define AFEC_CHSR_CH7_Msk (_U_(0x1) << AFEC_CHSR_CH7_Pos) /**< (AFEC_CHSR) Channel 7 Status Mask */ 568 #define AFEC_CHSR_CH7 AFEC_CHSR_CH7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH7_Msk instead */ 569 #define AFEC_CHSR_CH8_Pos 8 /**< (AFEC_CHSR) Channel 8 Status Position */ 570 #define AFEC_CHSR_CH8_Msk (_U_(0x1) << AFEC_CHSR_CH8_Pos) /**< (AFEC_CHSR) Channel 8 Status Mask */ 571 #define AFEC_CHSR_CH8 AFEC_CHSR_CH8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH8_Msk instead */ 572 #define AFEC_CHSR_CH9_Pos 9 /**< (AFEC_CHSR) Channel 9 Status Position */ 573 #define AFEC_CHSR_CH9_Msk (_U_(0x1) << AFEC_CHSR_CH9_Pos) /**< (AFEC_CHSR) Channel 9 Status Mask */ 574 #define AFEC_CHSR_CH9 AFEC_CHSR_CH9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH9_Msk instead */ 575 #define AFEC_CHSR_CH10_Pos 10 /**< (AFEC_CHSR) Channel 10 Status Position */ 576 #define AFEC_CHSR_CH10_Msk (_U_(0x1) << AFEC_CHSR_CH10_Pos) /**< (AFEC_CHSR) Channel 10 Status Mask */ 577 #define AFEC_CHSR_CH10 AFEC_CHSR_CH10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH10_Msk instead */ 578 #define AFEC_CHSR_CH11_Pos 11 /**< (AFEC_CHSR) Channel 11 Status Position */ 579 #define AFEC_CHSR_CH11_Msk (_U_(0x1) << AFEC_CHSR_CH11_Pos) /**< (AFEC_CHSR) Channel 11 Status Mask */ 580 #define AFEC_CHSR_CH11 AFEC_CHSR_CH11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CHSR_CH11_Msk instead */ 581 #define AFEC_CHSR_MASK _U_(0xFFF) /**< \deprecated (AFEC_CHSR) Register MASK (Use AFEC_CHSR_Msk instead) */ 582 #define AFEC_CHSR_Msk _U_(0xFFF) /**< (AFEC_CHSR) Register Mask */ 583 584 #define AFEC_CHSR_CH_Pos 0 /**< (AFEC_CHSR Position) Channel xx Status */ 585 #define AFEC_CHSR_CH_Msk (_U_(0xFFF) << AFEC_CHSR_CH_Pos) /**< (AFEC_CHSR Mask) CH */ 586 #define AFEC_CHSR_CH(value) (AFEC_CHSR_CH_Msk & ((value) << AFEC_CHSR_CH_Pos)) 587 588 /* -------- AFEC_LCDR : (AFEC Offset: 0x20) (R/ 32) AFEC Last Converted Data Register -------- */ 589 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 590 #if COMPONENT_TYPEDEF_STYLE == 'N' 591 typedef union { 592 struct { 593 uint32_t LDATA:16; /**< bit: 0..15 Last Data Converted */ 594 uint32_t :8; /**< bit: 16..23 Reserved */ 595 uint32_t CHNB:4; /**< bit: 24..27 Channel Number */ 596 uint32_t :4; /**< bit: 28..31 Reserved */ 597 } bit; /**< Structure used for bit access */ 598 uint32_t reg; /**< Type used for register access */ 599 } AFEC_LCDR_Type; 600 #endif 601 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 602 603 #define AFEC_LCDR_OFFSET (0x20) /**< (AFEC_LCDR) AFEC Last Converted Data Register Offset */ 604 605 #define AFEC_LCDR_LDATA_Pos 0 /**< (AFEC_LCDR) Last Data Converted Position */ 606 #define AFEC_LCDR_LDATA_Msk (_U_(0xFFFF) << AFEC_LCDR_LDATA_Pos) /**< (AFEC_LCDR) Last Data Converted Mask */ 607 #define AFEC_LCDR_LDATA(value) (AFEC_LCDR_LDATA_Msk & ((value) << AFEC_LCDR_LDATA_Pos)) 608 #define AFEC_LCDR_CHNB_Pos 24 /**< (AFEC_LCDR) Channel Number Position */ 609 #define AFEC_LCDR_CHNB_Msk (_U_(0xF) << AFEC_LCDR_CHNB_Pos) /**< (AFEC_LCDR) Channel Number Mask */ 610 #define AFEC_LCDR_CHNB(value) (AFEC_LCDR_CHNB_Msk & ((value) << AFEC_LCDR_CHNB_Pos)) 611 #define AFEC_LCDR_MASK _U_(0xF00FFFF) /**< \deprecated (AFEC_LCDR) Register MASK (Use AFEC_LCDR_Msk instead) */ 612 #define AFEC_LCDR_Msk _U_(0xF00FFFF) /**< (AFEC_LCDR) Register Mask */ 613 614 615 /* -------- AFEC_IER : (AFEC Offset: 0x24) (/W 32) AFEC Interrupt Enable Register -------- */ 616 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 617 #if COMPONENT_TYPEDEF_STYLE == 'N' 618 typedef union { 619 struct { 620 uint32_t EOC0:1; /**< bit: 0 End of Conversion Interrupt Enable 0 */ 621 uint32_t EOC1:1; /**< bit: 1 End of Conversion Interrupt Enable 1 */ 622 uint32_t EOC2:1; /**< bit: 2 End of Conversion Interrupt Enable 2 */ 623 uint32_t EOC3:1; /**< bit: 3 End of Conversion Interrupt Enable 3 */ 624 uint32_t EOC4:1; /**< bit: 4 End of Conversion Interrupt Enable 4 */ 625 uint32_t EOC5:1; /**< bit: 5 End of Conversion Interrupt Enable 5 */ 626 uint32_t EOC6:1; /**< bit: 6 End of Conversion Interrupt Enable 6 */ 627 uint32_t EOC7:1; /**< bit: 7 End of Conversion Interrupt Enable 7 */ 628 uint32_t EOC8:1; /**< bit: 8 End of Conversion Interrupt Enable 8 */ 629 uint32_t EOC9:1; /**< bit: 9 End of Conversion Interrupt Enable 9 */ 630 uint32_t EOC10:1; /**< bit: 10 End of Conversion Interrupt Enable 10 */ 631 uint32_t EOC11:1; /**< bit: 11 End of Conversion Interrupt Enable 11 */ 632 uint32_t :12; /**< bit: 12..23 Reserved */ 633 uint32_t DRDY:1; /**< bit: 24 Data Ready Interrupt Enable */ 634 uint32_t GOVRE:1; /**< bit: 25 General Overrun Error Interrupt Enable */ 635 uint32_t COMPE:1; /**< bit: 26 Comparison Event Interrupt Enable */ 636 uint32_t :3; /**< bit: 27..29 Reserved */ 637 uint32_t TEMPCHG:1; /**< bit: 30 Temperature Change Interrupt Enable */ 638 uint32_t :1; /**< bit: 31 Reserved */ 639 } bit; /**< Structure used for bit access */ 640 struct { 641 uint32_t EOC:12; /**< bit: 0..11 End of Conversion Interrupt Enable x */ 642 uint32_t :20; /**< bit: 12..31 Reserved */ 643 } vec; /**< Structure used for vec access */ 644 uint32_t reg; /**< Type used for register access */ 645 } AFEC_IER_Type; 646 #endif 647 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 648 649 #define AFEC_IER_OFFSET (0x24) /**< (AFEC_IER) AFEC Interrupt Enable Register Offset */ 650 651 #define AFEC_IER_EOC0_Pos 0 /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Position */ 652 #define AFEC_IER_EOC0_Msk (_U_(0x1) << AFEC_IER_EOC0_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 0 Mask */ 653 #define AFEC_IER_EOC0 AFEC_IER_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC0_Msk instead */ 654 #define AFEC_IER_EOC1_Pos 1 /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Position */ 655 #define AFEC_IER_EOC1_Msk (_U_(0x1) << AFEC_IER_EOC1_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 1 Mask */ 656 #define AFEC_IER_EOC1 AFEC_IER_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC1_Msk instead */ 657 #define AFEC_IER_EOC2_Pos 2 /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Position */ 658 #define AFEC_IER_EOC2_Msk (_U_(0x1) << AFEC_IER_EOC2_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 2 Mask */ 659 #define AFEC_IER_EOC2 AFEC_IER_EOC2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC2_Msk instead */ 660 #define AFEC_IER_EOC3_Pos 3 /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Position */ 661 #define AFEC_IER_EOC3_Msk (_U_(0x1) << AFEC_IER_EOC3_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 3 Mask */ 662 #define AFEC_IER_EOC3 AFEC_IER_EOC3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC3_Msk instead */ 663 #define AFEC_IER_EOC4_Pos 4 /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Position */ 664 #define AFEC_IER_EOC4_Msk (_U_(0x1) << AFEC_IER_EOC4_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 4 Mask */ 665 #define AFEC_IER_EOC4 AFEC_IER_EOC4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC4_Msk instead */ 666 #define AFEC_IER_EOC5_Pos 5 /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Position */ 667 #define AFEC_IER_EOC5_Msk (_U_(0x1) << AFEC_IER_EOC5_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 5 Mask */ 668 #define AFEC_IER_EOC5 AFEC_IER_EOC5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC5_Msk instead */ 669 #define AFEC_IER_EOC6_Pos 6 /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Position */ 670 #define AFEC_IER_EOC6_Msk (_U_(0x1) << AFEC_IER_EOC6_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 6 Mask */ 671 #define AFEC_IER_EOC6 AFEC_IER_EOC6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC6_Msk instead */ 672 #define AFEC_IER_EOC7_Pos 7 /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Position */ 673 #define AFEC_IER_EOC7_Msk (_U_(0x1) << AFEC_IER_EOC7_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 7 Mask */ 674 #define AFEC_IER_EOC7 AFEC_IER_EOC7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC7_Msk instead */ 675 #define AFEC_IER_EOC8_Pos 8 /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Position */ 676 #define AFEC_IER_EOC8_Msk (_U_(0x1) << AFEC_IER_EOC8_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 8 Mask */ 677 #define AFEC_IER_EOC8 AFEC_IER_EOC8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC8_Msk instead */ 678 #define AFEC_IER_EOC9_Pos 9 /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Position */ 679 #define AFEC_IER_EOC9_Msk (_U_(0x1) << AFEC_IER_EOC9_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 9 Mask */ 680 #define AFEC_IER_EOC9 AFEC_IER_EOC9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC9_Msk instead */ 681 #define AFEC_IER_EOC10_Pos 10 /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Position */ 682 #define AFEC_IER_EOC10_Msk (_U_(0x1) << AFEC_IER_EOC10_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 10 Mask */ 683 #define AFEC_IER_EOC10 AFEC_IER_EOC10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC10_Msk instead */ 684 #define AFEC_IER_EOC11_Pos 11 /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Position */ 685 #define AFEC_IER_EOC11_Msk (_U_(0x1) << AFEC_IER_EOC11_Pos) /**< (AFEC_IER) End of Conversion Interrupt Enable 11 Mask */ 686 #define AFEC_IER_EOC11 AFEC_IER_EOC11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_EOC11_Msk instead */ 687 #define AFEC_IER_DRDY_Pos 24 /**< (AFEC_IER) Data Ready Interrupt Enable Position */ 688 #define AFEC_IER_DRDY_Msk (_U_(0x1) << AFEC_IER_DRDY_Pos) /**< (AFEC_IER) Data Ready Interrupt Enable Mask */ 689 #define AFEC_IER_DRDY AFEC_IER_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_DRDY_Msk instead */ 690 #define AFEC_IER_GOVRE_Pos 25 /**< (AFEC_IER) General Overrun Error Interrupt Enable Position */ 691 #define AFEC_IER_GOVRE_Msk (_U_(0x1) << AFEC_IER_GOVRE_Pos) /**< (AFEC_IER) General Overrun Error Interrupt Enable Mask */ 692 #define AFEC_IER_GOVRE AFEC_IER_GOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_GOVRE_Msk instead */ 693 #define AFEC_IER_COMPE_Pos 26 /**< (AFEC_IER) Comparison Event Interrupt Enable Position */ 694 #define AFEC_IER_COMPE_Msk (_U_(0x1) << AFEC_IER_COMPE_Pos) /**< (AFEC_IER) Comparison Event Interrupt Enable Mask */ 695 #define AFEC_IER_COMPE AFEC_IER_COMPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_COMPE_Msk instead */ 696 #define AFEC_IER_TEMPCHG_Pos 30 /**< (AFEC_IER) Temperature Change Interrupt Enable Position */ 697 #define AFEC_IER_TEMPCHG_Msk (_U_(0x1) << AFEC_IER_TEMPCHG_Pos) /**< (AFEC_IER) Temperature Change Interrupt Enable Mask */ 698 #define AFEC_IER_TEMPCHG AFEC_IER_TEMPCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IER_TEMPCHG_Msk instead */ 699 #define AFEC_IER_MASK _U_(0x47000FFF) /**< \deprecated (AFEC_IER) Register MASK (Use AFEC_IER_Msk instead) */ 700 #define AFEC_IER_Msk _U_(0x47000FFF) /**< (AFEC_IER) Register Mask */ 701 702 #define AFEC_IER_EOC_Pos 0 /**< (AFEC_IER Position) End of Conversion Interrupt Enable x */ 703 #define AFEC_IER_EOC_Msk (_U_(0xFFF) << AFEC_IER_EOC_Pos) /**< (AFEC_IER Mask) EOC */ 704 #define AFEC_IER_EOC(value) (AFEC_IER_EOC_Msk & ((value) << AFEC_IER_EOC_Pos)) 705 706 /* -------- AFEC_IDR : (AFEC Offset: 0x28) (/W 32) AFEC Interrupt Disable Register -------- */ 707 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 708 #if COMPONENT_TYPEDEF_STYLE == 'N' 709 typedef union { 710 struct { 711 uint32_t EOC0:1; /**< bit: 0 End of Conversion Interrupt Disable 0 */ 712 uint32_t EOC1:1; /**< bit: 1 End of Conversion Interrupt Disable 1 */ 713 uint32_t EOC2:1; /**< bit: 2 End of Conversion Interrupt Disable 2 */ 714 uint32_t EOC3:1; /**< bit: 3 End of Conversion Interrupt Disable 3 */ 715 uint32_t EOC4:1; /**< bit: 4 End of Conversion Interrupt Disable 4 */ 716 uint32_t EOC5:1; /**< bit: 5 End of Conversion Interrupt Disable 5 */ 717 uint32_t EOC6:1; /**< bit: 6 End of Conversion Interrupt Disable 6 */ 718 uint32_t EOC7:1; /**< bit: 7 End of Conversion Interrupt Disable 7 */ 719 uint32_t EOC8:1; /**< bit: 8 End of Conversion Interrupt Disable 8 */ 720 uint32_t EOC9:1; /**< bit: 9 End of Conversion Interrupt Disable 9 */ 721 uint32_t EOC10:1; /**< bit: 10 End of Conversion Interrupt Disable 10 */ 722 uint32_t EOC11:1; /**< bit: 11 End of Conversion Interrupt Disable 11 */ 723 uint32_t :12; /**< bit: 12..23 Reserved */ 724 uint32_t DRDY:1; /**< bit: 24 Data Ready Interrupt Disable */ 725 uint32_t GOVRE:1; /**< bit: 25 General Overrun Error Interrupt Disable */ 726 uint32_t COMPE:1; /**< bit: 26 Comparison Event Interrupt Disable */ 727 uint32_t :3; /**< bit: 27..29 Reserved */ 728 uint32_t TEMPCHG:1; /**< bit: 30 Temperature Change Interrupt Disable */ 729 uint32_t :1; /**< bit: 31 Reserved */ 730 } bit; /**< Structure used for bit access */ 731 struct { 732 uint32_t EOC:12; /**< bit: 0..11 End of Conversion Interrupt Disable x */ 733 uint32_t :20; /**< bit: 12..31 Reserved */ 734 } vec; /**< Structure used for vec access */ 735 uint32_t reg; /**< Type used for register access */ 736 } AFEC_IDR_Type; 737 #endif 738 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 739 740 #define AFEC_IDR_OFFSET (0x28) /**< (AFEC_IDR) AFEC Interrupt Disable Register Offset */ 741 742 #define AFEC_IDR_EOC0_Pos 0 /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Position */ 743 #define AFEC_IDR_EOC0_Msk (_U_(0x1) << AFEC_IDR_EOC0_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 0 Mask */ 744 #define AFEC_IDR_EOC0 AFEC_IDR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC0_Msk instead */ 745 #define AFEC_IDR_EOC1_Pos 1 /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Position */ 746 #define AFEC_IDR_EOC1_Msk (_U_(0x1) << AFEC_IDR_EOC1_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 1 Mask */ 747 #define AFEC_IDR_EOC1 AFEC_IDR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC1_Msk instead */ 748 #define AFEC_IDR_EOC2_Pos 2 /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Position */ 749 #define AFEC_IDR_EOC2_Msk (_U_(0x1) << AFEC_IDR_EOC2_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 2 Mask */ 750 #define AFEC_IDR_EOC2 AFEC_IDR_EOC2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC2_Msk instead */ 751 #define AFEC_IDR_EOC3_Pos 3 /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Position */ 752 #define AFEC_IDR_EOC3_Msk (_U_(0x1) << AFEC_IDR_EOC3_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 3 Mask */ 753 #define AFEC_IDR_EOC3 AFEC_IDR_EOC3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC3_Msk instead */ 754 #define AFEC_IDR_EOC4_Pos 4 /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Position */ 755 #define AFEC_IDR_EOC4_Msk (_U_(0x1) << AFEC_IDR_EOC4_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 4 Mask */ 756 #define AFEC_IDR_EOC4 AFEC_IDR_EOC4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC4_Msk instead */ 757 #define AFEC_IDR_EOC5_Pos 5 /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Position */ 758 #define AFEC_IDR_EOC5_Msk (_U_(0x1) << AFEC_IDR_EOC5_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 5 Mask */ 759 #define AFEC_IDR_EOC5 AFEC_IDR_EOC5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC5_Msk instead */ 760 #define AFEC_IDR_EOC6_Pos 6 /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Position */ 761 #define AFEC_IDR_EOC6_Msk (_U_(0x1) << AFEC_IDR_EOC6_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 6 Mask */ 762 #define AFEC_IDR_EOC6 AFEC_IDR_EOC6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC6_Msk instead */ 763 #define AFEC_IDR_EOC7_Pos 7 /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Position */ 764 #define AFEC_IDR_EOC7_Msk (_U_(0x1) << AFEC_IDR_EOC7_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 7 Mask */ 765 #define AFEC_IDR_EOC7 AFEC_IDR_EOC7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC7_Msk instead */ 766 #define AFEC_IDR_EOC8_Pos 8 /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Position */ 767 #define AFEC_IDR_EOC8_Msk (_U_(0x1) << AFEC_IDR_EOC8_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 8 Mask */ 768 #define AFEC_IDR_EOC8 AFEC_IDR_EOC8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC8_Msk instead */ 769 #define AFEC_IDR_EOC9_Pos 9 /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Position */ 770 #define AFEC_IDR_EOC9_Msk (_U_(0x1) << AFEC_IDR_EOC9_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 9 Mask */ 771 #define AFEC_IDR_EOC9 AFEC_IDR_EOC9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC9_Msk instead */ 772 #define AFEC_IDR_EOC10_Pos 10 /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Position */ 773 #define AFEC_IDR_EOC10_Msk (_U_(0x1) << AFEC_IDR_EOC10_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 10 Mask */ 774 #define AFEC_IDR_EOC10 AFEC_IDR_EOC10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC10_Msk instead */ 775 #define AFEC_IDR_EOC11_Pos 11 /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Position */ 776 #define AFEC_IDR_EOC11_Msk (_U_(0x1) << AFEC_IDR_EOC11_Pos) /**< (AFEC_IDR) End of Conversion Interrupt Disable 11 Mask */ 777 #define AFEC_IDR_EOC11 AFEC_IDR_EOC11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_EOC11_Msk instead */ 778 #define AFEC_IDR_DRDY_Pos 24 /**< (AFEC_IDR) Data Ready Interrupt Disable Position */ 779 #define AFEC_IDR_DRDY_Msk (_U_(0x1) << AFEC_IDR_DRDY_Pos) /**< (AFEC_IDR) Data Ready Interrupt Disable Mask */ 780 #define AFEC_IDR_DRDY AFEC_IDR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_DRDY_Msk instead */ 781 #define AFEC_IDR_GOVRE_Pos 25 /**< (AFEC_IDR) General Overrun Error Interrupt Disable Position */ 782 #define AFEC_IDR_GOVRE_Msk (_U_(0x1) << AFEC_IDR_GOVRE_Pos) /**< (AFEC_IDR) General Overrun Error Interrupt Disable Mask */ 783 #define AFEC_IDR_GOVRE AFEC_IDR_GOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_GOVRE_Msk instead */ 784 #define AFEC_IDR_COMPE_Pos 26 /**< (AFEC_IDR) Comparison Event Interrupt Disable Position */ 785 #define AFEC_IDR_COMPE_Msk (_U_(0x1) << AFEC_IDR_COMPE_Pos) /**< (AFEC_IDR) Comparison Event Interrupt Disable Mask */ 786 #define AFEC_IDR_COMPE AFEC_IDR_COMPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_COMPE_Msk instead */ 787 #define AFEC_IDR_TEMPCHG_Pos 30 /**< (AFEC_IDR) Temperature Change Interrupt Disable Position */ 788 #define AFEC_IDR_TEMPCHG_Msk (_U_(0x1) << AFEC_IDR_TEMPCHG_Pos) /**< (AFEC_IDR) Temperature Change Interrupt Disable Mask */ 789 #define AFEC_IDR_TEMPCHG AFEC_IDR_TEMPCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IDR_TEMPCHG_Msk instead */ 790 #define AFEC_IDR_MASK _U_(0x47000FFF) /**< \deprecated (AFEC_IDR) Register MASK (Use AFEC_IDR_Msk instead) */ 791 #define AFEC_IDR_Msk _U_(0x47000FFF) /**< (AFEC_IDR) Register Mask */ 792 793 #define AFEC_IDR_EOC_Pos 0 /**< (AFEC_IDR Position) End of Conversion Interrupt Disable x */ 794 #define AFEC_IDR_EOC_Msk (_U_(0xFFF) << AFEC_IDR_EOC_Pos) /**< (AFEC_IDR Mask) EOC */ 795 #define AFEC_IDR_EOC(value) (AFEC_IDR_EOC_Msk & ((value) << AFEC_IDR_EOC_Pos)) 796 797 /* -------- AFEC_IMR : (AFEC Offset: 0x2c) (R/ 32) AFEC Interrupt Mask Register -------- */ 798 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 799 #if COMPONENT_TYPEDEF_STYLE == 'N' 800 typedef union { 801 struct { 802 uint32_t EOC0:1; /**< bit: 0 End of Conversion Interrupt Mask 0 */ 803 uint32_t EOC1:1; /**< bit: 1 End of Conversion Interrupt Mask 1 */ 804 uint32_t EOC2:1; /**< bit: 2 End of Conversion Interrupt Mask 2 */ 805 uint32_t EOC3:1; /**< bit: 3 End of Conversion Interrupt Mask 3 */ 806 uint32_t EOC4:1; /**< bit: 4 End of Conversion Interrupt Mask 4 */ 807 uint32_t EOC5:1; /**< bit: 5 End of Conversion Interrupt Mask 5 */ 808 uint32_t EOC6:1; /**< bit: 6 End of Conversion Interrupt Mask 6 */ 809 uint32_t EOC7:1; /**< bit: 7 End of Conversion Interrupt Mask 7 */ 810 uint32_t EOC8:1; /**< bit: 8 End of Conversion Interrupt Mask 8 */ 811 uint32_t EOC9:1; /**< bit: 9 End of Conversion Interrupt Mask 9 */ 812 uint32_t EOC10:1; /**< bit: 10 End of Conversion Interrupt Mask 10 */ 813 uint32_t EOC11:1; /**< bit: 11 End of Conversion Interrupt Mask 11 */ 814 uint32_t :12; /**< bit: 12..23 Reserved */ 815 uint32_t DRDY:1; /**< bit: 24 Data Ready Interrupt Mask */ 816 uint32_t GOVRE:1; /**< bit: 25 General Overrun Error Interrupt Mask */ 817 uint32_t COMPE:1; /**< bit: 26 Comparison Event Interrupt Mask */ 818 uint32_t :3; /**< bit: 27..29 Reserved */ 819 uint32_t TEMPCHG:1; /**< bit: 30 Temperature Change Interrupt Mask */ 820 uint32_t :1; /**< bit: 31 Reserved */ 821 } bit; /**< Structure used for bit access */ 822 struct { 823 uint32_t EOC:12; /**< bit: 0..11 End of Conversion Interrupt Mask x */ 824 uint32_t :20; /**< bit: 12..31 Reserved */ 825 } vec; /**< Structure used for vec access */ 826 uint32_t reg; /**< Type used for register access */ 827 } AFEC_IMR_Type; 828 #endif 829 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 830 831 #define AFEC_IMR_OFFSET (0x2C) /**< (AFEC_IMR) AFEC Interrupt Mask Register Offset */ 832 833 #define AFEC_IMR_EOC0_Pos 0 /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Position */ 834 #define AFEC_IMR_EOC0_Msk (_U_(0x1) << AFEC_IMR_EOC0_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 0 Mask */ 835 #define AFEC_IMR_EOC0 AFEC_IMR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC0_Msk instead */ 836 #define AFEC_IMR_EOC1_Pos 1 /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Position */ 837 #define AFEC_IMR_EOC1_Msk (_U_(0x1) << AFEC_IMR_EOC1_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 1 Mask */ 838 #define AFEC_IMR_EOC1 AFEC_IMR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC1_Msk instead */ 839 #define AFEC_IMR_EOC2_Pos 2 /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Position */ 840 #define AFEC_IMR_EOC2_Msk (_U_(0x1) << AFEC_IMR_EOC2_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 2 Mask */ 841 #define AFEC_IMR_EOC2 AFEC_IMR_EOC2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC2_Msk instead */ 842 #define AFEC_IMR_EOC3_Pos 3 /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Position */ 843 #define AFEC_IMR_EOC3_Msk (_U_(0x1) << AFEC_IMR_EOC3_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 3 Mask */ 844 #define AFEC_IMR_EOC3 AFEC_IMR_EOC3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC3_Msk instead */ 845 #define AFEC_IMR_EOC4_Pos 4 /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Position */ 846 #define AFEC_IMR_EOC4_Msk (_U_(0x1) << AFEC_IMR_EOC4_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 4 Mask */ 847 #define AFEC_IMR_EOC4 AFEC_IMR_EOC4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC4_Msk instead */ 848 #define AFEC_IMR_EOC5_Pos 5 /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Position */ 849 #define AFEC_IMR_EOC5_Msk (_U_(0x1) << AFEC_IMR_EOC5_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 5 Mask */ 850 #define AFEC_IMR_EOC5 AFEC_IMR_EOC5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC5_Msk instead */ 851 #define AFEC_IMR_EOC6_Pos 6 /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Position */ 852 #define AFEC_IMR_EOC6_Msk (_U_(0x1) << AFEC_IMR_EOC6_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 6 Mask */ 853 #define AFEC_IMR_EOC6 AFEC_IMR_EOC6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC6_Msk instead */ 854 #define AFEC_IMR_EOC7_Pos 7 /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Position */ 855 #define AFEC_IMR_EOC7_Msk (_U_(0x1) << AFEC_IMR_EOC7_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 7 Mask */ 856 #define AFEC_IMR_EOC7 AFEC_IMR_EOC7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC7_Msk instead */ 857 #define AFEC_IMR_EOC8_Pos 8 /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Position */ 858 #define AFEC_IMR_EOC8_Msk (_U_(0x1) << AFEC_IMR_EOC8_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 8 Mask */ 859 #define AFEC_IMR_EOC8 AFEC_IMR_EOC8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC8_Msk instead */ 860 #define AFEC_IMR_EOC9_Pos 9 /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Position */ 861 #define AFEC_IMR_EOC9_Msk (_U_(0x1) << AFEC_IMR_EOC9_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 9 Mask */ 862 #define AFEC_IMR_EOC9 AFEC_IMR_EOC9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC9_Msk instead */ 863 #define AFEC_IMR_EOC10_Pos 10 /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Position */ 864 #define AFEC_IMR_EOC10_Msk (_U_(0x1) << AFEC_IMR_EOC10_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 10 Mask */ 865 #define AFEC_IMR_EOC10 AFEC_IMR_EOC10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC10_Msk instead */ 866 #define AFEC_IMR_EOC11_Pos 11 /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Position */ 867 #define AFEC_IMR_EOC11_Msk (_U_(0x1) << AFEC_IMR_EOC11_Pos) /**< (AFEC_IMR) End of Conversion Interrupt Mask 11 Mask */ 868 #define AFEC_IMR_EOC11 AFEC_IMR_EOC11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_EOC11_Msk instead */ 869 #define AFEC_IMR_DRDY_Pos 24 /**< (AFEC_IMR) Data Ready Interrupt Mask Position */ 870 #define AFEC_IMR_DRDY_Msk (_U_(0x1) << AFEC_IMR_DRDY_Pos) /**< (AFEC_IMR) Data Ready Interrupt Mask Mask */ 871 #define AFEC_IMR_DRDY AFEC_IMR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_DRDY_Msk instead */ 872 #define AFEC_IMR_GOVRE_Pos 25 /**< (AFEC_IMR) General Overrun Error Interrupt Mask Position */ 873 #define AFEC_IMR_GOVRE_Msk (_U_(0x1) << AFEC_IMR_GOVRE_Pos) /**< (AFEC_IMR) General Overrun Error Interrupt Mask Mask */ 874 #define AFEC_IMR_GOVRE AFEC_IMR_GOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_GOVRE_Msk instead */ 875 #define AFEC_IMR_COMPE_Pos 26 /**< (AFEC_IMR) Comparison Event Interrupt Mask Position */ 876 #define AFEC_IMR_COMPE_Msk (_U_(0x1) << AFEC_IMR_COMPE_Pos) /**< (AFEC_IMR) Comparison Event Interrupt Mask Mask */ 877 #define AFEC_IMR_COMPE AFEC_IMR_COMPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_COMPE_Msk instead */ 878 #define AFEC_IMR_TEMPCHG_Pos 30 /**< (AFEC_IMR) Temperature Change Interrupt Mask Position */ 879 #define AFEC_IMR_TEMPCHG_Msk (_U_(0x1) << AFEC_IMR_TEMPCHG_Pos) /**< (AFEC_IMR) Temperature Change Interrupt Mask Mask */ 880 #define AFEC_IMR_TEMPCHG AFEC_IMR_TEMPCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_IMR_TEMPCHG_Msk instead */ 881 #define AFEC_IMR_MASK _U_(0x47000FFF) /**< \deprecated (AFEC_IMR) Register MASK (Use AFEC_IMR_Msk instead) */ 882 #define AFEC_IMR_Msk _U_(0x47000FFF) /**< (AFEC_IMR) Register Mask */ 883 884 #define AFEC_IMR_EOC_Pos 0 /**< (AFEC_IMR Position) End of Conversion Interrupt Mask x */ 885 #define AFEC_IMR_EOC_Msk (_U_(0xFFF) << AFEC_IMR_EOC_Pos) /**< (AFEC_IMR Mask) EOC */ 886 #define AFEC_IMR_EOC(value) (AFEC_IMR_EOC_Msk & ((value) << AFEC_IMR_EOC_Pos)) 887 888 /* -------- AFEC_ISR : (AFEC Offset: 0x30) (R/ 32) AFEC Interrupt Status Register -------- */ 889 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 890 #if COMPONENT_TYPEDEF_STYLE == 'N' 891 typedef union { 892 struct { 893 uint32_t EOC0:1; /**< bit: 0 End of Conversion 0 (cleared by reading AFEC_CDRx) */ 894 uint32_t EOC1:1; /**< bit: 1 End of Conversion 1 (cleared by reading AFEC_CDRx) */ 895 uint32_t EOC2:1; /**< bit: 2 End of Conversion 2 (cleared by reading AFEC_CDRx) */ 896 uint32_t EOC3:1; /**< bit: 3 End of Conversion 3 (cleared by reading AFEC_CDRx) */ 897 uint32_t EOC4:1; /**< bit: 4 End of Conversion 4 (cleared by reading AFEC_CDRx) */ 898 uint32_t EOC5:1; /**< bit: 5 End of Conversion 5 (cleared by reading AFEC_CDRx) */ 899 uint32_t EOC6:1; /**< bit: 6 End of Conversion 6 (cleared by reading AFEC_CDRx) */ 900 uint32_t EOC7:1; /**< bit: 7 End of Conversion 7 (cleared by reading AFEC_CDRx) */ 901 uint32_t EOC8:1; /**< bit: 8 End of Conversion 8 (cleared by reading AFEC_CDRx) */ 902 uint32_t EOC9:1; /**< bit: 9 End of Conversion 9 (cleared by reading AFEC_CDRx) */ 903 uint32_t EOC10:1; /**< bit: 10 End of Conversion 10 (cleared by reading AFEC_CDRx) */ 904 uint32_t EOC11:1; /**< bit: 11 End of Conversion 11 (cleared by reading AFEC_CDRx) */ 905 uint32_t :12; /**< bit: 12..23 Reserved */ 906 uint32_t DRDY:1; /**< bit: 24 Data Ready (cleared by reading AFEC_LCDR) */ 907 uint32_t GOVRE:1; /**< bit: 25 General Overrun Error (cleared by reading AFEC_ISR) */ 908 uint32_t COMPE:1; /**< bit: 26 Comparison Error (cleared by reading AFEC_ISR) */ 909 uint32_t :3; /**< bit: 27..29 Reserved */ 910 uint32_t TEMPCHG:1; /**< bit: 30 Temperature Change (cleared on read) */ 911 uint32_t :1; /**< bit: 31 Reserved */ 912 } bit; /**< Structure used for bit access */ 913 struct { 914 uint32_t EOC:12; /**< bit: 0..11 End of Conversion x (cleared by reading AFEC_CDRx) */ 915 uint32_t :20; /**< bit: 12..31 Reserved */ 916 } vec; /**< Structure used for vec access */ 917 uint32_t reg; /**< Type used for register access */ 918 } AFEC_ISR_Type; 919 #endif 920 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 921 922 #define AFEC_ISR_OFFSET (0x30) /**< (AFEC_ISR) AFEC Interrupt Status Register Offset */ 923 924 #define AFEC_ISR_EOC0_Pos 0 /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Position */ 925 #define AFEC_ISR_EOC0_Msk (_U_(0x1) << AFEC_ISR_EOC0_Pos) /**< (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) Mask */ 926 #define AFEC_ISR_EOC0 AFEC_ISR_EOC0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC0_Msk instead */ 927 #define AFEC_ISR_EOC1_Pos 1 /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Position */ 928 #define AFEC_ISR_EOC1_Msk (_U_(0x1) << AFEC_ISR_EOC1_Pos) /**< (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) Mask */ 929 #define AFEC_ISR_EOC1 AFEC_ISR_EOC1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC1_Msk instead */ 930 #define AFEC_ISR_EOC2_Pos 2 /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Position */ 931 #define AFEC_ISR_EOC2_Msk (_U_(0x1) << AFEC_ISR_EOC2_Pos) /**< (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) Mask */ 932 #define AFEC_ISR_EOC2 AFEC_ISR_EOC2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC2_Msk instead */ 933 #define AFEC_ISR_EOC3_Pos 3 /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Position */ 934 #define AFEC_ISR_EOC3_Msk (_U_(0x1) << AFEC_ISR_EOC3_Pos) /**< (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) Mask */ 935 #define AFEC_ISR_EOC3 AFEC_ISR_EOC3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC3_Msk instead */ 936 #define AFEC_ISR_EOC4_Pos 4 /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Position */ 937 #define AFEC_ISR_EOC4_Msk (_U_(0x1) << AFEC_ISR_EOC4_Pos) /**< (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) Mask */ 938 #define AFEC_ISR_EOC4 AFEC_ISR_EOC4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC4_Msk instead */ 939 #define AFEC_ISR_EOC5_Pos 5 /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Position */ 940 #define AFEC_ISR_EOC5_Msk (_U_(0x1) << AFEC_ISR_EOC5_Pos) /**< (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) Mask */ 941 #define AFEC_ISR_EOC5 AFEC_ISR_EOC5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC5_Msk instead */ 942 #define AFEC_ISR_EOC6_Pos 6 /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Position */ 943 #define AFEC_ISR_EOC6_Msk (_U_(0x1) << AFEC_ISR_EOC6_Pos) /**< (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) Mask */ 944 #define AFEC_ISR_EOC6 AFEC_ISR_EOC6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC6_Msk instead */ 945 #define AFEC_ISR_EOC7_Pos 7 /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Position */ 946 #define AFEC_ISR_EOC7_Msk (_U_(0x1) << AFEC_ISR_EOC7_Pos) /**< (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) Mask */ 947 #define AFEC_ISR_EOC7 AFEC_ISR_EOC7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC7_Msk instead */ 948 #define AFEC_ISR_EOC8_Pos 8 /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Position */ 949 #define AFEC_ISR_EOC8_Msk (_U_(0x1) << AFEC_ISR_EOC8_Pos) /**< (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) Mask */ 950 #define AFEC_ISR_EOC8 AFEC_ISR_EOC8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC8_Msk instead */ 951 #define AFEC_ISR_EOC9_Pos 9 /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Position */ 952 #define AFEC_ISR_EOC9_Msk (_U_(0x1) << AFEC_ISR_EOC9_Pos) /**< (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) Mask */ 953 #define AFEC_ISR_EOC9 AFEC_ISR_EOC9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC9_Msk instead */ 954 #define AFEC_ISR_EOC10_Pos 10 /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Position */ 955 #define AFEC_ISR_EOC10_Msk (_U_(0x1) << AFEC_ISR_EOC10_Pos) /**< (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) Mask */ 956 #define AFEC_ISR_EOC10 AFEC_ISR_EOC10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC10_Msk instead */ 957 #define AFEC_ISR_EOC11_Pos 11 /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Position */ 958 #define AFEC_ISR_EOC11_Msk (_U_(0x1) << AFEC_ISR_EOC11_Pos) /**< (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) Mask */ 959 #define AFEC_ISR_EOC11 AFEC_ISR_EOC11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_EOC11_Msk instead */ 960 #define AFEC_ISR_DRDY_Pos 24 /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Position */ 961 #define AFEC_ISR_DRDY_Msk (_U_(0x1) << AFEC_ISR_DRDY_Pos) /**< (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) Mask */ 962 #define AFEC_ISR_DRDY AFEC_ISR_DRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_DRDY_Msk instead */ 963 #define AFEC_ISR_GOVRE_Pos 25 /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Position */ 964 #define AFEC_ISR_GOVRE_Msk (_U_(0x1) << AFEC_ISR_GOVRE_Pos) /**< (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) Mask */ 965 #define AFEC_ISR_GOVRE AFEC_ISR_GOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_GOVRE_Msk instead */ 966 #define AFEC_ISR_COMPE_Pos 26 /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Position */ 967 #define AFEC_ISR_COMPE_Msk (_U_(0x1) << AFEC_ISR_COMPE_Pos) /**< (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) Mask */ 968 #define AFEC_ISR_COMPE AFEC_ISR_COMPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_COMPE_Msk instead */ 969 #define AFEC_ISR_TEMPCHG_Pos 30 /**< (AFEC_ISR) Temperature Change (cleared on read) Position */ 970 #define AFEC_ISR_TEMPCHG_Msk (_U_(0x1) << AFEC_ISR_TEMPCHG_Pos) /**< (AFEC_ISR) Temperature Change (cleared on read) Mask */ 971 #define AFEC_ISR_TEMPCHG AFEC_ISR_TEMPCHG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ISR_TEMPCHG_Msk instead */ 972 #define AFEC_ISR_MASK _U_(0x47000FFF) /**< \deprecated (AFEC_ISR) Register MASK (Use AFEC_ISR_Msk instead) */ 973 #define AFEC_ISR_Msk _U_(0x47000FFF) /**< (AFEC_ISR) Register Mask */ 974 975 #define AFEC_ISR_EOC_Pos 0 /**< (AFEC_ISR Position) End of Conversion x (cleared by reading AFEC_CDRx) */ 976 #define AFEC_ISR_EOC_Msk (_U_(0xFFF) << AFEC_ISR_EOC_Pos) /**< (AFEC_ISR Mask) EOC */ 977 #define AFEC_ISR_EOC(value) (AFEC_ISR_EOC_Msk & ((value) << AFEC_ISR_EOC_Pos)) 978 979 /* -------- AFEC_OVER : (AFEC Offset: 0x4c) (R/ 32) AFEC Overrun Status Register -------- */ 980 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 981 #if COMPONENT_TYPEDEF_STYLE == 'N' 982 typedef union { 983 struct { 984 uint32_t OVRE0:1; /**< bit: 0 Overrun Error 0 */ 985 uint32_t OVRE1:1; /**< bit: 1 Overrun Error 1 */ 986 uint32_t OVRE2:1; /**< bit: 2 Overrun Error 2 */ 987 uint32_t OVRE3:1; /**< bit: 3 Overrun Error 3 */ 988 uint32_t OVRE4:1; /**< bit: 4 Overrun Error 4 */ 989 uint32_t OVRE5:1; /**< bit: 5 Overrun Error 5 */ 990 uint32_t OVRE6:1; /**< bit: 6 Overrun Error 6 */ 991 uint32_t OVRE7:1; /**< bit: 7 Overrun Error 7 */ 992 uint32_t OVRE8:1; /**< bit: 8 Overrun Error 8 */ 993 uint32_t OVRE9:1; /**< bit: 9 Overrun Error 9 */ 994 uint32_t OVRE10:1; /**< bit: 10 Overrun Error 10 */ 995 uint32_t OVRE11:1; /**< bit: 11 Overrun Error 11 */ 996 uint32_t :20; /**< bit: 12..31 Reserved */ 997 } bit; /**< Structure used for bit access */ 998 struct { 999 uint32_t OVRE:12; /**< bit: 0..11 Overrun Error xx */ 1000 uint32_t :20; /**< bit: 12..31 Reserved */ 1001 } vec; /**< Structure used for vec access */ 1002 uint32_t reg; /**< Type used for register access */ 1003 } AFEC_OVER_Type; 1004 #endif 1005 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1006 1007 #define AFEC_OVER_OFFSET (0x4C) /**< (AFEC_OVER) AFEC Overrun Status Register Offset */ 1008 1009 #define AFEC_OVER_OVRE0_Pos 0 /**< (AFEC_OVER) Overrun Error 0 Position */ 1010 #define AFEC_OVER_OVRE0_Msk (_U_(0x1) << AFEC_OVER_OVRE0_Pos) /**< (AFEC_OVER) Overrun Error 0 Mask */ 1011 #define AFEC_OVER_OVRE0 AFEC_OVER_OVRE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE0_Msk instead */ 1012 #define AFEC_OVER_OVRE1_Pos 1 /**< (AFEC_OVER) Overrun Error 1 Position */ 1013 #define AFEC_OVER_OVRE1_Msk (_U_(0x1) << AFEC_OVER_OVRE1_Pos) /**< (AFEC_OVER) Overrun Error 1 Mask */ 1014 #define AFEC_OVER_OVRE1 AFEC_OVER_OVRE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE1_Msk instead */ 1015 #define AFEC_OVER_OVRE2_Pos 2 /**< (AFEC_OVER) Overrun Error 2 Position */ 1016 #define AFEC_OVER_OVRE2_Msk (_U_(0x1) << AFEC_OVER_OVRE2_Pos) /**< (AFEC_OVER) Overrun Error 2 Mask */ 1017 #define AFEC_OVER_OVRE2 AFEC_OVER_OVRE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE2_Msk instead */ 1018 #define AFEC_OVER_OVRE3_Pos 3 /**< (AFEC_OVER) Overrun Error 3 Position */ 1019 #define AFEC_OVER_OVRE3_Msk (_U_(0x1) << AFEC_OVER_OVRE3_Pos) /**< (AFEC_OVER) Overrun Error 3 Mask */ 1020 #define AFEC_OVER_OVRE3 AFEC_OVER_OVRE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE3_Msk instead */ 1021 #define AFEC_OVER_OVRE4_Pos 4 /**< (AFEC_OVER) Overrun Error 4 Position */ 1022 #define AFEC_OVER_OVRE4_Msk (_U_(0x1) << AFEC_OVER_OVRE4_Pos) /**< (AFEC_OVER) Overrun Error 4 Mask */ 1023 #define AFEC_OVER_OVRE4 AFEC_OVER_OVRE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE4_Msk instead */ 1024 #define AFEC_OVER_OVRE5_Pos 5 /**< (AFEC_OVER) Overrun Error 5 Position */ 1025 #define AFEC_OVER_OVRE5_Msk (_U_(0x1) << AFEC_OVER_OVRE5_Pos) /**< (AFEC_OVER) Overrun Error 5 Mask */ 1026 #define AFEC_OVER_OVRE5 AFEC_OVER_OVRE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE5_Msk instead */ 1027 #define AFEC_OVER_OVRE6_Pos 6 /**< (AFEC_OVER) Overrun Error 6 Position */ 1028 #define AFEC_OVER_OVRE6_Msk (_U_(0x1) << AFEC_OVER_OVRE6_Pos) /**< (AFEC_OVER) Overrun Error 6 Mask */ 1029 #define AFEC_OVER_OVRE6 AFEC_OVER_OVRE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE6_Msk instead */ 1030 #define AFEC_OVER_OVRE7_Pos 7 /**< (AFEC_OVER) Overrun Error 7 Position */ 1031 #define AFEC_OVER_OVRE7_Msk (_U_(0x1) << AFEC_OVER_OVRE7_Pos) /**< (AFEC_OVER) Overrun Error 7 Mask */ 1032 #define AFEC_OVER_OVRE7 AFEC_OVER_OVRE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE7_Msk instead */ 1033 #define AFEC_OVER_OVRE8_Pos 8 /**< (AFEC_OVER) Overrun Error 8 Position */ 1034 #define AFEC_OVER_OVRE8_Msk (_U_(0x1) << AFEC_OVER_OVRE8_Pos) /**< (AFEC_OVER) Overrun Error 8 Mask */ 1035 #define AFEC_OVER_OVRE8 AFEC_OVER_OVRE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE8_Msk instead */ 1036 #define AFEC_OVER_OVRE9_Pos 9 /**< (AFEC_OVER) Overrun Error 9 Position */ 1037 #define AFEC_OVER_OVRE9_Msk (_U_(0x1) << AFEC_OVER_OVRE9_Pos) /**< (AFEC_OVER) Overrun Error 9 Mask */ 1038 #define AFEC_OVER_OVRE9 AFEC_OVER_OVRE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE9_Msk instead */ 1039 #define AFEC_OVER_OVRE10_Pos 10 /**< (AFEC_OVER) Overrun Error 10 Position */ 1040 #define AFEC_OVER_OVRE10_Msk (_U_(0x1) << AFEC_OVER_OVRE10_Pos) /**< (AFEC_OVER) Overrun Error 10 Mask */ 1041 #define AFEC_OVER_OVRE10 AFEC_OVER_OVRE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE10_Msk instead */ 1042 #define AFEC_OVER_OVRE11_Pos 11 /**< (AFEC_OVER) Overrun Error 11 Position */ 1043 #define AFEC_OVER_OVRE11_Msk (_U_(0x1) << AFEC_OVER_OVRE11_Pos) /**< (AFEC_OVER) Overrun Error 11 Mask */ 1044 #define AFEC_OVER_OVRE11 AFEC_OVER_OVRE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_OVER_OVRE11_Msk instead */ 1045 #define AFEC_OVER_MASK _U_(0xFFF) /**< \deprecated (AFEC_OVER) Register MASK (Use AFEC_OVER_Msk instead) */ 1046 #define AFEC_OVER_Msk _U_(0xFFF) /**< (AFEC_OVER) Register Mask */ 1047 1048 #define AFEC_OVER_OVRE_Pos 0 /**< (AFEC_OVER Position) Overrun Error xx */ 1049 #define AFEC_OVER_OVRE_Msk (_U_(0xFFF) << AFEC_OVER_OVRE_Pos) /**< (AFEC_OVER Mask) OVRE */ 1050 #define AFEC_OVER_OVRE(value) (AFEC_OVER_OVRE_Msk & ((value) << AFEC_OVER_OVRE_Pos)) 1051 1052 /* -------- AFEC_CWR : (AFEC Offset: 0x50) (R/W 32) AFEC Compare Window Register -------- */ 1053 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1054 #if COMPONENT_TYPEDEF_STYLE == 'N' 1055 typedef union { 1056 struct { 1057 uint32_t LOWTHRES:16; /**< bit: 0..15 Low Threshold */ 1058 uint32_t HIGHTHRES:16; /**< bit: 16..31 High Threshold */ 1059 } bit; /**< Structure used for bit access */ 1060 uint32_t reg; /**< Type used for register access */ 1061 } AFEC_CWR_Type; 1062 #endif 1063 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1064 1065 #define AFEC_CWR_OFFSET (0x50) /**< (AFEC_CWR) AFEC Compare Window Register Offset */ 1066 1067 #define AFEC_CWR_LOWTHRES_Pos 0 /**< (AFEC_CWR) Low Threshold Position */ 1068 #define AFEC_CWR_LOWTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_LOWTHRES_Pos) /**< (AFEC_CWR) Low Threshold Mask */ 1069 #define AFEC_CWR_LOWTHRES(value) (AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos)) 1070 #define AFEC_CWR_HIGHTHRES_Pos 16 /**< (AFEC_CWR) High Threshold Position */ 1071 #define AFEC_CWR_HIGHTHRES_Msk (_U_(0xFFFF) << AFEC_CWR_HIGHTHRES_Pos) /**< (AFEC_CWR) High Threshold Mask */ 1072 #define AFEC_CWR_HIGHTHRES(value) (AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos)) 1073 #define AFEC_CWR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AFEC_CWR) Register MASK (Use AFEC_CWR_Msk instead) */ 1074 #define AFEC_CWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CWR) Register Mask */ 1075 1076 1077 /* -------- AFEC_CGR : (AFEC Offset: 0x54) (R/W 32) AFEC Channel Gain Register -------- */ 1078 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1079 #if COMPONENT_TYPEDEF_STYLE == 'N' 1080 typedef union { 1081 struct { 1082 uint32_t GAIN0:2; /**< bit: 0..1 Gain for Channel 0 */ 1083 uint32_t GAIN1:2; /**< bit: 2..3 Gain for Channel 1 */ 1084 uint32_t GAIN2:2; /**< bit: 4..5 Gain for Channel 2 */ 1085 uint32_t GAIN3:2; /**< bit: 6..7 Gain for Channel 3 */ 1086 uint32_t GAIN4:2; /**< bit: 8..9 Gain for Channel 4 */ 1087 uint32_t GAIN5:2; /**< bit: 10..11 Gain for Channel 5 */ 1088 uint32_t GAIN6:2; /**< bit: 12..13 Gain for Channel 6 */ 1089 uint32_t GAIN7:2; /**< bit: 14..15 Gain for Channel 7 */ 1090 uint32_t GAIN8:2; /**< bit: 16..17 Gain for Channel 8 */ 1091 uint32_t GAIN9:2; /**< bit: 18..19 Gain for Channel 9 */ 1092 uint32_t GAIN10:2; /**< bit: 20..21 Gain for Channel 10 */ 1093 uint32_t GAIN11:2; /**< bit: 22..23 Gain for Channel 11 */ 1094 uint32_t :8; /**< bit: 24..31 Reserved */ 1095 } bit; /**< Structure used for bit access */ 1096 uint32_t reg; /**< Type used for register access */ 1097 } AFEC_CGR_Type; 1098 #endif 1099 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1100 1101 #define AFEC_CGR_OFFSET (0x54) /**< (AFEC_CGR) AFEC Channel Gain Register Offset */ 1102 1103 #define AFEC_CGR_GAIN0_Pos 0 /**< (AFEC_CGR) Gain for Channel 0 Position */ 1104 #define AFEC_CGR_GAIN0_Msk (_U_(0x3) << AFEC_CGR_GAIN0_Pos) /**< (AFEC_CGR) Gain for Channel 0 Mask */ 1105 #define AFEC_CGR_GAIN0(value) (AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos)) 1106 #define AFEC_CGR_GAIN1_Pos 2 /**< (AFEC_CGR) Gain for Channel 1 Position */ 1107 #define AFEC_CGR_GAIN1_Msk (_U_(0x3) << AFEC_CGR_GAIN1_Pos) /**< (AFEC_CGR) Gain for Channel 1 Mask */ 1108 #define AFEC_CGR_GAIN1(value) (AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos)) 1109 #define AFEC_CGR_GAIN2_Pos 4 /**< (AFEC_CGR) Gain for Channel 2 Position */ 1110 #define AFEC_CGR_GAIN2_Msk (_U_(0x3) << AFEC_CGR_GAIN2_Pos) /**< (AFEC_CGR) Gain for Channel 2 Mask */ 1111 #define AFEC_CGR_GAIN2(value) (AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos)) 1112 #define AFEC_CGR_GAIN3_Pos 6 /**< (AFEC_CGR) Gain for Channel 3 Position */ 1113 #define AFEC_CGR_GAIN3_Msk (_U_(0x3) << AFEC_CGR_GAIN3_Pos) /**< (AFEC_CGR) Gain for Channel 3 Mask */ 1114 #define AFEC_CGR_GAIN3(value) (AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos)) 1115 #define AFEC_CGR_GAIN4_Pos 8 /**< (AFEC_CGR) Gain for Channel 4 Position */ 1116 #define AFEC_CGR_GAIN4_Msk (_U_(0x3) << AFEC_CGR_GAIN4_Pos) /**< (AFEC_CGR) Gain for Channel 4 Mask */ 1117 #define AFEC_CGR_GAIN4(value) (AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos)) 1118 #define AFEC_CGR_GAIN5_Pos 10 /**< (AFEC_CGR) Gain for Channel 5 Position */ 1119 #define AFEC_CGR_GAIN5_Msk (_U_(0x3) << AFEC_CGR_GAIN5_Pos) /**< (AFEC_CGR) Gain for Channel 5 Mask */ 1120 #define AFEC_CGR_GAIN5(value) (AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos)) 1121 #define AFEC_CGR_GAIN6_Pos 12 /**< (AFEC_CGR) Gain for Channel 6 Position */ 1122 #define AFEC_CGR_GAIN6_Msk (_U_(0x3) << AFEC_CGR_GAIN6_Pos) /**< (AFEC_CGR) Gain for Channel 6 Mask */ 1123 #define AFEC_CGR_GAIN6(value) (AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos)) 1124 #define AFEC_CGR_GAIN7_Pos 14 /**< (AFEC_CGR) Gain for Channel 7 Position */ 1125 #define AFEC_CGR_GAIN7_Msk (_U_(0x3) << AFEC_CGR_GAIN7_Pos) /**< (AFEC_CGR) Gain for Channel 7 Mask */ 1126 #define AFEC_CGR_GAIN7(value) (AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos)) 1127 #define AFEC_CGR_GAIN8_Pos 16 /**< (AFEC_CGR) Gain for Channel 8 Position */ 1128 #define AFEC_CGR_GAIN8_Msk (_U_(0x3) << AFEC_CGR_GAIN8_Pos) /**< (AFEC_CGR) Gain for Channel 8 Mask */ 1129 #define AFEC_CGR_GAIN8(value) (AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos)) 1130 #define AFEC_CGR_GAIN9_Pos 18 /**< (AFEC_CGR) Gain for Channel 9 Position */ 1131 #define AFEC_CGR_GAIN9_Msk (_U_(0x3) << AFEC_CGR_GAIN9_Pos) /**< (AFEC_CGR) Gain for Channel 9 Mask */ 1132 #define AFEC_CGR_GAIN9(value) (AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos)) 1133 #define AFEC_CGR_GAIN10_Pos 20 /**< (AFEC_CGR) Gain for Channel 10 Position */ 1134 #define AFEC_CGR_GAIN10_Msk (_U_(0x3) << AFEC_CGR_GAIN10_Pos) /**< (AFEC_CGR) Gain for Channel 10 Mask */ 1135 #define AFEC_CGR_GAIN10(value) (AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos)) 1136 #define AFEC_CGR_GAIN11_Pos 22 /**< (AFEC_CGR) Gain for Channel 11 Position */ 1137 #define AFEC_CGR_GAIN11_Msk (_U_(0x3) << AFEC_CGR_GAIN11_Pos) /**< (AFEC_CGR) Gain for Channel 11 Mask */ 1138 #define AFEC_CGR_GAIN11(value) (AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos)) 1139 #define AFEC_CGR_MASK _U_(0xFFFFFF) /**< \deprecated (AFEC_CGR) Register MASK (Use AFEC_CGR_Msk instead) */ 1140 #define AFEC_CGR_Msk _U_(0xFFFFFF) /**< (AFEC_CGR) Register Mask */ 1141 1142 1143 /* -------- AFEC_DIFFR : (AFEC Offset: 0x60) (R/W 32) AFEC Channel Differential Register -------- */ 1144 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1145 #if COMPONENT_TYPEDEF_STYLE == 'N' 1146 typedef union { 1147 struct { 1148 uint32_t DIFF0:1; /**< bit: 0 Differential inputs for channel 0 */ 1149 uint32_t DIFF1:1; /**< bit: 1 Differential inputs for channel 1 */ 1150 uint32_t DIFF2:1; /**< bit: 2 Differential inputs for channel 2 */ 1151 uint32_t DIFF3:1; /**< bit: 3 Differential inputs for channel 3 */ 1152 uint32_t DIFF4:1; /**< bit: 4 Differential inputs for channel 4 */ 1153 uint32_t DIFF5:1; /**< bit: 5 Differential inputs for channel 5 */ 1154 uint32_t DIFF6:1; /**< bit: 6 Differential inputs for channel 6 */ 1155 uint32_t DIFF7:1; /**< bit: 7 Differential inputs for channel 7 */ 1156 uint32_t DIFF8:1; /**< bit: 8 Differential inputs for channel 8 */ 1157 uint32_t DIFF9:1; /**< bit: 9 Differential inputs for channel 9 */ 1158 uint32_t DIFF10:1; /**< bit: 10 Differential inputs for channel 10 */ 1159 uint32_t DIFF11:1; /**< bit: 11 Differential inputs for channel 11 */ 1160 uint32_t :20; /**< bit: 12..31 Reserved */ 1161 } bit; /**< Structure used for bit access */ 1162 struct { 1163 uint32_t DIFF:12; /**< bit: 0..11 Differential inputs for channel xx */ 1164 uint32_t :20; /**< bit: 12..31 Reserved */ 1165 } vec; /**< Structure used for vec access */ 1166 uint32_t reg; /**< Type used for register access */ 1167 } AFEC_DIFFR_Type; 1168 #endif 1169 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1170 1171 #define AFEC_DIFFR_OFFSET (0x60) /**< (AFEC_DIFFR) AFEC Channel Differential Register Offset */ 1172 1173 #define AFEC_DIFFR_DIFF0_Pos 0 /**< (AFEC_DIFFR) Differential inputs for channel 0 Position */ 1174 #define AFEC_DIFFR_DIFF0_Msk (_U_(0x1) << AFEC_DIFFR_DIFF0_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 0 Mask */ 1175 #define AFEC_DIFFR_DIFF0 AFEC_DIFFR_DIFF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF0_Msk instead */ 1176 #define AFEC_DIFFR_DIFF1_Pos 1 /**< (AFEC_DIFFR) Differential inputs for channel 1 Position */ 1177 #define AFEC_DIFFR_DIFF1_Msk (_U_(0x1) << AFEC_DIFFR_DIFF1_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 1 Mask */ 1178 #define AFEC_DIFFR_DIFF1 AFEC_DIFFR_DIFF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF1_Msk instead */ 1179 #define AFEC_DIFFR_DIFF2_Pos 2 /**< (AFEC_DIFFR) Differential inputs for channel 2 Position */ 1180 #define AFEC_DIFFR_DIFF2_Msk (_U_(0x1) << AFEC_DIFFR_DIFF2_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 2 Mask */ 1181 #define AFEC_DIFFR_DIFF2 AFEC_DIFFR_DIFF2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF2_Msk instead */ 1182 #define AFEC_DIFFR_DIFF3_Pos 3 /**< (AFEC_DIFFR) Differential inputs for channel 3 Position */ 1183 #define AFEC_DIFFR_DIFF3_Msk (_U_(0x1) << AFEC_DIFFR_DIFF3_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 3 Mask */ 1184 #define AFEC_DIFFR_DIFF3 AFEC_DIFFR_DIFF3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF3_Msk instead */ 1185 #define AFEC_DIFFR_DIFF4_Pos 4 /**< (AFEC_DIFFR) Differential inputs for channel 4 Position */ 1186 #define AFEC_DIFFR_DIFF4_Msk (_U_(0x1) << AFEC_DIFFR_DIFF4_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 4 Mask */ 1187 #define AFEC_DIFFR_DIFF4 AFEC_DIFFR_DIFF4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF4_Msk instead */ 1188 #define AFEC_DIFFR_DIFF5_Pos 5 /**< (AFEC_DIFFR) Differential inputs for channel 5 Position */ 1189 #define AFEC_DIFFR_DIFF5_Msk (_U_(0x1) << AFEC_DIFFR_DIFF5_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 5 Mask */ 1190 #define AFEC_DIFFR_DIFF5 AFEC_DIFFR_DIFF5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF5_Msk instead */ 1191 #define AFEC_DIFFR_DIFF6_Pos 6 /**< (AFEC_DIFFR) Differential inputs for channel 6 Position */ 1192 #define AFEC_DIFFR_DIFF6_Msk (_U_(0x1) << AFEC_DIFFR_DIFF6_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 6 Mask */ 1193 #define AFEC_DIFFR_DIFF6 AFEC_DIFFR_DIFF6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF6_Msk instead */ 1194 #define AFEC_DIFFR_DIFF7_Pos 7 /**< (AFEC_DIFFR) Differential inputs for channel 7 Position */ 1195 #define AFEC_DIFFR_DIFF7_Msk (_U_(0x1) << AFEC_DIFFR_DIFF7_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 7 Mask */ 1196 #define AFEC_DIFFR_DIFF7 AFEC_DIFFR_DIFF7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF7_Msk instead */ 1197 #define AFEC_DIFFR_DIFF8_Pos 8 /**< (AFEC_DIFFR) Differential inputs for channel 8 Position */ 1198 #define AFEC_DIFFR_DIFF8_Msk (_U_(0x1) << AFEC_DIFFR_DIFF8_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 8 Mask */ 1199 #define AFEC_DIFFR_DIFF8 AFEC_DIFFR_DIFF8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF8_Msk instead */ 1200 #define AFEC_DIFFR_DIFF9_Pos 9 /**< (AFEC_DIFFR) Differential inputs for channel 9 Position */ 1201 #define AFEC_DIFFR_DIFF9_Msk (_U_(0x1) << AFEC_DIFFR_DIFF9_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 9 Mask */ 1202 #define AFEC_DIFFR_DIFF9 AFEC_DIFFR_DIFF9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF9_Msk instead */ 1203 #define AFEC_DIFFR_DIFF10_Pos 10 /**< (AFEC_DIFFR) Differential inputs for channel 10 Position */ 1204 #define AFEC_DIFFR_DIFF10_Msk (_U_(0x1) << AFEC_DIFFR_DIFF10_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 10 Mask */ 1205 #define AFEC_DIFFR_DIFF10 AFEC_DIFFR_DIFF10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF10_Msk instead */ 1206 #define AFEC_DIFFR_DIFF11_Pos 11 /**< (AFEC_DIFFR) Differential inputs for channel 11 Position */ 1207 #define AFEC_DIFFR_DIFF11_Msk (_U_(0x1) << AFEC_DIFFR_DIFF11_Pos) /**< (AFEC_DIFFR) Differential inputs for channel 11 Mask */ 1208 #define AFEC_DIFFR_DIFF11 AFEC_DIFFR_DIFF11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_DIFFR_DIFF11_Msk instead */ 1209 #define AFEC_DIFFR_MASK _U_(0xFFF) /**< \deprecated (AFEC_DIFFR) Register MASK (Use AFEC_DIFFR_Msk instead) */ 1210 #define AFEC_DIFFR_Msk _U_(0xFFF) /**< (AFEC_DIFFR) Register Mask */ 1211 1212 #define AFEC_DIFFR_DIFF_Pos 0 /**< (AFEC_DIFFR Position) Differential inputs for channel xx */ 1213 #define AFEC_DIFFR_DIFF_Msk (_U_(0xFFF) << AFEC_DIFFR_DIFF_Pos) /**< (AFEC_DIFFR Mask) DIFF */ 1214 #define AFEC_DIFFR_DIFF(value) (AFEC_DIFFR_DIFF_Msk & ((value) << AFEC_DIFFR_DIFF_Pos)) 1215 1216 /* -------- AFEC_CSELR : (AFEC Offset: 0x64) (R/W 32) AFEC Channel Selection Register -------- */ 1217 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1218 #if COMPONENT_TYPEDEF_STYLE == 'N' 1219 typedef union { 1220 struct { 1221 uint32_t CSEL:4; /**< bit: 0..3 Channel Selection */ 1222 uint32_t :28; /**< bit: 4..31 Reserved */ 1223 } bit; /**< Structure used for bit access */ 1224 uint32_t reg; /**< Type used for register access */ 1225 } AFEC_CSELR_Type; 1226 #endif 1227 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1228 1229 #define AFEC_CSELR_OFFSET (0x64) /**< (AFEC_CSELR) AFEC Channel Selection Register Offset */ 1230 1231 #define AFEC_CSELR_CSEL_Pos 0 /**< (AFEC_CSELR) Channel Selection Position */ 1232 #define AFEC_CSELR_CSEL_Msk (_U_(0xF) << AFEC_CSELR_CSEL_Pos) /**< (AFEC_CSELR) Channel Selection Mask */ 1233 #define AFEC_CSELR_CSEL(value) (AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos)) 1234 #define AFEC_CSELR_MASK _U_(0x0F) /**< \deprecated (AFEC_CSELR) Register MASK (Use AFEC_CSELR_Msk instead) */ 1235 #define AFEC_CSELR_Msk _U_(0x0F) /**< (AFEC_CSELR) Register Mask */ 1236 1237 1238 /* -------- AFEC_CDR : (AFEC Offset: 0x68) (R/ 32) AFEC Channel Data Register -------- */ 1239 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1240 #if COMPONENT_TYPEDEF_STYLE == 'N' 1241 typedef union { 1242 struct { 1243 uint32_t DATA:16; /**< bit: 0..15 Converted Data */ 1244 uint32_t :16; /**< bit: 16..31 Reserved */ 1245 } bit; /**< Structure used for bit access */ 1246 uint32_t reg; /**< Type used for register access */ 1247 } AFEC_CDR_Type; 1248 #endif 1249 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1250 1251 #define AFEC_CDR_OFFSET (0x68) /**< (AFEC_CDR) AFEC Channel Data Register Offset */ 1252 1253 #define AFEC_CDR_DATA_Pos 0 /**< (AFEC_CDR) Converted Data Position */ 1254 #define AFEC_CDR_DATA_Msk (_U_(0xFFFF) << AFEC_CDR_DATA_Pos) /**< (AFEC_CDR) Converted Data Mask */ 1255 #define AFEC_CDR_DATA(value) (AFEC_CDR_DATA_Msk & ((value) << AFEC_CDR_DATA_Pos)) 1256 #define AFEC_CDR_MASK _U_(0xFFFF) /**< \deprecated (AFEC_CDR) Register MASK (Use AFEC_CDR_Msk instead) */ 1257 #define AFEC_CDR_Msk _U_(0xFFFF) /**< (AFEC_CDR) Register Mask */ 1258 1259 1260 /* -------- AFEC_COCR : (AFEC Offset: 0x6c) (R/W 32) AFEC Channel Offset Compensation Register -------- */ 1261 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1262 #if COMPONENT_TYPEDEF_STYLE == 'N' 1263 typedef union { 1264 struct { 1265 uint32_t AOFF:10; /**< bit: 0..9 Analog Offset */ 1266 uint32_t :22; /**< bit: 10..31 Reserved */ 1267 } bit; /**< Structure used for bit access */ 1268 uint32_t reg; /**< Type used for register access */ 1269 } AFEC_COCR_Type; 1270 #endif 1271 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1272 1273 #define AFEC_COCR_OFFSET (0x6C) /**< (AFEC_COCR) AFEC Channel Offset Compensation Register Offset */ 1274 1275 #define AFEC_COCR_AOFF_Pos 0 /**< (AFEC_COCR) Analog Offset Position */ 1276 #define AFEC_COCR_AOFF_Msk (_U_(0x3FF) << AFEC_COCR_AOFF_Pos) /**< (AFEC_COCR) Analog Offset Mask */ 1277 #define AFEC_COCR_AOFF(value) (AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos)) 1278 #define AFEC_COCR_MASK _U_(0x3FF) /**< \deprecated (AFEC_COCR) Register MASK (Use AFEC_COCR_Msk instead) */ 1279 #define AFEC_COCR_Msk _U_(0x3FF) /**< (AFEC_COCR) Register Mask */ 1280 1281 1282 /* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) (R/W 32) AFEC Temperature Sensor Mode Register -------- */ 1283 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1284 #if COMPONENT_TYPEDEF_STYLE == 'N' 1285 typedef union { 1286 struct { 1287 uint32_t RTCT:1; /**< bit: 0 Temperature Sensor RTC Trigger Mode */ 1288 uint32_t :3; /**< bit: 1..3 Reserved */ 1289 uint32_t TEMPCMPMOD:2; /**< bit: 4..5 Temperature Comparison Mode */ 1290 uint32_t :26; /**< bit: 6..31 Reserved */ 1291 } bit; /**< Structure used for bit access */ 1292 uint32_t reg; /**< Type used for register access */ 1293 } AFEC_TEMPMR_Type; 1294 #endif 1295 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1296 1297 #define AFEC_TEMPMR_OFFSET (0x70) /**< (AFEC_TEMPMR) AFEC Temperature Sensor Mode Register Offset */ 1298 1299 #define AFEC_TEMPMR_RTCT_Pos 0 /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Position */ 1300 #define AFEC_TEMPMR_RTCT_Msk (_U_(0x1) << AFEC_TEMPMR_RTCT_Pos) /**< (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode Mask */ 1301 #define AFEC_TEMPMR_RTCT AFEC_TEMPMR_RTCT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_TEMPMR_RTCT_Msk instead */ 1302 #define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 /**< (AFEC_TEMPMR) Temperature Comparison Mode Position */ 1303 #define AFEC_TEMPMR_TEMPCMPMOD_Msk (_U_(0x3) << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Temperature Comparison Mode Mask */ 1304 #define AFEC_TEMPMR_TEMPCMPMOD(value) (AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos)) 1305 #define AFEC_TEMPMR_TEMPCMPMOD_LOW_Val _U_(0x0) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ 1306 #define AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val _U_(0x1) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ 1307 #define AFEC_TEMPMR_TEMPCMPMOD_IN_Val _U_(0x2) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ 1308 #define AFEC_TEMPMR_TEMPCMPMOD_OUT_Val _U_(0x3) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ 1309 #define AFEC_TEMPMR_TEMPCMPMOD_LOW (AFEC_TEMPMR_TEMPCMPMOD_LOW_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. Position */ 1310 #define AFEC_TEMPMR_TEMPCMPMOD_HIGH (AFEC_TEMPMR_TEMPCMPMOD_HIGH_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. Position */ 1311 #define AFEC_TEMPMR_TEMPCMPMOD_IN (AFEC_TEMPMR_TEMPCMPMOD_IN_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. Position */ 1312 #define AFEC_TEMPMR_TEMPCMPMOD_OUT (AFEC_TEMPMR_TEMPCMPMOD_OUT_Val << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. Position */ 1313 #define AFEC_TEMPMR_MASK _U_(0x31) /**< \deprecated (AFEC_TEMPMR) Register MASK (Use AFEC_TEMPMR_Msk instead) */ 1314 #define AFEC_TEMPMR_Msk _U_(0x31) /**< (AFEC_TEMPMR) Register Mask */ 1315 1316 1317 /* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) (R/W 32) AFEC Temperature Compare Window Register -------- */ 1318 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1319 #if COMPONENT_TYPEDEF_STYLE == 'N' 1320 typedef union { 1321 struct { 1322 uint32_t TLOWTHRES:16; /**< bit: 0..15 Temperature Low Threshold */ 1323 uint32_t THIGHTHRES:16; /**< bit: 16..31 Temperature High Threshold */ 1324 } bit; /**< Structure used for bit access */ 1325 uint32_t reg; /**< Type used for register access */ 1326 } AFEC_TEMPCWR_Type; 1327 #endif 1328 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1329 1330 #define AFEC_TEMPCWR_OFFSET (0x74) /**< (AFEC_TEMPCWR) AFEC Temperature Compare Window Register Offset */ 1331 1332 #define AFEC_TEMPCWR_TLOWTHRES_Pos 0 /**< (AFEC_TEMPCWR) Temperature Low Threshold Position */ 1333 #define AFEC_TEMPCWR_TLOWTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature Low Threshold Mask */ 1334 #define AFEC_TEMPCWR_TLOWTHRES(value) (AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos)) 1335 #define AFEC_TEMPCWR_THIGHTHRES_Pos 16 /**< (AFEC_TEMPCWR) Temperature High Threshold Position */ 1336 #define AFEC_TEMPCWR_THIGHTHRES_Msk (_U_(0xFFFF) << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< (AFEC_TEMPCWR) Temperature High Threshold Mask */ 1337 #define AFEC_TEMPCWR_THIGHTHRES(value) (AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos)) 1338 #define AFEC_TEMPCWR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AFEC_TEMPCWR) Register MASK (Use AFEC_TEMPCWR_Msk instead) */ 1339 #define AFEC_TEMPCWR_Msk _U_(0xFFFFFFFF) /**< (AFEC_TEMPCWR) Register Mask */ 1340 1341 1342 /* -------- AFEC_ACR : (AFEC Offset: 0x94) (R/W 32) AFEC Analog Control Register -------- */ 1343 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1344 #if COMPONENT_TYPEDEF_STYLE == 'N' 1345 typedef union { 1346 struct { 1347 uint32_t :2; /**< bit: 0..1 Reserved */ 1348 uint32_t PGA0EN:1; /**< bit: 2 PGA0 Enable */ 1349 uint32_t PGA1EN:1; /**< bit: 3 PGA1 Enable */ 1350 uint32_t :4; /**< bit: 4..7 Reserved */ 1351 uint32_t IBCTL:2; /**< bit: 8..9 AFE Bias Current Control */ 1352 uint32_t :22; /**< bit: 10..31 Reserved */ 1353 } bit; /**< Structure used for bit access */ 1354 uint32_t reg; /**< Type used for register access */ 1355 } AFEC_ACR_Type; 1356 #endif 1357 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1358 1359 #define AFEC_ACR_OFFSET (0x94) /**< (AFEC_ACR) AFEC Analog Control Register Offset */ 1360 1361 #define AFEC_ACR_PGA0EN_Pos 2 /**< (AFEC_ACR) PGA0 Enable Position */ 1362 #define AFEC_ACR_PGA0EN_Msk (_U_(0x1) << AFEC_ACR_PGA0EN_Pos) /**< (AFEC_ACR) PGA0 Enable Mask */ 1363 #define AFEC_ACR_PGA0EN AFEC_ACR_PGA0EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ACR_PGA0EN_Msk instead */ 1364 #define AFEC_ACR_PGA1EN_Pos 3 /**< (AFEC_ACR) PGA1 Enable Position */ 1365 #define AFEC_ACR_PGA1EN_Msk (_U_(0x1) << AFEC_ACR_PGA1EN_Pos) /**< (AFEC_ACR) PGA1 Enable Mask */ 1366 #define AFEC_ACR_PGA1EN AFEC_ACR_PGA1EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_ACR_PGA1EN_Msk instead */ 1367 #define AFEC_ACR_IBCTL_Pos 8 /**< (AFEC_ACR) AFE Bias Current Control Position */ 1368 #define AFEC_ACR_IBCTL_Msk (_U_(0x3) << AFEC_ACR_IBCTL_Pos) /**< (AFEC_ACR) AFE Bias Current Control Mask */ 1369 #define AFEC_ACR_IBCTL(value) (AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos)) 1370 #define AFEC_ACR_MASK _U_(0x30C) /**< \deprecated (AFEC_ACR) Register MASK (Use AFEC_ACR_Msk instead) */ 1371 #define AFEC_ACR_Msk _U_(0x30C) /**< (AFEC_ACR) Register Mask */ 1372 1373 1374 /* -------- AFEC_SHMR : (AFEC Offset: 0xa0) (R/W 32) AFEC Sample & Hold Mode Register -------- */ 1375 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1376 #if COMPONENT_TYPEDEF_STYLE == 'N' 1377 typedef union { 1378 struct { 1379 uint32_t DUAL0:1; /**< bit: 0 Dual Sample & Hold for channel 0 */ 1380 uint32_t DUAL1:1; /**< bit: 1 Dual Sample & Hold for channel 1 */ 1381 uint32_t DUAL2:1; /**< bit: 2 Dual Sample & Hold for channel 2 */ 1382 uint32_t DUAL3:1; /**< bit: 3 Dual Sample & Hold for channel 3 */ 1383 uint32_t DUAL4:1; /**< bit: 4 Dual Sample & Hold for channel 4 */ 1384 uint32_t DUAL5:1; /**< bit: 5 Dual Sample & Hold for channel 5 */ 1385 uint32_t DUAL6:1; /**< bit: 6 Dual Sample & Hold for channel 6 */ 1386 uint32_t DUAL7:1; /**< bit: 7 Dual Sample & Hold for channel 7 */ 1387 uint32_t DUAL8:1; /**< bit: 8 Dual Sample & Hold for channel 8 */ 1388 uint32_t DUAL9:1; /**< bit: 9 Dual Sample & Hold for channel 9 */ 1389 uint32_t DUAL10:1; /**< bit: 10 Dual Sample & Hold for channel 10 */ 1390 uint32_t DUAL11:1; /**< bit: 11 Dual Sample & Hold for channel 11 */ 1391 uint32_t :20; /**< bit: 12..31 Reserved */ 1392 } bit; /**< Structure used for bit access */ 1393 struct { 1394 uint32_t DUAL:12; /**< bit: 0..11 Dual Sample & Hold for channel xx */ 1395 uint32_t :20; /**< bit: 12..31 Reserved */ 1396 } vec; /**< Structure used for vec access */ 1397 uint32_t reg; /**< Type used for register access */ 1398 } AFEC_SHMR_Type; 1399 #endif 1400 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1401 1402 #define AFEC_SHMR_OFFSET (0xA0) /**< (AFEC_SHMR) AFEC Sample & Hold Mode Register Offset */ 1403 1404 #define AFEC_SHMR_DUAL0_Pos 0 /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Position */ 1405 #define AFEC_SHMR_DUAL0_Msk (_U_(0x1) << AFEC_SHMR_DUAL0_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 0 Mask */ 1406 #define AFEC_SHMR_DUAL0 AFEC_SHMR_DUAL0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL0_Msk instead */ 1407 #define AFEC_SHMR_DUAL1_Pos 1 /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Position */ 1408 #define AFEC_SHMR_DUAL1_Msk (_U_(0x1) << AFEC_SHMR_DUAL1_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 1 Mask */ 1409 #define AFEC_SHMR_DUAL1 AFEC_SHMR_DUAL1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL1_Msk instead */ 1410 #define AFEC_SHMR_DUAL2_Pos 2 /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Position */ 1411 #define AFEC_SHMR_DUAL2_Msk (_U_(0x1) << AFEC_SHMR_DUAL2_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 2 Mask */ 1412 #define AFEC_SHMR_DUAL2 AFEC_SHMR_DUAL2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL2_Msk instead */ 1413 #define AFEC_SHMR_DUAL3_Pos 3 /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Position */ 1414 #define AFEC_SHMR_DUAL3_Msk (_U_(0x1) << AFEC_SHMR_DUAL3_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 3 Mask */ 1415 #define AFEC_SHMR_DUAL3 AFEC_SHMR_DUAL3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL3_Msk instead */ 1416 #define AFEC_SHMR_DUAL4_Pos 4 /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Position */ 1417 #define AFEC_SHMR_DUAL4_Msk (_U_(0x1) << AFEC_SHMR_DUAL4_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 4 Mask */ 1418 #define AFEC_SHMR_DUAL4 AFEC_SHMR_DUAL4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL4_Msk instead */ 1419 #define AFEC_SHMR_DUAL5_Pos 5 /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Position */ 1420 #define AFEC_SHMR_DUAL5_Msk (_U_(0x1) << AFEC_SHMR_DUAL5_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 5 Mask */ 1421 #define AFEC_SHMR_DUAL5 AFEC_SHMR_DUAL5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL5_Msk instead */ 1422 #define AFEC_SHMR_DUAL6_Pos 6 /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Position */ 1423 #define AFEC_SHMR_DUAL6_Msk (_U_(0x1) << AFEC_SHMR_DUAL6_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 6 Mask */ 1424 #define AFEC_SHMR_DUAL6 AFEC_SHMR_DUAL6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL6_Msk instead */ 1425 #define AFEC_SHMR_DUAL7_Pos 7 /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Position */ 1426 #define AFEC_SHMR_DUAL7_Msk (_U_(0x1) << AFEC_SHMR_DUAL7_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 7 Mask */ 1427 #define AFEC_SHMR_DUAL7 AFEC_SHMR_DUAL7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL7_Msk instead */ 1428 #define AFEC_SHMR_DUAL8_Pos 8 /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Position */ 1429 #define AFEC_SHMR_DUAL8_Msk (_U_(0x1) << AFEC_SHMR_DUAL8_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 8 Mask */ 1430 #define AFEC_SHMR_DUAL8 AFEC_SHMR_DUAL8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL8_Msk instead */ 1431 #define AFEC_SHMR_DUAL9_Pos 9 /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Position */ 1432 #define AFEC_SHMR_DUAL9_Msk (_U_(0x1) << AFEC_SHMR_DUAL9_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 9 Mask */ 1433 #define AFEC_SHMR_DUAL9 AFEC_SHMR_DUAL9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL9_Msk instead */ 1434 #define AFEC_SHMR_DUAL10_Pos 10 /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Position */ 1435 #define AFEC_SHMR_DUAL10_Msk (_U_(0x1) << AFEC_SHMR_DUAL10_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 10 Mask */ 1436 #define AFEC_SHMR_DUAL10 AFEC_SHMR_DUAL10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL10_Msk instead */ 1437 #define AFEC_SHMR_DUAL11_Pos 11 /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Position */ 1438 #define AFEC_SHMR_DUAL11_Msk (_U_(0x1) << AFEC_SHMR_DUAL11_Pos) /**< (AFEC_SHMR) Dual Sample & Hold for channel 11 Mask */ 1439 #define AFEC_SHMR_DUAL11 AFEC_SHMR_DUAL11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_SHMR_DUAL11_Msk instead */ 1440 #define AFEC_SHMR_MASK _U_(0xFFF) /**< \deprecated (AFEC_SHMR) Register MASK (Use AFEC_SHMR_Msk instead) */ 1441 #define AFEC_SHMR_Msk _U_(0xFFF) /**< (AFEC_SHMR) Register Mask */ 1442 1443 #define AFEC_SHMR_DUAL_Pos 0 /**< (AFEC_SHMR Position) Dual Sample & Hold for channel xx */ 1444 #define AFEC_SHMR_DUAL_Msk (_U_(0xFFF) << AFEC_SHMR_DUAL_Pos) /**< (AFEC_SHMR Mask) DUAL */ 1445 #define AFEC_SHMR_DUAL(value) (AFEC_SHMR_DUAL_Msk & ((value) << AFEC_SHMR_DUAL_Pos)) 1446 1447 /* -------- AFEC_COSR : (AFEC Offset: 0xd0) (R/W 32) AFEC Correction Select Register -------- */ 1448 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1449 #if COMPONENT_TYPEDEF_STYLE == 'N' 1450 typedef union { 1451 struct { 1452 uint32_t CSEL:1; /**< bit: 0 Sample & Hold unit Correction Select */ 1453 uint32_t :31; /**< bit: 1..31 Reserved */ 1454 } bit; /**< Structure used for bit access */ 1455 uint32_t reg; /**< Type used for register access */ 1456 } AFEC_COSR_Type; 1457 #endif 1458 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1459 1460 #define AFEC_COSR_OFFSET (0xD0) /**< (AFEC_COSR) AFEC Correction Select Register Offset */ 1461 1462 #define AFEC_COSR_CSEL_Pos 0 /**< (AFEC_COSR) Sample & Hold unit Correction Select Position */ 1463 #define AFEC_COSR_CSEL_Msk (_U_(0x1) << AFEC_COSR_CSEL_Pos) /**< (AFEC_COSR) Sample & Hold unit Correction Select Mask */ 1464 #define AFEC_COSR_CSEL AFEC_COSR_CSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_COSR_CSEL_Msk instead */ 1465 #define AFEC_COSR_MASK _U_(0x01) /**< \deprecated (AFEC_COSR) Register MASK (Use AFEC_COSR_Msk instead) */ 1466 #define AFEC_COSR_Msk _U_(0x01) /**< (AFEC_COSR) Register Mask */ 1467 1468 1469 /* -------- AFEC_CVR : (AFEC Offset: 0xd4) (R/W 32) AFEC Correction Values Register -------- */ 1470 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1471 #if COMPONENT_TYPEDEF_STYLE == 'N' 1472 typedef union { 1473 struct { 1474 uint32_t OFFSETCORR:16; /**< bit: 0..15 Offset Correction */ 1475 uint32_t GAINCORR:16; /**< bit: 16..31 Gain Correction */ 1476 } bit; /**< Structure used for bit access */ 1477 uint32_t reg; /**< Type used for register access */ 1478 } AFEC_CVR_Type; 1479 #endif 1480 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1481 1482 #define AFEC_CVR_OFFSET (0xD4) /**< (AFEC_CVR) AFEC Correction Values Register Offset */ 1483 1484 #define AFEC_CVR_OFFSETCORR_Pos 0 /**< (AFEC_CVR) Offset Correction Position */ 1485 #define AFEC_CVR_OFFSETCORR_Msk (_U_(0xFFFF) << AFEC_CVR_OFFSETCORR_Pos) /**< (AFEC_CVR) Offset Correction Mask */ 1486 #define AFEC_CVR_OFFSETCORR(value) (AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos)) 1487 #define AFEC_CVR_GAINCORR_Pos 16 /**< (AFEC_CVR) Gain Correction Position */ 1488 #define AFEC_CVR_GAINCORR_Msk (_U_(0xFFFF) << AFEC_CVR_GAINCORR_Pos) /**< (AFEC_CVR) Gain Correction Mask */ 1489 #define AFEC_CVR_GAINCORR(value) (AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos)) 1490 #define AFEC_CVR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AFEC_CVR) Register MASK (Use AFEC_CVR_Msk instead) */ 1491 #define AFEC_CVR_Msk _U_(0xFFFFFFFF) /**< (AFEC_CVR) Register Mask */ 1492 1493 1494 /* -------- AFEC_CECR : (AFEC Offset: 0xd8) (R/W 32) AFEC Channel Error Correction Register -------- */ 1495 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1496 #if COMPONENT_TYPEDEF_STYLE == 'N' 1497 typedef union { 1498 struct { 1499 uint32_t ECORR0:1; /**< bit: 0 Error Correction Enable for channel 0 */ 1500 uint32_t ECORR1:1; /**< bit: 1 Error Correction Enable for channel 1 */ 1501 uint32_t ECORR2:1; /**< bit: 2 Error Correction Enable for channel 2 */ 1502 uint32_t ECORR3:1; /**< bit: 3 Error Correction Enable for channel 3 */ 1503 uint32_t ECORR4:1; /**< bit: 4 Error Correction Enable for channel 4 */ 1504 uint32_t ECORR5:1; /**< bit: 5 Error Correction Enable for channel 5 */ 1505 uint32_t ECORR6:1; /**< bit: 6 Error Correction Enable for channel 6 */ 1506 uint32_t ECORR7:1; /**< bit: 7 Error Correction Enable for channel 7 */ 1507 uint32_t ECORR8:1; /**< bit: 8 Error Correction Enable for channel 8 */ 1508 uint32_t ECORR9:1; /**< bit: 9 Error Correction Enable for channel 9 */ 1509 uint32_t ECORR10:1; /**< bit: 10 Error Correction Enable for channel 10 */ 1510 uint32_t ECORR11:1; /**< bit: 11 Error Correction Enable for channel 11 */ 1511 uint32_t :20; /**< bit: 12..31 Reserved */ 1512 } bit; /**< Structure used for bit access */ 1513 struct { 1514 uint32_t ECORR:12; /**< bit: 0..11 Error Correction Enable for channel xx */ 1515 uint32_t :20; /**< bit: 12..31 Reserved */ 1516 } vec; /**< Structure used for vec access */ 1517 uint32_t reg; /**< Type used for register access */ 1518 } AFEC_CECR_Type; 1519 #endif 1520 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1521 1522 #define AFEC_CECR_OFFSET (0xD8) /**< (AFEC_CECR) AFEC Channel Error Correction Register Offset */ 1523 1524 #define AFEC_CECR_ECORR0_Pos 0 /**< (AFEC_CECR) Error Correction Enable for channel 0 Position */ 1525 #define AFEC_CECR_ECORR0_Msk (_U_(0x1) << AFEC_CECR_ECORR0_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 0 Mask */ 1526 #define AFEC_CECR_ECORR0 AFEC_CECR_ECORR0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR0_Msk instead */ 1527 #define AFEC_CECR_ECORR1_Pos 1 /**< (AFEC_CECR) Error Correction Enable for channel 1 Position */ 1528 #define AFEC_CECR_ECORR1_Msk (_U_(0x1) << AFEC_CECR_ECORR1_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 1 Mask */ 1529 #define AFEC_CECR_ECORR1 AFEC_CECR_ECORR1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR1_Msk instead */ 1530 #define AFEC_CECR_ECORR2_Pos 2 /**< (AFEC_CECR) Error Correction Enable for channel 2 Position */ 1531 #define AFEC_CECR_ECORR2_Msk (_U_(0x1) << AFEC_CECR_ECORR2_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 2 Mask */ 1532 #define AFEC_CECR_ECORR2 AFEC_CECR_ECORR2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR2_Msk instead */ 1533 #define AFEC_CECR_ECORR3_Pos 3 /**< (AFEC_CECR) Error Correction Enable for channel 3 Position */ 1534 #define AFEC_CECR_ECORR3_Msk (_U_(0x1) << AFEC_CECR_ECORR3_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 3 Mask */ 1535 #define AFEC_CECR_ECORR3 AFEC_CECR_ECORR3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR3_Msk instead */ 1536 #define AFEC_CECR_ECORR4_Pos 4 /**< (AFEC_CECR) Error Correction Enable for channel 4 Position */ 1537 #define AFEC_CECR_ECORR4_Msk (_U_(0x1) << AFEC_CECR_ECORR4_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 4 Mask */ 1538 #define AFEC_CECR_ECORR4 AFEC_CECR_ECORR4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR4_Msk instead */ 1539 #define AFEC_CECR_ECORR5_Pos 5 /**< (AFEC_CECR) Error Correction Enable for channel 5 Position */ 1540 #define AFEC_CECR_ECORR5_Msk (_U_(0x1) << AFEC_CECR_ECORR5_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 5 Mask */ 1541 #define AFEC_CECR_ECORR5 AFEC_CECR_ECORR5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR5_Msk instead */ 1542 #define AFEC_CECR_ECORR6_Pos 6 /**< (AFEC_CECR) Error Correction Enable for channel 6 Position */ 1543 #define AFEC_CECR_ECORR6_Msk (_U_(0x1) << AFEC_CECR_ECORR6_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 6 Mask */ 1544 #define AFEC_CECR_ECORR6 AFEC_CECR_ECORR6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR6_Msk instead */ 1545 #define AFEC_CECR_ECORR7_Pos 7 /**< (AFEC_CECR) Error Correction Enable for channel 7 Position */ 1546 #define AFEC_CECR_ECORR7_Msk (_U_(0x1) << AFEC_CECR_ECORR7_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 7 Mask */ 1547 #define AFEC_CECR_ECORR7 AFEC_CECR_ECORR7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR7_Msk instead */ 1548 #define AFEC_CECR_ECORR8_Pos 8 /**< (AFEC_CECR) Error Correction Enable for channel 8 Position */ 1549 #define AFEC_CECR_ECORR8_Msk (_U_(0x1) << AFEC_CECR_ECORR8_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 8 Mask */ 1550 #define AFEC_CECR_ECORR8 AFEC_CECR_ECORR8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR8_Msk instead */ 1551 #define AFEC_CECR_ECORR9_Pos 9 /**< (AFEC_CECR) Error Correction Enable for channel 9 Position */ 1552 #define AFEC_CECR_ECORR9_Msk (_U_(0x1) << AFEC_CECR_ECORR9_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 9 Mask */ 1553 #define AFEC_CECR_ECORR9 AFEC_CECR_ECORR9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR9_Msk instead */ 1554 #define AFEC_CECR_ECORR10_Pos 10 /**< (AFEC_CECR) Error Correction Enable for channel 10 Position */ 1555 #define AFEC_CECR_ECORR10_Msk (_U_(0x1) << AFEC_CECR_ECORR10_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 10 Mask */ 1556 #define AFEC_CECR_ECORR10 AFEC_CECR_ECORR10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR10_Msk instead */ 1557 #define AFEC_CECR_ECORR11_Pos 11 /**< (AFEC_CECR) Error Correction Enable for channel 11 Position */ 1558 #define AFEC_CECR_ECORR11_Msk (_U_(0x1) << AFEC_CECR_ECORR11_Pos) /**< (AFEC_CECR) Error Correction Enable for channel 11 Mask */ 1559 #define AFEC_CECR_ECORR11 AFEC_CECR_ECORR11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_CECR_ECORR11_Msk instead */ 1560 #define AFEC_CECR_MASK _U_(0xFFF) /**< \deprecated (AFEC_CECR) Register MASK (Use AFEC_CECR_Msk instead) */ 1561 #define AFEC_CECR_Msk _U_(0xFFF) /**< (AFEC_CECR) Register Mask */ 1562 1563 #define AFEC_CECR_ECORR_Pos 0 /**< (AFEC_CECR Position) Error Correction Enable for channel xx */ 1564 #define AFEC_CECR_ECORR_Msk (_U_(0xFFF) << AFEC_CECR_ECORR_Pos) /**< (AFEC_CECR Mask) ECORR */ 1565 #define AFEC_CECR_ECORR(value) (AFEC_CECR_ECORR_Msk & ((value) << AFEC_CECR_ECORR_Pos)) 1566 1567 /* -------- AFEC_WPMR : (AFEC Offset: 0xe4) (R/W 32) AFEC Write Protection Mode Register -------- */ 1568 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1569 #if COMPONENT_TYPEDEF_STYLE == 'N' 1570 typedef union { 1571 struct { 1572 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 1573 uint32_t :7; /**< bit: 1..7 Reserved */ 1574 uint32_t WPKEY:24; /**< bit: 8..31 Write Protect KEY */ 1575 } bit; /**< Structure used for bit access */ 1576 uint32_t reg; /**< Type used for register access */ 1577 } AFEC_WPMR_Type; 1578 #endif 1579 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1580 1581 #define AFEC_WPMR_OFFSET (0xE4) /**< (AFEC_WPMR) AFEC Write Protection Mode Register Offset */ 1582 1583 #define AFEC_WPMR_WPEN_Pos 0 /**< (AFEC_WPMR) Write Protection Enable Position */ 1584 #define AFEC_WPMR_WPEN_Msk (_U_(0x1) << AFEC_WPMR_WPEN_Pos) /**< (AFEC_WPMR) Write Protection Enable Mask */ 1585 #define AFEC_WPMR_WPEN AFEC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_WPMR_WPEN_Msk instead */ 1586 #define AFEC_WPMR_WPKEY_Pos 8 /**< (AFEC_WPMR) Write Protect KEY Position */ 1587 #define AFEC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Write Protect KEY Mask */ 1588 #define AFEC_WPMR_WPKEY(value) (AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos)) 1589 #define AFEC_WPMR_WPKEY_PASSWD_Val _U_(0x414443) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ 1590 #define AFEC_WPMR_WPKEY_PASSWD (AFEC_WPMR_WPKEY_PASSWD_Val << AFEC_WPMR_WPKEY_Pos) /**< (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ 1591 #define AFEC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (AFEC_WPMR) Register MASK (Use AFEC_WPMR_Msk instead) */ 1592 #define AFEC_WPMR_Msk _U_(0xFFFFFF01) /**< (AFEC_WPMR) Register Mask */ 1593 1594 1595 /* -------- AFEC_WPSR : (AFEC Offset: 0xe8) (R/ 32) AFEC Write Protection Status Register -------- */ 1596 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1597 #if COMPONENT_TYPEDEF_STYLE == 'N' 1598 typedef union { 1599 struct { 1600 uint32_t WPVS:1; /**< bit: 0 Write Protect Violation Status */ 1601 uint32_t :7; /**< bit: 1..7 Reserved */ 1602 uint32_t WPVSRC:16; /**< bit: 8..23 Write Protect Violation Source */ 1603 uint32_t :8; /**< bit: 24..31 Reserved */ 1604 } bit; /**< Structure used for bit access */ 1605 uint32_t reg; /**< Type used for register access */ 1606 } AFEC_WPSR_Type; 1607 #endif 1608 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1609 1610 #define AFEC_WPSR_OFFSET (0xE8) /**< (AFEC_WPSR) AFEC Write Protection Status Register Offset */ 1611 1612 #define AFEC_WPSR_WPVS_Pos 0 /**< (AFEC_WPSR) Write Protect Violation Status Position */ 1613 #define AFEC_WPSR_WPVS_Msk (_U_(0x1) << AFEC_WPSR_WPVS_Pos) /**< (AFEC_WPSR) Write Protect Violation Status Mask */ 1614 #define AFEC_WPSR_WPVS AFEC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AFEC_WPSR_WPVS_Msk instead */ 1615 #define AFEC_WPSR_WPVSRC_Pos 8 /**< (AFEC_WPSR) Write Protect Violation Source Position */ 1616 #define AFEC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << AFEC_WPSR_WPVSRC_Pos) /**< (AFEC_WPSR) Write Protect Violation Source Mask */ 1617 #define AFEC_WPSR_WPVSRC(value) (AFEC_WPSR_WPVSRC_Msk & ((value) << AFEC_WPSR_WPVSRC_Pos)) 1618 #define AFEC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (AFEC_WPSR) Register MASK (Use AFEC_WPSR_Msk instead) */ 1619 #define AFEC_WPSR_Msk _U_(0xFFFF01) /**< (AFEC_WPSR) Register Mask */ 1620 1621 1622 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1623 #if COMPONENT_TYPEDEF_STYLE == 'R' 1624 /** \brief AFEC hardware registers */ 1625 typedef struct { 1626 __O uint32_t AFEC_CR; /**< (AFEC Offset: 0x00) AFEC Control Register */ 1627 __IO uint32_t AFEC_MR; /**< (AFEC Offset: 0x04) AFEC Mode Register */ 1628 __IO uint32_t AFEC_EMR; /**< (AFEC Offset: 0x08) AFEC Extended Mode Register */ 1629 __IO uint32_t AFEC_SEQ1R; /**< (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register */ 1630 __IO uint32_t AFEC_SEQ2R; /**< (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register */ 1631 __O uint32_t AFEC_CHER; /**< (AFEC Offset: 0x14) AFEC Channel Enable Register */ 1632 __O uint32_t AFEC_CHDR; /**< (AFEC Offset: 0x18) AFEC Channel Disable Register */ 1633 __I uint32_t AFEC_CHSR; /**< (AFEC Offset: 0x1C) AFEC Channel Status Register */ 1634 __I uint32_t AFEC_LCDR; /**< (AFEC Offset: 0x20) AFEC Last Converted Data Register */ 1635 __O uint32_t AFEC_IER; /**< (AFEC Offset: 0x24) AFEC Interrupt Enable Register */ 1636 __O uint32_t AFEC_IDR; /**< (AFEC Offset: 0x28) AFEC Interrupt Disable Register */ 1637 __I uint32_t AFEC_IMR; /**< (AFEC Offset: 0x2C) AFEC Interrupt Mask Register */ 1638 __I uint32_t AFEC_ISR; /**< (AFEC Offset: 0x30) AFEC Interrupt Status Register */ 1639 __I uint8_t Reserved1[24]; 1640 __I uint32_t AFEC_OVER; /**< (AFEC Offset: 0x4C) AFEC Overrun Status Register */ 1641 __IO uint32_t AFEC_CWR; /**< (AFEC Offset: 0x50) AFEC Compare Window Register */ 1642 __IO uint32_t AFEC_CGR; /**< (AFEC Offset: 0x54) AFEC Channel Gain Register */ 1643 __I uint8_t Reserved2[8]; 1644 __IO uint32_t AFEC_DIFFR; /**< (AFEC Offset: 0x60) AFEC Channel Differential Register */ 1645 __IO uint32_t AFEC_CSELR; /**< (AFEC Offset: 0x64) AFEC Channel Selection Register */ 1646 __I uint32_t AFEC_CDR; /**< (AFEC Offset: 0x68) AFEC Channel Data Register */ 1647 __IO uint32_t AFEC_COCR; /**< (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register */ 1648 __IO uint32_t AFEC_TEMPMR; /**< (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register */ 1649 __IO uint32_t AFEC_TEMPCWR; /**< (AFEC Offset: 0x74) AFEC Temperature Compare Window Register */ 1650 __I uint8_t Reserved3[28]; 1651 __IO uint32_t AFEC_ACR; /**< (AFEC Offset: 0x94) AFEC Analog Control Register */ 1652 __I uint8_t Reserved4[8]; 1653 __IO uint32_t AFEC_SHMR; /**< (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register */ 1654 __I uint8_t Reserved5[44]; 1655 __IO uint32_t AFEC_COSR; /**< (AFEC Offset: 0xD0) AFEC Correction Select Register */ 1656 __IO uint32_t AFEC_CVR; /**< (AFEC Offset: 0xD4) AFEC Correction Values Register */ 1657 __IO uint32_t AFEC_CECR; /**< (AFEC Offset: 0xD8) AFEC Channel Error Correction Register */ 1658 __I uint8_t Reserved6[8]; 1659 __IO uint32_t AFEC_WPMR; /**< (AFEC Offset: 0xE4) AFEC Write Protection Mode Register */ 1660 __I uint32_t AFEC_WPSR; /**< (AFEC Offset: 0xE8) AFEC Write Protection Status Register */ 1661 } Afec; 1662 1663 #elif COMPONENT_TYPEDEF_STYLE == 'N' 1664 /** \brief AFEC hardware registers */ 1665 typedef struct { 1666 __O AFEC_CR_Type AFEC_CR; /**< Offset: 0x00 ( /W 32) AFEC Control Register */ 1667 __IO AFEC_MR_Type AFEC_MR; /**< Offset: 0x04 (R/W 32) AFEC Mode Register */ 1668 __IO AFEC_EMR_Type AFEC_EMR; /**< Offset: 0x08 (R/W 32) AFEC Extended Mode Register */ 1669 __IO AFEC_SEQ1R_Type AFEC_SEQ1R; /**< Offset: 0x0C (R/W 32) AFEC Channel Sequence 1 Register */ 1670 __IO AFEC_SEQ2R_Type AFEC_SEQ2R; /**< Offset: 0x10 (R/W 32) AFEC Channel Sequence 2 Register */ 1671 __O AFEC_CHER_Type AFEC_CHER; /**< Offset: 0x14 ( /W 32) AFEC Channel Enable Register */ 1672 __O AFEC_CHDR_Type AFEC_CHDR; /**< Offset: 0x18 ( /W 32) AFEC Channel Disable Register */ 1673 __I AFEC_CHSR_Type AFEC_CHSR; /**< Offset: 0x1C (R/ 32) AFEC Channel Status Register */ 1674 __I AFEC_LCDR_Type AFEC_LCDR; /**< Offset: 0x20 (R/ 32) AFEC Last Converted Data Register */ 1675 __O AFEC_IER_Type AFEC_IER; /**< Offset: 0x24 ( /W 32) AFEC Interrupt Enable Register */ 1676 __O AFEC_IDR_Type AFEC_IDR; /**< Offset: 0x28 ( /W 32) AFEC Interrupt Disable Register */ 1677 __I AFEC_IMR_Type AFEC_IMR; /**< Offset: 0x2C (R/ 32) AFEC Interrupt Mask Register */ 1678 __I AFEC_ISR_Type AFEC_ISR; /**< Offset: 0x30 (R/ 32) AFEC Interrupt Status Register */ 1679 __I uint8_t Reserved1[24]; 1680 __I AFEC_OVER_Type AFEC_OVER; /**< Offset: 0x4C (R/ 32) AFEC Overrun Status Register */ 1681 __IO AFEC_CWR_Type AFEC_CWR; /**< Offset: 0x50 (R/W 32) AFEC Compare Window Register */ 1682 __IO AFEC_CGR_Type AFEC_CGR; /**< Offset: 0x54 (R/W 32) AFEC Channel Gain Register */ 1683 __I uint8_t Reserved2[8]; 1684 __IO AFEC_DIFFR_Type AFEC_DIFFR; /**< Offset: 0x60 (R/W 32) AFEC Channel Differential Register */ 1685 __IO AFEC_CSELR_Type AFEC_CSELR; /**< Offset: 0x64 (R/W 32) AFEC Channel Selection Register */ 1686 __I AFEC_CDR_Type AFEC_CDR; /**< Offset: 0x68 (R/ 32) AFEC Channel Data Register */ 1687 __IO AFEC_COCR_Type AFEC_COCR; /**< Offset: 0x6C (R/W 32) AFEC Channel Offset Compensation Register */ 1688 __IO AFEC_TEMPMR_Type AFEC_TEMPMR; /**< Offset: 0x70 (R/W 32) AFEC Temperature Sensor Mode Register */ 1689 __IO AFEC_TEMPCWR_Type AFEC_TEMPCWR; /**< Offset: 0x74 (R/W 32) AFEC Temperature Compare Window Register */ 1690 __I uint8_t Reserved3[28]; 1691 __IO AFEC_ACR_Type AFEC_ACR; /**< Offset: 0x94 (R/W 32) AFEC Analog Control Register */ 1692 __I uint8_t Reserved4[8]; 1693 __IO AFEC_SHMR_Type AFEC_SHMR; /**< Offset: 0xA0 (R/W 32) AFEC Sample & Hold Mode Register */ 1694 __I uint8_t Reserved5[44]; 1695 __IO AFEC_COSR_Type AFEC_COSR; /**< Offset: 0xD0 (R/W 32) AFEC Correction Select Register */ 1696 __IO AFEC_CVR_Type AFEC_CVR; /**< Offset: 0xD4 (R/W 32) AFEC Correction Values Register */ 1697 __IO AFEC_CECR_Type AFEC_CECR; /**< Offset: 0xD8 (R/W 32) AFEC Channel Error Correction Register */ 1698 __I uint8_t Reserved6[8]; 1699 __IO AFEC_WPMR_Type AFEC_WPMR; /**< Offset: 0xE4 (R/W 32) AFEC Write Protection Mode Register */ 1700 __I AFEC_WPSR_Type AFEC_WPSR; /**< Offset: 0xE8 (R/ 32) AFEC Write Protection Status Register */ 1701 } Afec; 1702 1703 #else /* COMPONENT_TYPEDEF_STYLE */ 1704 #error Unknown component typedef style 1705 #endif /* COMPONENT_TYPEDEF_STYLE */ 1706 1707 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1708 /** @} end of Analog Front-End Controller */ 1709 1710 #endif /* _SAMV71_AFEC_COMPONENT_H_ */ 1711
