1 /** 2 * \file 3 * 4 * \brief Header file for ATSAMV71N21 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71N21_H_ 32 #define _SAMV71N21_H_ 33 34 /** \addtogroup SAMV71N21_definitions SAMV71N21 definitions 35 This file defines all structures and symbols for SAMV71N21: 36 - registers and bitfields 37 - peripheral base address 38 - peripheral ID 39 - PIO definitions 40 * @{ 41 */ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 /** \defgroup Atmel_glob_defs Atmel Global Defines 48 49 <strong>IO Type Qualifiers</strong> are used 50 \li to specify the access to peripheral variables. 51 \li for automatic generation of peripheral register debug information. 52 53 \remark 54 CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint<size>_t' respective types. 55 Default the header files will follow the CMSIS core syntax. 56 * @{ 57 */ 58 59 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 60 #include <stdint.h> 61 62 /* IO definitions (access restrictions to peripheral registers) */ 63 #ifndef __cplusplus 64 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 65 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 66 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 67 #else 68 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 69 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 70 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 71 #endif 72 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 73 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 74 typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 75 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 76 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 77 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 78 79 #define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ 80 #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ 81 #else /* Assembler */ 82 #define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ 83 #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ 84 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 85 86 #if !defined(SKIP_INTEGER_LITERALS) 87 88 #if defined(_U_) || defined(_L_) || defined(_UL_) 89 #error "Integer Literals macros already defined elsewhere" 90 #endif 91 92 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 93 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */ 94 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 95 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 96 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 97 98 #else /* Assembler */ 99 100 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 101 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 102 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 103 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #endif /* SKIP_INTEGER_LITERALS */ 106 /** @} end of Atmel Global Defines */ 107 108 /** \addtogroup SAMV71N21_cmsis CMSIS Definitions 109 * @{ 110 */ 111 /* ************************************************************************** */ 112 /* CMSIS DEFINITIONS FOR SAMV71N21 */ 113 /* ************************************************************************** */ 114 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 115 /** Interrupt Number Definition */ 116 typedef enum IRQn 117 { 118 /****** CORTEX-M7 Processor Exceptions Numbers ******************************/ 119 Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ 120 NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ 121 HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ 122 MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ 123 BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 124 UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 125 SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ 126 DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ 127 PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ 128 SysTick_IRQn = -1 , /**< 15 System Tick Timer */ 129 /****** SAMV71N21 specific Interrupt Numbers ***********************************/ 130 SUPC_IRQn = 0 , /**< 0 SAMV71N21 Supply Controller (SUPC) */ 131 RSTC_IRQn = 1 , /**< 1 SAMV71N21 Reset Controller (RSTC) */ 132 RTC_IRQn = 2 , /**< 2 SAMV71N21 Real-time Clock (RTC) */ 133 RTT_IRQn = 3 , /**< 3 SAMV71N21 Real-time Timer (RTT) */ 134 WDT_IRQn = 4 , /**< 4 SAMV71N21 Watchdog Timer (WDT) */ 135 PMC_IRQn = 5 , /**< 5 SAMV71N21 Power Management Controller (PMC) */ 136 EFC_IRQn = 6 , /**< 6 SAMV71N21 Embedded Flash Controller (EFC) */ 137 UART0_IRQn = 7 , /**< 7 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART0) */ 138 UART1_IRQn = 8 , /**< 8 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART1) */ 139 PIOA_IRQn = 10 , /**< 10 SAMV71N21 Parallel Input/Output Controller (PIOA) */ 140 PIOB_IRQn = 11 , /**< 11 SAMV71N21 Parallel Input/Output Controller (PIOB) */ 141 USART0_IRQn = 13 , /**< 13 SAMV71N21 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ 142 USART1_IRQn = 14 , /**< 14 SAMV71N21 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ 143 USART2_IRQn = 15 , /**< 15 SAMV71N21 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ 144 PIOD_IRQn = 16 , /**< 16 SAMV71N21 Parallel Input/Output Controller (PIOD) */ 145 HSMCI_IRQn = 18 , /**< 18 SAMV71N21 High Speed MultiMedia Card Interface (HSMCI) */ 146 TWIHS0_IRQn = 19 , /**< 19 SAMV71N21 Two-wire Interface High Speed (TWIHS0) */ 147 TWIHS1_IRQn = 20 , /**< 20 SAMV71N21 Two-wire Interface High Speed (TWIHS1) */ 148 SPI0_IRQn = 21 , /**< 21 SAMV71N21 Serial Peripheral Interface (SPI0) */ 149 SSC_IRQn = 22 , /**< 22 SAMV71N21 Synchronous Serial Controller (SSC) */ 150 TC0_IRQn = 23 , /**< 23 SAMV71N21 Timer Counter (TC0) */ 151 TC1_IRQn = 24 , /**< 24 SAMV71N21 Timer Counter (TC0) */ 152 TC2_IRQn = 25 , /**< 25 SAMV71N21 Timer Counter (TC0) */ 153 TC3_IRQn = 26 , /**< 26 SAMV71N21 Timer Counter (TC1) */ 154 TC4_IRQn = 27 , /**< 27 SAMV71N21 Timer Counter (TC1) */ 155 TC5_IRQn = 28 , /**< 28 SAMV71N21 Timer Counter (TC1) */ 156 AFEC0_IRQn = 29 , /**< 29 SAMV71N21 Analog Front-End Controller (AFEC0) */ 157 PWM0_IRQn = 31 , /**< 31 SAMV71N21 Pulse Width Modulation Controller (PWM0) */ 158 ICM_IRQn = 32 , /**< 32 SAMV71N21 Integrity Check Monitor (ICM) */ 159 ACC_IRQn = 33 , /**< 33 SAMV71N21 Analog Comparator Controller (ACC) */ 160 USBHS_IRQn = 34 , /**< 34 SAMV71N21 USB High-Speed Interface (USBHS) */ 161 MCAN0_INT0_IRQn = 35 , /**< 35 SAMV71N21 Controller Area Network (MCAN0) */ 162 MCAN0_INT1_IRQn = 36 , /**< 36 SAMV71N21 Controller Area Network (MCAN0) */ 163 MCAN1_INT0_IRQn = 37 , /**< 37 SAMV71N21 Controller Area Network (MCAN1) */ 164 MCAN1_INT1_IRQn = 38 , /**< 38 SAMV71N21 Controller Area Network (MCAN1) */ 165 GMAC_IRQn = 39 , /**< 39 SAMV71N21 Gigabit Ethernet MAC (GMAC) */ 166 AFEC1_IRQn = 40 , /**< 40 SAMV71N21 Analog Front-End Controller (AFEC1) */ 167 TWIHS2_IRQn = 41 , /**< 41 SAMV71N21 Two-wire Interface High Speed (TWIHS2) */ 168 QSPI_IRQn = 43 , /**< 43 SAMV71N21 Quad Serial Peripheral Interface (QSPI) */ 169 UART2_IRQn = 44 , /**< 44 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART2) */ 170 UART3_IRQn = 45 , /**< 45 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART3) */ 171 UART4_IRQn = 46 , /**< 46 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART4) */ 172 TC6_IRQn = 47 , /**< 47 SAMV71N21 Timer Counter (TC2) */ 173 TC7_IRQn = 48 , /**< 48 SAMV71N21 Timer Counter (TC2) */ 174 TC8_IRQn = 49 , /**< 49 SAMV71N21 Timer Counter (TC2) */ 175 TC9_IRQn = 50 , /**< 50 SAMV71N21 Timer Counter (TC3) */ 176 TC10_IRQn = 51 , /**< 51 SAMV71N21 Timer Counter (TC3) */ 177 TC11_IRQn = 52 , /**< 52 SAMV71N21 Timer Counter (TC3) */ 178 MLB_IRQn = 53 , /**< 53 SAMV71N21 MediaLB (MLB) */ 179 AES_IRQn = 56 , /**< 56 SAMV71N21 Advanced Encryption Standard (AES) */ 180 TRNG_IRQn = 57 , /**< 57 SAMV71N21 True Random Number Generator (TRNG) */ 181 XDMAC_IRQn = 58 , /**< 58 SAMV71N21 Extensible DMA Controller (XDMAC) */ 182 ISI_IRQn = 59 , /**< 59 SAMV71N21 Image Sensor Interface (ISI) */ 183 PWM1_IRQn = 60 , /**< 60 SAMV71N21 Pulse Width Modulation Controller (PWM1) */ 184 FPU_IRQn = 61 , /**< 61 SAMV71N21 Floating Point Unit (FPU) */ 185 RSWDT_IRQn = 63 , /**< 63 SAMV71N21 Reinforced Safety Watchdog Timer (RSWDT) */ 186 GMAC_Q1_IRQn = 66 , /**< 66 SAMV71N21 Gigabit Ethernet MAC (GMAC) */ 187 GMAC_Q2_IRQn = 67 , /**< 67 SAMV71N21 Gigabit Ethernet MAC (GMAC) */ 188 IXC_IRQn = 68 , /**< 68 SAMV71N21 Floating Point Unit (FPU) */ 189 190 PERIPH_COUNT_IRQn = 69 /**< Number of peripheral IDs */ 191 } IRQn_Type; 192 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 193 194 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 195 typedef struct _DeviceVectors 196 { 197 /* Stack pointer */ 198 void* pvStack; 199 /* Cortex-M handlers */ 200 void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ 201 void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ 202 void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ 203 void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ 204 void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 205 void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 206 void* pvReservedC9; 207 void* pvReservedC8; 208 void* pvReservedC7; 209 void* pvReservedC6; 210 void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ 211 void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ 212 void* pvReservedC3; 213 void* pfnPendSV_Handler; /* -2 Pendable request for system service */ 214 void* pfnSysTick_Handler; /* -1 System Tick Timer */ 215 216 217 /* Peripheral handlers */ 218 void* pfnSUPC_Handler; /* 0 SAMV71N21 Supply Controller (SUPC) */ 219 void* pfnRSTC_Handler; /* 1 SAMV71N21 Reset Controller (RSTC) */ 220 void* pfnRTC_Handler; /* 2 SAMV71N21 Real-time Clock (RTC) */ 221 void* pfnRTT_Handler; /* 3 SAMV71N21 Real-time Timer (RTT) */ 222 void* pfnWDT_Handler; /* 4 SAMV71N21 Watchdog Timer (WDT) */ 223 void* pfnPMC_Handler; /* 5 SAMV71N21 Power Management Controller (PMC) */ 224 void* pfnEFC_Handler; /* 6 SAMV71N21 Embedded Flash Controller (EFC) */ 225 void* pfnUART0_Handler; /* 7 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART0) */ 226 void* pfnUART1_Handler; /* 8 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART1) */ 227 void* pvReserved9; 228 void* pfnPIOA_Handler; /* 10 SAMV71N21 Parallel Input/Output Controller (PIOA) */ 229 void* pfnPIOB_Handler; /* 11 SAMV71N21 Parallel Input/Output Controller (PIOB) */ 230 void* pvReserved12; 231 void* pfnUSART0_Handler; /* 13 SAMV71N21 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ 232 void* pfnUSART1_Handler; /* 14 SAMV71N21 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ 233 void* pfnUSART2_Handler; /* 15 SAMV71N21 Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ 234 void* pfnPIOD_Handler; /* 16 SAMV71N21 Parallel Input/Output Controller (PIOD) */ 235 void* pvReserved17; 236 void* pfnHSMCI_Handler; /* 18 SAMV71N21 High Speed MultiMedia Card Interface (HSMCI) */ 237 void* pfnTWIHS0_Handler; /* 19 SAMV71N21 Two-wire Interface High Speed (TWIHS0) */ 238 void* pfnTWIHS1_Handler; /* 20 SAMV71N21 Two-wire Interface High Speed (TWIHS1) */ 239 void* pfnSPI0_Handler; /* 21 SAMV71N21 Serial Peripheral Interface (SPI0) */ 240 void* pfnSSC_Handler; /* 22 SAMV71N21 Synchronous Serial Controller (SSC) */ 241 void* pfnTC0_Handler; /* 23 SAMV71N21 Timer Counter (TC0) */ 242 void* pfnTC1_Handler; /* 24 SAMV71N21 Timer Counter (TC0) */ 243 void* pfnTC2_Handler; /* 25 SAMV71N21 Timer Counter (TC0) */ 244 void* pfnTC3_Handler; /* 26 SAMV71N21 Timer Counter (TC1) */ 245 void* pfnTC4_Handler; /* 27 SAMV71N21 Timer Counter (TC1) */ 246 void* pfnTC5_Handler; /* 28 SAMV71N21 Timer Counter (TC1) */ 247 void* pfnAFEC0_Handler; /* 29 SAMV71N21 Analog Front-End Controller (AFEC0) */ 248 void* pvReserved30; 249 void* pfnPWM0_Handler; /* 31 SAMV71N21 Pulse Width Modulation Controller (PWM0) */ 250 void* pfnICM_Handler; /* 32 SAMV71N21 Integrity Check Monitor (ICM) */ 251 void* pfnACC_Handler; /* 33 SAMV71N21 Analog Comparator Controller (ACC) */ 252 void* pfnUSBHS_Handler; /* 34 SAMV71N21 USB High-Speed Interface (USBHS) */ 253 void* pfnMCAN0_INT0_Handler; /* 35 SAMV71N21 Controller Area Network (MCAN0) */ 254 void* pfnMCAN0_INT1_Handler; /* 36 SAMV71N21 Controller Area Network (MCAN0) */ 255 void* pfnMCAN1_INT0_Handler; /* 37 SAMV71N21 Controller Area Network (MCAN1) */ 256 void* pfnMCAN1_INT1_Handler; /* 38 SAMV71N21 Controller Area Network (MCAN1) */ 257 void* pfnGMAC_Handler; /* 39 SAMV71N21 Gigabit Ethernet MAC (GMAC) */ 258 void* pfnAFEC1_Handler; /* 40 SAMV71N21 Analog Front-End Controller (AFEC1) */ 259 void* pfnTWIHS2_Handler; /* 41 SAMV71N21 Two-wire Interface High Speed (TWIHS2) */ 260 void* pvReserved42; 261 void* pfnQSPI_Handler; /* 43 SAMV71N21 Quad Serial Peripheral Interface (QSPI) */ 262 void* pfnUART2_Handler; /* 44 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART2) */ 263 void* pfnUART3_Handler; /* 45 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART3) */ 264 void* pfnUART4_Handler; /* 46 SAMV71N21 Universal Asynchronous Receiver Transmitter (UART4) */ 265 void* pfnTC6_Handler; /* 47 SAMV71N21 Timer Counter (TC2) */ 266 void* pfnTC7_Handler; /* 48 SAMV71N21 Timer Counter (TC2) */ 267 void* pfnTC8_Handler; /* 49 SAMV71N21 Timer Counter (TC2) */ 268 void* pfnTC9_Handler; /* 50 SAMV71N21 Timer Counter (TC3) */ 269 void* pfnTC10_Handler; /* 51 SAMV71N21 Timer Counter (TC3) */ 270 void* pfnTC11_Handler; /* 52 SAMV71N21 Timer Counter (TC3) */ 271 void* pfnMLB_Handler; /* 53 SAMV71N21 MediaLB (MLB) */ 272 void* pvReserved54; 273 void* pvReserved55; 274 void* pfnAES_Handler; /* 56 SAMV71N21 Advanced Encryption Standard (AES) */ 275 void* pfnTRNG_Handler; /* 57 SAMV71N21 True Random Number Generator (TRNG) */ 276 void* pfnXDMAC_Handler; /* 58 SAMV71N21 Extensible DMA Controller (XDMAC) */ 277 void* pfnISI_Handler; /* 59 SAMV71N21 Image Sensor Interface (ISI) */ 278 void* pfnPWM1_Handler; /* 60 SAMV71N21 Pulse Width Modulation Controller (PWM1) */ 279 void* pfnFPU_Handler; /* 61 SAMV71N21 Floating Point Unit (FPU) */ 280 void* pvReserved62; 281 void* pfnRSWDT_Handler; /* 63 SAMV71N21 Reinforced Safety Watchdog Timer (RSWDT) */ 282 void* pvReserved64; 283 void* pvReserved65; 284 void* pfnGMAC_Q1_Handler; /* 66 SAMV71N21 Gigabit Ethernet MAC (GMAC) */ 285 void* pfnGMAC_Q2_Handler; /* 67 SAMV71N21 Gigabit Ethernet MAC (GMAC) */ 286 void* pfnIXC_Handler; /* 68 SAMV71N21 Floating Point Unit (FPU) */ 287 } DeviceVectors; 288 289 /* Defines for Deprecated Interrupt and Exceptions handler names */ 290 #define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ 291 #define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ 292 #define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ 293 #define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ 294 295 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 296 297 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 298 #if !defined DONT_USE_PREDEFINED_CORE_HANDLERS 299 300 /* CORTEX-M7 core handlers */ 301 void Reset_Handler ( void ); 302 void NonMaskableInt_Handler ( void ); 303 void HardFault_Handler ( void ); 304 void MemoryManagement_Handler ( void ); 305 void BusFault_Handler ( void ); 306 void UsageFault_Handler ( void ); 307 void SVCall_Handler ( void ); 308 void DebugMonitor_Handler ( void ); 309 void PendSV_Handler ( void ); 310 void SysTick_Handler ( void ); 311 #endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ 312 313 #if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS 314 315 /* Peripherals handlers */ 316 void ACC_Handler ( void ); 317 void AES_Handler ( void ); 318 void AFEC0_Handler ( void ); 319 void AFEC1_Handler ( void ); 320 void EFC_Handler ( void ); 321 void FPU_Handler ( void ); 322 void GMAC_Handler ( void ); 323 void GMAC_Q1_Handler ( void ); 324 void GMAC_Q2_Handler ( void ); 325 void HSMCI_Handler ( void ); 326 void ICM_Handler ( void ); 327 void ISI_Handler ( void ); 328 void IXC_Handler ( void ); 329 void MCAN0_INT0_Handler ( void ); 330 void MCAN0_INT1_Handler ( void ); 331 void MCAN1_INT0_Handler ( void ); 332 void MCAN1_INT1_Handler ( void ); 333 void MLB_Handler ( void ); 334 void PIOA_Handler ( void ); 335 void PIOB_Handler ( void ); 336 void PIOD_Handler ( void ); 337 void PMC_Handler ( void ); 338 void PWM0_Handler ( void ); 339 void PWM1_Handler ( void ); 340 void QSPI_Handler ( void ); 341 void RSTC_Handler ( void ); 342 void RSWDT_Handler ( void ); 343 void RTC_Handler ( void ); 344 void RTT_Handler ( void ); 345 void SPI0_Handler ( void ); 346 void SSC_Handler ( void ); 347 void SUPC_Handler ( void ); 348 void TC0_Handler ( void ); 349 void TC10_Handler ( void ); 350 void TC11_Handler ( void ); 351 void TC1_Handler ( void ); 352 void TC2_Handler ( void ); 353 void TC3_Handler ( void ); 354 void TC4_Handler ( void ); 355 void TC5_Handler ( void ); 356 void TC6_Handler ( void ); 357 void TC7_Handler ( void ); 358 void TC8_Handler ( void ); 359 void TC9_Handler ( void ); 360 void TRNG_Handler ( void ); 361 void TWIHS0_Handler ( void ); 362 void TWIHS1_Handler ( void ); 363 void TWIHS2_Handler ( void ); 364 void UART0_Handler ( void ); 365 void UART1_Handler ( void ); 366 void UART2_Handler ( void ); 367 void UART3_Handler ( void ); 368 void UART4_Handler ( void ); 369 void USART0_Handler ( void ); 370 void USART1_Handler ( void ); 371 void USART2_Handler ( void ); 372 void USBHS_Handler ( void ); 373 void WDT_Handler ( void ); 374 void XDMAC_Handler ( void ); 375 #endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ 376 377 378 /* Defines for Deprecated Interrupt and Exceptions handler names */ 379 #define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ 380 #define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ 381 #define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ 382 #define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ 383 384 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 385 386 387 /* 388 * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals 389 */ 390 391 #define __CM7_REV 0x0101 /**< CM7 Core Revision */ 392 #define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ 393 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ 394 #define __MPU_PRESENT 1 /**< MPU present or not */ 395 #define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ 396 #define __FPU_PRESENT 1 /**< FPU present or not */ 397 #define __FPU_DP 1 /**< Double Precision FPU */ 398 #define __ICACHE_PRESENT 1 /**< Instruction Cache present */ 399 #define __DCACHE_PRESENT 1 /**< Data Cache present */ 400 #define __ITCM_PRESENT 1 /**< Instruction TCM present */ 401 #define __DTCM_PRESENT 1 /**< Data TCM present */ 402 #define __DEBUG_LVL 1 403 #define __TRACE_LVL 1 404 #define __ARCH_ARM 1 405 #define __ARCH_ARM_CORTEX_M 1 406 #define __DEVICE_IS_SAM 1 407 408 /* 409 * \brief CMSIS includes 410 */ 411 #include <core_cm7.h> 412 #if !defined DONT_USE_CMSIS_INIT 413 #include "system_samv71.h" 414 #endif /* DONT_USE_CMSIS_INIT */ 415 416 /** @} end of SAMV71N21_cmsis CMSIS Definitions */ 417 418 /** \defgroup SAMV71N21_api Peripheral Software API 419 * @{ 420 */ 421 422 /* ************************************************************************** */ 423 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N21 */ 424 /* ************************************************************************** */ 425 #include "component/acc.h" 426 #include "component/aes.h" 427 #include "component/afec.h" 428 #include "component/chipid.h" 429 #include "component/efc.h" 430 #include "component/gmac.h" 431 #include "component/gpbr.h" 432 #include "component/hsmci.h" 433 #include "component/icm.h" 434 #include "component/isi.h" 435 #include "component/matrix.h" 436 #include "component/mcan.h" 437 #include "component/mlb.h" 438 #include "component/pio.h" 439 #include "component/pmc.h" 440 #include "component/pwm.h" 441 #include "component/qspi.h" 442 #include "component/rstc.h" 443 #include "component/rswdt.h" 444 #include "component/rtc.h" 445 #include "component/rtt.h" 446 #include "component/spi.h" 447 #include "component/ssc.h" 448 #include "component/supc.h" 449 #include "component/tc.h" 450 #include "component/trng.h" 451 #include "component/twihs.h" 452 #include "component/uart.h" 453 #include "component/usart.h" 454 #include "component/usbhs.h" 455 #include "component/utmi.h" 456 #include "component/wdt.h" 457 #include "component/xdmac.h" 458 /** @} end of Peripheral Software API */ 459 460 /** \defgroup SAMV71N21_reg Registers Access Definitions 461 * @{ 462 */ 463 464 /* ************************************************************************** */ 465 /* REGISTER ACCESS DEFINITIONS FOR SAMV71N21 */ 466 /* ************************************************************************** */ 467 #include "instance/acc.h" 468 #include "instance/aes.h" 469 #include "instance/afec0.h" 470 #include "instance/afec1.h" 471 #include "instance/chipid.h" 472 #include "instance/efc.h" 473 #include "instance/gmac.h" 474 #include "instance/gpbr.h" 475 #include "instance/hsmci.h" 476 #include "instance/icm.h" 477 #include "instance/isi.h" 478 #include "instance/matrix.h" 479 #include "instance/mcan0.h" 480 #include "instance/mcan1.h" 481 #include "instance/mlb.h" 482 #include "instance/pioa.h" 483 #include "instance/piob.h" 484 #include "instance/piod.h" 485 #include "instance/pmc.h" 486 #include "instance/pwm0.h" 487 #include "instance/pwm1.h" 488 #include "instance/qspi.h" 489 #include "instance/rstc.h" 490 #include "instance/rswdt.h" 491 #include "instance/rtc.h" 492 #include "instance/rtt.h" 493 #include "instance/spi0.h" 494 #include "instance/ssc.h" 495 #include "instance/supc.h" 496 #include "instance/tc0.h" 497 #include "instance/tc1.h" 498 #include "instance/tc2.h" 499 #include "instance/tc3.h" 500 #include "instance/trng.h" 501 #include "instance/twihs0.h" 502 #include "instance/twihs1.h" 503 #include "instance/twihs2.h" 504 #include "instance/uart0.h" 505 #include "instance/uart1.h" 506 #include "instance/uart2.h" 507 #include "instance/uart3.h" 508 #include "instance/uart4.h" 509 #include "instance/usart0.h" 510 #include "instance/usart1.h" 511 #include "instance/usart2.h" 512 #include "instance/usbhs.h" 513 #include "instance/utmi.h" 514 #include "instance/wdt.h" 515 #include "instance/xdmac.h" 516 /** @} end of Registers Access Definitions */ 517 518 /** \addtogroup SAMV71N21_id Peripheral Ids Definitions 519 * @{ 520 */ 521 522 /* ************************************************************************** */ 523 /* PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */ 524 /* ************************************************************************** */ 525 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ 526 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ 527 #define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ 528 #define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ 529 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ 530 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ 531 #define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ 532 #define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ 533 #define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ 534 #define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ 535 #define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ 536 #define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ 537 #define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ 538 #define ID_USART2 ( 15) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART2) */ 539 #define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ 540 #define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ 541 #define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ 542 #define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ 543 #define ID_SPI0 ( 21) /**< \brief Serial Peripheral Interface (SPI0) */ 544 #define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ 545 #define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ 546 #define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ 547 #define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ 548 #define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ 549 #define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ 550 #define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ 551 #define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ 552 #define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ 553 #define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ 554 #define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ 555 #define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ 556 #define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ 557 #define ID_MCAN1 ( 37) /**< \brief Controller Area Network (MCAN1) */ 558 #define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ 559 #define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ 560 #define ID_TWIHS2 ( 41) /**< \brief Two-wire Interface High Speed (TWIHS2) */ 561 #define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ 562 #define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ 563 #define ID_UART3 ( 45) /**< \brief Universal Asynchronous Receiver Transmitter (UART3) */ 564 #define ID_UART4 ( 46) /**< \brief Universal Asynchronous Receiver Transmitter (UART4) */ 565 #define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ 566 #define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ 567 #define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ 568 #define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ 569 #define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ 570 #define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ 571 #define ID_MLB ( 53) /**< \brief MediaLB (MLB) */ 572 #define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ 573 #define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ 574 #define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ 575 #define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ 576 #define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ 577 #define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ 578 579 #define ID_PERIPH_COUNT ( 64) /**< \brief Number of peripheral IDs */ 580 /** @} end of Peripheral Ids Definitions */ 581 582 /** \addtogroup legacy_SAMV71N21_id Legacy Peripheral Ids Definitions 583 * @{ 584 */ 585 586 /* ************************************************************************** */ 587 /* LEGACY PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */ 588 /* ************************************************************************** */ 589 #define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 590 #define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 591 #define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 592 #define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 593 #define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 594 #define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 595 #define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 596 #define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 597 #define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 598 #define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 599 #define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 600 #define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 601 /** @} end of Legacy Peripheral Ids Definitions */ 602 603 /** \addtogroup SAMV71N21_base Peripheral Base Address Definitions 604 * @{ 605 */ 606 607 /* ************************************************************************** */ 608 /* BASE ADDRESS DEFINITIONS FOR SAMV71N21 */ 609 /* ************************************************************************** */ 610 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 611 #define ACC (0x40044000) /**< \brief (ACC ) Base Address */ 612 #define AES (0x4006C000) /**< \brief (AES ) Base Address */ 613 #define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ 614 #define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ 615 #define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ 616 #define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ 617 #define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ 618 #define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ 619 #define HSMCI (0x40000000) /**< \brief (HSMCI ) Base Address */ 620 #define ICM (0x40048000) /**< \brief (ICM ) Base Address */ 621 #define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ 622 #define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ 623 #define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ 624 #define MCAN1 (0x40034000) /**< \brief (MCAN1 ) Base Address */ 625 #define MLB (0x40068000) /**< \brief (MLB ) Base Address */ 626 #define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ 627 #define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ 628 #define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ 629 #define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ 630 #define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ 631 #define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ 632 #define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ 633 #define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ 634 #define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ 635 #define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ 636 #define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ 637 #define SPI0 (0x40008000) /**< \brief (SPI0 ) Base Address */ 638 #define SSC (0x40004000) /**< \brief (SSC ) Base Address */ 639 #define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ 640 #define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ 641 #define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ 642 #define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ 643 #define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ 644 #define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ 645 #define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ 646 #define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ 647 #define TWIHS2 (0x40060000) /**< \brief (TWIHS2 ) Base Address */ 648 #define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ 649 #define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ 650 #define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ 651 #define UART3 (0x400E1C00) /**< \brief (UART3 ) Base Address */ 652 #define UART4 (0x400E1E00) /**< \brief (UART4 ) Base Address */ 653 #define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ 654 #define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ 655 #define USART2 (0x4002C000) /**< \brief (USART2 ) Base Address */ 656 #define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ 657 #define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ 658 #define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ 659 #define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ 660 661 #else /* For C/C++ compiler */ 662 663 #define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ 664 #define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ 665 #define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ 666 667 #define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ 668 #define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ 669 #define AES_INSTS { AES } /**< \brief (AES ) Instances List */ 670 671 #define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ 672 #define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ 673 #define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ 674 #define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ 675 676 #define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ 677 #define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ 678 #define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ 679 680 #define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ 681 #define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ 682 #define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ 683 684 #define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ 685 #define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ 686 #define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ 687 688 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ 689 #define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ 690 #define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ 691 692 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ 693 #define HSMCI_INST_NUM 1 /**< \brief (HSMCI ) Number of instances */ 694 #define HSMCI_INSTS { HSMCI } /**< \brief (HSMCI ) Instances List */ 695 696 #define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ 697 #define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ 698 #define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ 699 700 #define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ 701 #define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ 702 #define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ 703 704 #define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ 705 #define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ 706 #define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ 707 708 #define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ 709 #define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ 710 #define MCAN_INST_NUM 2 /**< \brief (MCAN ) Number of instances */ 711 #define MCAN_INSTS { MCAN0, MCAN1 } /**< \brief (MCAN ) Instances List */ 712 713 #define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ 714 #define MLB_INST_NUM 1 /**< \brief (MLB ) Number of instances */ 715 #define MLB_INSTS { MLB } /**< \brief (MLB ) Instances List */ 716 717 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ 718 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ 719 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ 720 #define PIO_INST_NUM 3 /**< \brief (PIO ) Number of instances */ 721 #define PIO_INSTS { PIOA, PIOB, PIOD } /**< \brief (PIO ) Instances List */ 722 723 #define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ 724 #define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ 725 #define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ 726 727 #define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ 728 #define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ 729 #define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ 730 #define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ 731 732 #define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ 733 #define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ 734 #define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ 735 736 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ 737 #define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ 738 #define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ 739 740 #define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ 741 #define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ 742 #define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ 743 744 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ 745 #define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ 746 #define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ 747 748 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ 749 #define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ 750 #define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ 751 752 #define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ 753 #define SPI_INST_NUM 1 /**< \brief (SPI ) Number of instances */ 754 #define SPI_INSTS { SPI0 } /**< \brief (SPI ) Instances List */ 755 756 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ 757 #define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ 758 #define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ 759 760 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ 761 #define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ 762 #define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ 763 764 #define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ 765 #define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ 766 #define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ 767 #define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ 768 #define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ 769 #define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ 770 771 #define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ 772 #define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ 773 #define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ 774 775 #define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ 776 #define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ 777 #define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2 ) Base Address */ 778 #define TWIHS_INST_NUM 3 /**< \brief (TWIHS ) Number of instances */ 779 #define TWIHS_INSTS { TWIHS0, TWIHS1, TWIHS2 } /**< \brief (TWIHS ) Instances List */ 780 781 #define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ 782 #define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ 783 #define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ 784 #define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ 785 #define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ 786 #define UART_INST_NUM 5 /**< \brief (UART ) Number of instances */ 787 #define UART_INSTS { UART0, UART1, UART2, UART3, UART4 } /**< \brief (UART ) Instances List */ 788 789 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ 790 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ 791 #define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2 ) Base Address */ 792 #define USART_INST_NUM 3 /**< \brief (USART ) Number of instances */ 793 #define USART_INSTS { USART0, USART1, USART2 } /**< \brief (USART ) Instances List */ 794 795 #define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ 796 #define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ 797 #define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ 798 799 #define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ 800 #define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ 801 #define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ 802 803 #define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ 804 #define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ 805 #define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ 806 807 #define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ 808 #define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ 809 #define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ 810 811 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 812 /** @} end of Peripheral Base Address Definitions */ 813 814 /** \addtogroup SAMV71N21_pio Peripheral Pio Definitions 815 * @{ 816 */ 817 818 /* ************************************************************************** */ 819 /* PIO DEFINITIONS FOR SAMV71N21*/ 820 /* ************************************************************************** */ 821 #include "pio/samv71n21.h" 822 /** @} end of Peripheral Pio Definitions */ 823 824 /* ************************************************************************** */ 825 /* MEMORY MAPPING DEFINITIONS FOR SAMV71N21*/ 826 /* ************************************************************************** */ 827 828 #define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ 829 #define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ 830 #define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ 831 #define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ 832 #define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ 833 #define IFLASH_SIZE _U_(0x00200000) /* 2048kB Memory segment type: flash */ 834 #define IFLASH_PAGE_SIZE _U_( 512) 835 #define IFLASH_NB_OF_PAGES _U_( 4096) 836 837 #define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ 838 #define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ 839 #define IRAM_SIZE _U_(0x00060000) /* 384kB Memory segment type: ram */ 840 841 #define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ 842 #define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ 843 #define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ 844 #define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ 845 #define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ 846 #define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ 847 #define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ 848 #define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ 849 #define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ 850 851 /* ************************************************************************** */ 852 /** DEVICE SIGNATURES FOR SAMV71N21 */ 853 /* ************************************************************************** */ 854 #define JTAGID _UL_(0X05B3D03F) 855 #define CHIP_JTAGID _UL_(0X05B3D03F) 856 #define CHIP_CIDR _UL_(0XA1220E00) 857 #define CHIP_EXID _UL_(0X00000001) 858 859 /* ************************************************************************** */ 860 /** ELECTRICAL DEFINITIONS FOR SAMV71N21 */ 861 /* ************************************************************************** */ 862 #define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) 863 #define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ 864 #define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) 865 #define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) 866 #define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) 867 #define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) 868 #define CHIP_FREQ_CPU_MAX _UL_(300000000) 869 #define CHIP_FREQ_XTAL_32K _UL_(32768) 870 #define CHIP_FREQ_XTAL_12M _UL_(12000000) 871 #define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ 872 #define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ 873 #define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ 874 #define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ 875 #define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ 876 #define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ 877 #define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ 878 #define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ 879 880 881 882 #ifdef __cplusplus 883 } 884 #endif 885 886 /** @} end of SAMV71N21 definitions */ 887 888 889 #endif /* _SAMV71N21_H_ */ 890
