1 /** 2 * \file 3 * 4 * \brief Instance description for PMC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_PMC_INSTANCE_H_ 32 #define _SAMV71_PMC_INSTANCE_H_ 33 34 /* ========== Register definition for PMC peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_PMC_SCER (0x400E0600) /**< (PMC) System Clock Enable Register */ 38 #define REG_PMC_SCDR (0x400E0604) /**< (PMC) System Clock Disable Register */ 39 #define REG_PMC_SCSR (0x400E0608) /**< (PMC) System Clock Status Register */ 40 #define REG_PMC_PCER0 (0x400E0610) /**< (PMC) Peripheral Clock Enable Register 0 */ 41 #define REG_PMC_PCDR0 (0x400E0614) /**< (PMC) Peripheral Clock Disable Register 0 */ 42 #define REG_PMC_PCSR0 (0x400E0618) /**< (PMC) Peripheral Clock Status Register 0 */ 43 #define REG_CKGR_UCKR (0x400E061C) /**< (PMC) UTMI Clock Register */ 44 #define REG_CKGR_MOR (0x400E0620) /**< (PMC) Main Oscillator Register */ 45 #define REG_CKGR_MCFR (0x400E0624) /**< (PMC) Main Clock Frequency Register */ 46 #define REG_CKGR_PLLAR (0x400E0628) /**< (PMC) PLLA Register */ 47 #define REG_PMC_MCKR (0x400E0630) /**< (PMC) Master Clock Register */ 48 #define REG_PMC_USB (0x400E0638) /**< (PMC) USB Clock Register */ 49 #define REG_PMC_PCK (0x400E0640) /**< (PMC) Programmable Clock Register (chid = 0) 0 */ 50 #define REG_PMC_PCK0 (0x400E0640) /**< (PMC) Programmable Clock Register (chid = 0) 0 */ 51 #define REG_PMC_PCK1 (0x400E0644) /**< (PMC) Programmable Clock Register (chid = 0) 1 */ 52 #define REG_PMC_PCK2 (0x400E0648) /**< (PMC) Programmable Clock Register (chid = 0) 2 */ 53 #define REG_PMC_PCK3 (0x400E064C) /**< (PMC) Programmable Clock Register (chid = 0) 3 */ 54 #define REG_PMC_PCK4 (0x400E0650) /**< (PMC) Programmable Clock Register (chid = 0) 4 */ 55 #define REG_PMC_PCK5 (0x400E0654) /**< (PMC) Programmable Clock Register (chid = 0) 5 */ 56 #define REG_PMC_PCK6 (0x400E0658) /**< (PMC) Programmable Clock Register (chid = 0) 6 */ 57 #define REG_PMC_PCK7 (0x400E065C) /**< (PMC) Programmable Clock Register (chid = 0) 7 */ 58 #define REG_PMC_IER (0x400E0660) /**< (PMC) Interrupt Enable Register */ 59 #define REG_PMC_IDR (0x400E0664) /**< (PMC) Interrupt Disable Register */ 60 #define REG_PMC_SR (0x400E0668) /**< (PMC) Status Register */ 61 #define REG_PMC_IMR (0x400E066C) /**< (PMC) Interrupt Mask Register */ 62 #define REG_PMC_FSMR (0x400E0670) /**< (PMC) Fast Startup Mode Register */ 63 #define REG_PMC_FSPR (0x400E0674) /**< (PMC) Fast Startup Polarity Register */ 64 #define REG_PMC_FOCR (0x400E0678) /**< (PMC) Fault Output Clear Register */ 65 #define REG_PMC_WPMR (0x400E06E4) /**< (PMC) Write Protection Mode Register */ 66 #define REG_PMC_WPSR (0x400E06E8) /**< (PMC) Write Protection Status Register */ 67 #define REG_PMC_VERSION (0x400E06FC) /**< (PMC) Version Register */ 68 #define REG_PMC_PCER1 (0x400E0700) /**< (PMC) Peripheral Clock Enable Register 1 */ 69 #define REG_PMC_PCDR1 (0x400E0704) /**< (PMC) Peripheral Clock Disable Register 1 */ 70 #define REG_PMC_PCSR1 (0x400E0708) /**< (PMC) Peripheral Clock Status Register 1 */ 71 #define REG_PMC_PCR (0x400E070C) /**< (PMC) Peripheral Control Register */ 72 #define REG_PMC_OCR (0x400E0710) /**< (PMC) Oscillator Calibration Register */ 73 #define REG_PMC_SLPWK_ER0 (0x400E0714) /**< (PMC) SleepWalking Enable Register 0 */ 74 #define REG_PMC_SLPWK_DR0 (0x400E0718) /**< (PMC) SleepWalking Disable Register 0 */ 75 #define REG_PMC_SLPWK_SR0 (0x400E071C) /**< (PMC) SleepWalking Status Register 0 */ 76 #define REG_PMC_SLPWK_ASR0 (0x400E0720) /**< (PMC) SleepWalking Activity Status Register 0 */ 77 #define REG_PMC_PMMR (0x400E0730) /**< (PMC) PLL Maximum Multiplier Value Register */ 78 #define REG_PMC_SLPWK_ER1 (0x400E0734) /**< (PMC) SleepWalking Enable Register 1 */ 79 #define REG_PMC_SLPWK_DR1 (0x400E0738) /**< (PMC) SleepWalking Disable Register 1 */ 80 #define REG_PMC_SLPWK_SR1 (0x400E073C) /**< (PMC) SleepWalking Status Register 1 */ 81 #define REG_PMC_SLPWK_ASR1 (0x400E0740) /**< (PMC) SleepWalking Activity Status Register 1 */ 82 #define REG_PMC_SLPWK_AIPR (0x400E0744) /**< (PMC) SleepWalking Activity In Progress Register */ 83 #define REG_PMC_APLLACR (0x400E0758) /**< (PMC) Audio PLL Analog Configuration Register */ 84 #define REG_PMC_WMST (0x400E075C) /**< (PMC) Wait Mode Startup Time Register */ 85 86 #else 87 88 #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< (PMC) System Clock Enable Register */ 89 #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< (PMC) System Clock Disable Register */ 90 #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< (PMC) System Clock Status Register */ 91 #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< (PMC) Peripheral Clock Enable Register 0 */ 92 #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< (PMC) Peripheral Clock Disable Register 0 */ 93 #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< (PMC) Peripheral Clock Status Register 0 */ 94 #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< (PMC) UTMI Clock Register */ 95 #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< (PMC) Main Oscillator Register */ 96 #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< (PMC) Main Clock Frequency Register */ 97 #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< (PMC) PLLA Register */ 98 #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< (PMC) Master Clock Register */ 99 #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< (PMC) USB Clock Register */ 100 #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< (PMC) Programmable Clock Register (chid = 0) 0 */ 101 #define REG_PMC_PCK0 (*(__IO uint32_t*)0x400E0640U) /**< (PMC) Programmable Clock Register (chid = 0) 0 */ 102 #define REG_PMC_PCK1 (*(__IO uint32_t*)0x400E0644U) /**< (PMC) Programmable Clock Register (chid = 0) 1 */ 103 #define REG_PMC_PCK2 (*(__IO uint32_t*)0x400E0648U) /**< (PMC) Programmable Clock Register (chid = 0) 2 */ 104 #define REG_PMC_PCK3 (*(__IO uint32_t*)0x400E064CU) /**< (PMC) Programmable Clock Register (chid = 0) 3 */ 105 #define REG_PMC_PCK4 (*(__IO uint32_t*)0x400E0650U) /**< (PMC) Programmable Clock Register (chid = 0) 4 */ 106 #define REG_PMC_PCK5 (*(__IO uint32_t*)0x400E0654U) /**< (PMC) Programmable Clock Register (chid = 0) 5 */ 107 #define REG_PMC_PCK6 (*(__IO uint32_t*)0x400E0658U) /**< (PMC) Programmable Clock Register (chid = 0) 6 */ 108 #define REG_PMC_PCK7 (*(__IO uint32_t*)0x400E065CU) /**< (PMC) Programmable Clock Register (chid = 0) 7 */ 109 #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< (PMC) Interrupt Enable Register */ 110 #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< (PMC) Interrupt Disable Register */ 111 #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< (PMC) Status Register */ 112 #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< (PMC) Interrupt Mask Register */ 113 #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< (PMC) Fast Startup Mode Register */ 114 #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< (PMC) Fast Startup Polarity Register */ 115 #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< (PMC) Fault Output Clear Register */ 116 #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< (PMC) Write Protection Mode Register */ 117 #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< (PMC) Write Protection Status Register */ 118 #define REG_PMC_VERSION (*(__I uint32_t*)0x400E06FCU) /**< (PMC) Version Register */ 119 #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< (PMC) Peripheral Clock Enable Register 1 */ 120 #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< (PMC) Peripheral Clock Disable Register 1 */ 121 #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< (PMC) Peripheral Clock Status Register 1 */ 122 #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< (PMC) Peripheral Control Register */ 123 #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< (PMC) Oscillator Calibration Register */ 124 #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< (PMC) SleepWalking Enable Register 0 */ 125 #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< (PMC) SleepWalking Disable Register 0 */ 126 #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< (PMC) SleepWalking Status Register 0 */ 127 #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< (PMC) SleepWalking Activity Status Register 0 */ 128 #define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0730U) /**< (PMC) PLL Maximum Multiplier Value Register */ 129 #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< (PMC) SleepWalking Enable Register 1 */ 130 #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< (PMC) SleepWalking Disable Register 1 */ 131 #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< (PMC) SleepWalking Status Register 1 */ 132 #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< (PMC) SleepWalking Activity Status Register 1 */ 133 #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< (PMC) SleepWalking Activity In Progress Register */ 134 #define REG_PMC_APLLACR (*(__IO uint32_t*)0x400E0758U) /**< (PMC) Audio PLL Analog Configuration Register */ 135 #define REG_PMC_WMST (*(__IO uint32_t*)0x400E075CU) /**< (PMC) Wait Mode Startup Time Register */ 136 137 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 138 139 /* ========== Instance Parameter definitions for PMC peripheral ========== */ 140 #define PMC_INSTANCE_ID 5 141 142 #endif /* _SAMV71_PMC_INSTANCE_ */ 143
