1 /** 2 * \file 3 * 4 * \brief Component description for WDT 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_WDT_COMPONENT_H_ 32 #define _SAMV71_WDT_COMPONENT_H_ 33 #define _SAMV71_WDT_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Watchdog Timer 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR WDT */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define WDT_6080 /**< (WDT) Module ID */ 46 #define REV_WDT M /**< (WDT) Module revision */ 47 48 /* -------- WDT_CR : (WDT Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t WDRSTT:1; /**< bit: 0 Watchdog Restart */ 54 uint32_t :23; /**< bit: 1..23 Reserved */ 55 uint32_t KEY:8; /**< bit: 24..31 Password */ 56 } bit; /**< Structure used for bit access */ 57 uint32_t reg; /**< Type used for register access */ 58 } WDT_CR_Type; 59 #endif 60 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 61 62 #define WDT_CR_OFFSET (0x00) /**< (WDT_CR) Control Register Offset */ 63 64 #define WDT_CR_WDRSTT_Pos 0 /**< (WDT_CR) Watchdog Restart Position */ 65 #define WDT_CR_WDRSTT_Msk (_U_(0x1) << WDT_CR_WDRSTT_Pos) /**< (WDT_CR) Watchdog Restart Mask */ 66 #define WDT_CR_WDRSTT WDT_CR_WDRSTT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_CR_WDRSTT_Msk instead */ 67 #define WDT_CR_KEY_Pos 24 /**< (WDT_CR) Password Position */ 68 #define WDT_CR_KEY_Msk (_U_(0xFF) << WDT_CR_KEY_Pos) /**< (WDT_CR) Password Mask */ 69 #define WDT_CR_KEY(value) (WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos)) 70 #define WDT_CR_KEY_PASSWD_Val _U_(0xA5) /**< (WDT_CR) Writing any other value in this field aborts the write operation. */ 71 #define WDT_CR_KEY_PASSWD (WDT_CR_KEY_PASSWD_Val << WDT_CR_KEY_Pos) /**< (WDT_CR) Writing any other value in this field aborts the write operation. Position */ 72 #define WDT_CR_MASK _U_(0xFF000001) /**< \deprecated (WDT_CR) Register MASK (Use WDT_CR_Msk instead) */ 73 #define WDT_CR_Msk _U_(0xFF000001) /**< (WDT_CR) Register Mask */ 74 75 76 /* -------- WDT_MR : (WDT Offset: 0x04) (R/W 32) Mode Register -------- */ 77 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 78 #if COMPONENT_TYPEDEF_STYLE == 'N' 79 typedef union { 80 struct { 81 uint32_t WDV:12; /**< bit: 0..11 Watchdog Counter Value */ 82 uint32_t WDFIEN:1; /**< bit: 12 Watchdog Fault Interrupt Enable */ 83 uint32_t WDRSTEN:1; /**< bit: 13 Watchdog Reset Enable */ 84 uint32_t :1; /**< bit: 14 Reserved */ 85 uint32_t WDDIS:1; /**< bit: 15 Watchdog Disable */ 86 uint32_t WDD:12; /**< bit: 16..27 Watchdog Delta Value */ 87 uint32_t WDDBGHLT:1; /**< bit: 28 Watchdog Debug Halt */ 88 uint32_t WDIDLEHLT:1; /**< bit: 29 Watchdog Idle Halt */ 89 uint32_t :2; /**< bit: 30..31 Reserved */ 90 } bit; /**< Structure used for bit access */ 91 uint32_t reg; /**< Type used for register access */ 92 } WDT_MR_Type; 93 #endif 94 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 96 #define WDT_MR_OFFSET (0x04) /**< (WDT_MR) Mode Register Offset */ 97 98 #define WDT_MR_WDV_Pos 0 /**< (WDT_MR) Watchdog Counter Value Position */ 99 #define WDT_MR_WDV_Msk (_U_(0xFFF) << WDT_MR_WDV_Pos) /**< (WDT_MR) Watchdog Counter Value Mask */ 100 #define WDT_MR_WDV(value) (WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos)) 101 #define WDT_MR_WDFIEN_Pos 12 /**< (WDT_MR) Watchdog Fault Interrupt Enable Position */ 102 #define WDT_MR_WDFIEN_Msk (_U_(0x1) << WDT_MR_WDFIEN_Pos) /**< (WDT_MR) Watchdog Fault Interrupt Enable Mask */ 103 #define WDT_MR_WDFIEN WDT_MR_WDFIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDFIEN_Msk instead */ 104 #define WDT_MR_WDRSTEN_Pos 13 /**< (WDT_MR) Watchdog Reset Enable Position */ 105 #define WDT_MR_WDRSTEN_Msk (_U_(0x1) << WDT_MR_WDRSTEN_Pos) /**< (WDT_MR) Watchdog Reset Enable Mask */ 106 #define WDT_MR_WDRSTEN WDT_MR_WDRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDRSTEN_Msk instead */ 107 #define WDT_MR_WDDIS_Pos 15 /**< (WDT_MR) Watchdog Disable Position */ 108 #define WDT_MR_WDDIS_Msk (_U_(0x1) << WDT_MR_WDDIS_Pos) /**< (WDT_MR) Watchdog Disable Mask */ 109 #define WDT_MR_WDDIS WDT_MR_WDDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDDIS_Msk instead */ 110 #define WDT_MR_WDD_Pos 16 /**< (WDT_MR) Watchdog Delta Value Position */ 111 #define WDT_MR_WDD_Msk (_U_(0xFFF) << WDT_MR_WDD_Pos) /**< (WDT_MR) Watchdog Delta Value Mask */ 112 #define WDT_MR_WDD(value) (WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos)) 113 #define WDT_MR_WDDBGHLT_Pos 28 /**< (WDT_MR) Watchdog Debug Halt Position */ 114 #define WDT_MR_WDDBGHLT_Msk (_U_(0x1) << WDT_MR_WDDBGHLT_Pos) /**< (WDT_MR) Watchdog Debug Halt Mask */ 115 #define WDT_MR_WDDBGHLT WDT_MR_WDDBGHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDDBGHLT_Msk instead */ 116 #define WDT_MR_WDIDLEHLT_Pos 29 /**< (WDT_MR) Watchdog Idle Halt Position */ 117 #define WDT_MR_WDIDLEHLT_Msk (_U_(0x1) << WDT_MR_WDIDLEHLT_Pos) /**< (WDT_MR) Watchdog Idle Halt Mask */ 118 #define WDT_MR_WDIDLEHLT WDT_MR_WDIDLEHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_MR_WDIDLEHLT_Msk instead */ 119 #define WDT_MR_MASK _U_(0x3FFFBFFF) /**< \deprecated (WDT_MR) Register MASK (Use WDT_MR_Msk instead) */ 120 #define WDT_MR_Msk _U_(0x3FFFBFFF) /**< (WDT_MR) Register Mask */ 121 122 123 /* -------- WDT_SR : (WDT Offset: 0x08) (R/ 32) Status Register -------- */ 124 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 125 #if COMPONENT_TYPEDEF_STYLE == 'N' 126 typedef union { 127 struct { 128 uint32_t WDUNF:1; /**< bit: 0 Watchdog Underflow (cleared on read) */ 129 uint32_t WDERR:1; /**< bit: 1 Watchdog Error (cleared on read) */ 130 uint32_t :30; /**< bit: 2..31 Reserved */ 131 } bit; /**< Structure used for bit access */ 132 uint32_t reg; /**< Type used for register access */ 133 } WDT_SR_Type; 134 #endif 135 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 #define WDT_SR_OFFSET (0x08) /**< (WDT_SR) Status Register Offset */ 138 139 #define WDT_SR_WDUNF_Pos 0 /**< (WDT_SR) Watchdog Underflow (cleared on read) Position */ 140 #define WDT_SR_WDUNF_Msk (_U_(0x1) << WDT_SR_WDUNF_Pos) /**< (WDT_SR) Watchdog Underflow (cleared on read) Mask */ 141 #define WDT_SR_WDUNF WDT_SR_WDUNF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_SR_WDUNF_Msk instead */ 142 #define WDT_SR_WDERR_Pos 1 /**< (WDT_SR) Watchdog Error (cleared on read) Position */ 143 #define WDT_SR_WDERR_Msk (_U_(0x1) << WDT_SR_WDERR_Pos) /**< (WDT_SR) Watchdog Error (cleared on read) Mask */ 144 #define WDT_SR_WDERR WDT_SR_WDERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use WDT_SR_WDERR_Msk instead */ 145 #define WDT_SR_MASK _U_(0x03) /**< \deprecated (WDT_SR) Register MASK (Use WDT_SR_Msk instead) */ 146 #define WDT_SR_Msk _U_(0x03) /**< (WDT_SR) Register Mask */ 147 148 149 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 150 #if COMPONENT_TYPEDEF_STYLE == 'R' 151 /** \brief WDT hardware registers */ 152 typedef struct { 153 __O uint32_t WDT_CR; /**< (WDT Offset: 0x00) Control Register */ 154 __IO uint32_t WDT_MR; /**< (WDT Offset: 0x04) Mode Register */ 155 __I uint32_t WDT_SR; /**< (WDT Offset: 0x08) Status Register */ 156 } Wdt; 157 158 #elif COMPONENT_TYPEDEF_STYLE == 'N' 159 /** \brief WDT hardware registers */ 160 typedef struct { 161 __O WDT_CR_Type WDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 162 __IO WDT_MR_Type WDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 163 __I WDT_SR_Type WDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */ 164 } Wdt; 165 166 #else /* COMPONENT_TYPEDEF_STYLE */ 167 #error Unknown component typedef style 168 #endif /* COMPONENT_TYPEDEF_STYLE */ 169 170 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 171 /** @} end of Watchdog Timer */ 172 173 #endif /* _SAMV71_WDT_COMPONENT_H_ */ 174
