1 /** 2 * \file 3 * 4 * \brief Component description for SMC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_SMC_COMPONENT_H_ 32 #define _SAMV71_SMC_COMPONENT_H_ 33 #define _SAMV71_SMC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Static Memory Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR SMC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define SMC_6498 /**< (SMC) Module ID */ 46 #define REV_SMC J /**< (SMC) Module revision */ 47 48 /* -------- SMC_SETUP : (SMC Offset: 0x00) (R/W 32) SMC Setup Register (CS_number = 0) -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t NWE_SETUP:6; /**< bit: 0..5 NWE Setup Length */ 54 uint32_t :2; /**< bit: 6..7 Reserved */ 55 uint32_t NCS_WR_SETUP:6; /**< bit: 8..13 NCS Setup Length in WRITE Access */ 56 uint32_t :2; /**< bit: 14..15 Reserved */ 57 uint32_t NRD_SETUP:6; /**< bit: 16..21 NRD Setup Length */ 58 uint32_t :2; /**< bit: 22..23 Reserved */ 59 uint32_t NCS_RD_SETUP:6; /**< bit: 24..29 NCS Setup Length in READ Access */ 60 uint32_t :2; /**< bit: 30..31 Reserved */ 61 } bit; /**< Structure used for bit access */ 62 uint32_t reg; /**< Type used for register access */ 63 } SMC_SETUP_Type; 64 #endif 65 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 #define SMC_SETUP_OFFSET (0x00) /**< (SMC_SETUP) SMC Setup Register (CS_number = 0) Offset */ 68 69 #define SMC_SETUP_NWE_SETUP_Pos 0 /**< (SMC_SETUP) NWE Setup Length Position */ 70 #define SMC_SETUP_NWE_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NWE_SETUP_Pos) /**< (SMC_SETUP) NWE Setup Length Mask */ 71 #define SMC_SETUP_NWE_SETUP(value) (SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos)) 72 #define SMC_SETUP_NCS_WR_SETUP_Pos 8 /**< (SMC_SETUP) NCS Setup Length in WRITE Access Position */ 73 #define SMC_SETUP_NCS_WR_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_WR_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in WRITE Access Mask */ 74 #define SMC_SETUP_NCS_WR_SETUP(value) (SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos)) 75 #define SMC_SETUP_NRD_SETUP_Pos 16 /**< (SMC_SETUP) NRD Setup Length Position */ 76 #define SMC_SETUP_NRD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NRD_SETUP_Pos) /**< (SMC_SETUP) NRD Setup Length Mask */ 77 #define SMC_SETUP_NRD_SETUP(value) (SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos)) 78 #define SMC_SETUP_NCS_RD_SETUP_Pos 24 /**< (SMC_SETUP) NCS Setup Length in READ Access Position */ 79 #define SMC_SETUP_NCS_RD_SETUP_Msk (_U_(0x3F) << SMC_SETUP_NCS_RD_SETUP_Pos) /**< (SMC_SETUP) NCS Setup Length in READ Access Mask */ 80 #define SMC_SETUP_NCS_RD_SETUP(value) (SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos)) 81 #define SMC_SETUP_MASK _U_(0x3F3F3F3F) /**< \deprecated (SMC_SETUP) Register MASK (Use SMC_SETUP_Msk instead) */ 82 #define SMC_SETUP_Msk _U_(0x3F3F3F3F) /**< (SMC_SETUP) Register Mask */ 83 84 85 /* -------- SMC_PULSE : (SMC Offset: 0x04) (R/W 32) SMC Pulse Register (CS_number = 0) -------- */ 86 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 87 #if COMPONENT_TYPEDEF_STYLE == 'N' 88 typedef union { 89 struct { 90 uint32_t NWE_PULSE:7; /**< bit: 0..6 NWE Pulse Length */ 91 uint32_t :1; /**< bit: 7 Reserved */ 92 uint32_t NCS_WR_PULSE:7; /**< bit: 8..14 NCS Pulse Length in WRITE Access */ 93 uint32_t :1; /**< bit: 15 Reserved */ 94 uint32_t NRD_PULSE:7; /**< bit: 16..22 NRD Pulse Length */ 95 uint32_t :1; /**< bit: 23 Reserved */ 96 uint32_t NCS_RD_PULSE:7; /**< bit: 24..30 NCS Pulse Length in READ Access */ 97 uint32_t :1; /**< bit: 31 Reserved */ 98 } bit; /**< Structure used for bit access */ 99 uint32_t reg; /**< Type used for register access */ 100 } SMC_PULSE_Type; 101 #endif 102 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 #define SMC_PULSE_OFFSET (0x04) /**< (SMC_PULSE) SMC Pulse Register (CS_number = 0) Offset */ 105 106 #define SMC_PULSE_NWE_PULSE_Pos 0 /**< (SMC_PULSE) NWE Pulse Length Position */ 107 #define SMC_PULSE_NWE_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NWE_PULSE_Pos) /**< (SMC_PULSE) NWE Pulse Length Mask */ 108 #define SMC_PULSE_NWE_PULSE(value) (SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos)) 109 #define SMC_PULSE_NCS_WR_PULSE_Pos 8 /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Position */ 110 #define SMC_PULSE_NCS_WR_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_WR_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in WRITE Access Mask */ 111 #define SMC_PULSE_NCS_WR_PULSE(value) (SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos)) 112 #define SMC_PULSE_NRD_PULSE_Pos 16 /**< (SMC_PULSE) NRD Pulse Length Position */ 113 #define SMC_PULSE_NRD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NRD_PULSE_Pos) /**< (SMC_PULSE) NRD Pulse Length Mask */ 114 #define SMC_PULSE_NRD_PULSE(value) (SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos)) 115 #define SMC_PULSE_NCS_RD_PULSE_Pos 24 /**< (SMC_PULSE) NCS Pulse Length in READ Access Position */ 116 #define SMC_PULSE_NCS_RD_PULSE_Msk (_U_(0x7F) << SMC_PULSE_NCS_RD_PULSE_Pos) /**< (SMC_PULSE) NCS Pulse Length in READ Access Mask */ 117 #define SMC_PULSE_NCS_RD_PULSE(value) (SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos)) 118 #define SMC_PULSE_MASK _U_(0x7F7F7F7F) /**< \deprecated (SMC_PULSE) Register MASK (Use SMC_PULSE_Msk instead) */ 119 #define SMC_PULSE_Msk _U_(0x7F7F7F7F) /**< (SMC_PULSE) Register Mask */ 120 121 122 /* -------- SMC_CYCLE : (SMC Offset: 0x08) (R/W 32) SMC Cycle Register (CS_number = 0) -------- */ 123 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 124 #if COMPONENT_TYPEDEF_STYLE == 'N' 125 typedef union { 126 struct { 127 uint32_t NWE_CYCLE:9; /**< bit: 0..8 Total Write Cycle Length */ 128 uint32_t :7; /**< bit: 9..15 Reserved */ 129 uint32_t NRD_CYCLE:9; /**< bit: 16..24 Total Read Cycle Length */ 130 uint32_t :7; /**< bit: 25..31 Reserved */ 131 } bit; /**< Structure used for bit access */ 132 uint32_t reg; /**< Type used for register access */ 133 } SMC_CYCLE_Type; 134 #endif 135 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 #define SMC_CYCLE_OFFSET (0x08) /**< (SMC_CYCLE) SMC Cycle Register (CS_number = 0) Offset */ 138 139 #define SMC_CYCLE_NWE_CYCLE_Pos 0 /**< (SMC_CYCLE) Total Write Cycle Length Position */ 140 #define SMC_CYCLE_NWE_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NWE_CYCLE_Pos) /**< (SMC_CYCLE) Total Write Cycle Length Mask */ 141 #define SMC_CYCLE_NWE_CYCLE(value) (SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos)) 142 #define SMC_CYCLE_NRD_CYCLE_Pos 16 /**< (SMC_CYCLE) Total Read Cycle Length Position */ 143 #define SMC_CYCLE_NRD_CYCLE_Msk (_U_(0x1FF) << SMC_CYCLE_NRD_CYCLE_Pos) /**< (SMC_CYCLE) Total Read Cycle Length Mask */ 144 #define SMC_CYCLE_NRD_CYCLE(value) (SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos)) 145 #define SMC_CYCLE_MASK _U_(0x1FF01FF) /**< \deprecated (SMC_CYCLE) Register MASK (Use SMC_CYCLE_Msk instead) */ 146 #define SMC_CYCLE_Msk _U_(0x1FF01FF) /**< (SMC_CYCLE) Register Mask */ 147 148 149 /* -------- SMC_MODE : (SMC Offset: 0x0c) (R/W 32) SMC Mode Register (CS_number = 0) -------- */ 150 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 151 #if COMPONENT_TYPEDEF_STYLE == 'N' 152 typedef union { 153 struct { 154 uint32_t READ_MODE:1; /**< bit: 0 Read Mode */ 155 uint32_t WRITE_MODE:1; /**< bit: 1 Write Mode */ 156 uint32_t :2; /**< bit: 2..3 Reserved */ 157 uint32_t EXNW_MODE:2; /**< bit: 4..5 NWAIT Mode */ 158 uint32_t :2; /**< bit: 6..7 Reserved */ 159 uint32_t BAT:1; /**< bit: 8 Byte Access Type */ 160 uint32_t :3; /**< bit: 9..11 Reserved */ 161 uint32_t DBW:1; /**< bit: 12 Data Bus Width */ 162 uint32_t :3; /**< bit: 13..15 Reserved */ 163 uint32_t TDF_CYCLES:4; /**< bit: 16..19 Data Float Time */ 164 uint32_t TDF_MODE:1; /**< bit: 20 TDF Optimization */ 165 uint32_t :3; /**< bit: 21..23 Reserved */ 166 uint32_t PMEN:1; /**< bit: 24 Page Mode Enabled */ 167 uint32_t :3; /**< bit: 25..27 Reserved */ 168 uint32_t PS:2; /**< bit: 28..29 Page Size */ 169 uint32_t :2; /**< bit: 30..31 Reserved */ 170 } bit; /**< Structure used for bit access */ 171 uint32_t reg; /**< Type used for register access */ 172 } SMC_MODE_Type; 173 #endif 174 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 #define SMC_MODE_OFFSET (0x0C) /**< (SMC_MODE) SMC Mode Register (CS_number = 0) Offset */ 177 178 #define SMC_MODE_READ_MODE_Pos 0 /**< (SMC_MODE) Read Mode Position */ 179 #define SMC_MODE_READ_MODE_Msk (_U_(0x1) << SMC_MODE_READ_MODE_Pos) /**< (SMC_MODE) Read Mode Mask */ 180 #define SMC_MODE_READ_MODE SMC_MODE_READ_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_READ_MODE_Msk instead */ 181 #define SMC_MODE_WRITE_MODE_Pos 1 /**< (SMC_MODE) Write Mode Position */ 182 #define SMC_MODE_WRITE_MODE_Msk (_U_(0x1) << SMC_MODE_WRITE_MODE_Pos) /**< (SMC_MODE) Write Mode Mask */ 183 #define SMC_MODE_WRITE_MODE SMC_MODE_WRITE_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_WRITE_MODE_Msk instead */ 184 #define SMC_MODE_EXNW_MODE_Pos 4 /**< (SMC_MODE) NWAIT Mode Position */ 185 #define SMC_MODE_EXNW_MODE_Msk (_U_(0x3) << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) NWAIT Mode Mask */ 186 #define SMC_MODE_EXNW_MODE(value) (SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos)) 187 #define SMC_MODE_EXNW_MODE_DISABLED_Val _U_(0x0) /**< (SMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding chip select. */ 188 #define SMC_MODE_EXNW_MODE_FROZEN_Val _U_(0x2) /**< (SMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. */ 189 #define SMC_MODE_EXNW_MODE_READY_Val _U_(0x3) /**< (SMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. */ 190 #define SMC_MODE_EXNW_MODE_DISABLED (SMC_MODE_EXNW_MODE_DISABLED_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Disabled-The NWAIT input signal is ignored on the corresponding chip select. Position */ 191 #define SMC_MODE_EXNW_MODE_FROZEN (SMC_MODE_EXNW_MODE_FROZEN_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Frozen Mode-If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. Position */ 192 #define SMC_MODE_EXNW_MODE_READY (SMC_MODE_EXNW_MODE_READY_Val << SMC_MODE_EXNW_MODE_Pos) /**< (SMC_MODE) Ready Mode-The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high. Position */ 193 #define SMC_MODE_BAT_Pos 8 /**< (SMC_MODE) Byte Access Type Position */ 194 #define SMC_MODE_BAT_Msk (_U_(0x1) << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte Access Type Mask */ 195 #define SMC_MODE_BAT SMC_MODE_BAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_BAT_Msk instead */ 196 #define SMC_MODE_BAT_BYTE_SELECT_Val _U_(0x0) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ 197 #define SMC_MODE_BAT_BYTE_WRITE_Val _U_(0x1) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ 198 #define SMC_MODE_BAT_BYTE_SELECT (SMC_MODE_BAT_BYTE_SELECT_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. Position */ 199 #define SMC_MODE_BAT_BYTE_WRITE (SMC_MODE_BAT_BYTE_WRITE_Val << SMC_MODE_BAT_Pos) /**< (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. Position */ 200 #define SMC_MODE_DBW_Pos 12 /**< (SMC_MODE) Data Bus Width Position */ 201 #define SMC_MODE_DBW_Msk (_U_(0x1) << SMC_MODE_DBW_Pos) /**< (SMC_MODE) Data Bus Width Mask */ 202 #define SMC_MODE_DBW SMC_MODE_DBW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_DBW_Msk instead */ 203 #define SMC_MODE_DBW_8_BIT_Val _U_(0x0) /**< (SMC_MODE) 8-bit Data Bus */ 204 #define SMC_MODE_DBW_16_BIT_Val _U_(0x1) /**< (SMC_MODE) 16-bit Data Bus */ 205 #define SMC_MODE_DBW_8_BIT (SMC_MODE_DBW_8_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 8-bit Data Bus Position */ 206 #define SMC_MODE_DBW_16_BIT (SMC_MODE_DBW_16_BIT_Val << SMC_MODE_DBW_Pos) /**< (SMC_MODE) 16-bit Data Bus Position */ 207 #define SMC_MODE_TDF_CYCLES_Pos 16 /**< (SMC_MODE) Data Float Time Position */ 208 #define SMC_MODE_TDF_CYCLES_Msk (_U_(0xF) << SMC_MODE_TDF_CYCLES_Pos) /**< (SMC_MODE) Data Float Time Mask */ 209 #define SMC_MODE_TDF_CYCLES(value) (SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos)) 210 #define SMC_MODE_TDF_MODE_Pos 20 /**< (SMC_MODE) TDF Optimization Position */ 211 #define SMC_MODE_TDF_MODE_Msk (_U_(0x1) << SMC_MODE_TDF_MODE_Pos) /**< (SMC_MODE) TDF Optimization Mask */ 212 #define SMC_MODE_TDF_MODE SMC_MODE_TDF_MODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_TDF_MODE_Msk instead */ 213 #define SMC_MODE_PMEN_Pos 24 /**< (SMC_MODE) Page Mode Enabled Position */ 214 #define SMC_MODE_PMEN_Msk (_U_(0x1) << SMC_MODE_PMEN_Pos) /**< (SMC_MODE) Page Mode Enabled Mask */ 215 #define SMC_MODE_PMEN SMC_MODE_PMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_MODE_PMEN_Msk instead */ 216 #define SMC_MODE_PS_Pos 28 /**< (SMC_MODE) Page Size Position */ 217 #define SMC_MODE_PS_Msk (_U_(0x3) << SMC_MODE_PS_Pos) /**< (SMC_MODE) Page Size Mask */ 218 #define SMC_MODE_PS(value) (SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos)) 219 #define SMC_MODE_PS_4_BYTE_Val _U_(0x0) /**< (SMC_MODE) 4-byte page */ 220 #define SMC_MODE_PS_8_BYTE_Val _U_(0x1) /**< (SMC_MODE) 8-byte page */ 221 #define SMC_MODE_PS_16_BYTE_Val _U_(0x2) /**< (SMC_MODE) 16-byte page */ 222 #define SMC_MODE_PS_32_BYTE_Val _U_(0x3) /**< (SMC_MODE) 32-byte page */ 223 #define SMC_MODE_PS_4_BYTE (SMC_MODE_PS_4_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 4-byte page Position */ 224 #define SMC_MODE_PS_8_BYTE (SMC_MODE_PS_8_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 8-byte page Position */ 225 #define SMC_MODE_PS_16_BYTE (SMC_MODE_PS_16_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 16-byte page Position */ 226 #define SMC_MODE_PS_32_BYTE (SMC_MODE_PS_32_BYTE_Val << SMC_MODE_PS_Pos) /**< (SMC_MODE) 32-byte page Position */ 227 #define SMC_MODE_MASK _U_(0x311F1133) /**< \deprecated (SMC_MODE) Register MASK (Use SMC_MODE_Msk instead) */ 228 #define SMC_MODE_Msk _U_(0x311F1133) /**< (SMC_MODE) Register Mask */ 229 230 231 /* -------- SMC_OCMS : (SMC Offset: 0x80) (R/W 32) SMC Off-Chip Memory Scrambling Register -------- */ 232 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 233 #if COMPONENT_TYPEDEF_STYLE == 'N' 234 typedef union { 235 struct { 236 uint32_t SMSE:1; /**< bit: 0 Static Memory Controller Scrambling Enable */ 237 uint32_t :7; /**< bit: 1..7 Reserved */ 238 uint32_t CS0SE:1; /**< bit: 8 Chip Select (x = 0 to 3) Scrambling Enable */ 239 uint32_t CS1SE:1; /**< bit: 9 Chip Select (x = 0 to 3) Scrambling Enable */ 240 uint32_t CS2SE:1; /**< bit: 10 Chip Select (x = 0 to 3) Scrambling Enable */ 241 uint32_t CS3SE:1; /**< bit: 11 Chip Select (x = 0 to 3) Scrambling Enable */ 242 uint32_t :20; /**< bit: 12..31 Reserved */ 243 } bit; /**< Structure used for bit access */ 244 uint32_t reg; /**< Type used for register access */ 245 } SMC_OCMS_Type; 246 #endif 247 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 248 249 #define SMC_OCMS_OFFSET (0x80) /**< (SMC_OCMS) SMC Off-Chip Memory Scrambling Register Offset */ 250 251 #define SMC_OCMS_SMSE_Pos 0 /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Position */ 252 #define SMC_OCMS_SMSE_Msk (_U_(0x1) << SMC_OCMS_SMSE_Pos) /**< (SMC_OCMS) Static Memory Controller Scrambling Enable Mask */ 253 #define SMC_OCMS_SMSE SMC_OCMS_SMSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_SMSE_Msk instead */ 254 #define SMC_OCMS_CS0SE_Pos 8 /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ 255 #define SMC_OCMS_CS0SE_Msk (_U_(0x1) << SMC_OCMS_CS0SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ 256 #define SMC_OCMS_CS0SE SMC_OCMS_CS0SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS0SE_Msk instead */ 257 #define SMC_OCMS_CS1SE_Pos 9 /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ 258 #define SMC_OCMS_CS1SE_Msk (_U_(0x1) << SMC_OCMS_CS1SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ 259 #define SMC_OCMS_CS1SE SMC_OCMS_CS1SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS1SE_Msk instead */ 260 #define SMC_OCMS_CS2SE_Pos 10 /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ 261 #define SMC_OCMS_CS2SE_Msk (_U_(0x1) << SMC_OCMS_CS2SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ 262 #define SMC_OCMS_CS2SE SMC_OCMS_CS2SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS2SE_Msk instead */ 263 #define SMC_OCMS_CS3SE_Pos 11 /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Position */ 264 #define SMC_OCMS_CS3SE_Msk (_U_(0x1) << SMC_OCMS_CS3SE_Pos) /**< (SMC_OCMS) Chip Select (x = 0 to 3) Scrambling Enable Mask */ 265 #define SMC_OCMS_CS3SE SMC_OCMS_CS3SE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_OCMS_CS3SE_Msk instead */ 266 #define SMC_OCMS_MASK _U_(0xF01) /**< \deprecated (SMC_OCMS) Register MASK (Use SMC_OCMS_Msk instead) */ 267 #define SMC_OCMS_Msk _U_(0xF01) /**< (SMC_OCMS) Register Mask */ 268 269 270 /* -------- SMC_KEY1 : (SMC Offset: 0x84) (/W 32) SMC Off-Chip Memory Scrambling KEY1 Register -------- */ 271 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 272 #if COMPONENT_TYPEDEF_STYLE == 'N' 273 typedef union { 274 struct { 275 uint32_t KEY1:32; /**< bit: 0..31 Off-Chip Memory Scrambling (OCMS) Key Part 1 */ 276 } bit; /**< Structure used for bit access */ 277 uint32_t reg; /**< Type used for register access */ 278 } SMC_KEY1_Type; 279 #endif 280 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 281 282 #define SMC_KEY1_OFFSET (0x84) /**< (SMC_KEY1) SMC Off-Chip Memory Scrambling KEY1 Register Offset */ 283 284 #define SMC_KEY1_KEY1_Pos 0 /**< (SMC_KEY1) Off-Chip Memory Scrambling (OCMS) Key Part 1 Position */ 285 #define SMC_KEY1_KEY1_Msk (_U_(0xFFFFFFFF) << SMC_KEY1_KEY1_Pos) /**< (SMC_KEY1) Off-Chip Memory Scrambling (OCMS) Key Part 1 Mask */ 286 #define SMC_KEY1_KEY1(value) (SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos)) 287 #define SMC_KEY1_MASK _U_(0xFFFFFFFF) /**< \deprecated (SMC_KEY1) Register MASK (Use SMC_KEY1_Msk instead) */ 288 #define SMC_KEY1_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY1) Register Mask */ 289 290 291 /* -------- SMC_KEY2 : (SMC Offset: 0x88) (/W 32) SMC Off-Chip Memory Scrambling KEY2 Register -------- */ 292 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 293 #if COMPONENT_TYPEDEF_STYLE == 'N' 294 typedef union { 295 struct { 296 uint32_t KEY2:32; /**< bit: 0..31 Off-Chip Memory Scrambling (OCMS) Key Part 2 */ 297 } bit; /**< Structure used for bit access */ 298 uint32_t reg; /**< Type used for register access */ 299 } SMC_KEY2_Type; 300 #endif 301 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 302 303 #define SMC_KEY2_OFFSET (0x88) /**< (SMC_KEY2) SMC Off-Chip Memory Scrambling KEY2 Register Offset */ 304 305 #define SMC_KEY2_KEY2_Pos 0 /**< (SMC_KEY2) Off-Chip Memory Scrambling (OCMS) Key Part 2 Position */ 306 #define SMC_KEY2_KEY2_Msk (_U_(0xFFFFFFFF) << SMC_KEY2_KEY2_Pos) /**< (SMC_KEY2) Off-Chip Memory Scrambling (OCMS) Key Part 2 Mask */ 307 #define SMC_KEY2_KEY2(value) (SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos)) 308 #define SMC_KEY2_MASK _U_(0xFFFFFFFF) /**< \deprecated (SMC_KEY2) Register MASK (Use SMC_KEY2_Msk instead) */ 309 #define SMC_KEY2_Msk _U_(0xFFFFFFFF) /**< (SMC_KEY2) Register Mask */ 310 311 312 /* -------- SMC_WPMR : (SMC Offset: 0xe4) (R/W 32) SMC Write Protection Mode Register -------- */ 313 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 314 #if COMPONENT_TYPEDEF_STYLE == 'N' 315 typedef union { 316 struct { 317 uint32_t WPEN:1; /**< bit: 0 Write Protect Enable */ 318 uint32_t :7; /**< bit: 1..7 Reserved */ 319 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 320 } bit; /**< Structure used for bit access */ 321 uint32_t reg; /**< Type used for register access */ 322 } SMC_WPMR_Type; 323 #endif 324 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 325 326 #define SMC_WPMR_OFFSET (0xE4) /**< (SMC_WPMR) SMC Write Protection Mode Register Offset */ 327 328 #define SMC_WPMR_WPEN_Pos 0 /**< (SMC_WPMR) Write Protect Enable Position */ 329 #define SMC_WPMR_WPEN_Msk (_U_(0x1) << SMC_WPMR_WPEN_Pos) /**< (SMC_WPMR) Write Protect Enable Mask */ 330 #define SMC_WPMR_WPEN SMC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_WPMR_WPEN_Msk instead */ 331 #define SMC_WPMR_WPKEY_Pos 8 /**< (SMC_WPMR) Write Protection Key Position */ 332 #define SMC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Write Protection Key Mask */ 333 #define SMC_WPMR_WPKEY(value) (SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos)) 334 #define SMC_WPMR_WPKEY_PASSWD_Val _U_(0x534D43) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ 335 #define SMC_WPMR_WPKEY_PASSWD (SMC_WPMR_WPKEY_PASSWD_Val << SMC_WPMR_WPKEY_Pos) /**< (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. Position */ 336 #define SMC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (SMC_WPMR) Register MASK (Use SMC_WPMR_Msk instead) */ 337 #define SMC_WPMR_Msk _U_(0xFFFFFF01) /**< (SMC_WPMR) Register Mask */ 338 339 340 /* -------- SMC_WPSR : (SMC Offset: 0xe8) (R/ 32) SMC Write Protection Status Register -------- */ 341 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 342 #if COMPONENT_TYPEDEF_STYLE == 'N' 343 typedef union { 344 struct { 345 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 346 uint32_t :7; /**< bit: 1..7 Reserved */ 347 uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ 348 uint32_t :8; /**< bit: 24..31 Reserved */ 349 } bit; /**< Structure used for bit access */ 350 uint32_t reg; /**< Type used for register access */ 351 } SMC_WPSR_Type; 352 #endif 353 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 354 355 #define SMC_WPSR_OFFSET (0xE8) /**< (SMC_WPSR) SMC Write Protection Status Register Offset */ 356 357 #define SMC_WPSR_WPVS_Pos 0 /**< (SMC_WPSR) Write Protection Violation Status Position */ 358 #define SMC_WPSR_WPVS_Msk (_U_(0x1) << SMC_WPSR_WPVS_Pos) /**< (SMC_WPSR) Write Protection Violation Status Mask */ 359 #define SMC_WPSR_WPVS SMC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SMC_WPSR_WPVS_Msk instead */ 360 #define SMC_WPSR_WPVSRC_Pos 8 /**< (SMC_WPSR) Write Protection Violation Source Position */ 361 #define SMC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SMC_WPSR_WPVSRC_Pos) /**< (SMC_WPSR) Write Protection Violation Source Mask */ 362 #define SMC_WPSR_WPVSRC(value) (SMC_WPSR_WPVSRC_Msk & ((value) << SMC_WPSR_WPVSRC_Pos)) 363 #define SMC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (SMC_WPSR) Register MASK (Use SMC_WPSR_Msk instead) */ 364 #define SMC_WPSR_Msk _U_(0xFFFF01) /**< (SMC_WPSR) Register Mask */ 365 366 367 /* -------- SMC_VERSION : (SMC Offset: 0xfc) (R/ 32) SMC Version Register -------- */ 368 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 369 #if COMPONENT_TYPEDEF_STYLE == 'N' 370 typedef union { 371 struct { 372 uint32_t VERSION:12; /**< bit: 0..11 Hardware Module Version */ 373 uint32_t :4; /**< bit: 12..15 Reserved */ 374 uint32_t MFN:3; /**< bit: 16..18 Metal Fix Number */ 375 uint32_t :13; /**< bit: 19..31 Reserved */ 376 } bit; /**< Structure used for bit access */ 377 uint32_t reg; /**< Type used for register access */ 378 } SMC_VERSION_Type; 379 #endif 380 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 381 382 #define SMC_VERSION_OFFSET (0xFC) /**< (SMC_VERSION) SMC Version Register Offset */ 383 384 #define SMC_VERSION_VERSION_Pos 0 /**< (SMC_VERSION) Hardware Module Version Position */ 385 #define SMC_VERSION_VERSION_Msk (_U_(0xFFF) << SMC_VERSION_VERSION_Pos) /**< (SMC_VERSION) Hardware Module Version Mask */ 386 #define SMC_VERSION_VERSION(value) (SMC_VERSION_VERSION_Msk & ((value) << SMC_VERSION_VERSION_Pos)) 387 #define SMC_VERSION_MFN_Pos 16 /**< (SMC_VERSION) Metal Fix Number Position */ 388 #define SMC_VERSION_MFN_Msk (_U_(0x7) << SMC_VERSION_MFN_Pos) /**< (SMC_VERSION) Metal Fix Number Mask */ 389 #define SMC_VERSION_MFN(value) (SMC_VERSION_MFN_Msk & ((value) << SMC_VERSION_MFN_Pos)) 390 #define SMC_VERSION_MASK _U_(0x70FFF) /**< \deprecated (SMC_VERSION) Register MASK (Use SMC_VERSION_Msk instead) */ 391 #define SMC_VERSION_Msk _U_(0x70FFF) /**< (SMC_VERSION) Register Mask */ 392 393 394 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 395 #if COMPONENT_TYPEDEF_STYLE == 'R' 396 /** \brief SMC_CS_NUMBER hardware registers */ 397 typedef struct { 398 __IO uint32_t SMC_SETUP; /**< (SMC_CS_NUMBER Offset: 0x00) SMC Setup Register (CS_number = 0) */ 399 __IO uint32_t SMC_PULSE; /**< (SMC_CS_NUMBER Offset: 0x04) SMC Pulse Register (CS_number = 0) */ 400 __IO uint32_t SMC_CYCLE; /**< (SMC_CS_NUMBER Offset: 0x08) SMC Cycle Register (CS_number = 0) */ 401 __IO uint32_t SMC_MODE; /**< (SMC_CS_NUMBER Offset: 0x0C) SMC Mode Register (CS_number = 0) */ 402 } SmcCsNumber; 403 404 #define SMCCSNUMBER_NUMBER 4 405 /** \brief SMC hardware registers */ 406 typedef struct { 407 SmcCsNumber SmcCsNumber[SMCCSNUMBER_NUMBER]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ 408 __I uint8_t Reserved1[64]; 409 __IO uint32_t SMC_OCMS; /**< (SMC Offset: 0x80) SMC Off-Chip Memory Scrambling Register */ 410 __O uint32_t SMC_KEY1; /**< (SMC Offset: 0x84) SMC Off-Chip Memory Scrambling KEY1 Register */ 411 __O uint32_t SMC_KEY2; /**< (SMC Offset: 0x88) SMC Off-Chip Memory Scrambling KEY2 Register */ 412 __I uint8_t Reserved2[88]; 413 __IO uint32_t SMC_WPMR; /**< (SMC Offset: 0xE4) SMC Write Protection Mode Register */ 414 __I uint32_t SMC_WPSR; /**< (SMC Offset: 0xE8) SMC Write Protection Status Register */ 415 __I uint8_t Reserved3[16]; 416 __I uint32_t SMC_VERSION; /**< (SMC Offset: 0xFC) SMC Version Register */ 417 } Smc; 418 419 #elif COMPONENT_TYPEDEF_STYLE == 'N' 420 /** \brief SMC_CS_NUMBER hardware registers */ 421 typedef struct { 422 __IO SMC_SETUP_Type SMC_SETUP; /**< Offset: 0x00 (R/W 32) SMC Setup Register (CS_number = 0) */ 423 __IO SMC_PULSE_Type SMC_PULSE; /**< Offset: 0x04 (R/W 32) SMC Pulse Register (CS_number = 0) */ 424 __IO SMC_CYCLE_Type SMC_CYCLE; /**< Offset: 0x08 (R/W 32) SMC Cycle Register (CS_number = 0) */ 425 __IO SMC_MODE_Type SMC_MODE; /**< Offset: 0x0C (R/W 32) SMC Mode Register (CS_number = 0) */ 426 } SmcCsNumber; 427 428 /** \brief SMC hardware registers */ 429 typedef struct { 430 SmcCsNumber SmcCsNumber[4]; /**< Offset: 0x00 SMC Setup Register (CS_number = 0) */ 431 __I uint8_t Reserved1[64]; 432 __IO SMC_OCMS_Type SMC_OCMS; /**< Offset: 0x80 (R/W 32) SMC Off-Chip Memory Scrambling Register */ 433 __O SMC_KEY1_Type SMC_KEY1; /**< Offset: 0x84 ( /W 32) SMC Off-Chip Memory Scrambling KEY1 Register */ 434 __O SMC_KEY2_Type SMC_KEY2; /**< Offset: 0x88 ( /W 32) SMC Off-Chip Memory Scrambling KEY2 Register */ 435 __I uint8_t Reserved2[88]; 436 __IO SMC_WPMR_Type SMC_WPMR; /**< Offset: 0xE4 (R/W 32) SMC Write Protection Mode Register */ 437 __I SMC_WPSR_Type SMC_WPSR; /**< Offset: 0xE8 (R/ 32) SMC Write Protection Status Register */ 438 __I uint8_t Reserved3[16]; 439 __I SMC_VERSION_Type SMC_VERSION; /**< Offset: 0xFC (R/ 32) SMC Version Register */ 440 } Smc; 441 442 #else /* COMPONENT_TYPEDEF_STYLE */ 443 #error Unknown component typedef style 444 #endif /* COMPONENT_TYPEDEF_STYLE */ 445 446 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 447 /** @} end of Static Memory Controller */ 448 449 #endif /* _SAMV71_SMC_COMPONENT_H_ */ 450
