1 /** 2 * \file 3 * 4 * \brief Component description for HSMCI 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_HSMCI_COMPONENT_H_ 32 #define _SAMV71_HSMCI_COMPONENT_H_ 33 #define _SAMV71_HSMCI_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 High Speed MultiMedia Card Interface 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR HSMCI */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define HSMCI_6449 /**< (HSMCI) Module ID */ 46 #define REV_HSMCI Q /**< (HSMCI) Module revision */ 47 48 /* -------- HSMCI_CR : (HSMCI Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t MCIEN:1; /**< bit: 0 Multi-Media Interface Enable */ 54 uint32_t MCIDIS:1; /**< bit: 1 Multi-Media Interface Disable */ 55 uint32_t PWSEN:1; /**< bit: 2 Power Save Mode Enable */ 56 uint32_t PWSDIS:1; /**< bit: 3 Power Save Mode Disable */ 57 uint32_t :3; /**< bit: 4..6 Reserved */ 58 uint32_t SWRST:1; /**< bit: 7 Software Reset */ 59 uint32_t :24; /**< bit: 8..31 Reserved */ 60 } bit; /**< Structure used for bit access */ 61 uint32_t reg; /**< Type used for register access */ 62 } HSMCI_CR_Type; 63 #endif 64 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 65 66 #define HSMCI_CR_OFFSET (0x00) /**< (HSMCI_CR) Control Register Offset */ 67 68 #define HSMCI_CR_MCIEN_Pos 0 /**< (HSMCI_CR) Multi-Media Interface Enable Position */ 69 #define HSMCI_CR_MCIEN_Msk (_U_(0x1) << HSMCI_CR_MCIEN_Pos) /**< (HSMCI_CR) Multi-Media Interface Enable Mask */ 70 #define HSMCI_CR_MCIEN HSMCI_CR_MCIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_MCIEN_Msk instead */ 71 #define HSMCI_CR_MCIDIS_Pos 1 /**< (HSMCI_CR) Multi-Media Interface Disable Position */ 72 #define HSMCI_CR_MCIDIS_Msk (_U_(0x1) << HSMCI_CR_MCIDIS_Pos) /**< (HSMCI_CR) Multi-Media Interface Disable Mask */ 73 #define HSMCI_CR_MCIDIS HSMCI_CR_MCIDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_MCIDIS_Msk instead */ 74 #define HSMCI_CR_PWSEN_Pos 2 /**< (HSMCI_CR) Power Save Mode Enable Position */ 75 #define HSMCI_CR_PWSEN_Msk (_U_(0x1) << HSMCI_CR_PWSEN_Pos) /**< (HSMCI_CR) Power Save Mode Enable Mask */ 76 #define HSMCI_CR_PWSEN HSMCI_CR_PWSEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_PWSEN_Msk instead */ 77 #define HSMCI_CR_PWSDIS_Pos 3 /**< (HSMCI_CR) Power Save Mode Disable Position */ 78 #define HSMCI_CR_PWSDIS_Msk (_U_(0x1) << HSMCI_CR_PWSDIS_Pos) /**< (HSMCI_CR) Power Save Mode Disable Mask */ 79 #define HSMCI_CR_PWSDIS HSMCI_CR_PWSDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_PWSDIS_Msk instead */ 80 #define HSMCI_CR_SWRST_Pos 7 /**< (HSMCI_CR) Software Reset Position */ 81 #define HSMCI_CR_SWRST_Msk (_U_(0x1) << HSMCI_CR_SWRST_Pos) /**< (HSMCI_CR) Software Reset Mask */ 82 #define HSMCI_CR_SWRST HSMCI_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CR_SWRST_Msk instead */ 83 #define HSMCI_CR_MASK _U_(0x8F) /**< \deprecated (HSMCI_CR) Register MASK (Use HSMCI_CR_Msk instead) */ 84 #define HSMCI_CR_Msk _U_(0x8F) /**< (HSMCI_CR) Register Mask */ 85 86 87 /* -------- HSMCI_MR : (HSMCI Offset: 0x04) (R/W 32) Mode Register -------- */ 88 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 89 #if COMPONENT_TYPEDEF_STYLE == 'N' 90 typedef union { 91 struct { 92 uint32_t CLKDIV:8; /**< bit: 0..7 Clock Divider */ 93 uint32_t PWSDIV:3; /**< bit: 8..10 Power Saving Divider */ 94 uint32_t RDPROOF:1; /**< bit: 11 Read Proof Enable */ 95 uint32_t WRPROOF:1; /**< bit: 12 Write Proof Enable */ 96 uint32_t FBYTE:1; /**< bit: 13 Force Byte Transfer */ 97 uint32_t PADV:1; /**< bit: 14 Padding Value */ 98 uint32_t :1; /**< bit: 15 Reserved */ 99 uint32_t CLKODD:1; /**< bit: 16 Clock divider is odd */ 100 uint32_t :15; /**< bit: 17..31 Reserved */ 101 } bit; /**< Structure used for bit access */ 102 uint32_t reg; /**< Type used for register access */ 103 } HSMCI_MR_Type; 104 #endif 105 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 106 107 #define HSMCI_MR_OFFSET (0x04) /**< (HSMCI_MR) Mode Register Offset */ 108 109 #define HSMCI_MR_CLKDIV_Pos 0 /**< (HSMCI_MR) Clock Divider Position */ 110 #define HSMCI_MR_CLKDIV_Msk (_U_(0xFF) << HSMCI_MR_CLKDIV_Pos) /**< (HSMCI_MR) Clock Divider Mask */ 111 #define HSMCI_MR_CLKDIV(value) (HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos)) 112 #define HSMCI_MR_PWSDIV_Pos 8 /**< (HSMCI_MR) Power Saving Divider Position */ 113 #define HSMCI_MR_PWSDIV_Msk (_U_(0x7) << HSMCI_MR_PWSDIV_Pos) /**< (HSMCI_MR) Power Saving Divider Mask */ 114 #define HSMCI_MR_PWSDIV(value) (HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos)) 115 #define HSMCI_MR_RDPROOF_Pos 11 /**< (HSMCI_MR) Read Proof Enable Position */ 116 #define HSMCI_MR_RDPROOF_Msk (_U_(0x1) << HSMCI_MR_RDPROOF_Pos) /**< (HSMCI_MR) Read Proof Enable Mask */ 117 #define HSMCI_MR_RDPROOF HSMCI_MR_RDPROOF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_RDPROOF_Msk instead */ 118 #define HSMCI_MR_WRPROOF_Pos 12 /**< (HSMCI_MR) Write Proof Enable Position */ 119 #define HSMCI_MR_WRPROOF_Msk (_U_(0x1) << HSMCI_MR_WRPROOF_Pos) /**< (HSMCI_MR) Write Proof Enable Mask */ 120 #define HSMCI_MR_WRPROOF HSMCI_MR_WRPROOF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_WRPROOF_Msk instead */ 121 #define HSMCI_MR_FBYTE_Pos 13 /**< (HSMCI_MR) Force Byte Transfer Position */ 122 #define HSMCI_MR_FBYTE_Msk (_U_(0x1) << HSMCI_MR_FBYTE_Pos) /**< (HSMCI_MR) Force Byte Transfer Mask */ 123 #define HSMCI_MR_FBYTE HSMCI_MR_FBYTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_FBYTE_Msk instead */ 124 #define HSMCI_MR_PADV_Pos 14 /**< (HSMCI_MR) Padding Value Position */ 125 #define HSMCI_MR_PADV_Msk (_U_(0x1) << HSMCI_MR_PADV_Pos) /**< (HSMCI_MR) Padding Value Mask */ 126 #define HSMCI_MR_PADV HSMCI_MR_PADV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_PADV_Msk instead */ 127 #define HSMCI_MR_CLKODD_Pos 16 /**< (HSMCI_MR) Clock divider is odd Position */ 128 #define HSMCI_MR_CLKODD_Msk (_U_(0x1) << HSMCI_MR_CLKODD_Pos) /**< (HSMCI_MR) Clock divider is odd Mask */ 129 #define HSMCI_MR_CLKODD HSMCI_MR_CLKODD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_MR_CLKODD_Msk instead */ 130 #define HSMCI_MR_MASK _U_(0x17FFF) /**< \deprecated (HSMCI_MR) Register MASK (Use HSMCI_MR_Msk instead) */ 131 #define HSMCI_MR_Msk _U_(0x17FFF) /**< (HSMCI_MR) Register Mask */ 132 133 134 /* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) (R/W 32) Data Timeout Register -------- */ 135 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 136 #if COMPONENT_TYPEDEF_STYLE == 'N' 137 typedef union { 138 struct { 139 uint32_t DTOCYC:4; /**< bit: 0..3 Data Timeout Cycle Number */ 140 uint32_t DTOMUL:3; /**< bit: 4..6 Data Timeout Multiplier */ 141 uint32_t :25; /**< bit: 7..31 Reserved */ 142 } bit; /**< Structure used for bit access */ 143 uint32_t reg; /**< Type used for register access */ 144 } HSMCI_DTOR_Type; 145 #endif 146 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 147 148 #define HSMCI_DTOR_OFFSET (0x08) /**< (HSMCI_DTOR) Data Timeout Register Offset */ 149 150 #define HSMCI_DTOR_DTOCYC_Pos 0 /**< (HSMCI_DTOR) Data Timeout Cycle Number Position */ 151 #define HSMCI_DTOR_DTOCYC_Msk (_U_(0xF) << HSMCI_DTOR_DTOCYC_Pos) /**< (HSMCI_DTOR) Data Timeout Cycle Number Mask */ 152 #define HSMCI_DTOR_DTOCYC(value) (HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos)) 153 #define HSMCI_DTOR_DTOMUL_Pos 4 /**< (HSMCI_DTOR) Data Timeout Multiplier Position */ 154 #define HSMCI_DTOR_DTOMUL_Msk (_U_(0x7) << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) Data Timeout Multiplier Mask */ 155 #define HSMCI_DTOR_DTOMUL(value) (HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos)) 156 #define HSMCI_DTOR_DTOMUL_1_Val _U_(0x0) /**< (HSMCI_DTOR) DTOCYC */ 157 #define HSMCI_DTOR_DTOMUL_16_Val _U_(0x1) /**< (HSMCI_DTOR) DTOCYC x 16 */ 158 #define HSMCI_DTOR_DTOMUL_128_Val _U_(0x2) /**< (HSMCI_DTOR) DTOCYC x 128 */ 159 #define HSMCI_DTOR_DTOMUL_256_Val _U_(0x3) /**< (HSMCI_DTOR) DTOCYC x 256 */ 160 #define HSMCI_DTOR_DTOMUL_1024_Val _U_(0x4) /**< (HSMCI_DTOR) DTOCYC x 1024 */ 161 #define HSMCI_DTOR_DTOMUL_4096_Val _U_(0x5) /**< (HSMCI_DTOR) DTOCYC x 4096 */ 162 #define HSMCI_DTOR_DTOMUL_65536_Val _U_(0x6) /**< (HSMCI_DTOR) DTOCYC x 65536 */ 163 #define HSMCI_DTOR_DTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_DTOR) DTOCYC x 1048576 */ 164 #define HSMCI_DTOR_DTOMUL_1 (HSMCI_DTOR_DTOMUL_1_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC Position */ 165 #define HSMCI_DTOR_DTOMUL_16 (HSMCI_DTOR_DTOMUL_16_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 16 Position */ 166 #define HSMCI_DTOR_DTOMUL_128 (HSMCI_DTOR_DTOMUL_128_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 128 Position */ 167 #define HSMCI_DTOR_DTOMUL_256 (HSMCI_DTOR_DTOMUL_256_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 256 Position */ 168 #define HSMCI_DTOR_DTOMUL_1024 (HSMCI_DTOR_DTOMUL_1024_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1024 Position */ 169 #define HSMCI_DTOR_DTOMUL_4096 (HSMCI_DTOR_DTOMUL_4096_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 4096 Position */ 170 #define HSMCI_DTOR_DTOMUL_65536 (HSMCI_DTOR_DTOMUL_65536_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 65536 Position */ 171 #define HSMCI_DTOR_DTOMUL_1048576 (HSMCI_DTOR_DTOMUL_1048576_Val << HSMCI_DTOR_DTOMUL_Pos) /**< (HSMCI_DTOR) DTOCYC x 1048576 Position */ 172 #define HSMCI_DTOR_MASK _U_(0x7F) /**< \deprecated (HSMCI_DTOR) Register MASK (Use HSMCI_DTOR_Msk instead) */ 173 #define HSMCI_DTOR_Msk _U_(0x7F) /**< (HSMCI_DTOR) Register Mask */ 174 175 176 /* -------- HSMCI_SDCR : (HSMCI Offset: 0x0c) (R/W 32) SD/SDIO Card Register -------- */ 177 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 178 #if COMPONENT_TYPEDEF_STYLE == 'N' 179 typedef union { 180 struct { 181 uint32_t SDCSEL:2; /**< bit: 0..1 SDCard/SDIO Slot */ 182 uint32_t :4; /**< bit: 2..5 Reserved */ 183 uint32_t SDCBUS:2; /**< bit: 6..7 SDCard/SDIO Bus Width */ 184 uint32_t :24; /**< bit: 8..31 Reserved */ 185 } bit; /**< Structure used for bit access */ 186 uint32_t reg; /**< Type used for register access */ 187 } HSMCI_SDCR_Type; 188 #endif 189 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 190 191 #define HSMCI_SDCR_OFFSET (0x0C) /**< (HSMCI_SDCR) SD/SDIO Card Register Offset */ 192 193 #define HSMCI_SDCR_SDCSEL_Pos 0 /**< (HSMCI_SDCR) SDCard/SDIO Slot Position */ 194 #define HSMCI_SDCR_SDCSEL_Msk (_U_(0x3) << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Slot Mask */ 195 #define HSMCI_SDCR_SDCSEL(value) (HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos)) 196 #define HSMCI_SDCR_SDCSEL_SLOTA_Val _U_(0x0) /**< (HSMCI_SDCR) Slot A is selected. */ 197 #define HSMCI_SDCR_SDCSEL_SLOTA (HSMCI_SDCR_SDCSEL_SLOTA_Val << HSMCI_SDCR_SDCSEL_Pos) /**< (HSMCI_SDCR) Slot A is selected. Position */ 198 #define HSMCI_SDCR_SDCBUS_Pos 6 /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Position */ 199 #define HSMCI_SDCR_SDCBUS_Msk (_U_(0x3) << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) SDCard/SDIO Bus Width Mask */ 200 #define HSMCI_SDCR_SDCBUS(value) (HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos)) 201 #define HSMCI_SDCR_SDCBUS_1_Val _U_(0x0) /**< (HSMCI_SDCR) 1 bit */ 202 #define HSMCI_SDCR_SDCBUS_4_Val _U_(0x2) /**< (HSMCI_SDCR) 4 bits */ 203 #define HSMCI_SDCR_SDCBUS_8_Val _U_(0x3) /**< (HSMCI_SDCR) 8 bits */ 204 #define HSMCI_SDCR_SDCBUS_1 (HSMCI_SDCR_SDCBUS_1_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 1 bit Position */ 205 #define HSMCI_SDCR_SDCBUS_4 (HSMCI_SDCR_SDCBUS_4_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 4 bits Position */ 206 #define HSMCI_SDCR_SDCBUS_8 (HSMCI_SDCR_SDCBUS_8_Val << HSMCI_SDCR_SDCBUS_Pos) /**< (HSMCI_SDCR) 8 bits Position */ 207 #define HSMCI_SDCR_MASK _U_(0xC3) /**< \deprecated (HSMCI_SDCR) Register MASK (Use HSMCI_SDCR_Msk instead) */ 208 #define HSMCI_SDCR_Msk _U_(0xC3) /**< (HSMCI_SDCR) Register Mask */ 209 210 211 /* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) (R/W 32) Argument Register -------- */ 212 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 213 #if COMPONENT_TYPEDEF_STYLE == 'N' 214 typedef union { 215 struct { 216 uint32_t ARG:32; /**< bit: 0..31 Command Argument */ 217 } bit; /**< Structure used for bit access */ 218 uint32_t reg; /**< Type used for register access */ 219 } HSMCI_ARGR_Type; 220 #endif 221 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 222 223 #define HSMCI_ARGR_OFFSET (0x10) /**< (HSMCI_ARGR) Argument Register Offset */ 224 225 #define HSMCI_ARGR_ARG_Pos 0 /**< (HSMCI_ARGR) Command Argument Position */ 226 #define HSMCI_ARGR_ARG_Msk (_U_(0xFFFFFFFF) << HSMCI_ARGR_ARG_Pos) /**< (HSMCI_ARGR) Command Argument Mask */ 227 #define HSMCI_ARGR_ARG(value) (HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos)) 228 #define HSMCI_ARGR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_ARGR) Register MASK (Use HSMCI_ARGR_Msk instead) */ 229 #define HSMCI_ARGR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_ARGR) Register Mask */ 230 231 232 /* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) (/W 32) Command Register -------- */ 233 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 234 #if COMPONENT_TYPEDEF_STYLE == 'N' 235 typedef union { 236 struct { 237 uint32_t CMDNB:6; /**< bit: 0..5 Command Number */ 238 uint32_t RSPTYP:2; /**< bit: 6..7 Response Type */ 239 uint32_t SPCMD:3; /**< bit: 8..10 Special Command */ 240 uint32_t OPDCMD:1; /**< bit: 11 Open Drain Command */ 241 uint32_t MAXLAT:1; /**< bit: 12 Max Latency for Command to Response */ 242 uint32_t :3; /**< bit: 13..15 Reserved */ 243 uint32_t TRCMD:2; /**< bit: 16..17 Transfer Command */ 244 uint32_t TRDIR:1; /**< bit: 18 Transfer Direction */ 245 uint32_t TRTYP:3; /**< bit: 19..21 Transfer Type */ 246 uint32_t :2; /**< bit: 22..23 Reserved */ 247 uint32_t IOSPCMD:2; /**< bit: 24..25 SDIO Special Command */ 248 uint32_t ATACS:1; /**< bit: 26 ATA with Command Completion Signal */ 249 uint32_t BOOT_ACK:1; /**< bit: 27 Boot Operation Acknowledge */ 250 uint32_t :4; /**< bit: 28..31 Reserved */ 251 } bit; /**< Structure used for bit access */ 252 uint32_t reg; /**< Type used for register access */ 253 } HSMCI_CMDR_Type; 254 #endif 255 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 256 257 #define HSMCI_CMDR_OFFSET (0x14) /**< (HSMCI_CMDR) Command Register Offset */ 258 259 #define HSMCI_CMDR_CMDNB_Pos 0 /**< (HSMCI_CMDR) Command Number Position */ 260 #define HSMCI_CMDR_CMDNB_Msk (_U_(0x3F) << HSMCI_CMDR_CMDNB_Pos) /**< (HSMCI_CMDR) Command Number Mask */ 261 #define HSMCI_CMDR_CMDNB(value) (HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos)) 262 #define HSMCI_CMDR_RSPTYP_Pos 6 /**< (HSMCI_CMDR) Response Type Position */ 263 #define HSMCI_CMDR_RSPTYP_Msk (_U_(0x3) << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) Response Type Mask */ 264 #define HSMCI_CMDR_RSPTYP(value) (HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos)) 265 #define HSMCI_CMDR_RSPTYP_NORESP_Val _U_(0x0) /**< (HSMCI_CMDR) No response */ 266 #define HSMCI_CMDR_RSPTYP_48_BIT_Val _U_(0x1) /**< (HSMCI_CMDR) 48-bit response */ 267 #define HSMCI_CMDR_RSPTYP_136_BIT_Val _U_(0x2) /**< (HSMCI_CMDR) 136-bit response */ 268 #define HSMCI_CMDR_RSPTYP_R1B_Val _U_(0x3) /**< (HSMCI_CMDR) R1b response type */ 269 #define HSMCI_CMDR_RSPTYP_NORESP (HSMCI_CMDR_RSPTYP_NORESP_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) No response Position */ 270 #define HSMCI_CMDR_RSPTYP_48_BIT (HSMCI_CMDR_RSPTYP_48_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 48-bit response Position */ 271 #define HSMCI_CMDR_RSPTYP_136_BIT (HSMCI_CMDR_RSPTYP_136_BIT_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) 136-bit response Position */ 272 #define HSMCI_CMDR_RSPTYP_R1B (HSMCI_CMDR_RSPTYP_R1B_Val << HSMCI_CMDR_RSPTYP_Pos) /**< (HSMCI_CMDR) R1b response type Position */ 273 #define HSMCI_CMDR_SPCMD_Pos 8 /**< (HSMCI_CMDR) Special Command Position */ 274 #define HSMCI_CMDR_SPCMD_Msk (_U_(0x7) << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Special Command Mask */ 275 #define HSMCI_CMDR_SPCMD(value) (HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos)) 276 #define HSMCI_CMDR_SPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not a special CMD. */ 277 #define HSMCI_CMDR_SPCMD_INIT_Val _U_(0x1) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ 278 #define HSMCI_CMDR_SPCMD_SYNC_Val _U_(0x2) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ 279 #define HSMCI_CMDR_SPCMD_CE_ATA_Val _U_(0x3) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ 280 #define HSMCI_CMDR_SPCMD_IT_CMD_Val _U_(0x4) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ 281 #define HSMCI_CMDR_SPCMD_IT_RESP_Val _U_(0x5) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ 282 #define HSMCI_CMDR_SPCMD_BOR_Val _U_(0x6) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ 283 #define HSMCI_CMDR_SPCMD_EBO_Val _U_(0x7) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ 284 #define HSMCI_CMDR_SPCMD_STD (HSMCI_CMDR_SPCMD_STD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Not a special CMD. Position */ 285 #define HSMCI_CMDR_SPCMD_INIT (HSMCI_CMDR_SPCMD_INIT_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. Position */ 286 #define HSMCI_CMDR_SPCMD_SYNC (HSMCI_CMDR_SPCMD_SYNC_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. Position */ 287 #define HSMCI_CMDR_SPCMD_CE_ATA (HSMCI_CMDR_SPCMD_CE_ATA_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. Position */ 288 #define HSMCI_CMDR_SPCMD_IT_CMD (HSMCI_CMDR_SPCMD_IT_CMD_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). Position */ 289 #define HSMCI_CMDR_SPCMD_IT_RESP (HSMCI_CMDR_SPCMD_IT_RESP_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). Position */ 290 #define HSMCI_CMDR_SPCMD_BOR (HSMCI_CMDR_SPCMD_BOR_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. Position */ 291 #define HSMCI_CMDR_SPCMD_EBO (HSMCI_CMDR_SPCMD_EBO_Val << HSMCI_CMDR_SPCMD_Pos) /**< (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. Position */ 292 #define HSMCI_CMDR_OPDCMD_Pos 11 /**< (HSMCI_CMDR) Open Drain Command Position */ 293 #define HSMCI_CMDR_OPDCMD_Msk (_U_(0x1) << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open Drain Command Mask */ 294 #define HSMCI_CMDR_OPDCMD HSMCI_CMDR_OPDCMD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_OPDCMD_Msk instead */ 295 #define HSMCI_CMDR_OPDCMD_PUSHPULL_Val _U_(0x0) /**< (HSMCI_CMDR) Push pull command. */ 296 #define HSMCI_CMDR_OPDCMD_OPENDRAIN_Val _U_(0x1) /**< (HSMCI_CMDR) Open drain command. */ 297 #define HSMCI_CMDR_OPDCMD_PUSHPULL (HSMCI_CMDR_OPDCMD_PUSHPULL_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Push pull command. Position */ 298 #define HSMCI_CMDR_OPDCMD_OPENDRAIN (HSMCI_CMDR_OPDCMD_OPENDRAIN_Val << HSMCI_CMDR_OPDCMD_Pos) /**< (HSMCI_CMDR) Open drain command. Position */ 299 #define HSMCI_CMDR_MAXLAT_Pos 12 /**< (HSMCI_CMDR) Max Latency for Command to Response Position */ 300 #define HSMCI_CMDR_MAXLAT_Msk (_U_(0x1) << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) Max Latency for Command to Response Mask */ 301 #define HSMCI_CMDR_MAXLAT HSMCI_CMDR_MAXLAT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_MAXLAT_Msk instead */ 302 #define HSMCI_CMDR_MAXLAT_5_Val _U_(0x0) /**< (HSMCI_CMDR) 5-cycle max latency. */ 303 #define HSMCI_CMDR_MAXLAT_64_Val _U_(0x1) /**< (HSMCI_CMDR) 64-cycle max latency. */ 304 #define HSMCI_CMDR_MAXLAT_5 (HSMCI_CMDR_MAXLAT_5_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 5-cycle max latency. Position */ 305 #define HSMCI_CMDR_MAXLAT_64 (HSMCI_CMDR_MAXLAT_64_Val << HSMCI_CMDR_MAXLAT_Pos) /**< (HSMCI_CMDR) 64-cycle max latency. Position */ 306 #define HSMCI_CMDR_TRCMD_Pos 16 /**< (HSMCI_CMDR) Transfer Command Position */ 307 #define HSMCI_CMDR_TRCMD_Msk (_U_(0x3) << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Transfer Command Mask */ 308 #define HSMCI_CMDR_TRCMD(value) (HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos)) 309 #define HSMCI_CMDR_TRCMD_NO_DATA_Val _U_(0x0) /**< (HSMCI_CMDR) No data transfer */ 310 #define HSMCI_CMDR_TRCMD_START_DATA_Val _U_(0x1) /**< (HSMCI_CMDR) Start data transfer */ 311 #define HSMCI_CMDR_TRCMD_STOP_DATA_Val _U_(0x2) /**< (HSMCI_CMDR) Stop data transfer */ 312 #define HSMCI_CMDR_TRCMD_NO_DATA (HSMCI_CMDR_TRCMD_NO_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) No data transfer Position */ 313 #define HSMCI_CMDR_TRCMD_START_DATA (HSMCI_CMDR_TRCMD_START_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Start data transfer Position */ 314 #define HSMCI_CMDR_TRCMD_STOP_DATA (HSMCI_CMDR_TRCMD_STOP_DATA_Val << HSMCI_CMDR_TRCMD_Pos) /**< (HSMCI_CMDR) Stop data transfer Position */ 315 #define HSMCI_CMDR_TRDIR_Pos 18 /**< (HSMCI_CMDR) Transfer Direction Position */ 316 #define HSMCI_CMDR_TRDIR_Msk (_U_(0x1) << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Transfer Direction Mask */ 317 #define HSMCI_CMDR_TRDIR HSMCI_CMDR_TRDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_TRDIR_Msk instead */ 318 #define HSMCI_CMDR_TRDIR_WRITE_Val _U_(0x0) /**< (HSMCI_CMDR) Write. */ 319 #define HSMCI_CMDR_TRDIR_READ_Val _U_(0x1) /**< (HSMCI_CMDR) Read. */ 320 #define HSMCI_CMDR_TRDIR_WRITE (HSMCI_CMDR_TRDIR_WRITE_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Write. Position */ 321 #define HSMCI_CMDR_TRDIR_READ (HSMCI_CMDR_TRDIR_READ_Val << HSMCI_CMDR_TRDIR_Pos) /**< (HSMCI_CMDR) Read. Position */ 322 #define HSMCI_CMDR_TRTYP_Pos 19 /**< (HSMCI_CMDR) Transfer Type Position */ 323 #define HSMCI_CMDR_TRTYP_Msk (_U_(0x7) << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) Transfer Type Mask */ 324 #define HSMCI_CMDR_TRTYP(value) (HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos)) 325 #define HSMCI_CMDR_TRTYP_SINGLE_Val _U_(0x0) /**< (HSMCI_CMDR) MMC/SD Card Single Block */ 326 #define HSMCI_CMDR_TRTYP_MULTIPLE_Val _U_(0x1) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block */ 327 #define HSMCI_CMDR_TRTYP_STREAM_Val _U_(0x2) /**< (HSMCI_CMDR) MMC Stream */ 328 #define HSMCI_CMDR_TRTYP_BYTE_Val _U_(0x4) /**< (HSMCI_CMDR) SDIO Byte */ 329 #define HSMCI_CMDR_TRTYP_BLOCK_Val _U_(0x5) /**< (HSMCI_CMDR) SDIO Block */ 330 #define HSMCI_CMDR_TRTYP_SINGLE (HSMCI_CMDR_TRTYP_SINGLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Single Block Position */ 331 #define HSMCI_CMDR_TRTYP_MULTIPLE (HSMCI_CMDR_TRTYP_MULTIPLE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC/SD Card Multiple Block Position */ 332 #define HSMCI_CMDR_TRTYP_STREAM (HSMCI_CMDR_TRTYP_STREAM_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) MMC Stream Position */ 333 #define HSMCI_CMDR_TRTYP_BYTE (HSMCI_CMDR_TRTYP_BYTE_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Byte Position */ 334 #define HSMCI_CMDR_TRTYP_BLOCK (HSMCI_CMDR_TRTYP_BLOCK_Val << HSMCI_CMDR_TRTYP_Pos) /**< (HSMCI_CMDR) SDIO Block Position */ 335 #define HSMCI_CMDR_IOSPCMD_Pos 24 /**< (HSMCI_CMDR) SDIO Special Command Position */ 336 #define HSMCI_CMDR_IOSPCMD_Msk (_U_(0x3) << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Special Command Mask */ 337 #define HSMCI_CMDR_IOSPCMD(value) (HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos)) 338 #define HSMCI_CMDR_IOSPCMD_STD_Val _U_(0x0) /**< (HSMCI_CMDR) Not an SDIO Special Command */ 339 #define HSMCI_CMDR_IOSPCMD_SUSPEND_Val _U_(0x1) /**< (HSMCI_CMDR) SDIO Suspend Command */ 340 #define HSMCI_CMDR_IOSPCMD_RESUME_Val _U_(0x2) /**< (HSMCI_CMDR) SDIO Resume Command */ 341 #define HSMCI_CMDR_IOSPCMD_STD (HSMCI_CMDR_IOSPCMD_STD_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) Not an SDIO Special Command Position */ 342 #define HSMCI_CMDR_IOSPCMD_SUSPEND (HSMCI_CMDR_IOSPCMD_SUSPEND_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Suspend Command Position */ 343 #define HSMCI_CMDR_IOSPCMD_RESUME (HSMCI_CMDR_IOSPCMD_RESUME_Val << HSMCI_CMDR_IOSPCMD_Pos) /**< (HSMCI_CMDR) SDIO Resume Command Position */ 344 #define HSMCI_CMDR_ATACS_Pos 26 /**< (HSMCI_CMDR) ATA with Command Completion Signal Position */ 345 #define HSMCI_CMDR_ATACS_Msk (_U_(0x1) << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) ATA with Command Completion Signal Mask */ 346 #define HSMCI_CMDR_ATACS HSMCI_CMDR_ATACS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_ATACS_Msk instead */ 347 #define HSMCI_CMDR_ATACS_NORMAL_Val _U_(0x0) /**< (HSMCI_CMDR) Normal operation mode. */ 348 #define HSMCI_CMDR_ATACS_COMPLETION_Val _U_(0x1) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ 349 #define HSMCI_CMDR_ATACS_NORMAL (HSMCI_CMDR_ATACS_NORMAL_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) Normal operation mode. Position */ 350 #define HSMCI_CMDR_ATACS_COMPLETION (HSMCI_CMDR_ATACS_COMPLETION_Val << HSMCI_CMDR_ATACS_Pos) /**< (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). Position */ 351 #define HSMCI_CMDR_BOOT_ACK_Pos 27 /**< (HSMCI_CMDR) Boot Operation Acknowledge Position */ 352 #define HSMCI_CMDR_BOOT_ACK_Msk (_U_(0x1) << HSMCI_CMDR_BOOT_ACK_Pos) /**< (HSMCI_CMDR) Boot Operation Acknowledge Mask */ 353 #define HSMCI_CMDR_BOOT_ACK HSMCI_CMDR_BOOT_ACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CMDR_BOOT_ACK_Msk instead */ 354 #define HSMCI_CMDR_MASK _U_(0xF3F1FFF) /**< \deprecated (HSMCI_CMDR) Register MASK (Use HSMCI_CMDR_Msk instead) */ 355 #define HSMCI_CMDR_Msk _U_(0xF3F1FFF) /**< (HSMCI_CMDR) Register Mask */ 356 357 358 /* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) (R/W 32) Block Register -------- */ 359 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 360 #if COMPONENT_TYPEDEF_STYLE == 'N' 361 typedef union { 362 struct { 363 uint32_t BCNT:16; /**< bit: 0..15 MMC/SDIO Block Count - SDIO Byte Count */ 364 uint32_t BLKLEN:16; /**< bit: 16..31 Data Block Length */ 365 } bit; /**< Structure used for bit access */ 366 uint32_t reg; /**< Type used for register access */ 367 } HSMCI_BLKR_Type; 368 #endif 369 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 370 371 #define HSMCI_BLKR_OFFSET (0x18) /**< (HSMCI_BLKR) Block Register Offset */ 372 373 #define HSMCI_BLKR_BCNT_Pos 0 /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Position */ 374 #define HSMCI_BLKR_BCNT_Msk (_U_(0xFFFF) << HSMCI_BLKR_BCNT_Pos) /**< (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count Mask */ 375 #define HSMCI_BLKR_BCNT(value) (HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos)) 376 #define HSMCI_BLKR_BLKLEN_Pos 16 /**< (HSMCI_BLKR) Data Block Length Position */ 377 #define HSMCI_BLKR_BLKLEN_Msk (_U_(0xFFFF) << HSMCI_BLKR_BLKLEN_Pos) /**< (HSMCI_BLKR) Data Block Length Mask */ 378 #define HSMCI_BLKR_BLKLEN(value) (HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos)) 379 #define HSMCI_BLKR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_BLKR) Register MASK (Use HSMCI_BLKR_Msk instead) */ 380 #define HSMCI_BLKR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_BLKR) Register Mask */ 381 382 383 /* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1c) (R/W 32) Completion Signal Timeout Register -------- */ 384 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 385 #if COMPONENT_TYPEDEF_STYLE == 'N' 386 typedef union { 387 struct { 388 uint32_t CSTOCYC:4; /**< bit: 0..3 Completion Signal Timeout Cycle Number */ 389 uint32_t CSTOMUL:3; /**< bit: 4..6 Completion Signal Timeout Multiplier */ 390 uint32_t :25; /**< bit: 7..31 Reserved */ 391 } bit; /**< Structure used for bit access */ 392 uint32_t reg; /**< Type used for register access */ 393 } HSMCI_CSTOR_Type; 394 #endif 395 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 396 397 #define HSMCI_CSTOR_OFFSET (0x1C) /**< (HSMCI_CSTOR) Completion Signal Timeout Register Offset */ 398 399 #define HSMCI_CSTOR_CSTOCYC_Pos 0 /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Position */ 400 #define HSMCI_CSTOR_CSTOCYC_Msk (_U_(0xF) << HSMCI_CSTOR_CSTOCYC_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Cycle Number Mask */ 401 #define HSMCI_CSTOR_CSTOCYC(value) (HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos)) 402 #define HSMCI_CSTOR_CSTOMUL_Pos 4 /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Position */ 403 #define HSMCI_CSTOR_CSTOMUL_Msk (_U_(0x7) << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) Completion Signal Timeout Multiplier Mask */ 404 #define HSMCI_CSTOR_CSTOMUL(value) (HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos)) 405 #define HSMCI_CSTOR_CSTOMUL_1_Val _U_(0x0) /**< (HSMCI_CSTOR) CSTOCYC x 1 */ 406 #define HSMCI_CSTOR_CSTOMUL_16_Val _U_(0x1) /**< (HSMCI_CSTOR) CSTOCYC x 16 */ 407 #define HSMCI_CSTOR_CSTOMUL_128_Val _U_(0x2) /**< (HSMCI_CSTOR) CSTOCYC x 128 */ 408 #define HSMCI_CSTOR_CSTOMUL_256_Val _U_(0x3) /**< (HSMCI_CSTOR) CSTOCYC x 256 */ 409 #define HSMCI_CSTOR_CSTOMUL_1024_Val _U_(0x4) /**< (HSMCI_CSTOR) CSTOCYC x 1024 */ 410 #define HSMCI_CSTOR_CSTOMUL_4096_Val _U_(0x5) /**< (HSMCI_CSTOR) CSTOCYC x 4096 */ 411 #define HSMCI_CSTOR_CSTOMUL_65536_Val _U_(0x6) /**< (HSMCI_CSTOR) CSTOCYC x 65536 */ 412 #define HSMCI_CSTOR_CSTOMUL_1048576_Val _U_(0x7) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 */ 413 #define HSMCI_CSTOR_CSTOMUL_1 (HSMCI_CSTOR_CSTOMUL_1_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1 Position */ 414 #define HSMCI_CSTOR_CSTOMUL_16 (HSMCI_CSTOR_CSTOMUL_16_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 16 Position */ 415 #define HSMCI_CSTOR_CSTOMUL_128 (HSMCI_CSTOR_CSTOMUL_128_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 128 Position */ 416 #define HSMCI_CSTOR_CSTOMUL_256 (HSMCI_CSTOR_CSTOMUL_256_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 256 Position */ 417 #define HSMCI_CSTOR_CSTOMUL_1024 (HSMCI_CSTOR_CSTOMUL_1024_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1024 Position */ 418 #define HSMCI_CSTOR_CSTOMUL_4096 (HSMCI_CSTOR_CSTOMUL_4096_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 4096 Position */ 419 #define HSMCI_CSTOR_CSTOMUL_65536 (HSMCI_CSTOR_CSTOMUL_65536_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 65536 Position */ 420 #define HSMCI_CSTOR_CSTOMUL_1048576 (HSMCI_CSTOR_CSTOMUL_1048576_Val << HSMCI_CSTOR_CSTOMUL_Pos) /**< (HSMCI_CSTOR) CSTOCYC x 1048576 Position */ 421 #define HSMCI_CSTOR_MASK _U_(0x7F) /**< \deprecated (HSMCI_CSTOR) Register MASK (Use HSMCI_CSTOR_Msk instead) */ 422 #define HSMCI_CSTOR_Msk _U_(0x7F) /**< (HSMCI_CSTOR) Register Mask */ 423 424 425 /* -------- HSMCI_RSPR : (HSMCI Offset: 0x20) (R/ 32) Response Register 0 -------- */ 426 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 427 #if COMPONENT_TYPEDEF_STYLE == 'N' 428 typedef union { 429 struct { 430 uint32_t RSP:32; /**< bit: 0..31 Response */ 431 } bit; /**< Structure used for bit access */ 432 uint32_t reg; /**< Type used for register access */ 433 } HSMCI_RSPR_Type; 434 #endif 435 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 436 437 #define HSMCI_RSPR_OFFSET (0x20) /**< (HSMCI_RSPR) Response Register 0 Offset */ 438 439 #define HSMCI_RSPR_RSP_Pos 0 /**< (HSMCI_RSPR) Response Position */ 440 #define HSMCI_RSPR_RSP_Msk (_U_(0xFFFFFFFF) << HSMCI_RSPR_RSP_Pos) /**< (HSMCI_RSPR) Response Mask */ 441 #define HSMCI_RSPR_RSP(value) (HSMCI_RSPR_RSP_Msk & ((value) << HSMCI_RSPR_RSP_Pos)) 442 #define HSMCI_RSPR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_RSPR) Register MASK (Use HSMCI_RSPR_Msk instead) */ 443 #define HSMCI_RSPR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RSPR) Register Mask */ 444 445 446 /* -------- HSMCI_RDR : (HSMCI Offset: 0x30) (R/ 32) Receive Data Register -------- */ 447 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 448 #if COMPONENT_TYPEDEF_STYLE == 'N' 449 typedef union { 450 struct { 451 uint32_t DATA:32; /**< bit: 0..31 Data to Read */ 452 } bit; /**< Structure used for bit access */ 453 uint32_t reg; /**< Type used for register access */ 454 } HSMCI_RDR_Type; 455 #endif 456 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 457 458 #define HSMCI_RDR_OFFSET (0x30) /**< (HSMCI_RDR) Receive Data Register Offset */ 459 460 #define HSMCI_RDR_DATA_Pos 0 /**< (HSMCI_RDR) Data to Read Position */ 461 #define HSMCI_RDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_RDR_DATA_Pos) /**< (HSMCI_RDR) Data to Read Mask */ 462 #define HSMCI_RDR_DATA(value) (HSMCI_RDR_DATA_Msk & ((value) << HSMCI_RDR_DATA_Pos)) 463 #define HSMCI_RDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_RDR) Register MASK (Use HSMCI_RDR_Msk instead) */ 464 #define HSMCI_RDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_RDR) Register Mask */ 465 466 467 /* -------- HSMCI_TDR : (HSMCI Offset: 0x34) (/W 32) Transmit Data Register -------- */ 468 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 469 #if COMPONENT_TYPEDEF_STYLE == 'N' 470 typedef union { 471 struct { 472 uint32_t DATA:32; /**< bit: 0..31 Data to Write */ 473 } bit; /**< Structure used for bit access */ 474 uint32_t reg; /**< Type used for register access */ 475 } HSMCI_TDR_Type; 476 #endif 477 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 478 479 #define HSMCI_TDR_OFFSET (0x34) /**< (HSMCI_TDR) Transmit Data Register Offset */ 480 481 #define HSMCI_TDR_DATA_Pos 0 /**< (HSMCI_TDR) Data to Write Position */ 482 #define HSMCI_TDR_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_TDR_DATA_Pos) /**< (HSMCI_TDR) Data to Write Mask */ 483 #define HSMCI_TDR_DATA(value) (HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos)) 484 #define HSMCI_TDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_TDR) Register MASK (Use HSMCI_TDR_Msk instead) */ 485 #define HSMCI_TDR_Msk _U_(0xFFFFFFFF) /**< (HSMCI_TDR) Register Mask */ 486 487 488 /* -------- HSMCI_SR : (HSMCI Offset: 0x40) (R/ 32) Status Register -------- */ 489 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 490 #if COMPONENT_TYPEDEF_STYLE == 'N' 491 typedef union { 492 struct { 493 uint32_t CMDRDY:1; /**< bit: 0 Command Ready (cleared by writing in HSMCI_CMDR) */ 494 uint32_t RXRDY:1; /**< bit: 1 Receiver Ready (cleared by reading HSMCI_RDR) */ 495 uint32_t TXRDY:1; /**< bit: 2 Transmit Ready (cleared by writing in HSMCI_TDR) */ 496 uint32_t BLKE:1; /**< bit: 3 Data Block Ended (cleared on read) */ 497 uint32_t DTIP:1; /**< bit: 4 Data Transfer in Progress (cleared at the end of CRC16 calculation) */ 498 uint32_t NOTBUSY:1; /**< bit: 5 HSMCI Not Busy */ 499 uint32_t :2; /**< bit: 6..7 Reserved */ 500 uint32_t SDIOIRQA:1; /**< bit: 8 SDIO Interrupt for Slot A (cleared on read) */ 501 uint32_t :3; /**< bit: 9..11 Reserved */ 502 uint32_t SDIOWAIT:1; /**< bit: 12 SDIO Read Wait Operation Status */ 503 uint32_t CSRCV:1; /**< bit: 13 CE-ATA Completion Signal Received (cleared on read) */ 504 uint32_t :2; /**< bit: 14..15 Reserved */ 505 uint32_t RINDE:1; /**< bit: 16 Response Index Error (cleared by writing in HSMCI_CMDR) */ 506 uint32_t RDIRE:1; /**< bit: 17 Response Direction Error (cleared by writing in HSMCI_CMDR) */ 507 uint32_t RCRCE:1; /**< bit: 18 Response CRC Error (cleared by writing in HSMCI_CMDR) */ 508 uint32_t RENDE:1; /**< bit: 19 Response End Bit Error (cleared by writing in HSMCI_CMDR) */ 509 uint32_t RTOE:1; /**< bit: 20 Response Time-out Error (cleared by writing in HSMCI_CMDR) */ 510 uint32_t DCRCE:1; /**< bit: 21 Data CRC Error (cleared on read) */ 511 uint32_t DTOE:1; /**< bit: 22 Data Time-out Error (cleared on read) */ 512 uint32_t CSTOE:1; /**< bit: 23 Completion Signal Time-out Error (cleared on read) */ 513 uint32_t BLKOVRE:1; /**< bit: 24 DMA Block Overrun Error (cleared on read) */ 514 uint32_t :1; /**< bit: 25 Reserved */ 515 uint32_t FIFOEMPTY:1; /**< bit: 26 FIFO empty flag */ 516 uint32_t XFRDONE:1; /**< bit: 27 Transfer Done flag */ 517 uint32_t ACKRCV:1; /**< bit: 28 Boot Operation Acknowledge Received (cleared on read) */ 518 uint32_t ACKRCVE:1; /**< bit: 29 Boot Operation Acknowledge Error (cleared on read) */ 519 uint32_t OVRE:1; /**< bit: 30 Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ 520 uint32_t UNRE:1; /**< bit: 31 Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ 521 } bit; /**< Structure used for bit access */ 522 uint32_t reg; /**< Type used for register access */ 523 } HSMCI_SR_Type; 524 #endif 525 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 526 527 #define HSMCI_SR_OFFSET (0x40) /**< (HSMCI_SR) Status Register Offset */ 528 529 #define HSMCI_SR_CMDRDY_Pos 0 /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Position */ 530 #define HSMCI_SR_CMDRDY_Msk (_U_(0x1) << HSMCI_SR_CMDRDY_Pos) /**< (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) Mask */ 531 #define HSMCI_SR_CMDRDY HSMCI_SR_CMDRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_CMDRDY_Msk instead */ 532 #define HSMCI_SR_RXRDY_Pos 1 /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Position */ 533 #define HSMCI_SR_RXRDY_Msk (_U_(0x1) << HSMCI_SR_RXRDY_Pos) /**< (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) Mask */ 534 #define HSMCI_SR_RXRDY HSMCI_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RXRDY_Msk instead */ 535 #define HSMCI_SR_TXRDY_Pos 2 /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Position */ 536 #define HSMCI_SR_TXRDY_Msk (_U_(0x1) << HSMCI_SR_TXRDY_Pos) /**< (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) Mask */ 537 #define HSMCI_SR_TXRDY HSMCI_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_TXRDY_Msk instead */ 538 #define HSMCI_SR_BLKE_Pos 3 /**< (HSMCI_SR) Data Block Ended (cleared on read) Position */ 539 #define HSMCI_SR_BLKE_Msk (_U_(0x1) << HSMCI_SR_BLKE_Pos) /**< (HSMCI_SR) Data Block Ended (cleared on read) Mask */ 540 #define HSMCI_SR_BLKE HSMCI_SR_BLKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_BLKE_Msk instead */ 541 #define HSMCI_SR_DTIP_Pos 4 /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Position */ 542 #define HSMCI_SR_DTIP_Msk (_U_(0x1) << HSMCI_SR_DTIP_Pos) /**< (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) Mask */ 543 #define HSMCI_SR_DTIP HSMCI_SR_DTIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_DTIP_Msk instead */ 544 #define HSMCI_SR_NOTBUSY_Pos 5 /**< (HSMCI_SR) HSMCI Not Busy Position */ 545 #define HSMCI_SR_NOTBUSY_Msk (_U_(0x1) << HSMCI_SR_NOTBUSY_Pos) /**< (HSMCI_SR) HSMCI Not Busy Mask */ 546 #define HSMCI_SR_NOTBUSY HSMCI_SR_NOTBUSY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_NOTBUSY_Msk instead */ 547 #define HSMCI_SR_SDIOIRQA_Pos 8 /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Position */ 548 #define HSMCI_SR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_SR_SDIOIRQA_Pos) /**< (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) Mask */ 549 #define HSMCI_SR_SDIOIRQA HSMCI_SR_SDIOIRQA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_SDIOIRQA_Msk instead */ 550 #define HSMCI_SR_SDIOWAIT_Pos 12 /**< (HSMCI_SR) SDIO Read Wait Operation Status Position */ 551 #define HSMCI_SR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_SR_SDIOWAIT_Pos) /**< (HSMCI_SR) SDIO Read Wait Operation Status Mask */ 552 #define HSMCI_SR_SDIOWAIT HSMCI_SR_SDIOWAIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_SDIOWAIT_Msk instead */ 553 #define HSMCI_SR_CSRCV_Pos 13 /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Position */ 554 #define HSMCI_SR_CSRCV_Msk (_U_(0x1) << HSMCI_SR_CSRCV_Pos) /**< (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) Mask */ 555 #define HSMCI_SR_CSRCV HSMCI_SR_CSRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_CSRCV_Msk instead */ 556 #define HSMCI_SR_RINDE_Pos 16 /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Position */ 557 #define HSMCI_SR_RINDE_Msk (_U_(0x1) << HSMCI_SR_RINDE_Pos) /**< (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) Mask */ 558 #define HSMCI_SR_RINDE HSMCI_SR_RINDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RINDE_Msk instead */ 559 #define HSMCI_SR_RDIRE_Pos 17 /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Position */ 560 #define HSMCI_SR_RDIRE_Msk (_U_(0x1) << HSMCI_SR_RDIRE_Pos) /**< (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) Mask */ 561 #define HSMCI_SR_RDIRE HSMCI_SR_RDIRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RDIRE_Msk instead */ 562 #define HSMCI_SR_RCRCE_Pos 18 /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Position */ 563 #define HSMCI_SR_RCRCE_Msk (_U_(0x1) << HSMCI_SR_RCRCE_Pos) /**< (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) Mask */ 564 #define HSMCI_SR_RCRCE HSMCI_SR_RCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RCRCE_Msk instead */ 565 #define HSMCI_SR_RENDE_Pos 19 /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Position */ 566 #define HSMCI_SR_RENDE_Msk (_U_(0x1) << HSMCI_SR_RENDE_Pos) /**< (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) Mask */ 567 #define HSMCI_SR_RENDE HSMCI_SR_RENDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RENDE_Msk instead */ 568 #define HSMCI_SR_RTOE_Pos 20 /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Position */ 569 #define HSMCI_SR_RTOE_Msk (_U_(0x1) << HSMCI_SR_RTOE_Pos) /**< (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) Mask */ 570 #define HSMCI_SR_RTOE HSMCI_SR_RTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_RTOE_Msk instead */ 571 #define HSMCI_SR_DCRCE_Pos 21 /**< (HSMCI_SR) Data CRC Error (cleared on read) Position */ 572 #define HSMCI_SR_DCRCE_Msk (_U_(0x1) << HSMCI_SR_DCRCE_Pos) /**< (HSMCI_SR) Data CRC Error (cleared on read) Mask */ 573 #define HSMCI_SR_DCRCE HSMCI_SR_DCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_DCRCE_Msk instead */ 574 #define HSMCI_SR_DTOE_Pos 22 /**< (HSMCI_SR) Data Time-out Error (cleared on read) Position */ 575 #define HSMCI_SR_DTOE_Msk (_U_(0x1) << HSMCI_SR_DTOE_Pos) /**< (HSMCI_SR) Data Time-out Error (cleared on read) Mask */ 576 #define HSMCI_SR_DTOE HSMCI_SR_DTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_DTOE_Msk instead */ 577 #define HSMCI_SR_CSTOE_Pos 23 /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Position */ 578 #define HSMCI_SR_CSTOE_Msk (_U_(0x1) << HSMCI_SR_CSTOE_Pos) /**< (HSMCI_SR) Completion Signal Time-out Error (cleared on read) Mask */ 579 #define HSMCI_SR_CSTOE HSMCI_SR_CSTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_CSTOE_Msk instead */ 580 #define HSMCI_SR_BLKOVRE_Pos 24 /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Position */ 581 #define HSMCI_SR_BLKOVRE_Msk (_U_(0x1) << HSMCI_SR_BLKOVRE_Pos) /**< (HSMCI_SR) DMA Block Overrun Error (cleared on read) Mask */ 582 #define HSMCI_SR_BLKOVRE HSMCI_SR_BLKOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_BLKOVRE_Msk instead */ 583 #define HSMCI_SR_FIFOEMPTY_Pos 26 /**< (HSMCI_SR) FIFO empty flag Position */ 584 #define HSMCI_SR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_SR_FIFOEMPTY_Pos) /**< (HSMCI_SR) FIFO empty flag Mask */ 585 #define HSMCI_SR_FIFOEMPTY HSMCI_SR_FIFOEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_FIFOEMPTY_Msk instead */ 586 #define HSMCI_SR_XFRDONE_Pos 27 /**< (HSMCI_SR) Transfer Done flag Position */ 587 #define HSMCI_SR_XFRDONE_Msk (_U_(0x1) << HSMCI_SR_XFRDONE_Pos) /**< (HSMCI_SR) Transfer Done flag Mask */ 588 #define HSMCI_SR_XFRDONE HSMCI_SR_XFRDONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_XFRDONE_Msk instead */ 589 #define HSMCI_SR_ACKRCV_Pos 28 /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Position */ 590 #define HSMCI_SR_ACKRCV_Msk (_U_(0x1) << HSMCI_SR_ACKRCV_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) Mask */ 591 #define HSMCI_SR_ACKRCV HSMCI_SR_ACKRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_ACKRCV_Msk instead */ 592 #define HSMCI_SR_ACKRCVE_Pos 29 /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Position */ 593 #define HSMCI_SR_ACKRCVE_Msk (_U_(0x1) << HSMCI_SR_ACKRCVE_Pos) /**< (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) Mask */ 594 #define HSMCI_SR_ACKRCVE HSMCI_SR_ACKRCVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_ACKRCVE_Msk instead */ 595 #define HSMCI_SR_OVRE_Pos 30 /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */ 596 #define HSMCI_SR_OVRE_Msk (_U_(0x1) << HSMCI_SR_OVRE_Pos) /**< (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */ 597 #define HSMCI_SR_OVRE HSMCI_SR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_OVRE_Msk instead */ 598 #define HSMCI_SR_UNRE_Pos 31 /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Position */ 599 #define HSMCI_SR_UNRE_Msk (_U_(0x1) << HSMCI_SR_UNRE_Pos) /**< (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) Mask */ 600 #define HSMCI_SR_UNRE HSMCI_SR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_SR_UNRE_Msk instead */ 601 #define HSMCI_SR_MASK _U_(0xFDFF313F) /**< \deprecated (HSMCI_SR) Register MASK (Use HSMCI_SR_Msk instead) */ 602 #define HSMCI_SR_Msk _U_(0xFDFF313F) /**< (HSMCI_SR) Register Mask */ 603 604 605 /* -------- HSMCI_IER : (HSMCI Offset: 0x44) (/W 32) Interrupt Enable Register -------- */ 606 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 607 #if COMPONENT_TYPEDEF_STYLE == 'N' 608 typedef union { 609 struct { 610 uint32_t CMDRDY:1; /**< bit: 0 Command Ready Interrupt Enable */ 611 uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Enable */ 612 uint32_t TXRDY:1; /**< bit: 2 Transmit Ready Interrupt Enable */ 613 uint32_t BLKE:1; /**< bit: 3 Data Block Ended Interrupt Enable */ 614 uint32_t DTIP:1; /**< bit: 4 Data Transfer in Progress Interrupt Enable */ 615 uint32_t NOTBUSY:1; /**< bit: 5 Data Not Busy Interrupt Enable */ 616 uint32_t :2; /**< bit: 6..7 Reserved */ 617 uint32_t SDIOIRQA:1; /**< bit: 8 SDIO Interrupt for Slot A Interrupt Enable */ 618 uint32_t :3; /**< bit: 9..11 Reserved */ 619 uint32_t SDIOWAIT:1; /**< bit: 12 SDIO Read Wait Operation Status Interrupt Enable */ 620 uint32_t CSRCV:1; /**< bit: 13 Completion Signal Received Interrupt Enable */ 621 uint32_t :2; /**< bit: 14..15 Reserved */ 622 uint32_t RINDE:1; /**< bit: 16 Response Index Error Interrupt Enable */ 623 uint32_t RDIRE:1; /**< bit: 17 Response Direction Error Interrupt Enable */ 624 uint32_t RCRCE:1; /**< bit: 18 Response CRC Error Interrupt Enable */ 625 uint32_t RENDE:1; /**< bit: 19 Response End Bit Error Interrupt Enable */ 626 uint32_t RTOE:1; /**< bit: 20 Response Time-out Error Interrupt Enable */ 627 uint32_t DCRCE:1; /**< bit: 21 Data CRC Error Interrupt Enable */ 628 uint32_t DTOE:1; /**< bit: 22 Data Time-out Error Interrupt Enable */ 629 uint32_t CSTOE:1; /**< bit: 23 Completion Signal Timeout Error Interrupt Enable */ 630 uint32_t BLKOVRE:1; /**< bit: 24 DMA Block Overrun Error Interrupt Enable */ 631 uint32_t :1; /**< bit: 25 Reserved */ 632 uint32_t FIFOEMPTY:1; /**< bit: 26 FIFO empty Interrupt enable */ 633 uint32_t XFRDONE:1; /**< bit: 27 Transfer Done Interrupt enable */ 634 uint32_t ACKRCV:1; /**< bit: 28 Boot Acknowledge Interrupt Enable */ 635 uint32_t ACKRCVE:1; /**< bit: 29 Boot Acknowledge Error Interrupt Enable */ 636 uint32_t OVRE:1; /**< bit: 30 Overrun Interrupt Enable */ 637 uint32_t UNRE:1; /**< bit: 31 Underrun Interrupt Enable */ 638 } bit; /**< Structure used for bit access */ 639 uint32_t reg; /**< Type used for register access */ 640 } HSMCI_IER_Type; 641 #endif 642 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 643 644 #define HSMCI_IER_OFFSET (0x44) /**< (HSMCI_IER) Interrupt Enable Register Offset */ 645 646 #define HSMCI_IER_CMDRDY_Pos 0 /**< (HSMCI_IER) Command Ready Interrupt Enable Position */ 647 #define HSMCI_IER_CMDRDY_Msk (_U_(0x1) << HSMCI_IER_CMDRDY_Pos) /**< (HSMCI_IER) Command Ready Interrupt Enable Mask */ 648 #define HSMCI_IER_CMDRDY HSMCI_IER_CMDRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_CMDRDY_Msk instead */ 649 #define HSMCI_IER_RXRDY_Pos 1 /**< (HSMCI_IER) Receiver Ready Interrupt Enable Position */ 650 #define HSMCI_IER_RXRDY_Msk (_U_(0x1) << HSMCI_IER_RXRDY_Pos) /**< (HSMCI_IER) Receiver Ready Interrupt Enable Mask */ 651 #define HSMCI_IER_RXRDY HSMCI_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RXRDY_Msk instead */ 652 #define HSMCI_IER_TXRDY_Pos 2 /**< (HSMCI_IER) Transmit Ready Interrupt Enable Position */ 653 #define HSMCI_IER_TXRDY_Msk (_U_(0x1) << HSMCI_IER_TXRDY_Pos) /**< (HSMCI_IER) Transmit Ready Interrupt Enable Mask */ 654 #define HSMCI_IER_TXRDY HSMCI_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_TXRDY_Msk instead */ 655 #define HSMCI_IER_BLKE_Pos 3 /**< (HSMCI_IER) Data Block Ended Interrupt Enable Position */ 656 #define HSMCI_IER_BLKE_Msk (_U_(0x1) << HSMCI_IER_BLKE_Pos) /**< (HSMCI_IER) Data Block Ended Interrupt Enable Mask */ 657 #define HSMCI_IER_BLKE HSMCI_IER_BLKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_BLKE_Msk instead */ 658 #define HSMCI_IER_DTIP_Pos 4 /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Position */ 659 #define HSMCI_IER_DTIP_Msk (_U_(0x1) << HSMCI_IER_DTIP_Pos) /**< (HSMCI_IER) Data Transfer in Progress Interrupt Enable Mask */ 660 #define HSMCI_IER_DTIP HSMCI_IER_DTIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_DTIP_Msk instead */ 661 #define HSMCI_IER_NOTBUSY_Pos 5 /**< (HSMCI_IER) Data Not Busy Interrupt Enable Position */ 662 #define HSMCI_IER_NOTBUSY_Msk (_U_(0x1) << HSMCI_IER_NOTBUSY_Pos) /**< (HSMCI_IER) Data Not Busy Interrupt Enable Mask */ 663 #define HSMCI_IER_NOTBUSY HSMCI_IER_NOTBUSY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_NOTBUSY_Msk instead */ 664 #define HSMCI_IER_SDIOIRQA_Pos 8 /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Position */ 665 #define HSMCI_IER_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IER_SDIOIRQA_Pos) /**< (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable Mask */ 666 #define HSMCI_IER_SDIOIRQA HSMCI_IER_SDIOIRQA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_SDIOIRQA_Msk instead */ 667 #define HSMCI_IER_SDIOWAIT_Pos 12 /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Position */ 668 #define HSMCI_IER_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IER_SDIOWAIT_Pos) /**< (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable Mask */ 669 #define HSMCI_IER_SDIOWAIT HSMCI_IER_SDIOWAIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_SDIOWAIT_Msk instead */ 670 #define HSMCI_IER_CSRCV_Pos 13 /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Position */ 671 #define HSMCI_IER_CSRCV_Msk (_U_(0x1) << HSMCI_IER_CSRCV_Pos) /**< (HSMCI_IER) Completion Signal Received Interrupt Enable Mask */ 672 #define HSMCI_IER_CSRCV HSMCI_IER_CSRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_CSRCV_Msk instead */ 673 #define HSMCI_IER_RINDE_Pos 16 /**< (HSMCI_IER) Response Index Error Interrupt Enable Position */ 674 #define HSMCI_IER_RINDE_Msk (_U_(0x1) << HSMCI_IER_RINDE_Pos) /**< (HSMCI_IER) Response Index Error Interrupt Enable Mask */ 675 #define HSMCI_IER_RINDE HSMCI_IER_RINDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RINDE_Msk instead */ 676 #define HSMCI_IER_RDIRE_Pos 17 /**< (HSMCI_IER) Response Direction Error Interrupt Enable Position */ 677 #define HSMCI_IER_RDIRE_Msk (_U_(0x1) << HSMCI_IER_RDIRE_Pos) /**< (HSMCI_IER) Response Direction Error Interrupt Enable Mask */ 678 #define HSMCI_IER_RDIRE HSMCI_IER_RDIRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RDIRE_Msk instead */ 679 #define HSMCI_IER_RCRCE_Pos 18 /**< (HSMCI_IER) Response CRC Error Interrupt Enable Position */ 680 #define HSMCI_IER_RCRCE_Msk (_U_(0x1) << HSMCI_IER_RCRCE_Pos) /**< (HSMCI_IER) Response CRC Error Interrupt Enable Mask */ 681 #define HSMCI_IER_RCRCE HSMCI_IER_RCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RCRCE_Msk instead */ 682 #define HSMCI_IER_RENDE_Pos 19 /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Position */ 683 #define HSMCI_IER_RENDE_Msk (_U_(0x1) << HSMCI_IER_RENDE_Pos) /**< (HSMCI_IER) Response End Bit Error Interrupt Enable Mask */ 684 #define HSMCI_IER_RENDE HSMCI_IER_RENDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RENDE_Msk instead */ 685 #define HSMCI_IER_RTOE_Pos 20 /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Position */ 686 #define HSMCI_IER_RTOE_Msk (_U_(0x1) << HSMCI_IER_RTOE_Pos) /**< (HSMCI_IER) Response Time-out Error Interrupt Enable Mask */ 687 #define HSMCI_IER_RTOE HSMCI_IER_RTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_RTOE_Msk instead */ 688 #define HSMCI_IER_DCRCE_Pos 21 /**< (HSMCI_IER) Data CRC Error Interrupt Enable Position */ 689 #define HSMCI_IER_DCRCE_Msk (_U_(0x1) << HSMCI_IER_DCRCE_Pos) /**< (HSMCI_IER) Data CRC Error Interrupt Enable Mask */ 690 #define HSMCI_IER_DCRCE HSMCI_IER_DCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_DCRCE_Msk instead */ 691 #define HSMCI_IER_DTOE_Pos 22 /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Position */ 692 #define HSMCI_IER_DTOE_Msk (_U_(0x1) << HSMCI_IER_DTOE_Pos) /**< (HSMCI_IER) Data Time-out Error Interrupt Enable Mask */ 693 #define HSMCI_IER_DTOE HSMCI_IER_DTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_DTOE_Msk instead */ 694 #define HSMCI_IER_CSTOE_Pos 23 /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Position */ 695 #define HSMCI_IER_CSTOE_Msk (_U_(0x1) << HSMCI_IER_CSTOE_Pos) /**< (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable Mask */ 696 #define HSMCI_IER_CSTOE HSMCI_IER_CSTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_CSTOE_Msk instead */ 697 #define HSMCI_IER_BLKOVRE_Pos 24 /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Position */ 698 #define HSMCI_IER_BLKOVRE_Msk (_U_(0x1) << HSMCI_IER_BLKOVRE_Pos) /**< (HSMCI_IER) DMA Block Overrun Error Interrupt Enable Mask */ 699 #define HSMCI_IER_BLKOVRE HSMCI_IER_BLKOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_BLKOVRE_Msk instead */ 700 #define HSMCI_IER_FIFOEMPTY_Pos 26 /**< (HSMCI_IER) FIFO empty Interrupt enable Position */ 701 #define HSMCI_IER_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IER_FIFOEMPTY_Pos) /**< (HSMCI_IER) FIFO empty Interrupt enable Mask */ 702 #define HSMCI_IER_FIFOEMPTY HSMCI_IER_FIFOEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_FIFOEMPTY_Msk instead */ 703 #define HSMCI_IER_XFRDONE_Pos 27 /**< (HSMCI_IER) Transfer Done Interrupt enable Position */ 704 #define HSMCI_IER_XFRDONE_Msk (_U_(0x1) << HSMCI_IER_XFRDONE_Pos) /**< (HSMCI_IER) Transfer Done Interrupt enable Mask */ 705 #define HSMCI_IER_XFRDONE HSMCI_IER_XFRDONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_XFRDONE_Msk instead */ 706 #define HSMCI_IER_ACKRCV_Pos 28 /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Position */ 707 #define HSMCI_IER_ACKRCV_Msk (_U_(0x1) << HSMCI_IER_ACKRCV_Pos) /**< (HSMCI_IER) Boot Acknowledge Interrupt Enable Mask */ 708 #define HSMCI_IER_ACKRCV HSMCI_IER_ACKRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_ACKRCV_Msk instead */ 709 #define HSMCI_IER_ACKRCVE_Pos 29 /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Position */ 710 #define HSMCI_IER_ACKRCVE_Msk (_U_(0x1) << HSMCI_IER_ACKRCVE_Pos) /**< (HSMCI_IER) Boot Acknowledge Error Interrupt Enable Mask */ 711 #define HSMCI_IER_ACKRCVE HSMCI_IER_ACKRCVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_ACKRCVE_Msk instead */ 712 #define HSMCI_IER_OVRE_Pos 30 /**< (HSMCI_IER) Overrun Interrupt Enable Position */ 713 #define HSMCI_IER_OVRE_Msk (_U_(0x1) << HSMCI_IER_OVRE_Pos) /**< (HSMCI_IER) Overrun Interrupt Enable Mask */ 714 #define HSMCI_IER_OVRE HSMCI_IER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_OVRE_Msk instead */ 715 #define HSMCI_IER_UNRE_Pos 31 /**< (HSMCI_IER) Underrun Interrupt Enable Position */ 716 #define HSMCI_IER_UNRE_Msk (_U_(0x1) << HSMCI_IER_UNRE_Pos) /**< (HSMCI_IER) Underrun Interrupt Enable Mask */ 717 #define HSMCI_IER_UNRE HSMCI_IER_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IER_UNRE_Msk instead */ 718 #define HSMCI_IER_MASK _U_(0xFDFF313F) /**< \deprecated (HSMCI_IER) Register MASK (Use HSMCI_IER_Msk instead) */ 719 #define HSMCI_IER_Msk _U_(0xFDFF313F) /**< (HSMCI_IER) Register Mask */ 720 721 722 /* -------- HSMCI_IDR : (HSMCI Offset: 0x48) (/W 32) Interrupt Disable Register -------- */ 723 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 724 #if COMPONENT_TYPEDEF_STYLE == 'N' 725 typedef union { 726 struct { 727 uint32_t CMDRDY:1; /**< bit: 0 Command Ready Interrupt Disable */ 728 uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Disable */ 729 uint32_t TXRDY:1; /**< bit: 2 Transmit Ready Interrupt Disable */ 730 uint32_t BLKE:1; /**< bit: 3 Data Block Ended Interrupt Disable */ 731 uint32_t DTIP:1; /**< bit: 4 Data Transfer in Progress Interrupt Disable */ 732 uint32_t NOTBUSY:1; /**< bit: 5 Data Not Busy Interrupt Disable */ 733 uint32_t :2; /**< bit: 6..7 Reserved */ 734 uint32_t SDIOIRQA:1; /**< bit: 8 SDIO Interrupt for Slot A Interrupt Disable */ 735 uint32_t :3; /**< bit: 9..11 Reserved */ 736 uint32_t SDIOWAIT:1; /**< bit: 12 SDIO Read Wait Operation Status Interrupt Disable */ 737 uint32_t CSRCV:1; /**< bit: 13 Completion Signal received interrupt Disable */ 738 uint32_t :2; /**< bit: 14..15 Reserved */ 739 uint32_t RINDE:1; /**< bit: 16 Response Index Error Interrupt Disable */ 740 uint32_t RDIRE:1; /**< bit: 17 Response Direction Error Interrupt Disable */ 741 uint32_t RCRCE:1; /**< bit: 18 Response CRC Error Interrupt Disable */ 742 uint32_t RENDE:1; /**< bit: 19 Response End Bit Error Interrupt Disable */ 743 uint32_t RTOE:1; /**< bit: 20 Response Time-out Error Interrupt Disable */ 744 uint32_t DCRCE:1; /**< bit: 21 Data CRC Error Interrupt Disable */ 745 uint32_t DTOE:1; /**< bit: 22 Data Time-out Error Interrupt Disable */ 746 uint32_t CSTOE:1; /**< bit: 23 Completion Signal Time out Error Interrupt Disable */ 747 uint32_t BLKOVRE:1; /**< bit: 24 DMA Block Overrun Error Interrupt Disable */ 748 uint32_t :1; /**< bit: 25 Reserved */ 749 uint32_t FIFOEMPTY:1; /**< bit: 26 FIFO empty Interrupt Disable */ 750 uint32_t XFRDONE:1; /**< bit: 27 Transfer Done Interrupt Disable */ 751 uint32_t ACKRCV:1; /**< bit: 28 Boot Acknowledge Interrupt Disable */ 752 uint32_t ACKRCVE:1; /**< bit: 29 Boot Acknowledge Error Interrupt Disable */ 753 uint32_t OVRE:1; /**< bit: 30 Overrun Interrupt Disable */ 754 uint32_t UNRE:1; /**< bit: 31 Underrun Interrupt Disable */ 755 } bit; /**< Structure used for bit access */ 756 uint32_t reg; /**< Type used for register access */ 757 } HSMCI_IDR_Type; 758 #endif 759 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 760 761 #define HSMCI_IDR_OFFSET (0x48) /**< (HSMCI_IDR) Interrupt Disable Register Offset */ 762 763 #define HSMCI_IDR_CMDRDY_Pos 0 /**< (HSMCI_IDR) Command Ready Interrupt Disable Position */ 764 #define HSMCI_IDR_CMDRDY_Msk (_U_(0x1) << HSMCI_IDR_CMDRDY_Pos) /**< (HSMCI_IDR) Command Ready Interrupt Disable Mask */ 765 #define HSMCI_IDR_CMDRDY HSMCI_IDR_CMDRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_CMDRDY_Msk instead */ 766 #define HSMCI_IDR_RXRDY_Pos 1 /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Position */ 767 #define HSMCI_IDR_RXRDY_Msk (_U_(0x1) << HSMCI_IDR_RXRDY_Pos) /**< (HSMCI_IDR) Receiver Ready Interrupt Disable Mask */ 768 #define HSMCI_IDR_RXRDY HSMCI_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RXRDY_Msk instead */ 769 #define HSMCI_IDR_TXRDY_Pos 2 /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Position */ 770 #define HSMCI_IDR_TXRDY_Msk (_U_(0x1) << HSMCI_IDR_TXRDY_Pos) /**< (HSMCI_IDR) Transmit Ready Interrupt Disable Mask */ 771 #define HSMCI_IDR_TXRDY HSMCI_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_TXRDY_Msk instead */ 772 #define HSMCI_IDR_BLKE_Pos 3 /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Position */ 773 #define HSMCI_IDR_BLKE_Msk (_U_(0x1) << HSMCI_IDR_BLKE_Pos) /**< (HSMCI_IDR) Data Block Ended Interrupt Disable Mask */ 774 #define HSMCI_IDR_BLKE HSMCI_IDR_BLKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_BLKE_Msk instead */ 775 #define HSMCI_IDR_DTIP_Pos 4 /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Position */ 776 #define HSMCI_IDR_DTIP_Msk (_U_(0x1) << HSMCI_IDR_DTIP_Pos) /**< (HSMCI_IDR) Data Transfer in Progress Interrupt Disable Mask */ 777 #define HSMCI_IDR_DTIP HSMCI_IDR_DTIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_DTIP_Msk instead */ 778 #define HSMCI_IDR_NOTBUSY_Pos 5 /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Position */ 779 #define HSMCI_IDR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IDR_NOTBUSY_Pos) /**< (HSMCI_IDR) Data Not Busy Interrupt Disable Mask */ 780 #define HSMCI_IDR_NOTBUSY HSMCI_IDR_NOTBUSY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_NOTBUSY_Msk instead */ 781 #define HSMCI_IDR_SDIOIRQA_Pos 8 /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Position */ 782 #define HSMCI_IDR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IDR_SDIOIRQA_Pos) /**< (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable Mask */ 783 #define HSMCI_IDR_SDIOIRQA HSMCI_IDR_SDIOIRQA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_SDIOIRQA_Msk instead */ 784 #define HSMCI_IDR_SDIOWAIT_Pos 12 /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Position */ 785 #define HSMCI_IDR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IDR_SDIOWAIT_Pos) /**< (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable Mask */ 786 #define HSMCI_IDR_SDIOWAIT HSMCI_IDR_SDIOWAIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_SDIOWAIT_Msk instead */ 787 #define HSMCI_IDR_CSRCV_Pos 13 /**< (HSMCI_IDR) Completion Signal received interrupt Disable Position */ 788 #define HSMCI_IDR_CSRCV_Msk (_U_(0x1) << HSMCI_IDR_CSRCV_Pos) /**< (HSMCI_IDR) Completion Signal received interrupt Disable Mask */ 789 #define HSMCI_IDR_CSRCV HSMCI_IDR_CSRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_CSRCV_Msk instead */ 790 #define HSMCI_IDR_RINDE_Pos 16 /**< (HSMCI_IDR) Response Index Error Interrupt Disable Position */ 791 #define HSMCI_IDR_RINDE_Msk (_U_(0x1) << HSMCI_IDR_RINDE_Pos) /**< (HSMCI_IDR) Response Index Error Interrupt Disable Mask */ 792 #define HSMCI_IDR_RINDE HSMCI_IDR_RINDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RINDE_Msk instead */ 793 #define HSMCI_IDR_RDIRE_Pos 17 /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Position */ 794 #define HSMCI_IDR_RDIRE_Msk (_U_(0x1) << HSMCI_IDR_RDIRE_Pos) /**< (HSMCI_IDR) Response Direction Error Interrupt Disable Mask */ 795 #define HSMCI_IDR_RDIRE HSMCI_IDR_RDIRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RDIRE_Msk instead */ 796 #define HSMCI_IDR_RCRCE_Pos 18 /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Position */ 797 #define HSMCI_IDR_RCRCE_Msk (_U_(0x1) << HSMCI_IDR_RCRCE_Pos) /**< (HSMCI_IDR) Response CRC Error Interrupt Disable Mask */ 798 #define HSMCI_IDR_RCRCE HSMCI_IDR_RCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RCRCE_Msk instead */ 799 #define HSMCI_IDR_RENDE_Pos 19 /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Position */ 800 #define HSMCI_IDR_RENDE_Msk (_U_(0x1) << HSMCI_IDR_RENDE_Pos) /**< (HSMCI_IDR) Response End Bit Error Interrupt Disable Mask */ 801 #define HSMCI_IDR_RENDE HSMCI_IDR_RENDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RENDE_Msk instead */ 802 #define HSMCI_IDR_RTOE_Pos 20 /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Position */ 803 #define HSMCI_IDR_RTOE_Msk (_U_(0x1) << HSMCI_IDR_RTOE_Pos) /**< (HSMCI_IDR) Response Time-out Error Interrupt Disable Mask */ 804 #define HSMCI_IDR_RTOE HSMCI_IDR_RTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_RTOE_Msk instead */ 805 #define HSMCI_IDR_DCRCE_Pos 21 /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Position */ 806 #define HSMCI_IDR_DCRCE_Msk (_U_(0x1) << HSMCI_IDR_DCRCE_Pos) /**< (HSMCI_IDR) Data CRC Error Interrupt Disable Mask */ 807 #define HSMCI_IDR_DCRCE HSMCI_IDR_DCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_DCRCE_Msk instead */ 808 #define HSMCI_IDR_DTOE_Pos 22 /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Position */ 809 #define HSMCI_IDR_DTOE_Msk (_U_(0x1) << HSMCI_IDR_DTOE_Pos) /**< (HSMCI_IDR) Data Time-out Error Interrupt Disable Mask */ 810 #define HSMCI_IDR_DTOE HSMCI_IDR_DTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_DTOE_Msk instead */ 811 #define HSMCI_IDR_CSTOE_Pos 23 /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Position */ 812 #define HSMCI_IDR_CSTOE_Msk (_U_(0x1) << HSMCI_IDR_CSTOE_Pos) /**< (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable Mask */ 813 #define HSMCI_IDR_CSTOE HSMCI_IDR_CSTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_CSTOE_Msk instead */ 814 #define HSMCI_IDR_BLKOVRE_Pos 24 /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Position */ 815 #define HSMCI_IDR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IDR_BLKOVRE_Pos) /**< (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable Mask */ 816 #define HSMCI_IDR_BLKOVRE HSMCI_IDR_BLKOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_BLKOVRE_Msk instead */ 817 #define HSMCI_IDR_FIFOEMPTY_Pos 26 /**< (HSMCI_IDR) FIFO empty Interrupt Disable Position */ 818 #define HSMCI_IDR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IDR_FIFOEMPTY_Pos) /**< (HSMCI_IDR) FIFO empty Interrupt Disable Mask */ 819 #define HSMCI_IDR_FIFOEMPTY HSMCI_IDR_FIFOEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_FIFOEMPTY_Msk instead */ 820 #define HSMCI_IDR_XFRDONE_Pos 27 /**< (HSMCI_IDR) Transfer Done Interrupt Disable Position */ 821 #define HSMCI_IDR_XFRDONE_Msk (_U_(0x1) << HSMCI_IDR_XFRDONE_Pos) /**< (HSMCI_IDR) Transfer Done Interrupt Disable Mask */ 822 #define HSMCI_IDR_XFRDONE HSMCI_IDR_XFRDONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_XFRDONE_Msk instead */ 823 #define HSMCI_IDR_ACKRCV_Pos 28 /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Position */ 824 #define HSMCI_IDR_ACKRCV_Msk (_U_(0x1) << HSMCI_IDR_ACKRCV_Pos) /**< (HSMCI_IDR) Boot Acknowledge Interrupt Disable Mask */ 825 #define HSMCI_IDR_ACKRCV HSMCI_IDR_ACKRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_ACKRCV_Msk instead */ 826 #define HSMCI_IDR_ACKRCVE_Pos 29 /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Position */ 827 #define HSMCI_IDR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IDR_ACKRCVE_Pos) /**< (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable Mask */ 828 #define HSMCI_IDR_ACKRCVE HSMCI_IDR_ACKRCVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_ACKRCVE_Msk instead */ 829 #define HSMCI_IDR_OVRE_Pos 30 /**< (HSMCI_IDR) Overrun Interrupt Disable Position */ 830 #define HSMCI_IDR_OVRE_Msk (_U_(0x1) << HSMCI_IDR_OVRE_Pos) /**< (HSMCI_IDR) Overrun Interrupt Disable Mask */ 831 #define HSMCI_IDR_OVRE HSMCI_IDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_OVRE_Msk instead */ 832 #define HSMCI_IDR_UNRE_Pos 31 /**< (HSMCI_IDR) Underrun Interrupt Disable Position */ 833 #define HSMCI_IDR_UNRE_Msk (_U_(0x1) << HSMCI_IDR_UNRE_Pos) /**< (HSMCI_IDR) Underrun Interrupt Disable Mask */ 834 #define HSMCI_IDR_UNRE HSMCI_IDR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IDR_UNRE_Msk instead */ 835 #define HSMCI_IDR_MASK _U_(0xFDFF313F) /**< \deprecated (HSMCI_IDR) Register MASK (Use HSMCI_IDR_Msk instead) */ 836 #define HSMCI_IDR_Msk _U_(0xFDFF313F) /**< (HSMCI_IDR) Register Mask */ 837 838 839 /* -------- HSMCI_IMR : (HSMCI Offset: 0x4c) (R/ 32) Interrupt Mask Register -------- */ 840 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 841 #if COMPONENT_TYPEDEF_STYLE == 'N' 842 typedef union { 843 struct { 844 uint32_t CMDRDY:1; /**< bit: 0 Command Ready Interrupt Mask */ 845 uint32_t RXRDY:1; /**< bit: 1 Receiver Ready Interrupt Mask */ 846 uint32_t TXRDY:1; /**< bit: 2 Transmit Ready Interrupt Mask */ 847 uint32_t BLKE:1; /**< bit: 3 Data Block Ended Interrupt Mask */ 848 uint32_t DTIP:1; /**< bit: 4 Data Transfer in Progress Interrupt Mask */ 849 uint32_t NOTBUSY:1; /**< bit: 5 Data Not Busy Interrupt Mask */ 850 uint32_t :2; /**< bit: 6..7 Reserved */ 851 uint32_t SDIOIRQA:1; /**< bit: 8 SDIO Interrupt for Slot A Interrupt Mask */ 852 uint32_t :3; /**< bit: 9..11 Reserved */ 853 uint32_t SDIOWAIT:1; /**< bit: 12 SDIO Read Wait Operation Status Interrupt Mask */ 854 uint32_t CSRCV:1; /**< bit: 13 Completion Signal Received Interrupt Mask */ 855 uint32_t :2; /**< bit: 14..15 Reserved */ 856 uint32_t RINDE:1; /**< bit: 16 Response Index Error Interrupt Mask */ 857 uint32_t RDIRE:1; /**< bit: 17 Response Direction Error Interrupt Mask */ 858 uint32_t RCRCE:1; /**< bit: 18 Response CRC Error Interrupt Mask */ 859 uint32_t RENDE:1; /**< bit: 19 Response End Bit Error Interrupt Mask */ 860 uint32_t RTOE:1; /**< bit: 20 Response Time-out Error Interrupt Mask */ 861 uint32_t DCRCE:1; /**< bit: 21 Data CRC Error Interrupt Mask */ 862 uint32_t DTOE:1; /**< bit: 22 Data Time-out Error Interrupt Mask */ 863 uint32_t CSTOE:1; /**< bit: 23 Completion Signal Time-out Error Interrupt Mask */ 864 uint32_t BLKOVRE:1; /**< bit: 24 DMA Block Overrun Error Interrupt Mask */ 865 uint32_t :1; /**< bit: 25 Reserved */ 866 uint32_t FIFOEMPTY:1; /**< bit: 26 FIFO Empty Interrupt Mask */ 867 uint32_t XFRDONE:1; /**< bit: 27 Transfer Done Interrupt Mask */ 868 uint32_t ACKRCV:1; /**< bit: 28 Boot Operation Acknowledge Received Interrupt Mask */ 869 uint32_t ACKRCVE:1; /**< bit: 29 Boot Operation Acknowledge Error Interrupt Mask */ 870 uint32_t OVRE:1; /**< bit: 30 Overrun Interrupt Mask */ 871 uint32_t UNRE:1; /**< bit: 31 Underrun Interrupt Mask */ 872 } bit; /**< Structure used for bit access */ 873 uint32_t reg; /**< Type used for register access */ 874 } HSMCI_IMR_Type; 875 #endif 876 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 877 878 #define HSMCI_IMR_OFFSET (0x4C) /**< (HSMCI_IMR) Interrupt Mask Register Offset */ 879 880 #define HSMCI_IMR_CMDRDY_Pos 0 /**< (HSMCI_IMR) Command Ready Interrupt Mask Position */ 881 #define HSMCI_IMR_CMDRDY_Msk (_U_(0x1) << HSMCI_IMR_CMDRDY_Pos) /**< (HSMCI_IMR) Command Ready Interrupt Mask Mask */ 882 #define HSMCI_IMR_CMDRDY HSMCI_IMR_CMDRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_CMDRDY_Msk instead */ 883 #define HSMCI_IMR_RXRDY_Pos 1 /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Position */ 884 #define HSMCI_IMR_RXRDY_Msk (_U_(0x1) << HSMCI_IMR_RXRDY_Pos) /**< (HSMCI_IMR) Receiver Ready Interrupt Mask Mask */ 885 #define HSMCI_IMR_RXRDY HSMCI_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RXRDY_Msk instead */ 886 #define HSMCI_IMR_TXRDY_Pos 2 /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Position */ 887 #define HSMCI_IMR_TXRDY_Msk (_U_(0x1) << HSMCI_IMR_TXRDY_Pos) /**< (HSMCI_IMR) Transmit Ready Interrupt Mask Mask */ 888 #define HSMCI_IMR_TXRDY HSMCI_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_TXRDY_Msk instead */ 889 #define HSMCI_IMR_BLKE_Pos 3 /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Position */ 890 #define HSMCI_IMR_BLKE_Msk (_U_(0x1) << HSMCI_IMR_BLKE_Pos) /**< (HSMCI_IMR) Data Block Ended Interrupt Mask Mask */ 891 #define HSMCI_IMR_BLKE HSMCI_IMR_BLKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_BLKE_Msk instead */ 892 #define HSMCI_IMR_DTIP_Pos 4 /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Position */ 893 #define HSMCI_IMR_DTIP_Msk (_U_(0x1) << HSMCI_IMR_DTIP_Pos) /**< (HSMCI_IMR) Data Transfer in Progress Interrupt Mask Mask */ 894 #define HSMCI_IMR_DTIP HSMCI_IMR_DTIP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_DTIP_Msk instead */ 895 #define HSMCI_IMR_NOTBUSY_Pos 5 /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Position */ 896 #define HSMCI_IMR_NOTBUSY_Msk (_U_(0x1) << HSMCI_IMR_NOTBUSY_Pos) /**< (HSMCI_IMR) Data Not Busy Interrupt Mask Mask */ 897 #define HSMCI_IMR_NOTBUSY HSMCI_IMR_NOTBUSY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_NOTBUSY_Msk instead */ 898 #define HSMCI_IMR_SDIOIRQA_Pos 8 /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Position */ 899 #define HSMCI_IMR_SDIOIRQA_Msk (_U_(0x1) << HSMCI_IMR_SDIOIRQA_Pos) /**< (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask Mask */ 900 #define HSMCI_IMR_SDIOIRQA HSMCI_IMR_SDIOIRQA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_SDIOIRQA_Msk instead */ 901 #define HSMCI_IMR_SDIOWAIT_Pos 12 /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Position */ 902 #define HSMCI_IMR_SDIOWAIT_Msk (_U_(0x1) << HSMCI_IMR_SDIOWAIT_Pos) /**< (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask Mask */ 903 #define HSMCI_IMR_SDIOWAIT HSMCI_IMR_SDIOWAIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_SDIOWAIT_Msk instead */ 904 #define HSMCI_IMR_CSRCV_Pos 13 /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Position */ 905 #define HSMCI_IMR_CSRCV_Msk (_U_(0x1) << HSMCI_IMR_CSRCV_Pos) /**< (HSMCI_IMR) Completion Signal Received Interrupt Mask Mask */ 906 #define HSMCI_IMR_CSRCV HSMCI_IMR_CSRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_CSRCV_Msk instead */ 907 #define HSMCI_IMR_RINDE_Pos 16 /**< (HSMCI_IMR) Response Index Error Interrupt Mask Position */ 908 #define HSMCI_IMR_RINDE_Msk (_U_(0x1) << HSMCI_IMR_RINDE_Pos) /**< (HSMCI_IMR) Response Index Error Interrupt Mask Mask */ 909 #define HSMCI_IMR_RINDE HSMCI_IMR_RINDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RINDE_Msk instead */ 910 #define HSMCI_IMR_RDIRE_Pos 17 /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Position */ 911 #define HSMCI_IMR_RDIRE_Msk (_U_(0x1) << HSMCI_IMR_RDIRE_Pos) /**< (HSMCI_IMR) Response Direction Error Interrupt Mask Mask */ 912 #define HSMCI_IMR_RDIRE HSMCI_IMR_RDIRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RDIRE_Msk instead */ 913 #define HSMCI_IMR_RCRCE_Pos 18 /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Position */ 914 #define HSMCI_IMR_RCRCE_Msk (_U_(0x1) << HSMCI_IMR_RCRCE_Pos) /**< (HSMCI_IMR) Response CRC Error Interrupt Mask Mask */ 915 #define HSMCI_IMR_RCRCE HSMCI_IMR_RCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RCRCE_Msk instead */ 916 #define HSMCI_IMR_RENDE_Pos 19 /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Position */ 917 #define HSMCI_IMR_RENDE_Msk (_U_(0x1) << HSMCI_IMR_RENDE_Pos) /**< (HSMCI_IMR) Response End Bit Error Interrupt Mask Mask */ 918 #define HSMCI_IMR_RENDE HSMCI_IMR_RENDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RENDE_Msk instead */ 919 #define HSMCI_IMR_RTOE_Pos 20 /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Position */ 920 #define HSMCI_IMR_RTOE_Msk (_U_(0x1) << HSMCI_IMR_RTOE_Pos) /**< (HSMCI_IMR) Response Time-out Error Interrupt Mask Mask */ 921 #define HSMCI_IMR_RTOE HSMCI_IMR_RTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_RTOE_Msk instead */ 922 #define HSMCI_IMR_DCRCE_Pos 21 /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Position */ 923 #define HSMCI_IMR_DCRCE_Msk (_U_(0x1) << HSMCI_IMR_DCRCE_Pos) /**< (HSMCI_IMR) Data CRC Error Interrupt Mask Mask */ 924 #define HSMCI_IMR_DCRCE HSMCI_IMR_DCRCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_DCRCE_Msk instead */ 925 #define HSMCI_IMR_DTOE_Pos 22 /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Position */ 926 #define HSMCI_IMR_DTOE_Msk (_U_(0x1) << HSMCI_IMR_DTOE_Pos) /**< (HSMCI_IMR) Data Time-out Error Interrupt Mask Mask */ 927 #define HSMCI_IMR_DTOE HSMCI_IMR_DTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_DTOE_Msk instead */ 928 #define HSMCI_IMR_CSTOE_Pos 23 /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Position */ 929 #define HSMCI_IMR_CSTOE_Msk (_U_(0x1) << HSMCI_IMR_CSTOE_Pos) /**< (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask Mask */ 930 #define HSMCI_IMR_CSTOE HSMCI_IMR_CSTOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_CSTOE_Msk instead */ 931 #define HSMCI_IMR_BLKOVRE_Pos 24 /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Position */ 932 #define HSMCI_IMR_BLKOVRE_Msk (_U_(0x1) << HSMCI_IMR_BLKOVRE_Pos) /**< (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask Mask */ 933 #define HSMCI_IMR_BLKOVRE HSMCI_IMR_BLKOVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_BLKOVRE_Msk instead */ 934 #define HSMCI_IMR_FIFOEMPTY_Pos 26 /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Position */ 935 #define HSMCI_IMR_FIFOEMPTY_Msk (_U_(0x1) << HSMCI_IMR_FIFOEMPTY_Pos) /**< (HSMCI_IMR) FIFO Empty Interrupt Mask Mask */ 936 #define HSMCI_IMR_FIFOEMPTY HSMCI_IMR_FIFOEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_FIFOEMPTY_Msk instead */ 937 #define HSMCI_IMR_XFRDONE_Pos 27 /**< (HSMCI_IMR) Transfer Done Interrupt Mask Position */ 938 #define HSMCI_IMR_XFRDONE_Msk (_U_(0x1) << HSMCI_IMR_XFRDONE_Pos) /**< (HSMCI_IMR) Transfer Done Interrupt Mask Mask */ 939 #define HSMCI_IMR_XFRDONE HSMCI_IMR_XFRDONE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_XFRDONE_Msk instead */ 940 #define HSMCI_IMR_ACKRCV_Pos 28 /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Position */ 941 #define HSMCI_IMR_ACKRCV_Msk (_U_(0x1) << HSMCI_IMR_ACKRCV_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask Mask */ 942 #define HSMCI_IMR_ACKRCV HSMCI_IMR_ACKRCV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_ACKRCV_Msk instead */ 943 #define HSMCI_IMR_ACKRCVE_Pos 29 /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Position */ 944 #define HSMCI_IMR_ACKRCVE_Msk (_U_(0x1) << HSMCI_IMR_ACKRCVE_Pos) /**< (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask Mask */ 945 #define HSMCI_IMR_ACKRCVE HSMCI_IMR_ACKRCVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_ACKRCVE_Msk instead */ 946 #define HSMCI_IMR_OVRE_Pos 30 /**< (HSMCI_IMR) Overrun Interrupt Mask Position */ 947 #define HSMCI_IMR_OVRE_Msk (_U_(0x1) << HSMCI_IMR_OVRE_Pos) /**< (HSMCI_IMR) Overrun Interrupt Mask Mask */ 948 #define HSMCI_IMR_OVRE HSMCI_IMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_OVRE_Msk instead */ 949 #define HSMCI_IMR_UNRE_Pos 31 /**< (HSMCI_IMR) Underrun Interrupt Mask Position */ 950 #define HSMCI_IMR_UNRE_Msk (_U_(0x1) << HSMCI_IMR_UNRE_Pos) /**< (HSMCI_IMR) Underrun Interrupt Mask Mask */ 951 #define HSMCI_IMR_UNRE HSMCI_IMR_UNRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_IMR_UNRE_Msk instead */ 952 #define HSMCI_IMR_MASK _U_(0xFDFF313F) /**< \deprecated (HSMCI_IMR) Register MASK (Use HSMCI_IMR_Msk instead) */ 953 #define HSMCI_IMR_Msk _U_(0xFDFF313F) /**< (HSMCI_IMR) Register Mask */ 954 955 956 /* -------- HSMCI_DMA : (HSMCI Offset: 0x50) (R/W 32) DMA Configuration Register -------- */ 957 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 958 #if COMPONENT_TYPEDEF_STYLE == 'N' 959 typedef union { 960 struct { 961 uint32_t :4; /**< bit: 0..3 Reserved */ 962 uint32_t CHKSIZE:3; /**< bit: 4..6 DMA Channel Read and Write Chunk Size */ 963 uint32_t :1; /**< bit: 7 Reserved */ 964 uint32_t DMAEN:1; /**< bit: 8 DMA Hardware Handshaking Enable */ 965 uint32_t :23; /**< bit: 9..31 Reserved */ 966 } bit; /**< Structure used for bit access */ 967 uint32_t reg; /**< Type used for register access */ 968 } HSMCI_DMA_Type; 969 #endif 970 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 971 972 #define HSMCI_DMA_OFFSET (0x50) /**< (HSMCI_DMA) DMA Configuration Register Offset */ 973 974 #define HSMCI_DMA_CHKSIZE_Pos 4 /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Position */ 975 #define HSMCI_DMA_CHKSIZE_Msk (_U_(0x7) << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) DMA Channel Read and Write Chunk Size Mask */ 976 #define HSMCI_DMA_CHKSIZE(value) (HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos)) 977 #define HSMCI_DMA_CHKSIZE_1_Val _U_(0x0) /**< (HSMCI_DMA) 1 data available */ 978 #define HSMCI_DMA_CHKSIZE_2_Val _U_(0x1) /**< (HSMCI_DMA) 2 data available */ 979 #define HSMCI_DMA_CHKSIZE_4_Val _U_(0x2) /**< (HSMCI_DMA) 4 data available */ 980 #define HSMCI_DMA_CHKSIZE_8_Val _U_(0x3) /**< (HSMCI_DMA) 8 data available */ 981 #define HSMCI_DMA_CHKSIZE_16_Val _U_(0x4) /**< (HSMCI_DMA) 16 data available */ 982 #define HSMCI_DMA_CHKSIZE_1 (HSMCI_DMA_CHKSIZE_1_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 1 data available Position */ 983 #define HSMCI_DMA_CHKSIZE_2 (HSMCI_DMA_CHKSIZE_2_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 2 data available Position */ 984 #define HSMCI_DMA_CHKSIZE_4 (HSMCI_DMA_CHKSIZE_4_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 4 data available Position */ 985 #define HSMCI_DMA_CHKSIZE_8 (HSMCI_DMA_CHKSIZE_8_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 8 data available Position */ 986 #define HSMCI_DMA_CHKSIZE_16 (HSMCI_DMA_CHKSIZE_16_Val << HSMCI_DMA_CHKSIZE_Pos) /**< (HSMCI_DMA) 16 data available Position */ 987 #define HSMCI_DMA_DMAEN_Pos 8 /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Position */ 988 #define HSMCI_DMA_DMAEN_Msk (_U_(0x1) << HSMCI_DMA_DMAEN_Pos) /**< (HSMCI_DMA) DMA Hardware Handshaking Enable Mask */ 989 #define HSMCI_DMA_DMAEN HSMCI_DMA_DMAEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_DMA_DMAEN_Msk instead */ 990 #define HSMCI_DMA_MASK _U_(0x170) /**< \deprecated (HSMCI_DMA) Register MASK (Use HSMCI_DMA_Msk instead) */ 991 #define HSMCI_DMA_Msk _U_(0x170) /**< (HSMCI_DMA) Register Mask */ 992 993 994 /* -------- HSMCI_CFG : (HSMCI Offset: 0x54) (R/W 32) Configuration Register -------- */ 995 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 996 #if COMPONENT_TYPEDEF_STYLE == 'N' 997 typedef union { 998 struct { 999 uint32_t FIFOMODE:1; /**< bit: 0 HSMCI Internal FIFO control mode */ 1000 uint32_t :3; /**< bit: 1..3 Reserved */ 1001 uint32_t FERRCTRL:1; /**< bit: 4 Flow Error flag reset control mode */ 1002 uint32_t :3; /**< bit: 5..7 Reserved */ 1003 uint32_t HSMODE:1; /**< bit: 8 High Speed Mode */ 1004 uint32_t :3; /**< bit: 9..11 Reserved */ 1005 uint32_t LSYNC:1; /**< bit: 12 Synchronize on the last block */ 1006 uint32_t :19; /**< bit: 13..31 Reserved */ 1007 } bit; /**< Structure used for bit access */ 1008 uint32_t reg; /**< Type used for register access */ 1009 } HSMCI_CFG_Type; 1010 #endif 1011 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1012 1013 #define HSMCI_CFG_OFFSET (0x54) /**< (HSMCI_CFG) Configuration Register Offset */ 1014 1015 #define HSMCI_CFG_FIFOMODE_Pos 0 /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Position */ 1016 #define HSMCI_CFG_FIFOMODE_Msk (_U_(0x1) << HSMCI_CFG_FIFOMODE_Pos) /**< (HSMCI_CFG) HSMCI Internal FIFO control mode Mask */ 1017 #define HSMCI_CFG_FIFOMODE HSMCI_CFG_FIFOMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CFG_FIFOMODE_Msk instead */ 1018 #define HSMCI_CFG_FERRCTRL_Pos 4 /**< (HSMCI_CFG) Flow Error flag reset control mode Position */ 1019 #define HSMCI_CFG_FERRCTRL_Msk (_U_(0x1) << HSMCI_CFG_FERRCTRL_Pos) /**< (HSMCI_CFG) Flow Error flag reset control mode Mask */ 1020 #define HSMCI_CFG_FERRCTRL HSMCI_CFG_FERRCTRL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CFG_FERRCTRL_Msk instead */ 1021 #define HSMCI_CFG_HSMODE_Pos 8 /**< (HSMCI_CFG) High Speed Mode Position */ 1022 #define HSMCI_CFG_HSMODE_Msk (_U_(0x1) << HSMCI_CFG_HSMODE_Pos) /**< (HSMCI_CFG) High Speed Mode Mask */ 1023 #define HSMCI_CFG_HSMODE HSMCI_CFG_HSMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CFG_HSMODE_Msk instead */ 1024 #define HSMCI_CFG_LSYNC_Pos 12 /**< (HSMCI_CFG) Synchronize on the last block Position */ 1025 #define HSMCI_CFG_LSYNC_Msk (_U_(0x1) << HSMCI_CFG_LSYNC_Pos) /**< (HSMCI_CFG) Synchronize on the last block Mask */ 1026 #define HSMCI_CFG_LSYNC HSMCI_CFG_LSYNC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_CFG_LSYNC_Msk instead */ 1027 #define HSMCI_CFG_MASK _U_(0x1111) /**< \deprecated (HSMCI_CFG) Register MASK (Use HSMCI_CFG_Msk instead) */ 1028 #define HSMCI_CFG_Msk _U_(0x1111) /**< (HSMCI_CFG) Register Mask */ 1029 1030 1031 /* -------- HSMCI_WPMR : (HSMCI Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 1032 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1033 #if COMPONENT_TYPEDEF_STYLE == 'N' 1034 typedef union { 1035 struct { 1036 uint32_t WPEN:1; /**< bit: 0 Write Protect Enable */ 1037 uint32_t :7; /**< bit: 1..7 Reserved */ 1038 uint32_t WPKEY:24; /**< bit: 8..31 Write Protect Key */ 1039 } bit; /**< Structure used for bit access */ 1040 uint32_t reg; /**< Type used for register access */ 1041 } HSMCI_WPMR_Type; 1042 #endif 1043 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1044 1045 #define HSMCI_WPMR_OFFSET (0xE4) /**< (HSMCI_WPMR) Write Protection Mode Register Offset */ 1046 1047 #define HSMCI_WPMR_WPEN_Pos 0 /**< (HSMCI_WPMR) Write Protect Enable Position */ 1048 #define HSMCI_WPMR_WPEN_Msk (_U_(0x1) << HSMCI_WPMR_WPEN_Pos) /**< (HSMCI_WPMR) Write Protect Enable Mask */ 1049 #define HSMCI_WPMR_WPEN HSMCI_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_WPMR_WPEN_Msk instead */ 1050 #define HSMCI_WPMR_WPKEY_Pos 8 /**< (HSMCI_WPMR) Write Protect Key Position */ 1051 #define HSMCI_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Write Protect Key Mask */ 1052 #define HSMCI_WPMR_WPKEY(value) (HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos)) 1053 #define HSMCI_WPMR_WPKEY_PASSWD_Val _U_(0x4D4349) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 1054 #define HSMCI_WPMR_WPKEY_PASSWD (HSMCI_WPMR_WPKEY_PASSWD_Val << HSMCI_WPMR_WPKEY_Pos) /**< (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 1055 #define HSMCI_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (HSMCI_WPMR) Register MASK (Use HSMCI_WPMR_Msk instead) */ 1056 #define HSMCI_WPMR_Msk _U_(0xFFFFFF01) /**< (HSMCI_WPMR) Register Mask */ 1057 1058 1059 /* -------- HSMCI_WPSR : (HSMCI Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 1060 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1061 #if COMPONENT_TYPEDEF_STYLE == 'N' 1062 typedef union { 1063 struct { 1064 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 1065 uint32_t :7; /**< bit: 1..7 Reserved */ 1066 uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ 1067 uint32_t :8; /**< bit: 24..31 Reserved */ 1068 } bit; /**< Structure used for bit access */ 1069 uint32_t reg; /**< Type used for register access */ 1070 } HSMCI_WPSR_Type; 1071 #endif 1072 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1073 1074 #define HSMCI_WPSR_OFFSET (0xE8) /**< (HSMCI_WPSR) Write Protection Status Register Offset */ 1075 1076 #define HSMCI_WPSR_WPVS_Pos 0 /**< (HSMCI_WPSR) Write Protection Violation Status Position */ 1077 #define HSMCI_WPSR_WPVS_Msk (_U_(0x1) << HSMCI_WPSR_WPVS_Pos) /**< (HSMCI_WPSR) Write Protection Violation Status Mask */ 1078 #define HSMCI_WPSR_WPVS HSMCI_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use HSMCI_WPSR_WPVS_Msk instead */ 1079 #define HSMCI_WPSR_WPVSRC_Pos 8 /**< (HSMCI_WPSR) Write Protection Violation Source Position */ 1080 #define HSMCI_WPSR_WPVSRC_Msk (_U_(0xFFFF) << HSMCI_WPSR_WPVSRC_Pos) /**< (HSMCI_WPSR) Write Protection Violation Source Mask */ 1081 #define HSMCI_WPSR_WPVSRC(value) (HSMCI_WPSR_WPVSRC_Msk & ((value) << HSMCI_WPSR_WPVSRC_Pos)) 1082 #define HSMCI_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (HSMCI_WPSR) Register MASK (Use HSMCI_WPSR_Msk instead) */ 1083 #define HSMCI_WPSR_Msk _U_(0xFFFF01) /**< (HSMCI_WPSR) Register Mask */ 1084 1085 1086 /* -------- HSMCI_VERSION : (HSMCI Offset: 0xfc) (R/ 32) Version Register -------- */ 1087 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1088 #if COMPONENT_TYPEDEF_STYLE == 'N' 1089 typedef union { 1090 struct { 1091 uint32_t VERSION:12; /**< bit: 0..11 Hardware Module Version */ 1092 uint32_t :4; /**< bit: 12..15 Reserved */ 1093 uint32_t MFN:3; /**< bit: 16..18 Metal Fix Number */ 1094 uint32_t :13; /**< bit: 19..31 Reserved */ 1095 } bit; /**< Structure used for bit access */ 1096 uint32_t reg; /**< Type used for register access */ 1097 } HSMCI_VERSION_Type; 1098 #endif 1099 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1100 1101 #define HSMCI_VERSION_OFFSET (0xFC) /**< (HSMCI_VERSION) Version Register Offset */ 1102 1103 #define HSMCI_VERSION_VERSION_Pos 0 /**< (HSMCI_VERSION) Hardware Module Version Position */ 1104 #define HSMCI_VERSION_VERSION_Msk (_U_(0xFFF) << HSMCI_VERSION_VERSION_Pos) /**< (HSMCI_VERSION) Hardware Module Version Mask */ 1105 #define HSMCI_VERSION_VERSION(value) (HSMCI_VERSION_VERSION_Msk & ((value) << HSMCI_VERSION_VERSION_Pos)) 1106 #define HSMCI_VERSION_MFN_Pos 16 /**< (HSMCI_VERSION) Metal Fix Number Position */ 1107 #define HSMCI_VERSION_MFN_Msk (_U_(0x7) << HSMCI_VERSION_MFN_Pos) /**< (HSMCI_VERSION) Metal Fix Number Mask */ 1108 #define HSMCI_VERSION_MFN(value) (HSMCI_VERSION_MFN_Msk & ((value) << HSMCI_VERSION_MFN_Pos)) 1109 #define HSMCI_VERSION_MASK _U_(0x70FFF) /**< \deprecated (HSMCI_VERSION) Register MASK (Use HSMCI_VERSION_Msk instead) */ 1110 #define HSMCI_VERSION_Msk _U_(0x70FFF) /**< (HSMCI_VERSION) Register Mask */ 1111 1112 1113 /* -------- HSMCI_FIFO : (HSMCI Offset: 0x200) (R/W 32) FIFO Memory Aperture0 0 -------- */ 1114 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1115 #if COMPONENT_TYPEDEF_STYLE == 'N' 1116 typedef union { 1117 struct { 1118 uint32_t DATA:32; /**< bit: 0..31 Data to Read or Data to Write */ 1119 } bit; /**< Structure used for bit access */ 1120 uint32_t reg; /**< Type used for register access */ 1121 } HSMCI_FIFO_Type; 1122 #endif 1123 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1124 1125 #define HSMCI_FIFO_OFFSET (0x200) /**< (HSMCI_FIFO) FIFO Memory Aperture0 0 Offset */ 1126 1127 #define HSMCI_FIFO_DATA_Pos 0 /**< (HSMCI_FIFO) Data to Read or Data to Write Position */ 1128 #define HSMCI_FIFO_DATA_Msk (_U_(0xFFFFFFFF) << HSMCI_FIFO_DATA_Pos) /**< (HSMCI_FIFO) Data to Read or Data to Write Mask */ 1129 #define HSMCI_FIFO_DATA(value) (HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos)) 1130 #define HSMCI_FIFO_MASK _U_(0xFFFFFFFF) /**< \deprecated (HSMCI_FIFO) Register MASK (Use HSMCI_FIFO_Msk instead) */ 1131 #define HSMCI_FIFO_Msk _U_(0xFFFFFFFF) /**< (HSMCI_FIFO) Register Mask */ 1132 1133 1134 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1135 #if COMPONENT_TYPEDEF_STYLE == 'R' 1136 /** \brief HSMCI hardware registers */ 1137 typedef struct { 1138 __O uint32_t HSMCI_CR; /**< (HSMCI Offset: 0x00) Control Register */ 1139 __IO uint32_t HSMCI_MR; /**< (HSMCI Offset: 0x04) Mode Register */ 1140 __IO uint32_t HSMCI_DTOR; /**< (HSMCI Offset: 0x08) Data Timeout Register */ 1141 __IO uint32_t HSMCI_SDCR; /**< (HSMCI Offset: 0x0C) SD/SDIO Card Register */ 1142 __IO uint32_t HSMCI_ARGR; /**< (HSMCI Offset: 0x10) Argument Register */ 1143 __O uint32_t HSMCI_CMDR; /**< (HSMCI Offset: 0x14) Command Register */ 1144 __IO uint32_t HSMCI_BLKR; /**< (HSMCI Offset: 0x18) Block Register */ 1145 __IO uint32_t HSMCI_CSTOR; /**< (HSMCI Offset: 0x1C) Completion Signal Timeout Register */ 1146 __I uint32_t HSMCI_RSPR[4]; /**< (HSMCI Offset: 0x20) Response Register 0 */ 1147 __I uint32_t HSMCI_RDR; /**< (HSMCI Offset: 0x30) Receive Data Register */ 1148 __O uint32_t HSMCI_TDR; /**< (HSMCI Offset: 0x34) Transmit Data Register */ 1149 __I uint8_t Reserved1[8]; 1150 __I uint32_t HSMCI_SR; /**< (HSMCI Offset: 0x40) Status Register */ 1151 __O uint32_t HSMCI_IER; /**< (HSMCI Offset: 0x44) Interrupt Enable Register */ 1152 __O uint32_t HSMCI_IDR; /**< (HSMCI Offset: 0x48) Interrupt Disable Register */ 1153 __I uint32_t HSMCI_IMR; /**< (HSMCI Offset: 0x4C) Interrupt Mask Register */ 1154 __IO uint32_t HSMCI_DMA; /**< (HSMCI Offset: 0x50) DMA Configuration Register */ 1155 __IO uint32_t HSMCI_CFG; /**< (HSMCI Offset: 0x54) Configuration Register */ 1156 __I uint8_t Reserved2[140]; 1157 __IO uint32_t HSMCI_WPMR; /**< (HSMCI Offset: 0xE4) Write Protection Mode Register */ 1158 __I uint32_t HSMCI_WPSR; /**< (HSMCI Offset: 0xE8) Write Protection Status Register */ 1159 __I uint8_t Reserved3[16]; 1160 __I uint32_t HSMCI_VERSION; /**< (HSMCI Offset: 0xFC) Version Register */ 1161 __I uint8_t Reserved4[256]; 1162 __IO uint32_t HSMCI_FIFO[256]; /**< (HSMCI Offset: 0x200) FIFO Memory Aperture0 0 */ 1163 } Hsmci; 1164 1165 #elif COMPONENT_TYPEDEF_STYLE == 'N' 1166 /** \brief HSMCI hardware registers */ 1167 typedef struct { 1168 __O HSMCI_CR_Type HSMCI_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 1169 __IO HSMCI_MR_Type HSMCI_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 1170 __IO HSMCI_DTOR_Type HSMCI_DTOR; /**< Offset: 0x08 (R/W 32) Data Timeout Register */ 1171 __IO HSMCI_SDCR_Type HSMCI_SDCR; /**< Offset: 0x0C (R/W 32) SD/SDIO Card Register */ 1172 __IO HSMCI_ARGR_Type HSMCI_ARGR; /**< Offset: 0x10 (R/W 32) Argument Register */ 1173 __O HSMCI_CMDR_Type HSMCI_CMDR; /**< Offset: 0x14 ( /W 32) Command Register */ 1174 __IO HSMCI_BLKR_Type HSMCI_BLKR; /**< Offset: 0x18 (R/W 32) Block Register */ 1175 __IO HSMCI_CSTOR_Type HSMCI_CSTOR; /**< Offset: 0x1C (R/W 32) Completion Signal Timeout Register */ 1176 __I HSMCI_RSPR_Type HSMCI_RSPR[4]; /**< Offset: 0x20 (R/ 32) Response Register 0 */ 1177 __I HSMCI_RDR_Type HSMCI_RDR; /**< Offset: 0x30 (R/ 32) Receive Data Register */ 1178 __O HSMCI_TDR_Type HSMCI_TDR; /**< Offset: 0x34 ( /W 32) Transmit Data Register */ 1179 __I uint8_t Reserved1[8]; 1180 __I HSMCI_SR_Type HSMCI_SR; /**< Offset: 0x40 (R/ 32) Status Register */ 1181 __O HSMCI_IER_Type HSMCI_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */ 1182 __O HSMCI_IDR_Type HSMCI_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */ 1183 __I HSMCI_IMR_Type HSMCI_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */ 1184 __IO HSMCI_DMA_Type HSMCI_DMA; /**< Offset: 0x50 (R/W 32) DMA Configuration Register */ 1185 __IO HSMCI_CFG_Type HSMCI_CFG; /**< Offset: 0x54 (R/W 32) Configuration Register */ 1186 __I uint8_t Reserved2[140]; 1187 __IO HSMCI_WPMR_Type HSMCI_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 1188 __I HSMCI_WPSR_Type HSMCI_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 1189 __I uint8_t Reserved3[16]; 1190 __I HSMCI_VERSION_Type HSMCI_VERSION; /**< Offset: 0xFC (R/ 32) Version Register */ 1191 __I uint8_t Reserved4[256]; 1192 __IO HSMCI_FIFO_Type HSMCI_FIFO[256]; /**< Offset: 0x200 (R/W 32) FIFO Memory Aperture0 0 */ 1193 } Hsmci; 1194 1195 #else /* COMPONENT_TYPEDEF_STYLE */ 1196 #error Unknown component typedef style 1197 #endif /* COMPONENT_TYPEDEF_STYLE */ 1198 1199 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1200 /** @} end of High Speed MultiMedia Card Interface */ 1201 1202 #endif /* _SAMV71_HSMCI_COMPONENT_H_ */ 1203
