1 /** 2 * \file 3 * 4 * \brief Component description for USBHS 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:19:59Z */ 31 #ifndef _SAME70_USBHS_COMPONENT_H_ 32 #define _SAME70_USBHS_COMPONENT_H_ 33 #define _SAME70_USBHS_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 USB High-Speed Interface 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR USBHS */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define USBHS_11292 /**< (USBHS) Module ID */ 46 #define REV_USBHS G /**< (USBHS) Module revision */ 47 48 /* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Device DMA Channel Next Descriptor Address Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t NXT_DSC_ADD:32; /**< bit: 0..31 Next Descriptor Address */ 54 } bit; /**< Structure used for bit access */ 55 uint32_t reg; /**< Type used for register access */ 56 } USBHS_DEVDMANXTDSC_Type; 57 #endif 58 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 59 60 #define USBHS_DEVDMANXTDSC_OFFSET (0x00) /**< (USBHS_DEVDMANXTDSC) Device DMA Channel Next Descriptor Address Register Offset */ 61 62 #define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (USBHS_DEVDMANXTDSC) Next Descriptor Address Position */ 63 #define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< (USBHS_DEVDMANXTDSC) Next Descriptor Address Mask */ 64 #define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) (USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos)) 65 #define USBHS_DEVDMANXTDSC_MASK _U_(0xFFFFFFFF) /**< \deprecated (USBHS_DEVDMANXTDSC) Register MASK (Use USBHS_DEVDMANXTDSC_Msk instead) */ 66 #define USBHS_DEVDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (USBHS_DEVDMANXTDSC) Register Mask */ 67 68 69 /* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Device DMA Channel Address Register -------- */ 70 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 71 #if COMPONENT_TYPEDEF_STYLE == 'N' 72 typedef union { 73 struct { 74 uint32_t BUFF_ADD:32; /**< bit: 0..31 Buffer Address */ 75 } bit; /**< Structure used for bit access */ 76 uint32_t reg; /**< Type used for register access */ 77 } USBHS_DEVDMAADDRESS_Type; 78 #endif 79 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 80 81 #define USBHS_DEVDMAADDRESS_OFFSET (0x04) /**< (USBHS_DEVDMAADDRESS) Device DMA Channel Address Register Offset */ 82 83 #define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 /**< (USBHS_DEVDMAADDRESS) Buffer Address Position */ 84 #define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< (USBHS_DEVDMAADDRESS) Buffer Address Mask */ 85 #define USBHS_DEVDMAADDRESS_BUFF_ADD(value) (USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos)) 86 #define USBHS_DEVDMAADDRESS_MASK _U_(0xFFFFFFFF) /**< \deprecated (USBHS_DEVDMAADDRESS) Register MASK (Use USBHS_DEVDMAADDRESS_Msk instead) */ 87 #define USBHS_DEVDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (USBHS_DEVDMAADDRESS) Register Mask */ 88 89 90 /* -------- USBHS_DEVDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Device DMA Channel Control Register -------- */ 91 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 92 #if COMPONENT_TYPEDEF_STYLE == 'N' 93 typedef union { 94 struct { 95 uint32_t CHANN_ENB:1; /**< bit: 0 Channel Enable Command */ 96 uint32_t LDNXT_DSC:1; /**< bit: 1 Load Next Channel Transfer Descriptor Enable Command */ 97 uint32_t END_TR_EN:1; /**< bit: 2 End of Transfer Enable Control (OUT transfers only) */ 98 uint32_t END_B_EN:1; /**< bit: 3 End of Buffer Enable Control */ 99 uint32_t END_TR_IT:1; /**< bit: 4 End of Transfer Interrupt Enable */ 100 uint32_t END_BUFFIT:1; /**< bit: 5 End of Buffer Interrupt Enable */ 101 uint32_t DESC_LD_IT:1; /**< bit: 6 Descriptor Loaded Interrupt Enable */ 102 uint32_t BURST_LCK:1; /**< bit: 7 Burst Lock Enable */ 103 uint32_t :8; /**< bit: 8..15 Reserved */ 104 uint32_t BUFF_LENGTH:16; /**< bit: 16..31 Buffer Byte Length (Write-only) */ 105 } bit; /**< Structure used for bit access */ 106 uint32_t reg; /**< Type used for register access */ 107 } USBHS_DEVDMACONTROL_Type; 108 #endif 109 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 110 111 #define USBHS_DEVDMACONTROL_OFFSET (0x08) /**< (USBHS_DEVDMACONTROL) Device DMA Channel Control Register Offset */ 112 113 #define USBHS_DEVDMACONTROL_CHANN_ENB_Pos 0 /**< (USBHS_DEVDMACONTROL) Channel Enable Command Position */ 114 #define USBHS_DEVDMACONTROL_CHANN_ENB_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_CHANN_ENB_Pos) /**< (USBHS_DEVDMACONTROL) Channel Enable Command Mask */ 115 #define USBHS_DEVDMACONTROL_CHANN_ENB USBHS_DEVDMACONTROL_CHANN_ENB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_CHANN_ENB_Msk instead */ 116 #define USBHS_DEVDMACONTROL_LDNXT_DSC_Pos 1 /**< (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ 117 #define USBHS_DEVDMACONTROL_LDNXT_DSC_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_LDNXT_DSC_Pos) /**< (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ 118 #define USBHS_DEVDMACONTROL_LDNXT_DSC USBHS_DEVDMACONTROL_LDNXT_DSC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_LDNXT_DSC_Msk instead */ 119 #define USBHS_DEVDMACONTROL_END_TR_EN_Pos 2 /**< (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ 120 #define USBHS_DEVDMACONTROL_END_TR_EN_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_TR_EN_Pos) /**< (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ 121 #define USBHS_DEVDMACONTROL_END_TR_EN USBHS_DEVDMACONTROL_END_TR_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_END_TR_EN_Msk instead */ 122 #define USBHS_DEVDMACONTROL_END_B_EN_Pos 3 /**< (USBHS_DEVDMACONTROL) End of Buffer Enable Control Position */ 123 #define USBHS_DEVDMACONTROL_END_B_EN_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_B_EN_Pos) /**< (USBHS_DEVDMACONTROL) End of Buffer Enable Control Mask */ 124 #define USBHS_DEVDMACONTROL_END_B_EN USBHS_DEVDMACONTROL_END_B_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_END_B_EN_Msk instead */ 125 #define USBHS_DEVDMACONTROL_END_TR_IT_Pos 4 /**< (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable Position */ 126 #define USBHS_DEVDMACONTROL_END_TR_IT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_TR_IT_Pos) /**< (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable Mask */ 127 #define USBHS_DEVDMACONTROL_END_TR_IT USBHS_DEVDMACONTROL_END_TR_IT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_END_TR_IT_Msk instead */ 128 #define USBHS_DEVDMACONTROL_END_BUFFIT_Pos 5 /**< (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable Position */ 129 #define USBHS_DEVDMACONTROL_END_BUFFIT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_END_BUFFIT_Pos) /**< (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable Mask */ 130 #define USBHS_DEVDMACONTROL_END_BUFFIT USBHS_DEVDMACONTROL_END_BUFFIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_END_BUFFIT_Msk instead */ 131 #define USBHS_DEVDMACONTROL_DESC_LD_IT_Pos 6 /**< (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable Position */ 132 #define USBHS_DEVDMACONTROL_DESC_LD_IT_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_DESC_LD_IT_Pos) /**< (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ 133 #define USBHS_DEVDMACONTROL_DESC_LD_IT USBHS_DEVDMACONTROL_DESC_LD_IT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_DESC_LD_IT_Msk instead */ 134 #define USBHS_DEVDMACONTROL_BURST_LCK_Pos 7 /**< (USBHS_DEVDMACONTROL) Burst Lock Enable Position */ 135 #define USBHS_DEVDMACONTROL_BURST_LCK_Msk (_U_(0x1) << USBHS_DEVDMACONTROL_BURST_LCK_Pos) /**< (USBHS_DEVDMACONTROL) Burst Lock Enable Mask */ 136 #define USBHS_DEVDMACONTROL_BURST_LCK USBHS_DEVDMACONTROL_BURST_LCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMACONTROL_BURST_LCK_Msk instead */ 137 #define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 /**< (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) Position */ 138 #define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (_U_(0xFFFF) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) Mask */ 139 #define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) (USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos)) 140 #define USBHS_DEVDMACONTROL_MASK _U_(0xFFFF00FF) /**< \deprecated (USBHS_DEVDMACONTROL) Register MASK (Use USBHS_DEVDMACONTROL_Msk instead) */ 141 #define USBHS_DEVDMACONTROL_Msk _U_(0xFFFF00FF) /**< (USBHS_DEVDMACONTROL) Register Mask */ 142 143 144 /* -------- USBHS_DEVDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Device DMA Channel Status Register -------- */ 145 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 146 #if COMPONENT_TYPEDEF_STYLE == 'N' 147 typedef union { 148 struct { 149 uint32_t CHANN_ENB:1; /**< bit: 0 Channel Enable Status */ 150 uint32_t CHANN_ACT:1; /**< bit: 1 Channel Active Status */ 151 uint32_t :2; /**< bit: 2..3 Reserved */ 152 uint32_t END_TR_ST:1; /**< bit: 4 End of Channel Transfer Status */ 153 uint32_t END_BF_ST:1; /**< bit: 5 End of Channel Buffer Status */ 154 uint32_t DESC_LDST:1; /**< bit: 6 Descriptor Loaded Status */ 155 uint32_t :9; /**< bit: 7..15 Reserved */ 156 uint32_t BUFF_COUNT:16; /**< bit: 16..31 Buffer Byte Count */ 157 } bit; /**< Structure used for bit access */ 158 uint32_t reg; /**< Type used for register access */ 159 } USBHS_DEVDMASTATUS_Type; 160 #endif 161 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 162 163 #define USBHS_DEVDMASTATUS_OFFSET (0x0C) /**< (USBHS_DEVDMASTATUS) Device DMA Channel Status Register Offset */ 164 165 #define USBHS_DEVDMASTATUS_CHANN_ENB_Pos 0 /**< (USBHS_DEVDMASTATUS) Channel Enable Status Position */ 166 #define USBHS_DEVDMASTATUS_CHANN_ENB_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_CHANN_ENB_Pos) /**< (USBHS_DEVDMASTATUS) Channel Enable Status Mask */ 167 #define USBHS_DEVDMASTATUS_CHANN_ENB USBHS_DEVDMASTATUS_CHANN_ENB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_CHANN_ENB_Msk instead */ 168 #define USBHS_DEVDMASTATUS_CHANN_ACT_Pos 1 /**< (USBHS_DEVDMASTATUS) Channel Active Status Position */ 169 #define USBHS_DEVDMASTATUS_CHANN_ACT_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_CHANN_ACT_Pos) /**< (USBHS_DEVDMASTATUS) Channel Active Status Mask */ 170 #define USBHS_DEVDMASTATUS_CHANN_ACT USBHS_DEVDMASTATUS_CHANN_ACT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_CHANN_ACT_Msk instead */ 171 #define USBHS_DEVDMASTATUS_END_TR_ST_Pos 4 /**< (USBHS_DEVDMASTATUS) End of Channel Transfer Status Position */ 172 #define USBHS_DEVDMASTATUS_END_TR_ST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_END_TR_ST_Pos) /**< (USBHS_DEVDMASTATUS) End of Channel Transfer Status Mask */ 173 #define USBHS_DEVDMASTATUS_END_TR_ST USBHS_DEVDMASTATUS_END_TR_ST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_END_TR_ST_Msk instead */ 174 #define USBHS_DEVDMASTATUS_END_BF_ST_Pos 5 /**< (USBHS_DEVDMASTATUS) End of Channel Buffer Status Position */ 175 #define USBHS_DEVDMASTATUS_END_BF_ST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_END_BF_ST_Pos) /**< (USBHS_DEVDMASTATUS) End of Channel Buffer Status Mask */ 176 #define USBHS_DEVDMASTATUS_END_BF_ST USBHS_DEVDMASTATUS_END_BF_ST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_END_BF_ST_Msk instead */ 177 #define USBHS_DEVDMASTATUS_DESC_LDST_Pos 6 /**< (USBHS_DEVDMASTATUS) Descriptor Loaded Status Position */ 178 #define USBHS_DEVDMASTATUS_DESC_LDST_Msk (_U_(0x1) << USBHS_DEVDMASTATUS_DESC_LDST_Pos) /**< (USBHS_DEVDMASTATUS) Descriptor Loaded Status Mask */ 179 #define USBHS_DEVDMASTATUS_DESC_LDST USBHS_DEVDMASTATUS_DESC_LDST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVDMASTATUS_DESC_LDST_Msk instead */ 180 #define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 /**< (USBHS_DEVDMASTATUS) Buffer Byte Count Position */ 181 #define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (_U_(0xFFFF) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< (USBHS_DEVDMASTATUS) Buffer Byte Count Mask */ 182 #define USBHS_DEVDMASTATUS_BUFF_COUNT(value) (USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos)) 183 #define USBHS_DEVDMASTATUS_MASK _U_(0xFFFF0073) /**< \deprecated (USBHS_DEVDMASTATUS) Register MASK (Use USBHS_DEVDMASTATUS_Msk instead) */ 184 #define USBHS_DEVDMASTATUS_Msk _U_(0xFFFF0073) /**< (USBHS_DEVDMASTATUS) Register Mask */ 185 186 187 /* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: 0x00) (R/W 32) Host DMA Channel Next Descriptor Address Register -------- */ 188 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 189 #if COMPONENT_TYPEDEF_STYLE == 'N' 190 typedef union { 191 struct { 192 uint32_t NXT_DSC_ADD:32; /**< bit: 0..31 Next Descriptor Address */ 193 } bit; /**< Structure used for bit access */ 194 uint32_t reg; /**< Type used for register access */ 195 } USBHS_HSTDMANXTDSC_Type; 196 #endif 197 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 198 199 #define USBHS_HSTDMANXTDSC_OFFSET (0x00) /**< (USBHS_HSTDMANXTDSC) Host DMA Channel Next Descriptor Address Register Offset */ 200 201 #define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 /**< (USBHS_HSTDMANXTDSC) Next Descriptor Address Position */ 202 #define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< (USBHS_HSTDMANXTDSC) Next Descriptor Address Mask */ 203 #define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) (USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos)) 204 #define USBHS_HSTDMANXTDSC_MASK _U_(0xFFFFFFFF) /**< \deprecated (USBHS_HSTDMANXTDSC) Register MASK (Use USBHS_HSTDMANXTDSC_Msk instead) */ 205 #define USBHS_HSTDMANXTDSC_Msk _U_(0xFFFFFFFF) /**< (USBHS_HSTDMANXTDSC) Register Mask */ 206 207 208 /* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: 0x04) (R/W 32) Host DMA Channel Address Register -------- */ 209 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 210 #if COMPONENT_TYPEDEF_STYLE == 'N' 211 typedef union { 212 struct { 213 uint32_t BUFF_ADD:32; /**< bit: 0..31 Buffer Address */ 214 } bit; /**< Structure used for bit access */ 215 uint32_t reg; /**< Type used for register access */ 216 } USBHS_HSTDMAADDRESS_Type; 217 #endif 218 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 219 220 #define USBHS_HSTDMAADDRESS_OFFSET (0x04) /**< (USBHS_HSTDMAADDRESS) Host DMA Channel Address Register Offset */ 221 222 #define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 /**< (USBHS_HSTDMAADDRESS) Buffer Address Position */ 223 #define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (_U_(0xFFFFFFFF) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< (USBHS_HSTDMAADDRESS) Buffer Address Mask */ 224 #define USBHS_HSTDMAADDRESS_BUFF_ADD(value) (USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos)) 225 #define USBHS_HSTDMAADDRESS_MASK _U_(0xFFFFFFFF) /**< \deprecated (USBHS_HSTDMAADDRESS) Register MASK (Use USBHS_HSTDMAADDRESS_Msk instead) */ 226 #define USBHS_HSTDMAADDRESS_Msk _U_(0xFFFFFFFF) /**< (USBHS_HSTDMAADDRESS) Register Mask */ 227 228 229 /* -------- USBHS_HSTDMACONTROL : (USBHS Offset: 0x08) (R/W 32) Host DMA Channel Control Register -------- */ 230 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 231 #if COMPONENT_TYPEDEF_STYLE == 'N' 232 typedef union { 233 struct { 234 uint32_t CHANN_ENB:1; /**< bit: 0 Channel Enable Command */ 235 uint32_t LDNXT_DSC:1; /**< bit: 1 Load Next Channel Transfer Descriptor Enable Command */ 236 uint32_t END_TR_EN:1; /**< bit: 2 End of Transfer Enable Control (OUT transfers only) */ 237 uint32_t END_B_EN:1; /**< bit: 3 End of Buffer Enable Control */ 238 uint32_t END_TR_IT:1; /**< bit: 4 End of Transfer Interrupt Enable */ 239 uint32_t END_BUFFIT:1; /**< bit: 5 End of Buffer Interrupt Enable */ 240 uint32_t DESC_LD_IT:1; /**< bit: 6 Descriptor Loaded Interrupt Enable */ 241 uint32_t BURST_LCK:1; /**< bit: 7 Burst Lock Enable */ 242 uint32_t :8; /**< bit: 8..15 Reserved */ 243 uint32_t BUFF_LENGTH:16; /**< bit: 16..31 Buffer Byte Length (Write-only) */ 244 } bit; /**< Structure used for bit access */ 245 uint32_t reg; /**< Type used for register access */ 246 } USBHS_HSTDMACONTROL_Type; 247 #endif 248 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 249 250 #define USBHS_HSTDMACONTROL_OFFSET (0x08) /**< (USBHS_HSTDMACONTROL) Host DMA Channel Control Register Offset */ 251 252 #define USBHS_HSTDMACONTROL_CHANN_ENB_Pos 0 /**< (USBHS_HSTDMACONTROL) Channel Enable Command Position */ 253 #define USBHS_HSTDMACONTROL_CHANN_ENB_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_CHANN_ENB_Pos) /**< (USBHS_HSTDMACONTROL) Channel Enable Command Mask */ 254 #define USBHS_HSTDMACONTROL_CHANN_ENB USBHS_HSTDMACONTROL_CHANN_ENB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_CHANN_ENB_Msk instead */ 255 #define USBHS_HSTDMACONTROL_LDNXT_DSC_Pos 1 /**< (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Position */ 256 #define USBHS_HSTDMACONTROL_LDNXT_DSC_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_LDNXT_DSC_Pos) /**< (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command Mask */ 257 #define USBHS_HSTDMACONTROL_LDNXT_DSC USBHS_HSTDMACONTROL_LDNXT_DSC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_LDNXT_DSC_Msk instead */ 258 #define USBHS_HSTDMACONTROL_END_TR_EN_Pos 2 /**< (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Position */ 259 #define USBHS_HSTDMACONTROL_END_TR_EN_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_TR_EN_Pos) /**< (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) Mask */ 260 #define USBHS_HSTDMACONTROL_END_TR_EN USBHS_HSTDMACONTROL_END_TR_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_END_TR_EN_Msk instead */ 261 #define USBHS_HSTDMACONTROL_END_B_EN_Pos 3 /**< (USBHS_HSTDMACONTROL) End of Buffer Enable Control Position */ 262 #define USBHS_HSTDMACONTROL_END_B_EN_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_B_EN_Pos) /**< (USBHS_HSTDMACONTROL) End of Buffer Enable Control Mask */ 263 #define USBHS_HSTDMACONTROL_END_B_EN USBHS_HSTDMACONTROL_END_B_EN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_END_B_EN_Msk instead */ 264 #define USBHS_HSTDMACONTROL_END_TR_IT_Pos 4 /**< (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable Position */ 265 #define USBHS_HSTDMACONTROL_END_TR_IT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_TR_IT_Pos) /**< (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable Mask */ 266 #define USBHS_HSTDMACONTROL_END_TR_IT USBHS_HSTDMACONTROL_END_TR_IT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_END_TR_IT_Msk instead */ 267 #define USBHS_HSTDMACONTROL_END_BUFFIT_Pos 5 /**< (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable Position */ 268 #define USBHS_HSTDMACONTROL_END_BUFFIT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_END_BUFFIT_Pos) /**< (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable Mask */ 269 #define USBHS_HSTDMACONTROL_END_BUFFIT USBHS_HSTDMACONTROL_END_BUFFIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_END_BUFFIT_Msk instead */ 270 #define USBHS_HSTDMACONTROL_DESC_LD_IT_Pos 6 /**< (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable Position */ 271 #define USBHS_HSTDMACONTROL_DESC_LD_IT_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_DESC_LD_IT_Pos) /**< (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable Mask */ 272 #define USBHS_HSTDMACONTROL_DESC_LD_IT USBHS_HSTDMACONTROL_DESC_LD_IT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_DESC_LD_IT_Msk instead */ 273 #define USBHS_HSTDMACONTROL_BURST_LCK_Pos 7 /**< (USBHS_HSTDMACONTROL) Burst Lock Enable Position */ 274 #define USBHS_HSTDMACONTROL_BURST_LCK_Msk (_U_(0x1) << USBHS_HSTDMACONTROL_BURST_LCK_Pos) /**< (USBHS_HSTDMACONTROL) Burst Lock Enable Mask */ 275 #define USBHS_HSTDMACONTROL_BURST_LCK USBHS_HSTDMACONTROL_BURST_LCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMACONTROL_BURST_LCK_Msk instead */ 276 #define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 /**< (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) Position */ 277 #define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (_U_(0xFFFF) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) Mask */ 278 #define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) (USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos)) 279 #define USBHS_HSTDMACONTROL_MASK _U_(0xFFFF00FF) /**< \deprecated (USBHS_HSTDMACONTROL) Register MASK (Use USBHS_HSTDMACONTROL_Msk instead) */ 280 #define USBHS_HSTDMACONTROL_Msk _U_(0xFFFF00FF) /**< (USBHS_HSTDMACONTROL) Register Mask */ 281 282 283 /* -------- USBHS_HSTDMASTATUS : (USBHS Offset: 0x0c) (R/W 32) Host DMA Channel Status Register -------- */ 284 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 285 #if COMPONENT_TYPEDEF_STYLE == 'N' 286 typedef union { 287 struct { 288 uint32_t CHANN_ENB:1; /**< bit: 0 Channel Enable Status */ 289 uint32_t CHANN_ACT:1; /**< bit: 1 Channel Active Status */ 290 uint32_t :2; /**< bit: 2..3 Reserved */ 291 uint32_t END_TR_ST:1; /**< bit: 4 End of Channel Transfer Status */ 292 uint32_t END_BF_ST:1; /**< bit: 5 End of Channel Buffer Status */ 293 uint32_t DESC_LDST:1; /**< bit: 6 Descriptor Loaded Status */ 294 uint32_t :9; /**< bit: 7..15 Reserved */ 295 uint32_t BUFF_COUNT:16; /**< bit: 16..31 Buffer Byte Count */ 296 } bit; /**< Structure used for bit access */ 297 uint32_t reg; /**< Type used for register access */ 298 } USBHS_HSTDMASTATUS_Type; 299 #endif 300 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 301 302 #define USBHS_HSTDMASTATUS_OFFSET (0x0C) /**< (USBHS_HSTDMASTATUS) Host DMA Channel Status Register Offset */ 303 304 #define USBHS_HSTDMASTATUS_CHANN_ENB_Pos 0 /**< (USBHS_HSTDMASTATUS) Channel Enable Status Position */ 305 #define USBHS_HSTDMASTATUS_CHANN_ENB_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_CHANN_ENB_Pos) /**< (USBHS_HSTDMASTATUS) Channel Enable Status Mask */ 306 #define USBHS_HSTDMASTATUS_CHANN_ENB USBHS_HSTDMASTATUS_CHANN_ENB_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_CHANN_ENB_Msk instead */ 307 #define USBHS_HSTDMASTATUS_CHANN_ACT_Pos 1 /**< (USBHS_HSTDMASTATUS) Channel Active Status Position */ 308 #define USBHS_HSTDMASTATUS_CHANN_ACT_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_CHANN_ACT_Pos) /**< (USBHS_HSTDMASTATUS) Channel Active Status Mask */ 309 #define USBHS_HSTDMASTATUS_CHANN_ACT USBHS_HSTDMASTATUS_CHANN_ACT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_CHANN_ACT_Msk instead */ 310 #define USBHS_HSTDMASTATUS_END_TR_ST_Pos 4 /**< (USBHS_HSTDMASTATUS) End of Channel Transfer Status Position */ 311 #define USBHS_HSTDMASTATUS_END_TR_ST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_END_TR_ST_Pos) /**< (USBHS_HSTDMASTATUS) End of Channel Transfer Status Mask */ 312 #define USBHS_HSTDMASTATUS_END_TR_ST USBHS_HSTDMASTATUS_END_TR_ST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_END_TR_ST_Msk instead */ 313 #define USBHS_HSTDMASTATUS_END_BF_ST_Pos 5 /**< (USBHS_HSTDMASTATUS) End of Channel Buffer Status Position */ 314 #define USBHS_HSTDMASTATUS_END_BF_ST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_END_BF_ST_Pos) /**< (USBHS_HSTDMASTATUS) End of Channel Buffer Status Mask */ 315 #define USBHS_HSTDMASTATUS_END_BF_ST USBHS_HSTDMASTATUS_END_BF_ST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_END_BF_ST_Msk instead */ 316 #define USBHS_HSTDMASTATUS_DESC_LDST_Pos 6 /**< (USBHS_HSTDMASTATUS) Descriptor Loaded Status Position */ 317 #define USBHS_HSTDMASTATUS_DESC_LDST_Msk (_U_(0x1) << USBHS_HSTDMASTATUS_DESC_LDST_Pos) /**< (USBHS_HSTDMASTATUS) Descriptor Loaded Status Mask */ 318 #define USBHS_HSTDMASTATUS_DESC_LDST USBHS_HSTDMASTATUS_DESC_LDST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTDMASTATUS_DESC_LDST_Msk instead */ 319 #define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 /**< (USBHS_HSTDMASTATUS) Buffer Byte Count Position */ 320 #define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (_U_(0xFFFF) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< (USBHS_HSTDMASTATUS) Buffer Byte Count Mask */ 321 #define USBHS_HSTDMASTATUS_BUFF_COUNT(value) (USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos)) 322 #define USBHS_HSTDMASTATUS_MASK _U_(0xFFFF0073) /**< \deprecated (USBHS_HSTDMASTATUS) Register MASK (Use USBHS_HSTDMASTATUS_Msk instead) */ 323 #define USBHS_HSTDMASTATUS_Msk _U_(0xFFFF0073) /**< (USBHS_HSTDMASTATUS) Register Mask */ 324 325 326 /* -------- USBHS_DEVCTRL : (USBHS Offset: 0x00) (R/W 32) Device General Control Register -------- */ 327 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 328 #if COMPONENT_TYPEDEF_STYLE == 'N' 329 typedef union { 330 struct { 331 uint32_t UADD:7; /**< bit: 0..6 USB Address */ 332 uint32_t ADDEN:1; /**< bit: 7 Address Enable */ 333 uint32_t DETACH:1; /**< bit: 8 Detach */ 334 uint32_t RMWKUP:1; /**< bit: 9 Remote Wake-Up */ 335 uint32_t SPDCONF:2; /**< bit: 10..11 Mode Configuration */ 336 uint32_t LS:1; /**< bit: 12 Low-Speed Mode Force */ 337 uint32_t TSTJ:1; /**< bit: 13 Test mode J */ 338 uint32_t TSTK:1; /**< bit: 14 Test mode K */ 339 uint32_t TSTPCKT:1; /**< bit: 15 Test packet mode */ 340 uint32_t OPMODE2:1; /**< bit: 16 Specific Operational mode */ 341 uint32_t :15; /**< bit: 17..31 Reserved */ 342 } bit; /**< Structure used for bit access */ 343 struct { 344 uint32_t :16; /**< bit: 0..15 Reserved */ 345 uint32_t OPMODE:1; /**< bit: 16 Specific Operational mode */ 346 uint32_t :15; /**< bit: 17..31 Reserved */ 347 } vec; /**< Structure used for vec access */ 348 uint32_t reg; /**< Type used for register access */ 349 } USBHS_DEVCTRL_Type; 350 #endif 351 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 352 353 #define USBHS_DEVCTRL_OFFSET (0x00) /**< (USBHS_DEVCTRL) Device General Control Register Offset */ 354 355 #define USBHS_DEVCTRL_UADD_Pos 0 /**< (USBHS_DEVCTRL) USB Address Position */ 356 #define USBHS_DEVCTRL_UADD_Msk (_U_(0x7F) << USBHS_DEVCTRL_UADD_Pos) /**< (USBHS_DEVCTRL) USB Address Mask */ 357 #define USBHS_DEVCTRL_UADD(value) (USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos)) 358 #define USBHS_DEVCTRL_ADDEN_Pos 7 /**< (USBHS_DEVCTRL) Address Enable Position */ 359 #define USBHS_DEVCTRL_ADDEN_Msk (_U_(0x1) << USBHS_DEVCTRL_ADDEN_Pos) /**< (USBHS_DEVCTRL) Address Enable Mask */ 360 #define USBHS_DEVCTRL_ADDEN USBHS_DEVCTRL_ADDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_ADDEN_Msk instead */ 361 #define USBHS_DEVCTRL_DETACH_Pos 8 /**< (USBHS_DEVCTRL) Detach Position */ 362 #define USBHS_DEVCTRL_DETACH_Msk (_U_(0x1) << USBHS_DEVCTRL_DETACH_Pos) /**< (USBHS_DEVCTRL) Detach Mask */ 363 #define USBHS_DEVCTRL_DETACH USBHS_DEVCTRL_DETACH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_DETACH_Msk instead */ 364 #define USBHS_DEVCTRL_RMWKUP_Pos 9 /**< (USBHS_DEVCTRL) Remote Wake-Up Position */ 365 #define USBHS_DEVCTRL_RMWKUP_Msk (_U_(0x1) << USBHS_DEVCTRL_RMWKUP_Pos) /**< (USBHS_DEVCTRL) Remote Wake-Up Mask */ 366 #define USBHS_DEVCTRL_RMWKUP USBHS_DEVCTRL_RMWKUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_RMWKUP_Msk instead */ 367 #define USBHS_DEVCTRL_SPDCONF_Pos 10 /**< (USBHS_DEVCTRL) Mode Configuration Position */ 368 #define USBHS_DEVCTRL_SPDCONF_Msk (_U_(0x3) << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) Mode Configuration Mask */ 369 #define USBHS_DEVCTRL_SPDCONF(value) (USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos)) 370 #define USBHS_DEVCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ 371 #define USBHS_DEVCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ 372 #define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (USBHS_DEVCTRL) Forced high speed. */ 373 #define USBHS_DEVCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ 374 #define USBHS_DEVCTRL_SPDCONF_NORMAL (USBHS_DEVCTRL_SPDCONF_NORMAL_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. Position */ 375 #define USBHS_DEVCTRL_SPDCONF_LOW_POWER (USBHS_DEVCTRL_SPDCONF_LOW_POWER_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. Position */ 376 #define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (USBHS_DEVCTRL_SPDCONF_HIGH_SPEED_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) Forced high speed. Position */ 377 #define USBHS_DEVCTRL_SPDCONF_FORCED_FS (USBHS_DEVCTRL_SPDCONF_FORCED_FS_Val << USBHS_DEVCTRL_SPDCONF_Pos) /**< (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. Position */ 378 #define USBHS_DEVCTRL_LS_Pos 12 /**< (USBHS_DEVCTRL) Low-Speed Mode Force Position */ 379 #define USBHS_DEVCTRL_LS_Msk (_U_(0x1) << USBHS_DEVCTRL_LS_Pos) /**< (USBHS_DEVCTRL) Low-Speed Mode Force Mask */ 380 #define USBHS_DEVCTRL_LS USBHS_DEVCTRL_LS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_LS_Msk instead */ 381 #define USBHS_DEVCTRL_TSTJ_Pos 13 /**< (USBHS_DEVCTRL) Test mode J Position */ 382 #define USBHS_DEVCTRL_TSTJ_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTJ_Pos) /**< (USBHS_DEVCTRL) Test mode J Mask */ 383 #define USBHS_DEVCTRL_TSTJ USBHS_DEVCTRL_TSTJ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_TSTJ_Msk instead */ 384 #define USBHS_DEVCTRL_TSTK_Pos 14 /**< (USBHS_DEVCTRL) Test mode K Position */ 385 #define USBHS_DEVCTRL_TSTK_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTK_Pos) /**< (USBHS_DEVCTRL) Test mode K Mask */ 386 #define USBHS_DEVCTRL_TSTK USBHS_DEVCTRL_TSTK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_TSTK_Msk instead */ 387 #define USBHS_DEVCTRL_TSTPCKT_Pos 15 /**< (USBHS_DEVCTRL) Test packet mode Position */ 388 #define USBHS_DEVCTRL_TSTPCKT_Msk (_U_(0x1) << USBHS_DEVCTRL_TSTPCKT_Pos) /**< (USBHS_DEVCTRL) Test packet mode Mask */ 389 #define USBHS_DEVCTRL_TSTPCKT USBHS_DEVCTRL_TSTPCKT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_TSTPCKT_Msk instead */ 390 #define USBHS_DEVCTRL_OPMODE2_Pos 16 /**< (USBHS_DEVCTRL) Specific Operational mode Position */ 391 #define USBHS_DEVCTRL_OPMODE2_Msk (_U_(0x1) << USBHS_DEVCTRL_OPMODE2_Pos) /**< (USBHS_DEVCTRL) Specific Operational mode Mask */ 392 #define USBHS_DEVCTRL_OPMODE2 USBHS_DEVCTRL_OPMODE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVCTRL_OPMODE2_Msk instead */ 393 #define USBHS_DEVCTRL_MASK _U_(0x1FFFF) /**< \deprecated (USBHS_DEVCTRL) Register MASK (Use USBHS_DEVCTRL_Msk instead) */ 394 #define USBHS_DEVCTRL_Msk _U_(0x1FFFF) /**< (USBHS_DEVCTRL) Register Mask */ 395 396 #define USBHS_DEVCTRL_OPMODE_Pos 16 /**< (USBHS_DEVCTRL Position) Specific Operational mode */ 397 #define USBHS_DEVCTRL_OPMODE_Msk (_U_(0x1) << USBHS_DEVCTRL_OPMODE_Pos) /**< (USBHS_DEVCTRL Mask) OPMODE */ 398 #define USBHS_DEVCTRL_OPMODE(value) (USBHS_DEVCTRL_OPMODE_Msk & ((value) << USBHS_DEVCTRL_OPMODE_Pos)) 399 400 /* -------- USBHS_DEVISR : (USBHS Offset: 0x04) (R/ 32) Device Global Interrupt Status Register -------- */ 401 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 402 #if COMPONENT_TYPEDEF_STYLE == 'N' 403 typedef union { 404 struct { 405 uint32_t SUSP:1; /**< bit: 0 Suspend Interrupt */ 406 uint32_t MSOF:1; /**< bit: 1 Micro Start of Frame Interrupt */ 407 uint32_t SOF:1; /**< bit: 2 Start of Frame Interrupt */ 408 uint32_t EORST:1; /**< bit: 3 End of Reset Interrupt */ 409 uint32_t WAKEUP:1; /**< bit: 4 Wake-Up Interrupt */ 410 uint32_t EORSM:1; /**< bit: 5 End of Resume Interrupt */ 411 uint32_t UPRSM:1; /**< bit: 6 Upstream Resume Interrupt */ 412 uint32_t :5; /**< bit: 7..11 Reserved */ 413 uint32_t PEP_0:1; /**< bit: 12 Endpoint 0 Interrupt */ 414 uint32_t PEP_1:1; /**< bit: 13 Endpoint 1 Interrupt */ 415 uint32_t PEP_2:1; /**< bit: 14 Endpoint 2 Interrupt */ 416 uint32_t PEP_3:1; /**< bit: 15 Endpoint 3 Interrupt */ 417 uint32_t PEP_4:1; /**< bit: 16 Endpoint 4 Interrupt */ 418 uint32_t PEP_5:1; /**< bit: 17 Endpoint 5 Interrupt */ 419 uint32_t PEP_6:1; /**< bit: 18 Endpoint 6 Interrupt */ 420 uint32_t PEP_7:1; /**< bit: 19 Endpoint 7 Interrupt */ 421 uint32_t PEP_8:1; /**< bit: 20 Endpoint 8 Interrupt */ 422 uint32_t PEP_9:1; /**< bit: 21 Endpoint 9 Interrupt */ 423 uint32_t :3; /**< bit: 22..24 Reserved */ 424 uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt */ 425 uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt */ 426 uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt */ 427 uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt */ 428 uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt */ 429 uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt */ 430 uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt */ 431 } bit; /**< Structure used for bit access */ 432 struct { 433 uint32_t :12; /**< bit: 0..11 Reserved */ 434 uint32_t PEP_:10; /**< bit: 12..21 Endpoint x Interrupt */ 435 uint32_t :3; /**< bit: 22..24 Reserved */ 436 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt */ 437 } vec; /**< Structure used for vec access */ 438 uint32_t reg; /**< Type used for register access */ 439 } USBHS_DEVISR_Type; 440 #endif 441 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 442 443 #define USBHS_DEVISR_OFFSET (0x04) /**< (USBHS_DEVISR) Device Global Interrupt Status Register Offset */ 444 445 #define USBHS_DEVISR_SUSP_Pos 0 /**< (USBHS_DEVISR) Suspend Interrupt Position */ 446 #define USBHS_DEVISR_SUSP_Msk (_U_(0x1) << USBHS_DEVISR_SUSP_Pos) /**< (USBHS_DEVISR) Suspend Interrupt Mask */ 447 #define USBHS_DEVISR_SUSP USBHS_DEVISR_SUSP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_SUSP_Msk instead */ 448 #define USBHS_DEVISR_MSOF_Pos 1 /**< (USBHS_DEVISR) Micro Start of Frame Interrupt Position */ 449 #define USBHS_DEVISR_MSOF_Msk (_U_(0x1) << USBHS_DEVISR_MSOF_Pos) /**< (USBHS_DEVISR) Micro Start of Frame Interrupt Mask */ 450 #define USBHS_DEVISR_MSOF USBHS_DEVISR_MSOF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_MSOF_Msk instead */ 451 #define USBHS_DEVISR_SOF_Pos 2 /**< (USBHS_DEVISR) Start of Frame Interrupt Position */ 452 #define USBHS_DEVISR_SOF_Msk (_U_(0x1) << USBHS_DEVISR_SOF_Pos) /**< (USBHS_DEVISR) Start of Frame Interrupt Mask */ 453 #define USBHS_DEVISR_SOF USBHS_DEVISR_SOF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_SOF_Msk instead */ 454 #define USBHS_DEVISR_EORST_Pos 3 /**< (USBHS_DEVISR) End of Reset Interrupt Position */ 455 #define USBHS_DEVISR_EORST_Msk (_U_(0x1) << USBHS_DEVISR_EORST_Pos) /**< (USBHS_DEVISR) End of Reset Interrupt Mask */ 456 #define USBHS_DEVISR_EORST USBHS_DEVISR_EORST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_EORST_Msk instead */ 457 #define USBHS_DEVISR_WAKEUP_Pos 4 /**< (USBHS_DEVISR) Wake-Up Interrupt Position */ 458 #define USBHS_DEVISR_WAKEUP_Msk (_U_(0x1) << USBHS_DEVISR_WAKEUP_Pos) /**< (USBHS_DEVISR) Wake-Up Interrupt Mask */ 459 #define USBHS_DEVISR_WAKEUP USBHS_DEVISR_WAKEUP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_WAKEUP_Msk instead */ 460 #define USBHS_DEVISR_EORSM_Pos 5 /**< (USBHS_DEVISR) End of Resume Interrupt Position */ 461 #define USBHS_DEVISR_EORSM_Msk (_U_(0x1) << USBHS_DEVISR_EORSM_Pos) /**< (USBHS_DEVISR) End of Resume Interrupt Mask */ 462 #define USBHS_DEVISR_EORSM USBHS_DEVISR_EORSM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_EORSM_Msk instead */ 463 #define USBHS_DEVISR_UPRSM_Pos 6 /**< (USBHS_DEVISR) Upstream Resume Interrupt Position */ 464 #define USBHS_DEVISR_UPRSM_Msk (_U_(0x1) << USBHS_DEVISR_UPRSM_Pos) /**< (USBHS_DEVISR) Upstream Resume Interrupt Mask */ 465 #define USBHS_DEVISR_UPRSM USBHS_DEVISR_UPRSM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_UPRSM_Msk instead */ 466 #define USBHS_DEVISR_PEP_0_Pos 12 /**< (USBHS_DEVISR) Endpoint 0 Interrupt Position */ 467 #define USBHS_DEVISR_PEP_0_Msk (_U_(0x1) << USBHS_DEVISR_PEP_0_Pos) /**< (USBHS_DEVISR) Endpoint 0 Interrupt Mask */ 468 #define USBHS_DEVISR_PEP_0 USBHS_DEVISR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_0_Msk instead */ 469 #define USBHS_DEVISR_PEP_1_Pos 13 /**< (USBHS_DEVISR) Endpoint 1 Interrupt Position */ 470 #define USBHS_DEVISR_PEP_1_Msk (_U_(0x1) << USBHS_DEVISR_PEP_1_Pos) /**< (USBHS_DEVISR) Endpoint 1 Interrupt Mask */ 471 #define USBHS_DEVISR_PEP_1 USBHS_DEVISR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_1_Msk instead */ 472 #define USBHS_DEVISR_PEP_2_Pos 14 /**< (USBHS_DEVISR) Endpoint 2 Interrupt Position */ 473 #define USBHS_DEVISR_PEP_2_Msk (_U_(0x1) << USBHS_DEVISR_PEP_2_Pos) /**< (USBHS_DEVISR) Endpoint 2 Interrupt Mask */ 474 #define USBHS_DEVISR_PEP_2 USBHS_DEVISR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_2_Msk instead */ 475 #define USBHS_DEVISR_PEP_3_Pos 15 /**< (USBHS_DEVISR) Endpoint 3 Interrupt Position */ 476 #define USBHS_DEVISR_PEP_3_Msk (_U_(0x1) << USBHS_DEVISR_PEP_3_Pos) /**< (USBHS_DEVISR) Endpoint 3 Interrupt Mask */ 477 #define USBHS_DEVISR_PEP_3 USBHS_DEVISR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_3_Msk instead */ 478 #define USBHS_DEVISR_PEP_4_Pos 16 /**< (USBHS_DEVISR) Endpoint 4 Interrupt Position */ 479 #define USBHS_DEVISR_PEP_4_Msk (_U_(0x1) << USBHS_DEVISR_PEP_4_Pos) /**< (USBHS_DEVISR) Endpoint 4 Interrupt Mask */ 480 #define USBHS_DEVISR_PEP_4 USBHS_DEVISR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_4_Msk instead */ 481 #define USBHS_DEVISR_PEP_5_Pos 17 /**< (USBHS_DEVISR) Endpoint 5 Interrupt Position */ 482 #define USBHS_DEVISR_PEP_5_Msk (_U_(0x1) << USBHS_DEVISR_PEP_5_Pos) /**< (USBHS_DEVISR) Endpoint 5 Interrupt Mask */ 483 #define USBHS_DEVISR_PEP_5 USBHS_DEVISR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_5_Msk instead */ 484 #define USBHS_DEVISR_PEP_6_Pos 18 /**< (USBHS_DEVISR) Endpoint 6 Interrupt Position */ 485 #define USBHS_DEVISR_PEP_6_Msk (_U_(0x1) << USBHS_DEVISR_PEP_6_Pos) /**< (USBHS_DEVISR) Endpoint 6 Interrupt Mask */ 486 #define USBHS_DEVISR_PEP_6 USBHS_DEVISR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_6_Msk instead */ 487 #define USBHS_DEVISR_PEP_7_Pos 19 /**< (USBHS_DEVISR) Endpoint 7 Interrupt Position */ 488 #define USBHS_DEVISR_PEP_7_Msk (_U_(0x1) << USBHS_DEVISR_PEP_7_Pos) /**< (USBHS_DEVISR) Endpoint 7 Interrupt Mask */ 489 #define USBHS_DEVISR_PEP_7 USBHS_DEVISR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_7_Msk instead */ 490 #define USBHS_DEVISR_PEP_8_Pos 20 /**< (USBHS_DEVISR) Endpoint 8 Interrupt Position */ 491 #define USBHS_DEVISR_PEP_8_Msk (_U_(0x1) << USBHS_DEVISR_PEP_8_Pos) /**< (USBHS_DEVISR) Endpoint 8 Interrupt Mask */ 492 #define USBHS_DEVISR_PEP_8 USBHS_DEVISR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_8_Msk instead */ 493 #define USBHS_DEVISR_PEP_9_Pos 21 /**< (USBHS_DEVISR) Endpoint 9 Interrupt Position */ 494 #define USBHS_DEVISR_PEP_9_Msk (_U_(0x1) << USBHS_DEVISR_PEP_9_Pos) /**< (USBHS_DEVISR) Endpoint 9 Interrupt Mask */ 495 #define USBHS_DEVISR_PEP_9 USBHS_DEVISR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_PEP_9_Msk instead */ 496 #define USBHS_DEVISR_DMA_1_Pos 25 /**< (USBHS_DEVISR) DMA Channel 1 Interrupt Position */ 497 #define USBHS_DEVISR_DMA_1_Msk (_U_(0x1) << USBHS_DEVISR_DMA_1_Pos) /**< (USBHS_DEVISR) DMA Channel 1 Interrupt Mask */ 498 #define USBHS_DEVISR_DMA_1 USBHS_DEVISR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_1_Msk instead */ 499 #define USBHS_DEVISR_DMA_2_Pos 26 /**< (USBHS_DEVISR) DMA Channel 2 Interrupt Position */ 500 #define USBHS_DEVISR_DMA_2_Msk (_U_(0x1) << USBHS_DEVISR_DMA_2_Pos) /**< (USBHS_DEVISR) DMA Channel 2 Interrupt Mask */ 501 #define USBHS_DEVISR_DMA_2 USBHS_DEVISR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_2_Msk instead */ 502 #define USBHS_DEVISR_DMA_3_Pos 27 /**< (USBHS_DEVISR) DMA Channel 3 Interrupt Position */ 503 #define USBHS_DEVISR_DMA_3_Msk (_U_(0x1) << USBHS_DEVISR_DMA_3_Pos) /**< (USBHS_DEVISR) DMA Channel 3 Interrupt Mask */ 504 #define USBHS_DEVISR_DMA_3 USBHS_DEVISR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_3_Msk instead */ 505 #define USBHS_DEVISR_DMA_4_Pos 28 /**< (USBHS_DEVISR) DMA Channel 4 Interrupt Position */ 506 #define USBHS_DEVISR_DMA_4_Msk (_U_(0x1) << USBHS_DEVISR_DMA_4_Pos) /**< (USBHS_DEVISR) DMA Channel 4 Interrupt Mask */ 507 #define USBHS_DEVISR_DMA_4 USBHS_DEVISR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_4_Msk instead */ 508 #define USBHS_DEVISR_DMA_5_Pos 29 /**< (USBHS_DEVISR) DMA Channel 5 Interrupt Position */ 509 #define USBHS_DEVISR_DMA_5_Msk (_U_(0x1) << USBHS_DEVISR_DMA_5_Pos) /**< (USBHS_DEVISR) DMA Channel 5 Interrupt Mask */ 510 #define USBHS_DEVISR_DMA_5 USBHS_DEVISR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_5_Msk instead */ 511 #define USBHS_DEVISR_DMA_6_Pos 30 /**< (USBHS_DEVISR) DMA Channel 6 Interrupt Position */ 512 #define USBHS_DEVISR_DMA_6_Msk (_U_(0x1) << USBHS_DEVISR_DMA_6_Pos) /**< (USBHS_DEVISR) DMA Channel 6 Interrupt Mask */ 513 #define USBHS_DEVISR_DMA_6 USBHS_DEVISR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_6_Msk instead */ 514 #define USBHS_DEVISR_DMA_7_Pos 31 /**< (USBHS_DEVISR) DMA Channel 7 Interrupt Position */ 515 #define USBHS_DEVISR_DMA_7_Msk (_U_(0x1) << USBHS_DEVISR_DMA_7_Pos) /**< (USBHS_DEVISR) DMA Channel 7 Interrupt Mask */ 516 #define USBHS_DEVISR_DMA_7 USBHS_DEVISR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVISR_DMA_7_Msk instead */ 517 #define USBHS_DEVISR_MASK _U_(0xFE3FF07F) /**< \deprecated (USBHS_DEVISR) Register MASK (Use USBHS_DEVISR_Msk instead) */ 518 #define USBHS_DEVISR_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVISR) Register Mask */ 519 520 #define USBHS_DEVISR_PEP__Pos 12 /**< (USBHS_DEVISR Position) Endpoint x Interrupt */ 521 #define USBHS_DEVISR_PEP__Msk (_U_(0x3FF) << USBHS_DEVISR_PEP__Pos) /**< (USBHS_DEVISR Mask) PEP_ */ 522 #define USBHS_DEVISR_PEP_(value) (USBHS_DEVISR_PEP__Msk & ((value) << USBHS_DEVISR_PEP__Pos)) 523 #define USBHS_DEVISR_DMA__Pos 25 /**< (USBHS_DEVISR Position) DMA Channel 7 Interrupt */ 524 #define USBHS_DEVISR_DMA__Msk (_U_(0x7F) << USBHS_DEVISR_DMA__Pos) /**< (USBHS_DEVISR Mask) DMA_ */ 525 #define USBHS_DEVISR_DMA_(value) (USBHS_DEVISR_DMA__Msk & ((value) << USBHS_DEVISR_DMA__Pos)) 526 527 /* -------- USBHS_DEVICR : (USBHS Offset: 0x08) (/W 32) Device Global Interrupt Clear Register -------- */ 528 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 529 #if COMPONENT_TYPEDEF_STYLE == 'N' 530 typedef union { 531 struct { 532 uint32_t SUSPC:1; /**< bit: 0 Suspend Interrupt Clear */ 533 uint32_t MSOFC:1; /**< bit: 1 Micro Start of Frame Interrupt Clear */ 534 uint32_t SOFC:1; /**< bit: 2 Start of Frame Interrupt Clear */ 535 uint32_t EORSTC:1; /**< bit: 3 End of Reset Interrupt Clear */ 536 uint32_t WAKEUPC:1; /**< bit: 4 Wake-Up Interrupt Clear */ 537 uint32_t EORSMC:1; /**< bit: 5 End of Resume Interrupt Clear */ 538 uint32_t UPRSMC:1; /**< bit: 6 Upstream Resume Interrupt Clear */ 539 uint32_t :25; /**< bit: 7..31 Reserved */ 540 } bit; /**< Structure used for bit access */ 541 uint32_t reg; /**< Type used for register access */ 542 } USBHS_DEVICR_Type; 543 #endif 544 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 545 546 #define USBHS_DEVICR_OFFSET (0x08) /**< (USBHS_DEVICR) Device Global Interrupt Clear Register Offset */ 547 548 #define USBHS_DEVICR_SUSPC_Pos 0 /**< (USBHS_DEVICR) Suspend Interrupt Clear Position */ 549 #define USBHS_DEVICR_SUSPC_Msk (_U_(0x1) << USBHS_DEVICR_SUSPC_Pos) /**< (USBHS_DEVICR) Suspend Interrupt Clear Mask */ 550 #define USBHS_DEVICR_SUSPC USBHS_DEVICR_SUSPC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_SUSPC_Msk instead */ 551 #define USBHS_DEVICR_MSOFC_Pos 1 /**< (USBHS_DEVICR) Micro Start of Frame Interrupt Clear Position */ 552 #define USBHS_DEVICR_MSOFC_Msk (_U_(0x1) << USBHS_DEVICR_MSOFC_Pos) /**< (USBHS_DEVICR) Micro Start of Frame Interrupt Clear Mask */ 553 #define USBHS_DEVICR_MSOFC USBHS_DEVICR_MSOFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_MSOFC_Msk instead */ 554 #define USBHS_DEVICR_SOFC_Pos 2 /**< (USBHS_DEVICR) Start of Frame Interrupt Clear Position */ 555 #define USBHS_DEVICR_SOFC_Msk (_U_(0x1) << USBHS_DEVICR_SOFC_Pos) /**< (USBHS_DEVICR) Start of Frame Interrupt Clear Mask */ 556 #define USBHS_DEVICR_SOFC USBHS_DEVICR_SOFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_SOFC_Msk instead */ 557 #define USBHS_DEVICR_EORSTC_Pos 3 /**< (USBHS_DEVICR) End of Reset Interrupt Clear Position */ 558 #define USBHS_DEVICR_EORSTC_Msk (_U_(0x1) << USBHS_DEVICR_EORSTC_Pos) /**< (USBHS_DEVICR) End of Reset Interrupt Clear Mask */ 559 #define USBHS_DEVICR_EORSTC USBHS_DEVICR_EORSTC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_EORSTC_Msk instead */ 560 #define USBHS_DEVICR_WAKEUPC_Pos 4 /**< (USBHS_DEVICR) Wake-Up Interrupt Clear Position */ 561 #define USBHS_DEVICR_WAKEUPC_Msk (_U_(0x1) << USBHS_DEVICR_WAKEUPC_Pos) /**< (USBHS_DEVICR) Wake-Up Interrupt Clear Mask */ 562 #define USBHS_DEVICR_WAKEUPC USBHS_DEVICR_WAKEUPC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_WAKEUPC_Msk instead */ 563 #define USBHS_DEVICR_EORSMC_Pos 5 /**< (USBHS_DEVICR) End of Resume Interrupt Clear Position */ 564 #define USBHS_DEVICR_EORSMC_Msk (_U_(0x1) << USBHS_DEVICR_EORSMC_Pos) /**< (USBHS_DEVICR) End of Resume Interrupt Clear Mask */ 565 #define USBHS_DEVICR_EORSMC USBHS_DEVICR_EORSMC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_EORSMC_Msk instead */ 566 #define USBHS_DEVICR_UPRSMC_Pos 6 /**< (USBHS_DEVICR) Upstream Resume Interrupt Clear Position */ 567 #define USBHS_DEVICR_UPRSMC_Msk (_U_(0x1) << USBHS_DEVICR_UPRSMC_Pos) /**< (USBHS_DEVICR) Upstream Resume Interrupt Clear Mask */ 568 #define USBHS_DEVICR_UPRSMC USBHS_DEVICR_UPRSMC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVICR_UPRSMC_Msk instead */ 569 #define USBHS_DEVICR_MASK _U_(0x7F) /**< \deprecated (USBHS_DEVICR) Register MASK (Use USBHS_DEVICR_Msk instead) */ 570 #define USBHS_DEVICR_Msk _U_(0x7F) /**< (USBHS_DEVICR) Register Mask */ 571 572 573 /* -------- USBHS_DEVIFR : (USBHS Offset: 0x0c) (/W 32) Device Global Interrupt Set Register -------- */ 574 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 575 #if COMPONENT_TYPEDEF_STYLE == 'N' 576 typedef union { 577 struct { 578 uint32_t SUSPS:1; /**< bit: 0 Suspend Interrupt Set */ 579 uint32_t MSOFS:1; /**< bit: 1 Micro Start of Frame Interrupt Set */ 580 uint32_t SOFS:1; /**< bit: 2 Start of Frame Interrupt Set */ 581 uint32_t EORSTS:1; /**< bit: 3 End of Reset Interrupt Set */ 582 uint32_t WAKEUPS:1; /**< bit: 4 Wake-Up Interrupt Set */ 583 uint32_t EORSMS:1; /**< bit: 5 End of Resume Interrupt Set */ 584 uint32_t UPRSMS:1; /**< bit: 6 Upstream Resume Interrupt Set */ 585 uint32_t :18; /**< bit: 7..24 Reserved */ 586 uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt Set */ 587 uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt Set */ 588 uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt Set */ 589 uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt Set */ 590 uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt Set */ 591 uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt Set */ 592 uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt Set */ 593 } bit; /**< Structure used for bit access */ 594 struct { 595 uint32_t :25; /**< bit: 0..24 Reserved */ 596 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt Set */ 597 } vec; /**< Structure used for vec access */ 598 uint32_t reg; /**< Type used for register access */ 599 } USBHS_DEVIFR_Type; 600 #endif 601 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 602 603 #define USBHS_DEVIFR_OFFSET (0x0C) /**< (USBHS_DEVIFR) Device Global Interrupt Set Register Offset */ 604 605 #define USBHS_DEVIFR_SUSPS_Pos 0 /**< (USBHS_DEVIFR) Suspend Interrupt Set Position */ 606 #define USBHS_DEVIFR_SUSPS_Msk (_U_(0x1) << USBHS_DEVIFR_SUSPS_Pos) /**< (USBHS_DEVIFR) Suspend Interrupt Set Mask */ 607 #define USBHS_DEVIFR_SUSPS USBHS_DEVIFR_SUSPS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_SUSPS_Msk instead */ 608 #define USBHS_DEVIFR_MSOFS_Pos 1 /**< (USBHS_DEVIFR) Micro Start of Frame Interrupt Set Position */ 609 #define USBHS_DEVIFR_MSOFS_Msk (_U_(0x1) << USBHS_DEVIFR_MSOFS_Pos) /**< (USBHS_DEVIFR) Micro Start of Frame Interrupt Set Mask */ 610 #define USBHS_DEVIFR_MSOFS USBHS_DEVIFR_MSOFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_MSOFS_Msk instead */ 611 #define USBHS_DEVIFR_SOFS_Pos 2 /**< (USBHS_DEVIFR) Start of Frame Interrupt Set Position */ 612 #define USBHS_DEVIFR_SOFS_Msk (_U_(0x1) << USBHS_DEVIFR_SOFS_Pos) /**< (USBHS_DEVIFR) Start of Frame Interrupt Set Mask */ 613 #define USBHS_DEVIFR_SOFS USBHS_DEVIFR_SOFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_SOFS_Msk instead */ 614 #define USBHS_DEVIFR_EORSTS_Pos 3 /**< (USBHS_DEVIFR) End of Reset Interrupt Set Position */ 615 #define USBHS_DEVIFR_EORSTS_Msk (_U_(0x1) << USBHS_DEVIFR_EORSTS_Pos) /**< (USBHS_DEVIFR) End of Reset Interrupt Set Mask */ 616 #define USBHS_DEVIFR_EORSTS USBHS_DEVIFR_EORSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_EORSTS_Msk instead */ 617 #define USBHS_DEVIFR_WAKEUPS_Pos 4 /**< (USBHS_DEVIFR) Wake-Up Interrupt Set Position */ 618 #define USBHS_DEVIFR_WAKEUPS_Msk (_U_(0x1) << USBHS_DEVIFR_WAKEUPS_Pos) /**< (USBHS_DEVIFR) Wake-Up Interrupt Set Mask */ 619 #define USBHS_DEVIFR_WAKEUPS USBHS_DEVIFR_WAKEUPS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_WAKEUPS_Msk instead */ 620 #define USBHS_DEVIFR_EORSMS_Pos 5 /**< (USBHS_DEVIFR) End of Resume Interrupt Set Position */ 621 #define USBHS_DEVIFR_EORSMS_Msk (_U_(0x1) << USBHS_DEVIFR_EORSMS_Pos) /**< (USBHS_DEVIFR) End of Resume Interrupt Set Mask */ 622 #define USBHS_DEVIFR_EORSMS USBHS_DEVIFR_EORSMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_EORSMS_Msk instead */ 623 #define USBHS_DEVIFR_UPRSMS_Pos 6 /**< (USBHS_DEVIFR) Upstream Resume Interrupt Set Position */ 624 #define USBHS_DEVIFR_UPRSMS_Msk (_U_(0x1) << USBHS_DEVIFR_UPRSMS_Pos) /**< (USBHS_DEVIFR) Upstream Resume Interrupt Set Mask */ 625 #define USBHS_DEVIFR_UPRSMS USBHS_DEVIFR_UPRSMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_UPRSMS_Msk instead */ 626 #define USBHS_DEVIFR_DMA_1_Pos 25 /**< (USBHS_DEVIFR) DMA Channel 1 Interrupt Set Position */ 627 #define USBHS_DEVIFR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_1_Pos) /**< (USBHS_DEVIFR) DMA Channel 1 Interrupt Set Mask */ 628 #define USBHS_DEVIFR_DMA_1 USBHS_DEVIFR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_1_Msk instead */ 629 #define USBHS_DEVIFR_DMA_2_Pos 26 /**< (USBHS_DEVIFR) DMA Channel 2 Interrupt Set Position */ 630 #define USBHS_DEVIFR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_2_Pos) /**< (USBHS_DEVIFR) DMA Channel 2 Interrupt Set Mask */ 631 #define USBHS_DEVIFR_DMA_2 USBHS_DEVIFR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_2_Msk instead */ 632 #define USBHS_DEVIFR_DMA_3_Pos 27 /**< (USBHS_DEVIFR) DMA Channel 3 Interrupt Set Position */ 633 #define USBHS_DEVIFR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_3_Pos) /**< (USBHS_DEVIFR) DMA Channel 3 Interrupt Set Mask */ 634 #define USBHS_DEVIFR_DMA_3 USBHS_DEVIFR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_3_Msk instead */ 635 #define USBHS_DEVIFR_DMA_4_Pos 28 /**< (USBHS_DEVIFR) DMA Channel 4 Interrupt Set Position */ 636 #define USBHS_DEVIFR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_4_Pos) /**< (USBHS_DEVIFR) DMA Channel 4 Interrupt Set Mask */ 637 #define USBHS_DEVIFR_DMA_4 USBHS_DEVIFR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_4_Msk instead */ 638 #define USBHS_DEVIFR_DMA_5_Pos 29 /**< (USBHS_DEVIFR) DMA Channel 5 Interrupt Set Position */ 639 #define USBHS_DEVIFR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_5_Pos) /**< (USBHS_DEVIFR) DMA Channel 5 Interrupt Set Mask */ 640 #define USBHS_DEVIFR_DMA_5 USBHS_DEVIFR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_5_Msk instead */ 641 #define USBHS_DEVIFR_DMA_6_Pos 30 /**< (USBHS_DEVIFR) DMA Channel 6 Interrupt Set Position */ 642 #define USBHS_DEVIFR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_6_Pos) /**< (USBHS_DEVIFR) DMA Channel 6 Interrupt Set Mask */ 643 #define USBHS_DEVIFR_DMA_6 USBHS_DEVIFR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_6_Msk instead */ 644 #define USBHS_DEVIFR_DMA_7_Pos 31 /**< (USBHS_DEVIFR) DMA Channel 7 Interrupt Set Position */ 645 #define USBHS_DEVIFR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIFR_DMA_7_Pos) /**< (USBHS_DEVIFR) DMA Channel 7 Interrupt Set Mask */ 646 #define USBHS_DEVIFR_DMA_7 USBHS_DEVIFR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIFR_DMA_7_Msk instead */ 647 #define USBHS_DEVIFR_MASK _U_(0xFE00007F) /**< \deprecated (USBHS_DEVIFR) Register MASK (Use USBHS_DEVIFR_Msk instead) */ 648 #define USBHS_DEVIFR_Msk _U_(0xFE00007F) /**< (USBHS_DEVIFR) Register Mask */ 649 650 #define USBHS_DEVIFR_DMA__Pos 25 /**< (USBHS_DEVIFR Position) DMA Channel 7 Interrupt Set */ 651 #define USBHS_DEVIFR_DMA__Msk (_U_(0x7F) << USBHS_DEVIFR_DMA__Pos) /**< (USBHS_DEVIFR Mask) DMA_ */ 652 #define USBHS_DEVIFR_DMA_(value) (USBHS_DEVIFR_DMA__Msk & ((value) << USBHS_DEVIFR_DMA__Pos)) 653 654 /* -------- USBHS_DEVIMR : (USBHS Offset: 0x10) (R/ 32) Device Global Interrupt Mask Register -------- */ 655 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 656 #if COMPONENT_TYPEDEF_STYLE == 'N' 657 typedef union { 658 struct { 659 uint32_t SUSPE:1; /**< bit: 0 Suspend Interrupt Mask */ 660 uint32_t MSOFE:1; /**< bit: 1 Micro Start of Frame Interrupt Mask */ 661 uint32_t SOFE:1; /**< bit: 2 Start of Frame Interrupt Mask */ 662 uint32_t EORSTE:1; /**< bit: 3 End of Reset Interrupt Mask */ 663 uint32_t WAKEUPE:1; /**< bit: 4 Wake-Up Interrupt Mask */ 664 uint32_t EORSME:1; /**< bit: 5 End of Resume Interrupt Mask */ 665 uint32_t UPRSME:1; /**< bit: 6 Upstream Resume Interrupt Mask */ 666 uint32_t :5; /**< bit: 7..11 Reserved */ 667 uint32_t PEP_0:1; /**< bit: 12 Endpoint 0 Interrupt Mask */ 668 uint32_t PEP_1:1; /**< bit: 13 Endpoint 1 Interrupt Mask */ 669 uint32_t PEP_2:1; /**< bit: 14 Endpoint 2 Interrupt Mask */ 670 uint32_t PEP_3:1; /**< bit: 15 Endpoint 3 Interrupt Mask */ 671 uint32_t PEP_4:1; /**< bit: 16 Endpoint 4 Interrupt Mask */ 672 uint32_t PEP_5:1; /**< bit: 17 Endpoint 5 Interrupt Mask */ 673 uint32_t PEP_6:1; /**< bit: 18 Endpoint 6 Interrupt Mask */ 674 uint32_t PEP_7:1; /**< bit: 19 Endpoint 7 Interrupt Mask */ 675 uint32_t PEP_8:1; /**< bit: 20 Endpoint 8 Interrupt Mask */ 676 uint32_t PEP_9:1; /**< bit: 21 Endpoint 9 Interrupt Mask */ 677 uint32_t :3; /**< bit: 22..24 Reserved */ 678 uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt Mask */ 679 uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt Mask */ 680 uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt Mask */ 681 uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt Mask */ 682 uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt Mask */ 683 uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt Mask */ 684 uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt Mask */ 685 } bit; /**< Structure used for bit access */ 686 struct { 687 uint32_t :12; /**< bit: 0..11 Reserved */ 688 uint32_t PEP_:10; /**< bit: 12..21 Endpoint x Interrupt Mask */ 689 uint32_t :3; /**< bit: 22..24 Reserved */ 690 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt Mask */ 691 } vec; /**< Structure used for vec access */ 692 uint32_t reg; /**< Type used for register access */ 693 } USBHS_DEVIMR_Type; 694 #endif 695 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 696 697 #define USBHS_DEVIMR_OFFSET (0x10) /**< (USBHS_DEVIMR) Device Global Interrupt Mask Register Offset */ 698 699 #define USBHS_DEVIMR_SUSPE_Pos 0 /**< (USBHS_DEVIMR) Suspend Interrupt Mask Position */ 700 #define USBHS_DEVIMR_SUSPE_Msk (_U_(0x1) << USBHS_DEVIMR_SUSPE_Pos) /**< (USBHS_DEVIMR) Suspend Interrupt Mask Mask */ 701 #define USBHS_DEVIMR_SUSPE USBHS_DEVIMR_SUSPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_SUSPE_Msk instead */ 702 #define USBHS_DEVIMR_MSOFE_Pos 1 /**< (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask Position */ 703 #define USBHS_DEVIMR_MSOFE_Msk (_U_(0x1) << USBHS_DEVIMR_MSOFE_Pos) /**< (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask Mask */ 704 #define USBHS_DEVIMR_MSOFE USBHS_DEVIMR_MSOFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_MSOFE_Msk instead */ 705 #define USBHS_DEVIMR_SOFE_Pos 2 /**< (USBHS_DEVIMR) Start of Frame Interrupt Mask Position */ 706 #define USBHS_DEVIMR_SOFE_Msk (_U_(0x1) << USBHS_DEVIMR_SOFE_Pos) /**< (USBHS_DEVIMR) Start of Frame Interrupt Mask Mask */ 707 #define USBHS_DEVIMR_SOFE USBHS_DEVIMR_SOFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_SOFE_Msk instead */ 708 #define USBHS_DEVIMR_EORSTE_Pos 3 /**< (USBHS_DEVIMR) End of Reset Interrupt Mask Position */ 709 #define USBHS_DEVIMR_EORSTE_Msk (_U_(0x1) << USBHS_DEVIMR_EORSTE_Pos) /**< (USBHS_DEVIMR) End of Reset Interrupt Mask Mask */ 710 #define USBHS_DEVIMR_EORSTE USBHS_DEVIMR_EORSTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_EORSTE_Msk instead */ 711 #define USBHS_DEVIMR_WAKEUPE_Pos 4 /**< (USBHS_DEVIMR) Wake-Up Interrupt Mask Position */ 712 #define USBHS_DEVIMR_WAKEUPE_Msk (_U_(0x1) << USBHS_DEVIMR_WAKEUPE_Pos) /**< (USBHS_DEVIMR) Wake-Up Interrupt Mask Mask */ 713 #define USBHS_DEVIMR_WAKEUPE USBHS_DEVIMR_WAKEUPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_WAKEUPE_Msk instead */ 714 #define USBHS_DEVIMR_EORSME_Pos 5 /**< (USBHS_DEVIMR) End of Resume Interrupt Mask Position */ 715 #define USBHS_DEVIMR_EORSME_Msk (_U_(0x1) << USBHS_DEVIMR_EORSME_Pos) /**< (USBHS_DEVIMR) End of Resume Interrupt Mask Mask */ 716 #define USBHS_DEVIMR_EORSME USBHS_DEVIMR_EORSME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_EORSME_Msk instead */ 717 #define USBHS_DEVIMR_UPRSME_Pos 6 /**< (USBHS_DEVIMR) Upstream Resume Interrupt Mask Position */ 718 #define USBHS_DEVIMR_UPRSME_Msk (_U_(0x1) << USBHS_DEVIMR_UPRSME_Pos) /**< (USBHS_DEVIMR) Upstream Resume Interrupt Mask Mask */ 719 #define USBHS_DEVIMR_UPRSME USBHS_DEVIMR_UPRSME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_UPRSME_Msk instead */ 720 #define USBHS_DEVIMR_PEP_0_Pos 12 /**< (USBHS_DEVIMR) Endpoint 0 Interrupt Mask Position */ 721 #define USBHS_DEVIMR_PEP_0_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_0_Pos) /**< (USBHS_DEVIMR) Endpoint 0 Interrupt Mask Mask */ 722 #define USBHS_DEVIMR_PEP_0 USBHS_DEVIMR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_0_Msk instead */ 723 #define USBHS_DEVIMR_PEP_1_Pos 13 /**< (USBHS_DEVIMR) Endpoint 1 Interrupt Mask Position */ 724 #define USBHS_DEVIMR_PEP_1_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_1_Pos) /**< (USBHS_DEVIMR) Endpoint 1 Interrupt Mask Mask */ 725 #define USBHS_DEVIMR_PEP_1 USBHS_DEVIMR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_1_Msk instead */ 726 #define USBHS_DEVIMR_PEP_2_Pos 14 /**< (USBHS_DEVIMR) Endpoint 2 Interrupt Mask Position */ 727 #define USBHS_DEVIMR_PEP_2_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_2_Pos) /**< (USBHS_DEVIMR) Endpoint 2 Interrupt Mask Mask */ 728 #define USBHS_DEVIMR_PEP_2 USBHS_DEVIMR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_2_Msk instead */ 729 #define USBHS_DEVIMR_PEP_3_Pos 15 /**< (USBHS_DEVIMR) Endpoint 3 Interrupt Mask Position */ 730 #define USBHS_DEVIMR_PEP_3_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_3_Pos) /**< (USBHS_DEVIMR) Endpoint 3 Interrupt Mask Mask */ 731 #define USBHS_DEVIMR_PEP_3 USBHS_DEVIMR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_3_Msk instead */ 732 #define USBHS_DEVIMR_PEP_4_Pos 16 /**< (USBHS_DEVIMR) Endpoint 4 Interrupt Mask Position */ 733 #define USBHS_DEVIMR_PEP_4_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_4_Pos) /**< (USBHS_DEVIMR) Endpoint 4 Interrupt Mask Mask */ 734 #define USBHS_DEVIMR_PEP_4 USBHS_DEVIMR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_4_Msk instead */ 735 #define USBHS_DEVIMR_PEP_5_Pos 17 /**< (USBHS_DEVIMR) Endpoint 5 Interrupt Mask Position */ 736 #define USBHS_DEVIMR_PEP_5_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_5_Pos) /**< (USBHS_DEVIMR) Endpoint 5 Interrupt Mask Mask */ 737 #define USBHS_DEVIMR_PEP_5 USBHS_DEVIMR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_5_Msk instead */ 738 #define USBHS_DEVIMR_PEP_6_Pos 18 /**< (USBHS_DEVIMR) Endpoint 6 Interrupt Mask Position */ 739 #define USBHS_DEVIMR_PEP_6_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_6_Pos) /**< (USBHS_DEVIMR) Endpoint 6 Interrupt Mask Mask */ 740 #define USBHS_DEVIMR_PEP_6 USBHS_DEVIMR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_6_Msk instead */ 741 #define USBHS_DEVIMR_PEP_7_Pos 19 /**< (USBHS_DEVIMR) Endpoint 7 Interrupt Mask Position */ 742 #define USBHS_DEVIMR_PEP_7_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_7_Pos) /**< (USBHS_DEVIMR) Endpoint 7 Interrupt Mask Mask */ 743 #define USBHS_DEVIMR_PEP_7 USBHS_DEVIMR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_7_Msk instead */ 744 #define USBHS_DEVIMR_PEP_8_Pos 20 /**< (USBHS_DEVIMR) Endpoint 8 Interrupt Mask Position */ 745 #define USBHS_DEVIMR_PEP_8_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_8_Pos) /**< (USBHS_DEVIMR) Endpoint 8 Interrupt Mask Mask */ 746 #define USBHS_DEVIMR_PEP_8 USBHS_DEVIMR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_8_Msk instead */ 747 #define USBHS_DEVIMR_PEP_9_Pos 21 /**< (USBHS_DEVIMR) Endpoint 9 Interrupt Mask Position */ 748 #define USBHS_DEVIMR_PEP_9_Msk (_U_(0x1) << USBHS_DEVIMR_PEP_9_Pos) /**< (USBHS_DEVIMR) Endpoint 9 Interrupt Mask Mask */ 749 #define USBHS_DEVIMR_PEP_9 USBHS_DEVIMR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_PEP_9_Msk instead */ 750 #define USBHS_DEVIMR_DMA_1_Pos 25 /**< (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask Position */ 751 #define USBHS_DEVIMR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_1_Pos) /**< (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask Mask */ 752 #define USBHS_DEVIMR_DMA_1 USBHS_DEVIMR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_1_Msk instead */ 753 #define USBHS_DEVIMR_DMA_2_Pos 26 /**< (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask Position */ 754 #define USBHS_DEVIMR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_2_Pos) /**< (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask Mask */ 755 #define USBHS_DEVIMR_DMA_2 USBHS_DEVIMR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_2_Msk instead */ 756 #define USBHS_DEVIMR_DMA_3_Pos 27 /**< (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask Position */ 757 #define USBHS_DEVIMR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_3_Pos) /**< (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask Mask */ 758 #define USBHS_DEVIMR_DMA_3 USBHS_DEVIMR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_3_Msk instead */ 759 #define USBHS_DEVIMR_DMA_4_Pos 28 /**< (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask Position */ 760 #define USBHS_DEVIMR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_4_Pos) /**< (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask Mask */ 761 #define USBHS_DEVIMR_DMA_4 USBHS_DEVIMR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_4_Msk instead */ 762 #define USBHS_DEVIMR_DMA_5_Pos 29 /**< (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask Position */ 763 #define USBHS_DEVIMR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_5_Pos) /**< (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask Mask */ 764 #define USBHS_DEVIMR_DMA_5 USBHS_DEVIMR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_5_Msk instead */ 765 #define USBHS_DEVIMR_DMA_6_Pos 30 /**< (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask Position */ 766 #define USBHS_DEVIMR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_6_Pos) /**< (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask Mask */ 767 #define USBHS_DEVIMR_DMA_6 USBHS_DEVIMR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_6_Msk instead */ 768 #define USBHS_DEVIMR_DMA_7_Pos 31 /**< (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask Position */ 769 #define USBHS_DEVIMR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIMR_DMA_7_Pos) /**< (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask Mask */ 770 #define USBHS_DEVIMR_DMA_7 USBHS_DEVIMR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIMR_DMA_7_Msk instead */ 771 #define USBHS_DEVIMR_MASK _U_(0xFE3FF07F) /**< \deprecated (USBHS_DEVIMR) Register MASK (Use USBHS_DEVIMR_Msk instead) */ 772 #define USBHS_DEVIMR_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVIMR) Register Mask */ 773 774 #define USBHS_DEVIMR_PEP__Pos 12 /**< (USBHS_DEVIMR Position) Endpoint x Interrupt Mask */ 775 #define USBHS_DEVIMR_PEP__Msk (_U_(0x3FF) << USBHS_DEVIMR_PEP__Pos) /**< (USBHS_DEVIMR Mask) PEP_ */ 776 #define USBHS_DEVIMR_PEP_(value) (USBHS_DEVIMR_PEP__Msk & ((value) << USBHS_DEVIMR_PEP__Pos)) 777 #define USBHS_DEVIMR_DMA__Pos 25 /**< (USBHS_DEVIMR Position) DMA Channel 7 Interrupt Mask */ 778 #define USBHS_DEVIMR_DMA__Msk (_U_(0x7F) << USBHS_DEVIMR_DMA__Pos) /**< (USBHS_DEVIMR Mask) DMA_ */ 779 #define USBHS_DEVIMR_DMA_(value) (USBHS_DEVIMR_DMA__Msk & ((value) << USBHS_DEVIMR_DMA__Pos)) 780 781 /* -------- USBHS_DEVIDR : (USBHS Offset: 0x14) (/W 32) Device Global Interrupt Disable Register -------- */ 782 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 783 #if COMPONENT_TYPEDEF_STYLE == 'N' 784 typedef union { 785 struct { 786 uint32_t SUSPEC:1; /**< bit: 0 Suspend Interrupt Disable */ 787 uint32_t MSOFEC:1; /**< bit: 1 Micro Start of Frame Interrupt Disable */ 788 uint32_t SOFEC:1; /**< bit: 2 Start of Frame Interrupt Disable */ 789 uint32_t EORSTEC:1; /**< bit: 3 End of Reset Interrupt Disable */ 790 uint32_t WAKEUPEC:1; /**< bit: 4 Wake-Up Interrupt Disable */ 791 uint32_t EORSMEC:1; /**< bit: 5 End of Resume Interrupt Disable */ 792 uint32_t UPRSMEC:1; /**< bit: 6 Upstream Resume Interrupt Disable */ 793 uint32_t :5; /**< bit: 7..11 Reserved */ 794 uint32_t PEP_0:1; /**< bit: 12 Endpoint 0 Interrupt Disable */ 795 uint32_t PEP_1:1; /**< bit: 13 Endpoint 1 Interrupt Disable */ 796 uint32_t PEP_2:1; /**< bit: 14 Endpoint 2 Interrupt Disable */ 797 uint32_t PEP_3:1; /**< bit: 15 Endpoint 3 Interrupt Disable */ 798 uint32_t PEP_4:1; /**< bit: 16 Endpoint 4 Interrupt Disable */ 799 uint32_t PEP_5:1; /**< bit: 17 Endpoint 5 Interrupt Disable */ 800 uint32_t PEP_6:1; /**< bit: 18 Endpoint 6 Interrupt Disable */ 801 uint32_t PEP_7:1; /**< bit: 19 Endpoint 7 Interrupt Disable */ 802 uint32_t PEP_8:1; /**< bit: 20 Endpoint 8 Interrupt Disable */ 803 uint32_t PEP_9:1; /**< bit: 21 Endpoint 9 Interrupt Disable */ 804 uint32_t :3; /**< bit: 22..24 Reserved */ 805 uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt Disable */ 806 uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt Disable */ 807 uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt Disable */ 808 uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt Disable */ 809 uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt Disable */ 810 uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt Disable */ 811 uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt Disable */ 812 } bit; /**< Structure used for bit access */ 813 struct { 814 uint32_t :12; /**< bit: 0..11 Reserved */ 815 uint32_t PEP_:10; /**< bit: 12..21 Endpoint x Interrupt Disable */ 816 uint32_t :3; /**< bit: 22..24 Reserved */ 817 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt Disable */ 818 } vec; /**< Structure used for vec access */ 819 uint32_t reg; /**< Type used for register access */ 820 } USBHS_DEVIDR_Type; 821 #endif 822 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 823 824 #define USBHS_DEVIDR_OFFSET (0x14) /**< (USBHS_DEVIDR) Device Global Interrupt Disable Register Offset */ 825 826 #define USBHS_DEVIDR_SUSPEC_Pos 0 /**< (USBHS_DEVIDR) Suspend Interrupt Disable Position */ 827 #define USBHS_DEVIDR_SUSPEC_Msk (_U_(0x1) << USBHS_DEVIDR_SUSPEC_Pos) /**< (USBHS_DEVIDR) Suspend Interrupt Disable Mask */ 828 #define USBHS_DEVIDR_SUSPEC USBHS_DEVIDR_SUSPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_SUSPEC_Msk instead */ 829 #define USBHS_DEVIDR_MSOFEC_Pos 1 /**< (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable Position */ 830 #define USBHS_DEVIDR_MSOFEC_Msk (_U_(0x1) << USBHS_DEVIDR_MSOFEC_Pos) /**< (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable Mask */ 831 #define USBHS_DEVIDR_MSOFEC USBHS_DEVIDR_MSOFEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_MSOFEC_Msk instead */ 832 #define USBHS_DEVIDR_SOFEC_Pos 2 /**< (USBHS_DEVIDR) Start of Frame Interrupt Disable Position */ 833 #define USBHS_DEVIDR_SOFEC_Msk (_U_(0x1) << USBHS_DEVIDR_SOFEC_Pos) /**< (USBHS_DEVIDR) Start of Frame Interrupt Disable Mask */ 834 #define USBHS_DEVIDR_SOFEC USBHS_DEVIDR_SOFEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_SOFEC_Msk instead */ 835 #define USBHS_DEVIDR_EORSTEC_Pos 3 /**< (USBHS_DEVIDR) End of Reset Interrupt Disable Position */ 836 #define USBHS_DEVIDR_EORSTEC_Msk (_U_(0x1) << USBHS_DEVIDR_EORSTEC_Pos) /**< (USBHS_DEVIDR) End of Reset Interrupt Disable Mask */ 837 #define USBHS_DEVIDR_EORSTEC USBHS_DEVIDR_EORSTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_EORSTEC_Msk instead */ 838 #define USBHS_DEVIDR_WAKEUPEC_Pos 4 /**< (USBHS_DEVIDR) Wake-Up Interrupt Disable Position */ 839 #define USBHS_DEVIDR_WAKEUPEC_Msk (_U_(0x1) << USBHS_DEVIDR_WAKEUPEC_Pos) /**< (USBHS_DEVIDR) Wake-Up Interrupt Disable Mask */ 840 #define USBHS_DEVIDR_WAKEUPEC USBHS_DEVIDR_WAKEUPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_WAKEUPEC_Msk instead */ 841 #define USBHS_DEVIDR_EORSMEC_Pos 5 /**< (USBHS_DEVIDR) End of Resume Interrupt Disable Position */ 842 #define USBHS_DEVIDR_EORSMEC_Msk (_U_(0x1) << USBHS_DEVIDR_EORSMEC_Pos) /**< (USBHS_DEVIDR) End of Resume Interrupt Disable Mask */ 843 #define USBHS_DEVIDR_EORSMEC USBHS_DEVIDR_EORSMEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_EORSMEC_Msk instead */ 844 #define USBHS_DEVIDR_UPRSMEC_Pos 6 /**< (USBHS_DEVIDR) Upstream Resume Interrupt Disable Position */ 845 #define USBHS_DEVIDR_UPRSMEC_Msk (_U_(0x1) << USBHS_DEVIDR_UPRSMEC_Pos) /**< (USBHS_DEVIDR) Upstream Resume Interrupt Disable Mask */ 846 #define USBHS_DEVIDR_UPRSMEC USBHS_DEVIDR_UPRSMEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_UPRSMEC_Msk instead */ 847 #define USBHS_DEVIDR_PEP_0_Pos 12 /**< (USBHS_DEVIDR) Endpoint 0 Interrupt Disable Position */ 848 #define USBHS_DEVIDR_PEP_0_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_0_Pos) /**< (USBHS_DEVIDR) Endpoint 0 Interrupt Disable Mask */ 849 #define USBHS_DEVIDR_PEP_0 USBHS_DEVIDR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_0_Msk instead */ 850 #define USBHS_DEVIDR_PEP_1_Pos 13 /**< (USBHS_DEVIDR) Endpoint 1 Interrupt Disable Position */ 851 #define USBHS_DEVIDR_PEP_1_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_1_Pos) /**< (USBHS_DEVIDR) Endpoint 1 Interrupt Disable Mask */ 852 #define USBHS_DEVIDR_PEP_1 USBHS_DEVIDR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_1_Msk instead */ 853 #define USBHS_DEVIDR_PEP_2_Pos 14 /**< (USBHS_DEVIDR) Endpoint 2 Interrupt Disable Position */ 854 #define USBHS_DEVIDR_PEP_2_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_2_Pos) /**< (USBHS_DEVIDR) Endpoint 2 Interrupt Disable Mask */ 855 #define USBHS_DEVIDR_PEP_2 USBHS_DEVIDR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_2_Msk instead */ 856 #define USBHS_DEVIDR_PEP_3_Pos 15 /**< (USBHS_DEVIDR) Endpoint 3 Interrupt Disable Position */ 857 #define USBHS_DEVIDR_PEP_3_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_3_Pos) /**< (USBHS_DEVIDR) Endpoint 3 Interrupt Disable Mask */ 858 #define USBHS_DEVIDR_PEP_3 USBHS_DEVIDR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_3_Msk instead */ 859 #define USBHS_DEVIDR_PEP_4_Pos 16 /**< (USBHS_DEVIDR) Endpoint 4 Interrupt Disable Position */ 860 #define USBHS_DEVIDR_PEP_4_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_4_Pos) /**< (USBHS_DEVIDR) Endpoint 4 Interrupt Disable Mask */ 861 #define USBHS_DEVIDR_PEP_4 USBHS_DEVIDR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_4_Msk instead */ 862 #define USBHS_DEVIDR_PEP_5_Pos 17 /**< (USBHS_DEVIDR) Endpoint 5 Interrupt Disable Position */ 863 #define USBHS_DEVIDR_PEP_5_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_5_Pos) /**< (USBHS_DEVIDR) Endpoint 5 Interrupt Disable Mask */ 864 #define USBHS_DEVIDR_PEP_5 USBHS_DEVIDR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_5_Msk instead */ 865 #define USBHS_DEVIDR_PEP_6_Pos 18 /**< (USBHS_DEVIDR) Endpoint 6 Interrupt Disable Position */ 866 #define USBHS_DEVIDR_PEP_6_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_6_Pos) /**< (USBHS_DEVIDR) Endpoint 6 Interrupt Disable Mask */ 867 #define USBHS_DEVIDR_PEP_6 USBHS_DEVIDR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_6_Msk instead */ 868 #define USBHS_DEVIDR_PEP_7_Pos 19 /**< (USBHS_DEVIDR) Endpoint 7 Interrupt Disable Position */ 869 #define USBHS_DEVIDR_PEP_7_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_7_Pos) /**< (USBHS_DEVIDR) Endpoint 7 Interrupt Disable Mask */ 870 #define USBHS_DEVIDR_PEP_7 USBHS_DEVIDR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_7_Msk instead */ 871 #define USBHS_DEVIDR_PEP_8_Pos 20 /**< (USBHS_DEVIDR) Endpoint 8 Interrupt Disable Position */ 872 #define USBHS_DEVIDR_PEP_8_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_8_Pos) /**< (USBHS_DEVIDR) Endpoint 8 Interrupt Disable Mask */ 873 #define USBHS_DEVIDR_PEP_8 USBHS_DEVIDR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_8_Msk instead */ 874 #define USBHS_DEVIDR_PEP_9_Pos 21 /**< (USBHS_DEVIDR) Endpoint 9 Interrupt Disable Position */ 875 #define USBHS_DEVIDR_PEP_9_Msk (_U_(0x1) << USBHS_DEVIDR_PEP_9_Pos) /**< (USBHS_DEVIDR) Endpoint 9 Interrupt Disable Mask */ 876 #define USBHS_DEVIDR_PEP_9 USBHS_DEVIDR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_PEP_9_Msk instead */ 877 #define USBHS_DEVIDR_DMA_1_Pos 25 /**< (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable Position */ 878 #define USBHS_DEVIDR_DMA_1_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_1_Pos) /**< (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable Mask */ 879 #define USBHS_DEVIDR_DMA_1 USBHS_DEVIDR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_1_Msk instead */ 880 #define USBHS_DEVIDR_DMA_2_Pos 26 /**< (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable Position */ 881 #define USBHS_DEVIDR_DMA_2_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_2_Pos) /**< (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable Mask */ 882 #define USBHS_DEVIDR_DMA_2 USBHS_DEVIDR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_2_Msk instead */ 883 #define USBHS_DEVIDR_DMA_3_Pos 27 /**< (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable Position */ 884 #define USBHS_DEVIDR_DMA_3_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_3_Pos) /**< (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable Mask */ 885 #define USBHS_DEVIDR_DMA_3 USBHS_DEVIDR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_3_Msk instead */ 886 #define USBHS_DEVIDR_DMA_4_Pos 28 /**< (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable Position */ 887 #define USBHS_DEVIDR_DMA_4_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_4_Pos) /**< (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable Mask */ 888 #define USBHS_DEVIDR_DMA_4 USBHS_DEVIDR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_4_Msk instead */ 889 #define USBHS_DEVIDR_DMA_5_Pos 29 /**< (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable Position */ 890 #define USBHS_DEVIDR_DMA_5_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_5_Pos) /**< (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable Mask */ 891 #define USBHS_DEVIDR_DMA_5 USBHS_DEVIDR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_5_Msk instead */ 892 #define USBHS_DEVIDR_DMA_6_Pos 30 /**< (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable Position */ 893 #define USBHS_DEVIDR_DMA_6_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_6_Pos) /**< (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable Mask */ 894 #define USBHS_DEVIDR_DMA_6 USBHS_DEVIDR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_6_Msk instead */ 895 #define USBHS_DEVIDR_DMA_7_Pos 31 /**< (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable Position */ 896 #define USBHS_DEVIDR_DMA_7_Msk (_U_(0x1) << USBHS_DEVIDR_DMA_7_Pos) /**< (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable Mask */ 897 #define USBHS_DEVIDR_DMA_7 USBHS_DEVIDR_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIDR_DMA_7_Msk instead */ 898 #define USBHS_DEVIDR_MASK _U_(0xFE3FF07F) /**< \deprecated (USBHS_DEVIDR) Register MASK (Use USBHS_DEVIDR_Msk instead) */ 899 #define USBHS_DEVIDR_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVIDR) Register Mask */ 900 901 #define USBHS_DEVIDR_PEP__Pos 12 /**< (USBHS_DEVIDR Position) Endpoint x Interrupt Disable */ 902 #define USBHS_DEVIDR_PEP__Msk (_U_(0x3FF) << USBHS_DEVIDR_PEP__Pos) /**< (USBHS_DEVIDR Mask) PEP_ */ 903 #define USBHS_DEVIDR_PEP_(value) (USBHS_DEVIDR_PEP__Msk & ((value) << USBHS_DEVIDR_PEP__Pos)) 904 #define USBHS_DEVIDR_DMA__Pos 25 /**< (USBHS_DEVIDR Position) DMA Channel 7 Interrupt Disable */ 905 #define USBHS_DEVIDR_DMA__Msk (_U_(0x7F) << USBHS_DEVIDR_DMA__Pos) /**< (USBHS_DEVIDR Mask) DMA_ */ 906 #define USBHS_DEVIDR_DMA_(value) (USBHS_DEVIDR_DMA__Msk & ((value) << USBHS_DEVIDR_DMA__Pos)) 907 908 /* -------- USBHS_DEVIER : (USBHS Offset: 0x18) (/W 32) Device Global Interrupt Enable Register -------- */ 909 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 910 #if COMPONENT_TYPEDEF_STYLE == 'N' 911 typedef union { 912 struct { 913 uint32_t SUSPES:1; /**< bit: 0 Suspend Interrupt Enable */ 914 uint32_t MSOFES:1; /**< bit: 1 Micro Start of Frame Interrupt Enable */ 915 uint32_t SOFES:1; /**< bit: 2 Start of Frame Interrupt Enable */ 916 uint32_t EORSTES:1; /**< bit: 3 End of Reset Interrupt Enable */ 917 uint32_t WAKEUPES:1; /**< bit: 4 Wake-Up Interrupt Enable */ 918 uint32_t EORSMES:1; /**< bit: 5 End of Resume Interrupt Enable */ 919 uint32_t UPRSMES:1; /**< bit: 6 Upstream Resume Interrupt Enable */ 920 uint32_t :5; /**< bit: 7..11 Reserved */ 921 uint32_t PEP_0:1; /**< bit: 12 Endpoint 0 Interrupt Enable */ 922 uint32_t PEP_1:1; /**< bit: 13 Endpoint 1 Interrupt Enable */ 923 uint32_t PEP_2:1; /**< bit: 14 Endpoint 2 Interrupt Enable */ 924 uint32_t PEP_3:1; /**< bit: 15 Endpoint 3 Interrupt Enable */ 925 uint32_t PEP_4:1; /**< bit: 16 Endpoint 4 Interrupt Enable */ 926 uint32_t PEP_5:1; /**< bit: 17 Endpoint 5 Interrupt Enable */ 927 uint32_t PEP_6:1; /**< bit: 18 Endpoint 6 Interrupt Enable */ 928 uint32_t PEP_7:1; /**< bit: 19 Endpoint 7 Interrupt Enable */ 929 uint32_t PEP_8:1; /**< bit: 20 Endpoint 8 Interrupt Enable */ 930 uint32_t PEP_9:1; /**< bit: 21 Endpoint 9 Interrupt Enable */ 931 uint32_t :3; /**< bit: 22..24 Reserved */ 932 uint32_t DMA_1:1; /**< bit: 25 DMA Channel 1 Interrupt Enable */ 933 uint32_t DMA_2:1; /**< bit: 26 DMA Channel 2 Interrupt Enable */ 934 uint32_t DMA_3:1; /**< bit: 27 DMA Channel 3 Interrupt Enable */ 935 uint32_t DMA_4:1; /**< bit: 28 DMA Channel 4 Interrupt Enable */ 936 uint32_t DMA_5:1; /**< bit: 29 DMA Channel 5 Interrupt Enable */ 937 uint32_t DMA_6:1; /**< bit: 30 DMA Channel 6 Interrupt Enable */ 938 uint32_t DMA_7:1; /**< bit: 31 DMA Channel 7 Interrupt Enable */ 939 } bit; /**< Structure used for bit access */ 940 struct { 941 uint32_t :12; /**< bit: 0..11 Reserved */ 942 uint32_t PEP_:10; /**< bit: 12..21 Endpoint x Interrupt Enable */ 943 uint32_t :3; /**< bit: 22..24 Reserved */ 944 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 7 Interrupt Enable */ 945 } vec; /**< Structure used for vec access */ 946 uint32_t reg; /**< Type used for register access */ 947 } USBHS_DEVIER_Type; 948 #endif 949 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 950 951 #define USBHS_DEVIER_OFFSET (0x18) /**< (USBHS_DEVIER) Device Global Interrupt Enable Register Offset */ 952 953 #define USBHS_DEVIER_SUSPES_Pos 0 /**< (USBHS_DEVIER) Suspend Interrupt Enable Position */ 954 #define USBHS_DEVIER_SUSPES_Msk (_U_(0x1) << USBHS_DEVIER_SUSPES_Pos) /**< (USBHS_DEVIER) Suspend Interrupt Enable Mask */ 955 #define USBHS_DEVIER_SUSPES USBHS_DEVIER_SUSPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_SUSPES_Msk instead */ 956 #define USBHS_DEVIER_MSOFES_Pos 1 /**< (USBHS_DEVIER) Micro Start of Frame Interrupt Enable Position */ 957 #define USBHS_DEVIER_MSOFES_Msk (_U_(0x1) << USBHS_DEVIER_MSOFES_Pos) /**< (USBHS_DEVIER) Micro Start of Frame Interrupt Enable Mask */ 958 #define USBHS_DEVIER_MSOFES USBHS_DEVIER_MSOFES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_MSOFES_Msk instead */ 959 #define USBHS_DEVIER_SOFES_Pos 2 /**< (USBHS_DEVIER) Start of Frame Interrupt Enable Position */ 960 #define USBHS_DEVIER_SOFES_Msk (_U_(0x1) << USBHS_DEVIER_SOFES_Pos) /**< (USBHS_DEVIER) Start of Frame Interrupt Enable Mask */ 961 #define USBHS_DEVIER_SOFES USBHS_DEVIER_SOFES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_SOFES_Msk instead */ 962 #define USBHS_DEVIER_EORSTES_Pos 3 /**< (USBHS_DEVIER) End of Reset Interrupt Enable Position */ 963 #define USBHS_DEVIER_EORSTES_Msk (_U_(0x1) << USBHS_DEVIER_EORSTES_Pos) /**< (USBHS_DEVIER) End of Reset Interrupt Enable Mask */ 964 #define USBHS_DEVIER_EORSTES USBHS_DEVIER_EORSTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_EORSTES_Msk instead */ 965 #define USBHS_DEVIER_WAKEUPES_Pos 4 /**< (USBHS_DEVIER) Wake-Up Interrupt Enable Position */ 966 #define USBHS_DEVIER_WAKEUPES_Msk (_U_(0x1) << USBHS_DEVIER_WAKEUPES_Pos) /**< (USBHS_DEVIER) Wake-Up Interrupt Enable Mask */ 967 #define USBHS_DEVIER_WAKEUPES USBHS_DEVIER_WAKEUPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_WAKEUPES_Msk instead */ 968 #define USBHS_DEVIER_EORSMES_Pos 5 /**< (USBHS_DEVIER) End of Resume Interrupt Enable Position */ 969 #define USBHS_DEVIER_EORSMES_Msk (_U_(0x1) << USBHS_DEVIER_EORSMES_Pos) /**< (USBHS_DEVIER) End of Resume Interrupt Enable Mask */ 970 #define USBHS_DEVIER_EORSMES USBHS_DEVIER_EORSMES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_EORSMES_Msk instead */ 971 #define USBHS_DEVIER_UPRSMES_Pos 6 /**< (USBHS_DEVIER) Upstream Resume Interrupt Enable Position */ 972 #define USBHS_DEVIER_UPRSMES_Msk (_U_(0x1) << USBHS_DEVIER_UPRSMES_Pos) /**< (USBHS_DEVIER) Upstream Resume Interrupt Enable Mask */ 973 #define USBHS_DEVIER_UPRSMES USBHS_DEVIER_UPRSMES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_UPRSMES_Msk instead */ 974 #define USBHS_DEVIER_PEP_0_Pos 12 /**< (USBHS_DEVIER) Endpoint 0 Interrupt Enable Position */ 975 #define USBHS_DEVIER_PEP_0_Msk (_U_(0x1) << USBHS_DEVIER_PEP_0_Pos) /**< (USBHS_DEVIER) Endpoint 0 Interrupt Enable Mask */ 976 #define USBHS_DEVIER_PEP_0 USBHS_DEVIER_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_0_Msk instead */ 977 #define USBHS_DEVIER_PEP_1_Pos 13 /**< (USBHS_DEVIER) Endpoint 1 Interrupt Enable Position */ 978 #define USBHS_DEVIER_PEP_1_Msk (_U_(0x1) << USBHS_DEVIER_PEP_1_Pos) /**< (USBHS_DEVIER) Endpoint 1 Interrupt Enable Mask */ 979 #define USBHS_DEVIER_PEP_1 USBHS_DEVIER_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_1_Msk instead */ 980 #define USBHS_DEVIER_PEP_2_Pos 14 /**< (USBHS_DEVIER) Endpoint 2 Interrupt Enable Position */ 981 #define USBHS_DEVIER_PEP_2_Msk (_U_(0x1) << USBHS_DEVIER_PEP_2_Pos) /**< (USBHS_DEVIER) Endpoint 2 Interrupt Enable Mask */ 982 #define USBHS_DEVIER_PEP_2 USBHS_DEVIER_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_2_Msk instead */ 983 #define USBHS_DEVIER_PEP_3_Pos 15 /**< (USBHS_DEVIER) Endpoint 3 Interrupt Enable Position */ 984 #define USBHS_DEVIER_PEP_3_Msk (_U_(0x1) << USBHS_DEVIER_PEP_3_Pos) /**< (USBHS_DEVIER) Endpoint 3 Interrupt Enable Mask */ 985 #define USBHS_DEVIER_PEP_3 USBHS_DEVIER_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_3_Msk instead */ 986 #define USBHS_DEVIER_PEP_4_Pos 16 /**< (USBHS_DEVIER) Endpoint 4 Interrupt Enable Position */ 987 #define USBHS_DEVIER_PEP_4_Msk (_U_(0x1) << USBHS_DEVIER_PEP_4_Pos) /**< (USBHS_DEVIER) Endpoint 4 Interrupt Enable Mask */ 988 #define USBHS_DEVIER_PEP_4 USBHS_DEVIER_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_4_Msk instead */ 989 #define USBHS_DEVIER_PEP_5_Pos 17 /**< (USBHS_DEVIER) Endpoint 5 Interrupt Enable Position */ 990 #define USBHS_DEVIER_PEP_5_Msk (_U_(0x1) << USBHS_DEVIER_PEP_5_Pos) /**< (USBHS_DEVIER) Endpoint 5 Interrupt Enable Mask */ 991 #define USBHS_DEVIER_PEP_5 USBHS_DEVIER_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_5_Msk instead */ 992 #define USBHS_DEVIER_PEP_6_Pos 18 /**< (USBHS_DEVIER) Endpoint 6 Interrupt Enable Position */ 993 #define USBHS_DEVIER_PEP_6_Msk (_U_(0x1) << USBHS_DEVIER_PEP_6_Pos) /**< (USBHS_DEVIER) Endpoint 6 Interrupt Enable Mask */ 994 #define USBHS_DEVIER_PEP_6 USBHS_DEVIER_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_6_Msk instead */ 995 #define USBHS_DEVIER_PEP_7_Pos 19 /**< (USBHS_DEVIER) Endpoint 7 Interrupt Enable Position */ 996 #define USBHS_DEVIER_PEP_7_Msk (_U_(0x1) << USBHS_DEVIER_PEP_7_Pos) /**< (USBHS_DEVIER) Endpoint 7 Interrupt Enable Mask */ 997 #define USBHS_DEVIER_PEP_7 USBHS_DEVIER_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_7_Msk instead */ 998 #define USBHS_DEVIER_PEP_8_Pos 20 /**< (USBHS_DEVIER) Endpoint 8 Interrupt Enable Position */ 999 #define USBHS_DEVIER_PEP_8_Msk (_U_(0x1) << USBHS_DEVIER_PEP_8_Pos) /**< (USBHS_DEVIER) Endpoint 8 Interrupt Enable Mask */ 1000 #define USBHS_DEVIER_PEP_8 USBHS_DEVIER_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_8_Msk instead */ 1001 #define USBHS_DEVIER_PEP_9_Pos 21 /**< (USBHS_DEVIER) Endpoint 9 Interrupt Enable Position */ 1002 #define USBHS_DEVIER_PEP_9_Msk (_U_(0x1) << USBHS_DEVIER_PEP_9_Pos) /**< (USBHS_DEVIER) Endpoint 9 Interrupt Enable Mask */ 1003 #define USBHS_DEVIER_PEP_9 USBHS_DEVIER_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_PEP_9_Msk instead */ 1004 #define USBHS_DEVIER_DMA_1_Pos 25 /**< (USBHS_DEVIER) DMA Channel 1 Interrupt Enable Position */ 1005 #define USBHS_DEVIER_DMA_1_Msk (_U_(0x1) << USBHS_DEVIER_DMA_1_Pos) /**< (USBHS_DEVIER) DMA Channel 1 Interrupt Enable Mask */ 1006 #define USBHS_DEVIER_DMA_1 USBHS_DEVIER_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_1_Msk instead */ 1007 #define USBHS_DEVIER_DMA_2_Pos 26 /**< (USBHS_DEVIER) DMA Channel 2 Interrupt Enable Position */ 1008 #define USBHS_DEVIER_DMA_2_Msk (_U_(0x1) << USBHS_DEVIER_DMA_2_Pos) /**< (USBHS_DEVIER) DMA Channel 2 Interrupt Enable Mask */ 1009 #define USBHS_DEVIER_DMA_2 USBHS_DEVIER_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_2_Msk instead */ 1010 #define USBHS_DEVIER_DMA_3_Pos 27 /**< (USBHS_DEVIER) DMA Channel 3 Interrupt Enable Position */ 1011 #define USBHS_DEVIER_DMA_3_Msk (_U_(0x1) << USBHS_DEVIER_DMA_3_Pos) /**< (USBHS_DEVIER) DMA Channel 3 Interrupt Enable Mask */ 1012 #define USBHS_DEVIER_DMA_3 USBHS_DEVIER_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_3_Msk instead */ 1013 #define USBHS_DEVIER_DMA_4_Pos 28 /**< (USBHS_DEVIER) DMA Channel 4 Interrupt Enable Position */ 1014 #define USBHS_DEVIER_DMA_4_Msk (_U_(0x1) << USBHS_DEVIER_DMA_4_Pos) /**< (USBHS_DEVIER) DMA Channel 4 Interrupt Enable Mask */ 1015 #define USBHS_DEVIER_DMA_4 USBHS_DEVIER_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_4_Msk instead */ 1016 #define USBHS_DEVIER_DMA_5_Pos 29 /**< (USBHS_DEVIER) DMA Channel 5 Interrupt Enable Position */ 1017 #define USBHS_DEVIER_DMA_5_Msk (_U_(0x1) << USBHS_DEVIER_DMA_5_Pos) /**< (USBHS_DEVIER) DMA Channel 5 Interrupt Enable Mask */ 1018 #define USBHS_DEVIER_DMA_5 USBHS_DEVIER_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_5_Msk instead */ 1019 #define USBHS_DEVIER_DMA_6_Pos 30 /**< (USBHS_DEVIER) DMA Channel 6 Interrupt Enable Position */ 1020 #define USBHS_DEVIER_DMA_6_Msk (_U_(0x1) << USBHS_DEVIER_DMA_6_Pos) /**< (USBHS_DEVIER) DMA Channel 6 Interrupt Enable Mask */ 1021 #define USBHS_DEVIER_DMA_6 USBHS_DEVIER_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_6_Msk instead */ 1022 #define USBHS_DEVIER_DMA_7_Pos 31 /**< (USBHS_DEVIER) DMA Channel 7 Interrupt Enable Position */ 1023 #define USBHS_DEVIER_DMA_7_Msk (_U_(0x1) << USBHS_DEVIER_DMA_7_Pos) /**< (USBHS_DEVIER) DMA Channel 7 Interrupt Enable Mask */ 1024 #define USBHS_DEVIER_DMA_7 USBHS_DEVIER_DMA_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVIER_DMA_7_Msk instead */ 1025 #define USBHS_DEVIER_MASK _U_(0xFE3FF07F) /**< \deprecated (USBHS_DEVIER) Register MASK (Use USBHS_DEVIER_Msk instead) */ 1026 #define USBHS_DEVIER_Msk _U_(0xFE3FF07F) /**< (USBHS_DEVIER) Register Mask */ 1027 1028 #define USBHS_DEVIER_PEP__Pos 12 /**< (USBHS_DEVIER Position) Endpoint x Interrupt Enable */ 1029 #define USBHS_DEVIER_PEP__Msk (_U_(0x3FF) << USBHS_DEVIER_PEP__Pos) /**< (USBHS_DEVIER Mask) PEP_ */ 1030 #define USBHS_DEVIER_PEP_(value) (USBHS_DEVIER_PEP__Msk & ((value) << USBHS_DEVIER_PEP__Pos)) 1031 #define USBHS_DEVIER_DMA__Pos 25 /**< (USBHS_DEVIER Position) DMA Channel 7 Interrupt Enable */ 1032 #define USBHS_DEVIER_DMA__Msk (_U_(0x7F) << USBHS_DEVIER_DMA__Pos) /**< (USBHS_DEVIER Mask) DMA_ */ 1033 #define USBHS_DEVIER_DMA_(value) (USBHS_DEVIER_DMA__Msk & ((value) << USBHS_DEVIER_DMA__Pos)) 1034 1035 /* -------- USBHS_DEVEPT : (USBHS Offset: 0x1c) (R/W 32) Device Endpoint Register -------- */ 1036 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1037 #if COMPONENT_TYPEDEF_STYLE == 'N' 1038 typedef union { 1039 struct { 1040 uint32_t EPEN0:1; /**< bit: 0 Endpoint 0 Enable */ 1041 uint32_t EPEN1:1; /**< bit: 1 Endpoint 1 Enable */ 1042 uint32_t EPEN2:1; /**< bit: 2 Endpoint 2 Enable */ 1043 uint32_t EPEN3:1; /**< bit: 3 Endpoint 3 Enable */ 1044 uint32_t EPEN4:1; /**< bit: 4 Endpoint 4 Enable */ 1045 uint32_t EPEN5:1; /**< bit: 5 Endpoint 5 Enable */ 1046 uint32_t EPEN6:1; /**< bit: 6 Endpoint 6 Enable */ 1047 uint32_t EPEN7:1; /**< bit: 7 Endpoint 7 Enable */ 1048 uint32_t EPEN8:1; /**< bit: 8 Endpoint 8 Enable */ 1049 uint32_t EPEN9:1; /**< bit: 9 Endpoint 9 Enable */ 1050 uint32_t :6; /**< bit: 10..15 Reserved */ 1051 uint32_t EPRST0:1; /**< bit: 16 Endpoint 0 Reset */ 1052 uint32_t EPRST1:1; /**< bit: 17 Endpoint 1 Reset */ 1053 uint32_t EPRST2:1; /**< bit: 18 Endpoint 2 Reset */ 1054 uint32_t EPRST3:1; /**< bit: 19 Endpoint 3 Reset */ 1055 uint32_t EPRST4:1; /**< bit: 20 Endpoint 4 Reset */ 1056 uint32_t EPRST5:1; /**< bit: 21 Endpoint 5 Reset */ 1057 uint32_t EPRST6:1; /**< bit: 22 Endpoint 6 Reset */ 1058 uint32_t EPRST7:1; /**< bit: 23 Endpoint 7 Reset */ 1059 uint32_t EPRST8:1; /**< bit: 24 Endpoint 8 Reset */ 1060 uint32_t EPRST9:1; /**< bit: 25 Endpoint 9 Reset */ 1061 uint32_t :6; /**< bit: 26..31 Reserved */ 1062 } bit; /**< Structure used for bit access */ 1063 struct { 1064 uint32_t EPEN:10; /**< bit: 0..9 Endpoint x Enable */ 1065 uint32_t :6; /**< bit: 10..15 Reserved */ 1066 uint32_t EPRST:10; /**< bit: 16..25 Endpoint 9 Reset */ 1067 uint32_t :6; /**< bit: 26..31 Reserved */ 1068 } vec; /**< Structure used for vec access */ 1069 uint32_t reg; /**< Type used for register access */ 1070 } USBHS_DEVEPT_Type; 1071 #endif 1072 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1073 1074 #define USBHS_DEVEPT_OFFSET (0x1C) /**< (USBHS_DEVEPT) Device Endpoint Register Offset */ 1075 1076 #define USBHS_DEVEPT_EPEN0_Pos 0 /**< (USBHS_DEVEPT) Endpoint 0 Enable Position */ 1077 #define USBHS_DEVEPT_EPEN0_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN0_Pos) /**< (USBHS_DEVEPT) Endpoint 0 Enable Mask */ 1078 #define USBHS_DEVEPT_EPEN0 USBHS_DEVEPT_EPEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN0_Msk instead */ 1079 #define USBHS_DEVEPT_EPEN1_Pos 1 /**< (USBHS_DEVEPT) Endpoint 1 Enable Position */ 1080 #define USBHS_DEVEPT_EPEN1_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN1_Pos) /**< (USBHS_DEVEPT) Endpoint 1 Enable Mask */ 1081 #define USBHS_DEVEPT_EPEN1 USBHS_DEVEPT_EPEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN1_Msk instead */ 1082 #define USBHS_DEVEPT_EPEN2_Pos 2 /**< (USBHS_DEVEPT) Endpoint 2 Enable Position */ 1083 #define USBHS_DEVEPT_EPEN2_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN2_Pos) /**< (USBHS_DEVEPT) Endpoint 2 Enable Mask */ 1084 #define USBHS_DEVEPT_EPEN2 USBHS_DEVEPT_EPEN2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN2_Msk instead */ 1085 #define USBHS_DEVEPT_EPEN3_Pos 3 /**< (USBHS_DEVEPT) Endpoint 3 Enable Position */ 1086 #define USBHS_DEVEPT_EPEN3_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN3_Pos) /**< (USBHS_DEVEPT) Endpoint 3 Enable Mask */ 1087 #define USBHS_DEVEPT_EPEN3 USBHS_DEVEPT_EPEN3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN3_Msk instead */ 1088 #define USBHS_DEVEPT_EPEN4_Pos 4 /**< (USBHS_DEVEPT) Endpoint 4 Enable Position */ 1089 #define USBHS_DEVEPT_EPEN4_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN4_Pos) /**< (USBHS_DEVEPT) Endpoint 4 Enable Mask */ 1090 #define USBHS_DEVEPT_EPEN4 USBHS_DEVEPT_EPEN4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN4_Msk instead */ 1091 #define USBHS_DEVEPT_EPEN5_Pos 5 /**< (USBHS_DEVEPT) Endpoint 5 Enable Position */ 1092 #define USBHS_DEVEPT_EPEN5_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN5_Pos) /**< (USBHS_DEVEPT) Endpoint 5 Enable Mask */ 1093 #define USBHS_DEVEPT_EPEN5 USBHS_DEVEPT_EPEN5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN5_Msk instead */ 1094 #define USBHS_DEVEPT_EPEN6_Pos 6 /**< (USBHS_DEVEPT) Endpoint 6 Enable Position */ 1095 #define USBHS_DEVEPT_EPEN6_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN6_Pos) /**< (USBHS_DEVEPT) Endpoint 6 Enable Mask */ 1096 #define USBHS_DEVEPT_EPEN6 USBHS_DEVEPT_EPEN6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN6_Msk instead */ 1097 #define USBHS_DEVEPT_EPEN7_Pos 7 /**< (USBHS_DEVEPT) Endpoint 7 Enable Position */ 1098 #define USBHS_DEVEPT_EPEN7_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN7_Pos) /**< (USBHS_DEVEPT) Endpoint 7 Enable Mask */ 1099 #define USBHS_DEVEPT_EPEN7 USBHS_DEVEPT_EPEN7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN7_Msk instead */ 1100 #define USBHS_DEVEPT_EPEN8_Pos 8 /**< (USBHS_DEVEPT) Endpoint 8 Enable Position */ 1101 #define USBHS_DEVEPT_EPEN8_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN8_Pos) /**< (USBHS_DEVEPT) Endpoint 8 Enable Mask */ 1102 #define USBHS_DEVEPT_EPEN8 USBHS_DEVEPT_EPEN8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN8_Msk instead */ 1103 #define USBHS_DEVEPT_EPEN9_Pos 9 /**< (USBHS_DEVEPT) Endpoint 9 Enable Position */ 1104 #define USBHS_DEVEPT_EPEN9_Msk (_U_(0x1) << USBHS_DEVEPT_EPEN9_Pos) /**< (USBHS_DEVEPT) Endpoint 9 Enable Mask */ 1105 #define USBHS_DEVEPT_EPEN9 USBHS_DEVEPT_EPEN9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPEN9_Msk instead */ 1106 #define USBHS_DEVEPT_EPRST0_Pos 16 /**< (USBHS_DEVEPT) Endpoint 0 Reset Position */ 1107 #define USBHS_DEVEPT_EPRST0_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST0_Pos) /**< (USBHS_DEVEPT) Endpoint 0 Reset Mask */ 1108 #define USBHS_DEVEPT_EPRST0 USBHS_DEVEPT_EPRST0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST0_Msk instead */ 1109 #define USBHS_DEVEPT_EPRST1_Pos 17 /**< (USBHS_DEVEPT) Endpoint 1 Reset Position */ 1110 #define USBHS_DEVEPT_EPRST1_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST1_Pos) /**< (USBHS_DEVEPT) Endpoint 1 Reset Mask */ 1111 #define USBHS_DEVEPT_EPRST1 USBHS_DEVEPT_EPRST1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST1_Msk instead */ 1112 #define USBHS_DEVEPT_EPRST2_Pos 18 /**< (USBHS_DEVEPT) Endpoint 2 Reset Position */ 1113 #define USBHS_DEVEPT_EPRST2_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST2_Pos) /**< (USBHS_DEVEPT) Endpoint 2 Reset Mask */ 1114 #define USBHS_DEVEPT_EPRST2 USBHS_DEVEPT_EPRST2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST2_Msk instead */ 1115 #define USBHS_DEVEPT_EPRST3_Pos 19 /**< (USBHS_DEVEPT) Endpoint 3 Reset Position */ 1116 #define USBHS_DEVEPT_EPRST3_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST3_Pos) /**< (USBHS_DEVEPT) Endpoint 3 Reset Mask */ 1117 #define USBHS_DEVEPT_EPRST3 USBHS_DEVEPT_EPRST3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST3_Msk instead */ 1118 #define USBHS_DEVEPT_EPRST4_Pos 20 /**< (USBHS_DEVEPT) Endpoint 4 Reset Position */ 1119 #define USBHS_DEVEPT_EPRST4_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST4_Pos) /**< (USBHS_DEVEPT) Endpoint 4 Reset Mask */ 1120 #define USBHS_DEVEPT_EPRST4 USBHS_DEVEPT_EPRST4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST4_Msk instead */ 1121 #define USBHS_DEVEPT_EPRST5_Pos 21 /**< (USBHS_DEVEPT) Endpoint 5 Reset Position */ 1122 #define USBHS_DEVEPT_EPRST5_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST5_Pos) /**< (USBHS_DEVEPT) Endpoint 5 Reset Mask */ 1123 #define USBHS_DEVEPT_EPRST5 USBHS_DEVEPT_EPRST5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST5_Msk instead */ 1124 #define USBHS_DEVEPT_EPRST6_Pos 22 /**< (USBHS_DEVEPT) Endpoint 6 Reset Position */ 1125 #define USBHS_DEVEPT_EPRST6_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST6_Pos) /**< (USBHS_DEVEPT) Endpoint 6 Reset Mask */ 1126 #define USBHS_DEVEPT_EPRST6 USBHS_DEVEPT_EPRST6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST6_Msk instead */ 1127 #define USBHS_DEVEPT_EPRST7_Pos 23 /**< (USBHS_DEVEPT) Endpoint 7 Reset Position */ 1128 #define USBHS_DEVEPT_EPRST7_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST7_Pos) /**< (USBHS_DEVEPT) Endpoint 7 Reset Mask */ 1129 #define USBHS_DEVEPT_EPRST7 USBHS_DEVEPT_EPRST7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST7_Msk instead */ 1130 #define USBHS_DEVEPT_EPRST8_Pos 24 /**< (USBHS_DEVEPT) Endpoint 8 Reset Position */ 1131 #define USBHS_DEVEPT_EPRST8_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST8_Pos) /**< (USBHS_DEVEPT) Endpoint 8 Reset Mask */ 1132 #define USBHS_DEVEPT_EPRST8 USBHS_DEVEPT_EPRST8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST8_Msk instead */ 1133 #define USBHS_DEVEPT_EPRST9_Pos 25 /**< (USBHS_DEVEPT) Endpoint 9 Reset Position */ 1134 #define USBHS_DEVEPT_EPRST9_Msk (_U_(0x1) << USBHS_DEVEPT_EPRST9_Pos) /**< (USBHS_DEVEPT) Endpoint 9 Reset Mask */ 1135 #define USBHS_DEVEPT_EPRST9 USBHS_DEVEPT_EPRST9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPT_EPRST9_Msk instead */ 1136 #define USBHS_DEVEPT_MASK _U_(0x3FF03FF) /**< \deprecated (USBHS_DEVEPT) Register MASK (Use USBHS_DEVEPT_Msk instead) */ 1137 #define USBHS_DEVEPT_Msk _U_(0x3FF03FF) /**< (USBHS_DEVEPT) Register Mask */ 1138 1139 #define USBHS_DEVEPT_EPEN_Pos 0 /**< (USBHS_DEVEPT Position) Endpoint x Enable */ 1140 #define USBHS_DEVEPT_EPEN_Msk (_U_(0x3FF) << USBHS_DEVEPT_EPEN_Pos) /**< (USBHS_DEVEPT Mask) EPEN */ 1141 #define USBHS_DEVEPT_EPEN(value) (USBHS_DEVEPT_EPEN_Msk & ((value) << USBHS_DEVEPT_EPEN_Pos)) 1142 #define USBHS_DEVEPT_EPRST_Pos 16 /**< (USBHS_DEVEPT Position) Endpoint 9 Reset */ 1143 #define USBHS_DEVEPT_EPRST_Msk (_U_(0x3FF) << USBHS_DEVEPT_EPRST_Pos) /**< (USBHS_DEVEPT Mask) EPRST */ 1144 #define USBHS_DEVEPT_EPRST(value) (USBHS_DEVEPT_EPRST_Msk & ((value) << USBHS_DEVEPT_EPRST_Pos)) 1145 1146 /* -------- USBHS_DEVFNUM : (USBHS Offset: 0x20) (R/ 32) Device Frame Number Register -------- */ 1147 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1148 #if COMPONENT_TYPEDEF_STYLE == 'N' 1149 typedef union { 1150 struct { 1151 uint32_t MFNUM:3; /**< bit: 0..2 Micro Frame Number */ 1152 uint32_t FNUM:11; /**< bit: 3..13 Frame Number */ 1153 uint32_t :1; /**< bit: 14 Reserved */ 1154 uint32_t FNCERR:1; /**< bit: 15 Frame Number CRC Error */ 1155 uint32_t :16; /**< bit: 16..31 Reserved */ 1156 } bit; /**< Structure used for bit access */ 1157 uint32_t reg; /**< Type used for register access */ 1158 } USBHS_DEVFNUM_Type; 1159 #endif 1160 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1161 1162 #define USBHS_DEVFNUM_OFFSET (0x20) /**< (USBHS_DEVFNUM) Device Frame Number Register Offset */ 1163 1164 #define USBHS_DEVFNUM_MFNUM_Pos 0 /**< (USBHS_DEVFNUM) Micro Frame Number Position */ 1165 #define USBHS_DEVFNUM_MFNUM_Msk (_U_(0x7) << USBHS_DEVFNUM_MFNUM_Pos) /**< (USBHS_DEVFNUM) Micro Frame Number Mask */ 1166 #define USBHS_DEVFNUM_MFNUM(value) (USBHS_DEVFNUM_MFNUM_Msk & ((value) << USBHS_DEVFNUM_MFNUM_Pos)) 1167 #define USBHS_DEVFNUM_FNUM_Pos 3 /**< (USBHS_DEVFNUM) Frame Number Position */ 1168 #define USBHS_DEVFNUM_FNUM_Msk (_U_(0x7FF) << USBHS_DEVFNUM_FNUM_Pos) /**< (USBHS_DEVFNUM) Frame Number Mask */ 1169 #define USBHS_DEVFNUM_FNUM(value) (USBHS_DEVFNUM_FNUM_Msk & ((value) << USBHS_DEVFNUM_FNUM_Pos)) 1170 #define USBHS_DEVFNUM_FNCERR_Pos 15 /**< (USBHS_DEVFNUM) Frame Number CRC Error Position */ 1171 #define USBHS_DEVFNUM_FNCERR_Msk (_U_(0x1) << USBHS_DEVFNUM_FNCERR_Pos) /**< (USBHS_DEVFNUM) Frame Number CRC Error Mask */ 1172 #define USBHS_DEVFNUM_FNCERR USBHS_DEVFNUM_FNCERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVFNUM_FNCERR_Msk instead */ 1173 #define USBHS_DEVFNUM_MASK _U_(0xBFFF) /**< \deprecated (USBHS_DEVFNUM) Register MASK (Use USBHS_DEVFNUM_Msk instead) */ 1174 #define USBHS_DEVFNUM_Msk _U_(0xBFFF) /**< (USBHS_DEVFNUM) Register Mask */ 1175 1176 1177 /* -------- USBHS_DEVEPTCFG : (USBHS Offset: 0x100) (R/W 32) Device Endpoint Configuration Register -------- */ 1178 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1179 #if COMPONENT_TYPEDEF_STYLE == 'N' 1180 typedef union { 1181 struct { 1182 uint32_t :1; /**< bit: 0 Reserved */ 1183 uint32_t ALLOC:1; /**< bit: 1 Endpoint Memory Allocate */ 1184 uint32_t EPBK:2; /**< bit: 2..3 Endpoint Banks */ 1185 uint32_t EPSIZE:3; /**< bit: 4..6 Endpoint Size */ 1186 uint32_t :1; /**< bit: 7 Reserved */ 1187 uint32_t EPDIR:1; /**< bit: 8 Endpoint Direction */ 1188 uint32_t AUTOSW:1; /**< bit: 9 Automatic Switch */ 1189 uint32_t :1; /**< bit: 10 Reserved */ 1190 uint32_t EPTYPE:2; /**< bit: 11..12 Endpoint Type */ 1191 uint32_t NBTRANS:2; /**< bit: 13..14 Number of transactions per microframe for isochronous endpoint */ 1192 uint32_t :17; /**< bit: 15..31 Reserved */ 1193 } bit; /**< Structure used for bit access */ 1194 uint32_t reg; /**< Type used for register access */ 1195 } USBHS_DEVEPTCFG_Type; 1196 #endif 1197 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1198 1199 #define USBHS_DEVEPTCFG_OFFSET (0x100) /**< (USBHS_DEVEPTCFG) Device Endpoint Configuration Register Offset */ 1200 1201 #define USBHS_DEVEPTCFG_ALLOC_Pos 1 /**< (USBHS_DEVEPTCFG) Endpoint Memory Allocate Position */ 1202 #define USBHS_DEVEPTCFG_ALLOC_Msk (_U_(0x1) << USBHS_DEVEPTCFG_ALLOC_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Memory Allocate Mask */ 1203 #define USBHS_DEVEPTCFG_ALLOC USBHS_DEVEPTCFG_ALLOC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTCFG_ALLOC_Msk instead */ 1204 #define USBHS_DEVEPTCFG_EPBK_Pos 2 /**< (USBHS_DEVEPTCFG) Endpoint Banks Position */ 1205 #define USBHS_DEVEPTCFG_EPBK_Msk (_U_(0x3) << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Banks Mask */ 1206 #define USBHS_DEVEPTCFG_EPBK(value) (USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos)) 1207 #define USBHS_DEVEPTCFG_EPBK_1_BANK_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Single-bank endpoint */ 1208 #define USBHS_DEVEPTCFG_EPBK_2_BANK_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Double-bank endpoint */ 1209 #define USBHS_DEVEPTCFG_EPBK_3_BANK_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Triple-bank endpoint */ 1210 #define USBHS_DEVEPTCFG_EPBK_1_BANK (USBHS_DEVEPTCFG_EPBK_1_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Single-bank endpoint Position */ 1211 #define USBHS_DEVEPTCFG_EPBK_2_BANK (USBHS_DEVEPTCFG_EPBK_2_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Double-bank endpoint Position */ 1212 #define USBHS_DEVEPTCFG_EPBK_3_BANK (USBHS_DEVEPTCFG_EPBK_3_BANK_Val << USBHS_DEVEPTCFG_EPBK_Pos) /**< (USBHS_DEVEPTCFG) Triple-bank endpoint Position */ 1213 #define USBHS_DEVEPTCFG_EPSIZE_Pos 4 /**< (USBHS_DEVEPTCFG) Endpoint Size Position */ 1214 #define USBHS_DEVEPTCFG_EPSIZE_Msk (_U_(0x7) << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Size Mask */ 1215 #define USBHS_DEVEPTCFG_EPSIZE(value) (USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos)) 1216 #define USBHS_DEVEPTCFG_EPSIZE_8_BYTE_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) 8 bytes */ 1217 #define USBHS_DEVEPTCFG_EPSIZE_16_BYTE_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) 16 bytes */ 1218 #define USBHS_DEVEPTCFG_EPSIZE_32_BYTE_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) 32 bytes */ 1219 #define USBHS_DEVEPTCFG_EPSIZE_64_BYTE_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) 64 bytes */ 1220 #define USBHS_DEVEPTCFG_EPSIZE_128_BYTE_Val _U_(0x4) /**< (USBHS_DEVEPTCFG) 128 bytes */ 1221 #define USBHS_DEVEPTCFG_EPSIZE_256_BYTE_Val _U_(0x5) /**< (USBHS_DEVEPTCFG) 256 bytes */ 1222 #define USBHS_DEVEPTCFG_EPSIZE_512_BYTE_Val _U_(0x6) /**< (USBHS_DEVEPTCFG) 512 bytes */ 1223 #define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE_Val _U_(0x7) /**< (USBHS_DEVEPTCFG) 1024 bytes */ 1224 #define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (USBHS_DEVEPTCFG_EPSIZE_8_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 8 bytes Position */ 1225 #define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (USBHS_DEVEPTCFG_EPSIZE_16_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 16 bytes Position */ 1226 #define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (USBHS_DEVEPTCFG_EPSIZE_32_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 32 bytes Position */ 1227 #define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (USBHS_DEVEPTCFG_EPSIZE_64_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 64 bytes Position */ 1228 #define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (USBHS_DEVEPTCFG_EPSIZE_128_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 128 bytes Position */ 1229 #define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (USBHS_DEVEPTCFG_EPSIZE_256_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 256 bytes Position */ 1230 #define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (USBHS_DEVEPTCFG_EPSIZE_512_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 512 bytes Position */ 1231 #define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (USBHS_DEVEPTCFG_EPSIZE_1024_BYTE_Val << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< (USBHS_DEVEPTCFG) 1024 bytes Position */ 1232 #define USBHS_DEVEPTCFG_EPDIR_Pos 8 /**< (USBHS_DEVEPTCFG) Endpoint Direction Position */ 1233 #define USBHS_DEVEPTCFG_EPDIR_Msk (_U_(0x1) << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Direction Mask */ 1234 #define USBHS_DEVEPTCFG_EPDIR USBHS_DEVEPTCFG_EPDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTCFG_EPDIR_Msk instead */ 1235 #define USBHS_DEVEPTCFG_EPDIR_OUT_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) The endpoint direction is OUT. */ 1236 #define USBHS_DEVEPTCFG_EPDIR_IN_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). */ 1237 #define USBHS_DEVEPTCFG_EPDIR_OUT (USBHS_DEVEPTCFG_EPDIR_OUT_Val << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) The endpoint direction is OUT. Position */ 1238 #define USBHS_DEVEPTCFG_EPDIR_IN (USBHS_DEVEPTCFG_EPDIR_IN_Val << USBHS_DEVEPTCFG_EPDIR_Pos) /**< (USBHS_DEVEPTCFG) The endpoint direction is IN (nor for control endpoints). Position */ 1239 #define USBHS_DEVEPTCFG_AUTOSW_Pos 9 /**< (USBHS_DEVEPTCFG) Automatic Switch Position */ 1240 #define USBHS_DEVEPTCFG_AUTOSW_Msk (_U_(0x1) << USBHS_DEVEPTCFG_AUTOSW_Pos) /**< (USBHS_DEVEPTCFG) Automatic Switch Mask */ 1241 #define USBHS_DEVEPTCFG_AUTOSW USBHS_DEVEPTCFG_AUTOSW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTCFG_AUTOSW_Msk instead */ 1242 #define USBHS_DEVEPTCFG_EPTYPE_Pos 11 /**< (USBHS_DEVEPTCFG) Endpoint Type Position */ 1243 #define USBHS_DEVEPTCFG_EPTYPE_Msk (_U_(0x3) << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Endpoint Type Mask */ 1244 #define USBHS_DEVEPTCFG_EPTYPE(value) (USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos)) 1245 #define USBHS_DEVEPTCFG_EPTYPE_CTRL_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Control */ 1246 #define USBHS_DEVEPTCFG_EPTYPE_ISO_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Isochronous */ 1247 #define USBHS_DEVEPTCFG_EPTYPE_BLK_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Bulk */ 1248 #define USBHS_DEVEPTCFG_EPTYPE_INTRPT_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) Interrupt */ 1249 #define USBHS_DEVEPTCFG_EPTYPE_CTRL (USBHS_DEVEPTCFG_EPTYPE_CTRL_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Control Position */ 1250 #define USBHS_DEVEPTCFG_EPTYPE_ISO (USBHS_DEVEPTCFG_EPTYPE_ISO_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Isochronous Position */ 1251 #define USBHS_DEVEPTCFG_EPTYPE_BLK (USBHS_DEVEPTCFG_EPTYPE_BLK_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Bulk Position */ 1252 #define USBHS_DEVEPTCFG_EPTYPE_INTRPT (USBHS_DEVEPTCFG_EPTYPE_INTRPT_Val << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< (USBHS_DEVEPTCFG) Interrupt Position */ 1253 #define USBHS_DEVEPTCFG_NBTRANS_Pos 13 /**< (USBHS_DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Position */ 1254 #define USBHS_DEVEPTCFG_NBTRANS_Msk (_U_(0x3) << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Number of transactions per microframe for isochronous endpoint Mask */ 1255 #define USBHS_DEVEPTCFG_NBTRANS(value) (USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos)) 1256 #define USBHS_DEVEPTCFG_NBTRANS_0_TRANS_Val _U_(0x0) /**< (USBHS_DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ 1257 #define USBHS_DEVEPTCFG_NBTRANS_1_TRANS_Val _U_(0x1) /**< (USBHS_DEVEPTCFG) Default value: one transaction per microframe. */ 1258 #define USBHS_DEVEPTCFG_NBTRANS_2_TRANS_Val _U_(0x2) /**< (USBHS_DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. */ 1259 #define USBHS_DEVEPTCFG_NBTRANS_3_TRANS_Val _U_(0x3) /**< (USBHS_DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. */ 1260 #define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (USBHS_DEVEPTCFG_NBTRANS_0_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Reserved to endpoint that does not have the high-bandwidth isochronous capability. Position */ 1261 #define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (USBHS_DEVEPTCFG_NBTRANS_1_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Default value: one transaction per microframe. Position */ 1262 #define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (USBHS_DEVEPTCFG_NBTRANS_2_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Two transactions per microframe. This endpoint should be configured as double-bank. Position */ 1263 #define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (USBHS_DEVEPTCFG_NBTRANS_3_TRANS_Val << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< (USBHS_DEVEPTCFG) Three transactions per microframe. This endpoint should be configured as triple-bank. Position */ 1264 #define USBHS_DEVEPTCFG_MASK _U_(0x7B7E) /**< \deprecated (USBHS_DEVEPTCFG) Register MASK (Use USBHS_DEVEPTCFG_Msk instead) */ 1265 #define USBHS_DEVEPTCFG_Msk _U_(0x7B7E) /**< (USBHS_DEVEPTCFG) Register Mask */ 1266 1267 1268 /* -------- USBHS_DEVEPTISR : (USBHS Offset: 0x130) (R/ 32) Device Endpoint Interrupt Status Register -------- */ 1269 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1270 #if COMPONENT_TYPEDEF_STYLE == 'N' 1271 typedef union { 1272 struct { 1273 uint32_t TXINI:1; /**< bit: 0 Transmitted IN Data Interrupt */ 1274 uint32_t RXOUTI:1; /**< bit: 1 Received OUT Data Interrupt */ 1275 uint32_t :3; /**< bit: 2..4 Reserved */ 1276 uint32_t OVERFI:1; /**< bit: 5 Overflow Interrupt */ 1277 uint32_t :1; /**< bit: 6 Reserved */ 1278 uint32_t SHORTPACKET:1; /**< bit: 7 Short Packet Interrupt */ 1279 uint32_t DTSEQ:2; /**< bit: 8..9 Data Toggle Sequence */ 1280 uint32_t :2; /**< bit: 10..11 Reserved */ 1281 uint32_t NBUSYBK:2; /**< bit: 12..13 Number of Busy Banks */ 1282 uint32_t CURRBK:2; /**< bit: 14..15 Current Bank */ 1283 uint32_t RWALL:1; /**< bit: 16 Read/Write Allowed */ 1284 uint32_t :1; /**< bit: 17 Reserved */ 1285 uint32_t CFGOK:1; /**< bit: 18 Configuration OK Status */ 1286 uint32_t :1; /**< bit: 19 Reserved */ 1287 uint32_t BYCT:11; /**< bit: 20..30 Byte Count */ 1288 uint32_t :1; /**< bit: 31 Reserved */ 1289 } bit; /**< Structure used for bit access */ 1290 struct { // CTRL mode 1291 uint32_t :2; /**< bit: 0..1 Reserved */ 1292 uint32_t RXSTPI:1; /**< bit: 2 Received SETUP Interrupt */ 1293 uint32_t NAKOUTI:1; /**< bit: 3 NAKed OUT Interrupt */ 1294 uint32_t NAKINI:1; /**< bit: 4 NAKed IN Interrupt */ 1295 uint32_t :1; /**< bit: 5 Reserved */ 1296 uint32_t STALLEDI:1; /**< bit: 6 STALLed Interrupt */ 1297 uint32_t :10; /**< bit: 7..16 Reserved */ 1298 uint32_t CTRLDIR:1; /**< bit: 17 Control Direction */ 1299 uint32_t :14; /**< bit: 18..31 Reserved */ 1300 } CTRL; /**< Structure used for CTRL mode access */ 1301 struct { // ISO mode 1302 uint32_t :2; /**< bit: 0..1 Reserved */ 1303 uint32_t UNDERFI:1; /**< bit: 2 Underflow Interrupt */ 1304 uint32_t HBISOINERRI:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt */ 1305 uint32_t HBISOFLUSHI:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt */ 1306 uint32_t :1; /**< bit: 5 Reserved */ 1307 uint32_t CRCERRI:1; /**< bit: 6 CRC Error Interrupt */ 1308 uint32_t :3; /**< bit: 7..9 Reserved */ 1309 uint32_t ERRORTRANS:1; /**< bit: 10 High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ 1310 uint32_t :21; /**< bit: 11..31 Reserved */ 1311 } ISO; /**< Structure used for ISO mode access */ 1312 struct { // BLK mode 1313 uint32_t :2; /**< bit: 0..1 Reserved */ 1314 uint32_t RXSTPI:1; /**< bit: 2 Received SETUP Interrupt */ 1315 uint32_t NAKOUTI:1; /**< bit: 3 NAKed OUT Interrupt */ 1316 uint32_t NAKINI:1; /**< bit: 4 NAKed IN Interrupt */ 1317 uint32_t :1; /**< bit: 5 Reserved */ 1318 uint32_t STALLEDI:1; /**< bit: 6 STALLed Interrupt */ 1319 uint32_t :10; /**< bit: 7..16 Reserved */ 1320 uint32_t CTRLDIR:1; /**< bit: 17 Control Direction */ 1321 uint32_t :14; /**< bit: 18..31 Reserved */ 1322 } BLK; /**< Structure used for BLK mode access */ 1323 struct { // INTRPT mode 1324 uint32_t :2; /**< bit: 0..1 Reserved */ 1325 uint32_t RXSTPI:1; /**< bit: 2 Received SETUP Interrupt */ 1326 uint32_t NAKOUTI:1; /**< bit: 3 NAKed OUT Interrupt */ 1327 uint32_t NAKINI:1; /**< bit: 4 NAKed IN Interrupt */ 1328 uint32_t :1; /**< bit: 5 Reserved */ 1329 uint32_t STALLEDI:1; /**< bit: 6 STALLed Interrupt */ 1330 uint32_t :10; /**< bit: 7..16 Reserved */ 1331 uint32_t CTRLDIR:1; /**< bit: 17 Control Direction */ 1332 uint32_t :14; /**< bit: 18..31 Reserved */ 1333 } INTRPT; /**< Structure used for INTRPT mode access */ 1334 uint32_t reg; /**< Type used for register access */ 1335 } USBHS_DEVEPTISR_Type; 1336 #endif 1337 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1338 1339 #define USBHS_DEVEPTISR_OFFSET (0x130) /**< (USBHS_DEVEPTISR) Device Endpoint Interrupt Status Register Offset */ 1340 1341 #define USBHS_DEVEPTISR_TXINI_Pos 0 /**< (USBHS_DEVEPTISR) Transmitted IN Data Interrupt Position */ 1342 #define USBHS_DEVEPTISR_TXINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_TXINI_Pos) /**< (USBHS_DEVEPTISR) Transmitted IN Data Interrupt Mask */ 1343 #define USBHS_DEVEPTISR_TXINI USBHS_DEVEPTISR_TXINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_TXINI_Msk instead */ 1344 #define USBHS_DEVEPTISR_RXOUTI_Pos 1 /**< (USBHS_DEVEPTISR) Received OUT Data Interrupt Position */ 1345 #define USBHS_DEVEPTISR_RXOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_RXOUTI_Pos) /**< (USBHS_DEVEPTISR) Received OUT Data Interrupt Mask */ 1346 #define USBHS_DEVEPTISR_RXOUTI USBHS_DEVEPTISR_RXOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_RXOUTI_Msk instead */ 1347 #define USBHS_DEVEPTISR_OVERFI_Pos 5 /**< (USBHS_DEVEPTISR) Overflow Interrupt Position */ 1348 #define USBHS_DEVEPTISR_OVERFI_Msk (_U_(0x1) << USBHS_DEVEPTISR_OVERFI_Pos) /**< (USBHS_DEVEPTISR) Overflow Interrupt Mask */ 1349 #define USBHS_DEVEPTISR_OVERFI USBHS_DEVEPTISR_OVERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_OVERFI_Msk instead */ 1350 #define USBHS_DEVEPTISR_SHORTPACKET_Pos 7 /**< (USBHS_DEVEPTISR) Short Packet Interrupt Position */ 1351 #define USBHS_DEVEPTISR_SHORTPACKET_Msk (_U_(0x1) << USBHS_DEVEPTISR_SHORTPACKET_Pos) /**< (USBHS_DEVEPTISR) Short Packet Interrupt Mask */ 1352 #define USBHS_DEVEPTISR_SHORTPACKET USBHS_DEVEPTISR_SHORTPACKET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_SHORTPACKET_Msk instead */ 1353 #define USBHS_DEVEPTISR_DTSEQ_Pos 8 /**< (USBHS_DEVEPTISR) Data Toggle Sequence Position */ 1354 #define USBHS_DEVEPTISR_DTSEQ_Msk (_U_(0x3) << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data Toggle Sequence Mask */ 1355 #define USBHS_DEVEPTISR_DTSEQ(value) (USBHS_DEVEPTISR_DTSEQ_Msk & ((value) << USBHS_DEVEPTISR_DTSEQ_Pos)) 1356 #define USBHS_DEVEPTISR_DTSEQ_DATA0_Val _U_(0x0) /**< (USBHS_DEVEPTISR) Data0 toggle sequence */ 1357 #define USBHS_DEVEPTISR_DTSEQ_DATA1_Val _U_(0x1) /**< (USBHS_DEVEPTISR) Data1 toggle sequence */ 1358 #define USBHS_DEVEPTISR_DTSEQ_DATA2_Val _U_(0x2) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ 1359 #define USBHS_DEVEPTISR_DTSEQ_MDATA_Val _U_(0x3) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint */ 1360 #define USBHS_DEVEPTISR_DTSEQ_DATA0 (USBHS_DEVEPTISR_DTSEQ_DATA0_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data0 toggle sequence Position */ 1361 #define USBHS_DEVEPTISR_DTSEQ_DATA1 (USBHS_DEVEPTISR_DTSEQ_DATA1_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Data1 toggle sequence Position */ 1362 #define USBHS_DEVEPTISR_DTSEQ_DATA2 (USBHS_DEVEPTISR_DTSEQ_DATA2_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ 1363 #define USBHS_DEVEPTISR_DTSEQ_MDATA (USBHS_DEVEPTISR_DTSEQ_MDATA_Val << USBHS_DEVEPTISR_DTSEQ_Pos) /**< (USBHS_DEVEPTISR) Reserved for high-bandwidth isochronous endpoint Position */ 1364 #define USBHS_DEVEPTISR_NBUSYBK_Pos 12 /**< (USBHS_DEVEPTISR) Number of Busy Banks Position */ 1365 #define USBHS_DEVEPTISR_NBUSYBK_Msk (_U_(0x3) << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) Number of Busy Banks Mask */ 1366 #define USBHS_DEVEPTISR_NBUSYBK(value) (USBHS_DEVEPTISR_NBUSYBK_Msk & ((value) << USBHS_DEVEPTISR_NBUSYBK_Pos)) 1367 #define USBHS_DEVEPTISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (USBHS_DEVEPTISR) 0 busy bank (all banks free) */ 1368 #define USBHS_DEVEPTISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (USBHS_DEVEPTISR) 1 busy bank */ 1369 #define USBHS_DEVEPTISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (USBHS_DEVEPTISR) 2 busy banks */ 1370 #define USBHS_DEVEPTISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (USBHS_DEVEPTISR) 3 busy banks */ 1371 #define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (USBHS_DEVEPTISR_NBUSYBK_0_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 0 busy bank (all banks free) Position */ 1372 #define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (USBHS_DEVEPTISR_NBUSYBK_1_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 1 busy bank Position */ 1373 #define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (USBHS_DEVEPTISR_NBUSYBK_2_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 2 busy banks Position */ 1374 #define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (USBHS_DEVEPTISR_NBUSYBK_3_BUSY_Val << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< (USBHS_DEVEPTISR) 3 busy banks Position */ 1375 #define USBHS_DEVEPTISR_CURRBK_Pos 14 /**< (USBHS_DEVEPTISR) Current Bank Position */ 1376 #define USBHS_DEVEPTISR_CURRBK_Msk (_U_(0x3) << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current Bank Mask */ 1377 #define USBHS_DEVEPTISR_CURRBK(value) (USBHS_DEVEPTISR_CURRBK_Msk & ((value) << USBHS_DEVEPTISR_CURRBK_Pos)) 1378 #define USBHS_DEVEPTISR_CURRBK_BANK0_Val _U_(0x0) /**< (USBHS_DEVEPTISR) Current bank is bank0 */ 1379 #define USBHS_DEVEPTISR_CURRBK_BANK1_Val _U_(0x1) /**< (USBHS_DEVEPTISR) Current bank is bank1 */ 1380 #define USBHS_DEVEPTISR_CURRBK_BANK2_Val _U_(0x2) /**< (USBHS_DEVEPTISR) Current bank is bank2 */ 1381 #define USBHS_DEVEPTISR_CURRBK_BANK0 (USBHS_DEVEPTISR_CURRBK_BANK0_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank0 Position */ 1382 #define USBHS_DEVEPTISR_CURRBK_BANK1 (USBHS_DEVEPTISR_CURRBK_BANK1_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank1 Position */ 1383 #define USBHS_DEVEPTISR_CURRBK_BANK2 (USBHS_DEVEPTISR_CURRBK_BANK2_Val << USBHS_DEVEPTISR_CURRBK_Pos) /**< (USBHS_DEVEPTISR) Current bank is bank2 Position */ 1384 #define USBHS_DEVEPTISR_RWALL_Pos 16 /**< (USBHS_DEVEPTISR) Read/Write Allowed Position */ 1385 #define USBHS_DEVEPTISR_RWALL_Msk (_U_(0x1) << USBHS_DEVEPTISR_RWALL_Pos) /**< (USBHS_DEVEPTISR) Read/Write Allowed Mask */ 1386 #define USBHS_DEVEPTISR_RWALL USBHS_DEVEPTISR_RWALL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_RWALL_Msk instead */ 1387 #define USBHS_DEVEPTISR_CFGOK_Pos 18 /**< (USBHS_DEVEPTISR) Configuration OK Status Position */ 1388 #define USBHS_DEVEPTISR_CFGOK_Msk (_U_(0x1) << USBHS_DEVEPTISR_CFGOK_Pos) /**< (USBHS_DEVEPTISR) Configuration OK Status Mask */ 1389 #define USBHS_DEVEPTISR_CFGOK USBHS_DEVEPTISR_CFGOK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CFGOK_Msk instead */ 1390 #define USBHS_DEVEPTISR_BYCT_Pos 20 /**< (USBHS_DEVEPTISR) Byte Count Position */ 1391 #define USBHS_DEVEPTISR_BYCT_Msk (_U_(0x7FF) << USBHS_DEVEPTISR_BYCT_Pos) /**< (USBHS_DEVEPTISR) Byte Count Mask */ 1392 #define USBHS_DEVEPTISR_BYCT(value) (USBHS_DEVEPTISR_BYCT_Msk & ((value) << USBHS_DEVEPTISR_BYCT_Pos)) 1393 #define USBHS_DEVEPTISR_MASK _U_(0x7FF5F3A3) /**< \deprecated (USBHS_DEVEPTISR) Register MASK (Use USBHS_DEVEPTISR_Msk instead) */ 1394 #define USBHS_DEVEPTISR_Msk _U_(0x7FF5F3A3) /**< (USBHS_DEVEPTISR) Register Mask */ 1395 1396 /* CTRL mode */ 1397 #define USBHS_DEVEPTISR_CTRL_RXSTPI_Pos 2 /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ 1398 #define USBHS_DEVEPTISR_CTRL_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ 1399 #define USBHS_DEVEPTISR_CTRL_RXSTPI USBHS_DEVEPTISR_CTRL_RXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_RXSTPI_Msk instead */ 1400 #define USBHS_DEVEPTISR_CTRL_NAKOUTI_Pos 3 /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ 1401 #define USBHS_DEVEPTISR_CTRL_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ 1402 #define USBHS_DEVEPTISR_CTRL_NAKOUTI USBHS_DEVEPTISR_CTRL_NAKOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_NAKOUTI_Msk instead */ 1403 #define USBHS_DEVEPTISR_CTRL_NAKINI_Pos 4 /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ 1404 #define USBHS_DEVEPTISR_CTRL_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ 1405 #define USBHS_DEVEPTISR_CTRL_NAKINI USBHS_DEVEPTISR_CTRL_NAKINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_NAKINI_Msk instead */ 1406 #define USBHS_DEVEPTISR_CTRL_STALLEDI_Pos 6 /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ 1407 #define USBHS_DEVEPTISR_CTRL_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ 1408 #define USBHS_DEVEPTISR_CTRL_STALLEDI USBHS_DEVEPTISR_CTRL_STALLEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_STALLEDI_Msk instead */ 1409 #define USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos 17 /**< (USBHS_DEVEPTISR) Control Direction Position */ 1410 #define USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_CTRL_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ 1411 #define USBHS_DEVEPTISR_CTRL_CTRLDIR USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_CTRL_CTRLDIR_Msk instead */ 1412 #define USBHS_DEVEPTISR_CTRL_MASK _U_(0x2005C) /**< \deprecated (USBHS_DEVEPTISR_CTRL) Register MASK (Use USBHS_DEVEPTISR_CTRL_Msk instead) */ 1413 #define USBHS_DEVEPTISR_CTRL_Msk _U_(0x2005C) /**< (USBHS_DEVEPTISR_CTRL) Register Mask */ 1414 1415 /* ISO mode */ 1416 #define USBHS_DEVEPTISR_ISO_UNDERFI_Pos 2 /**< (USBHS_DEVEPTISR) Underflow Interrupt Position */ 1417 #define USBHS_DEVEPTISR_ISO_UNDERFI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_UNDERFI_Pos) /**< (USBHS_DEVEPTISR) Underflow Interrupt Mask */ 1418 #define USBHS_DEVEPTISR_ISO_UNDERFI USBHS_DEVEPTISR_ISO_UNDERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_UNDERFI_Msk instead */ 1419 #define USBHS_DEVEPTISR_ISO_HBISOINERRI_Pos 3 /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ 1420 #define USBHS_DEVEPTISR_ISO_HBISOINERRI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_HBISOINERRI_Pos) /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ 1421 #define USBHS_DEVEPTISR_ISO_HBISOINERRI USBHS_DEVEPTISR_ISO_HBISOINERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_HBISOINERRI_Msk instead */ 1422 #define USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Pos 4 /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Position */ 1423 #define USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Pos) /**< (USBHS_DEVEPTISR) High Bandwidth Isochronous IN Flush Interrupt Mask */ 1424 #define USBHS_DEVEPTISR_ISO_HBISOFLUSHI USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_HBISOFLUSHI_Msk instead */ 1425 #define USBHS_DEVEPTISR_ISO_CRCERRI_Pos 6 /**< (USBHS_DEVEPTISR) CRC Error Interrupt Position */ 1426 #define USBHS_DEVEPTISR_ISO_CRCERRI_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_CRCERRI_Pos) /**< (USBHS_DEVEPTISR) CRC Error Interrupt Mask */ 1427 #define USBHS_DEVEPTISR_ISO_CRCERRI USBHS_DEVEPTISR_ISO_CRCERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_CRCERRI_Msk instead */ 1428 #define USBHS_DEVEPTISR_ISO_ERRORTRANS_Pos 10 /**< (USBHS_DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Position */ 1429 #define USBHS_DEVEPTISR_ISO_ERRORTRANS_Msk (_U_(0x1) << USBHS_DEVEPTISR_ISO_ERRORTRANS_Pos) /**< (USBHS_DEVEPTISR) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt Mask */ 1430 #define USBHS_DEVEPTISR_ISO_ERRORTRANS USBHS_DEVEPTISR_ISO_ERRORTRANS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_ISO_ERRORTRANS_Msk instead */ 1431 #define USBHS_DEVEPTISR_ISO_MASK _U_(0x45C) /**< \deprecated (USBHS_DEVEPTISR_ISO) Register MASK (Use USBHS_DEVEPTISR_ISO_Msk instead) */ 1432 #define USBHS_DEVEPTISR_ISO_Msk _U_(0x45C) /**< (USBHS_DEVEPTISR_ISO) Register Mask */ 1433 1434 /* BLK mode */ 1435 #define USBHS_DEVEPTISR_BLK_RXSTPI_Pos 2 /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ 1436 #define USBHS_DEVEPTISR_BLK_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ 1437 #define USBHS_DEVEPTISR_BLK_RXSTPI USBHS_DEVEPTISR_BLK_RXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_RXSTPI_Msk instead */ 1438 #define USBHS_DEVEPTISR_BLK_NAKOUTI_Pos 3 /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ 1439 #define USBHS_DEVEPTISR_BLK_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ 1440 #define USBHS_DEVEPTISR_BLK_NAKOUTI USBHS_DEVEPTISR_BLK_NAKOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_NAKOUTI_Msk instead */ 1441 #define USBHS_DEVEPTISR_BLK_NAKINI_Pos 4 /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ 1442 #define USBHS_DEVEPTISR_BLK_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ 1443 #define USBHS_DEVEPTISR_BLK_NAKINI USBHS_DEVEPTISR_BLK_NAKINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_NAKINI_Msk instead */ 1444 #define USBHS_DEVEPTISR_BLK_STALLEDI_Pos 6 /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ 1445 #define USBHS_DEVEPTISR_BLK_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ 1446 #define USBHS_DEVEPTISR_BLK_STALLEDI USBHS_DEVEPTISR_BLK_STALLEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_STALLEDI_Msk instead */ 1447 #define USBHS_DEVEPTISR_BLK_CTRLDIR_Pos 17 /**< (USBHS_DEVEPTISR) Control Direction Position */ 1448 #define USBHS_DEVEPTISR_BLK_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_BLK_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ 1449 #define USBHS_DEVEPTISR_BLK_CTRLDIR USBHS_DEVEPTISR_BLK_CTRLDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_BLK_CTRLDIR_Msk instead */ 1450 #define USBHS_DEVEPTISR_BLK_MASK _U_(0x2005C) /**< \deprecated (USBHS_DEVEPTISR_BLK) Register MASK (Use USBHS_DEVEPTISR_BLK_Msk instead) */ 1451 #define USBHS_DEVEPTISR_BLK_Msk _U_(0x2005C) /**< (USBHS_DEVEPTISR_BLK) Register Mask */ 1452 1453 /* INTRPT mode */ 1454 #define USBHS_DEVEPTISR_INTRPT_RXSTPI_Pos 2 /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Position */ 1455 #define USBHS_DEVEPTISR_INTRPT_RXSTPI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_RXSTPI_Pos) /**< (USBHS_DEVEPTISR) Received SETUP Interrupt Mask */ 1456 #define USBHS_DEVEPTISR_INTRPT_RXSTPI USBHS_DEVEPTISR_INTRPT_RXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_RXSTPI_Msk instead */ 1457 #define USBHS_DEVEPTISR_INTRPT_NAKOUTI_Pos 3 /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Position */ 1458 #define USBHS_DEVEPTISR_INTRPT_NAKOUTI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_NAKOUTI_Pos) /**< (USBHS_DEVEPTISR) NAKed OUT Interrupt Mask */ 1459 #define USBHS_DEVEPTISR_INTRPT_NAKOUTI USBHS_DEVEPTISR_INTRPT_NAKOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_NAKOUTI_Msk instead */ 1460 #define USBHS_DEVEPTISR_INTRPT_NAKINI_Pos 4 /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Position */ 1461 #define USBHS_DEVEPTISR_INTRPT_NAKINI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_NAKINI_Pos) /**< (USBHS_DEVEPTISR) NAKed IN Interrupt Mask */ 1462 #define USBHS_DEVEPTISR_INTRPT_NAKINI USBHS_DEVEPTISR_INTRPT_NAKINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_NAKINI_Msk instead */ 1463 #define USBHS_DEVEPTISR_INTRPT_STALLEDI_Pos 6 /**< (USBHS_DEVEPTISR) STALLed Interrupt Position */ 1464 #define USBHS_DEVEPTISR_INTRPT_STALLEDI_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_STALLEDI_Pos) /**< (USBHS_DEVEPTISR) STALLed Interrupt Mask */ 1465 #define USBHS_DEVEPTISR_INTRPT_STALLEDI USBHS_DEVEPTISR_INTRPT_STALLEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_STALLEDI_Msk instead */ 1466 #define USBHS_DEVEPTISR_INTRPT_CTRLDIR_Pos 17 /**< (USBHS_DEVEPTISR) Control Direction Position */ 1467 #define USBHS_DEVEPTISR_INTRPT_CTRLDIR_Msk (_U_(0x1) << USBHS_DEVEPTISR_INTRPT_CTRLDIR_Pos) /**< (USBHS_DEVEPTISR) Control Direction Mask */ 1468 #define USBHS_DEVEPTISR_INTRPT_CTRLDIR USBHS_DEVEPTISR_INTRPT_CTRLDIR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTISR_INTRPT_CTRLDIR_Msk instead */ 1469 #define USBHS_DEVEPTISR_INTRPT_MASK _U_(0x2005C) /**< \deprecated (USBHS_DEVEPTISR_INTRPT) Register MASK (Use USBHS_DEVEPTISR_INTRPT_Msk instead) */ 1470 #define USBHS_DEVEPTISR_INTRPT_Msk _U_(0x2005C) /**< (USBHS_DEVEPTISR_INTRPT) Register Mask */ 1471 1472 1473 /* -------- USBHS_DEVEPTICR : (USBHS Offset: 0x160) (/W 32) Device Endpoint Interrupt Clear Register -------- */ 1474 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1475 #if COMPONENT_TYPEDEF_STYLE == 'N' 1476 typedef union { 1477 struct { 1478 uint32_t TXINIC:1; /**< bit: 0 Transmitted IN Data Interrupt Clear */ 1479 uint32_t RXOUTIC:1; /**< bit: 1 Received OUT Data Interrupt Clear */ 1480 uint32_t :3; /**< bit: 2..4 Reserved */ 1481 uint32_t OVERFIC:1; /**< bit: 5 Overflow Interrupt Clear */ 1482 uint32_t :1; /**< bit: 6 Reserved */ 1483 uint32_t SHORTPACKETC:1; /**< bit: 7 Short Packet Interrupt Clear */ 1484 uint32_t :24; /**< bit: 8..31 Reserved */ 1485 } bit; /**< Structure used for bit access */ 1486 struct { // CTRL mode 1487 uint32_t :2; /**< bit: 0..1 Reserved */ 1488 uint32_t RXSTPIC:1; /**< bit: 2 Received SETUP Interrupt Clear */ 1489 uint32_t NAKOUTIC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ 1490 uint32_t NAKINIC:1; /**< bit: 4 NAKed IN Interrupt Clear */ 1491 uint32_t :1; /**< bit: 5 Reserved */ 1492 uint32_t STALLEDIC:1; /**< bit: 6 STALLed Interrupt Clear */ 1493 uint32_t :25; /**< bit: 7..31 Reserved */ 1494 } CTRL; /**< Structure used for CTRL mode access */ 1495 struct { // ISO mode 1496 uint32_t :2; /**< bit: 0..1 Reserved */ 1497 uint32_t UNDERFIC:1; /**< bit: 2 Underflow Interrupt Clear */ 1498 uint32_t HBISOINERRIC:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ 1499 uint32_t HBISOFLUSHIC:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt Clear */ 1500 uint32_t :1; /**< bit: 5 Reserved */ 1501 uint32_t CRCERRIC:1; /**< bit: 6 CRC Error Interrupt Clear */ 1502 uint32_t :25; /**< bit: 7..31 Reserved */ 1503 } ISO; /**< Structure used for ISO mode access */ 1504 struct { // BLK mode 1505 uint32_t :2; /**< bit: 0..1 Reserved */ 1506 uint32_t RXSTPIC:1; /**< bit: 2 Received SETUP Interrupt Clear */ 1507 uint32_t NAKOUTIC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ 1508 uint32_t NAKINIC:1; /**< bit: 4 NAKed IN Interrupt Clear */ 1509 uint32_t :1; /**< bit: 5 Reserved */ 1510 uint32_t STALLEDIC:1; /**< bit: 6 STALLed Interrupt Clear */ 1511 uint32_t :25; /**< bit: 7..31 Reserved */ 1512 } BLK; /**< Structure used for BLK mode access */ 1513 struct { // INTRPT mode 1514 uint32_t :2; /**< bit: 0..1 Reserved */ 1515 uint32_t RXSTPIC:1; /**< bit: 2 Received SETUP Interrupt Clear */ 1516 uint32_t NAKOUTIC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ 1517 uint32_t NAKINIC:1; /**< bit: 4 NAKed IN Interrupt Clear */ 1518 uint32_t :1; /**< bit: 5 Reserved */ 1519 uint32_t STALLEDIC:1; /**< bit: 6 STALLed Interrupt Clear */ 1520 uint32_t :25; /**< bit: 7..31 Reserved */ 1521 } INTRPT; /**< Structure used for INTRPT mode access */ 1522 uint32_t reg; /**< Type used for register access */ 1523 } USBHS_DEVEPTICR_Type; 1524 #endif 1525 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1526 1527 #define USBHS_DEVEPTICR_OFFSET (0x160) /**< (USBHS_DEVEPTICR) Device Endpoint Interrupt Clear Register Offset */ 1528 1529 #define USBHS_DEVEPTICR_TXINIC_Pos 0 /**< (USBHS_DEVEPTICR) Transmitted IN Data Interrupt Clear Position */ 1530 #define USBHS_DEVEPTICR_TXINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_TXINIC_Pos) /**< (USBHS_DEVEPTICR) Transmitted IN Data Interrupt Clear Mask */ 1531 #define USBHS_DEVEPTICR_TXINIC USBHS_DEVEPTICR_TXINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_TXINIC_Msk instead */ 1532 #define USBHS_DEVEPTICR_RXOUTIC_Pos 1 /**< (USBHS_DEVEPTICR) Received OUT Data Interrupt Clear Position */ 1533 #define USBHS_DEVEPTICR_RXOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_RXOUTIC_Pos) /**< (USBHS_DEVEPTICR) Received OUT Data Interrupt Clear Mask */ 1534 #define USBHS_DEVEPTICR_RXOUTIC USBHS_DEVEPTICR_RXOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_RXOUTIC_Msk instead */ 1535 #define USBHS_DEVEPTICR_OVERFIC_Pos 5 /**< (USBHS_DEVEPTICR) Overflow Interrupt Clear Position */ 1536 #define USBHS_DEVEPTICR_OVERFIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_OVERFIC_Pos) /**< (USBHS_DEVEPTICR) Overflow Interrupt Clear Mask */ 1537 #define USBHS_DEVEPTICR_OVERFIC USBHS_DEVEPTICR_OVERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_OVERFIC_Msk instead */ 1538 #define USBHS_DEVEPTICR_SHORTPACKETC_Pos 7 /**< (USBHS_DEVEPTICR) Short Packet Interrupt Clear Position */ 1539 #define USBHS_DEVEPTICR_SHORTPACKETC_Msk (_U_(0x1) << USBHS_DEVEPTICR_SHORTPACKETC_Pos) /**< (USBHS_DEVEPTICR) Short Packet Interrupt Clear Mask */ 1540 #define USBHS_DEVEPTICR_SHORTPACKETC USBHS_DEVEPTICR_SHORTPACKETC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_SHORTPACKETC_Msk instead */ 1541 #define USBHS_DEVEPTICR_MASK _U_(0xA3) /**< \deprecated (USBHS_DEVEPTICR) Register MASK (Use USBHS_DEVEPTICR_Msk instead) */ 1542 #define USBHS_DEVEPTICR_Msk _U_(0xA3) /**< (USBHS_DEVEPTICR) Register Mask */ 1543 1544 /* CTRL mode */ 1545 #define USBHS_DEVEPTICR_CTRL_RXSTPIC_Pos 2 /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ 1546 #define USBHS_DEVEPTICR_CTRL_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ 1547 #define USBHS_DEVEPTICR_CTRL_RXSTPIC USBHS_DEVEPTICR_CTRL_RXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_CTRL_RXSTPIC_Msk instead */ 1548 #define USBHS_DEVEPTICR_CTRL_NAKOUTIC_Pos 3 /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ 1549 #define USBHS_DEVEPTICR_CTRL_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ 1550 #define USBHS_DEVEPTICR_CTRL_NAKOUTIC USBHS_DEVEPTICR_CTRL_NAKOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_CTRL_NAKOUTIC_Msk instead */ 1551 #define USBHS_DEVEPTICR_CTRL_NAKINIC_Pos 4 /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ 1552 #define USBHS_DEVEPTICR_CTRL_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ 1553 #define USBHS_DEVEPTICR_CTRL_NAKINIC USBHS_DEVEPTICR_CTRL_NAKINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_CTRL_NAKINIC_Msk instead */ 1554 #define USBHS_DEVEPTICR_CTRL_STALLEDIC_Pos 6 /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ 1555 #define USBHS_DEVEPTICR_CTRL_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_CTRL_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ 1556 #define USBHS_DEVEPTICR_CTRL_STALLEDIC USBHS_DEVEPTICR_CTRL_STALLEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_CTRL_STALLEDIC_Msk instead */ 1557 #define USBHS_DEVEPTICR_CTRL_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTICR_CTRL) Register MASK (Use USBHS_DEVEPTICR_CTRL_Msk instead) */ 1558 #define USBHS_DEVEPTICR_CTRL_Msk _U_(0x5C) /**< (USBHS_DEVEPTICR_CTRL) Register Mask */ 1559 1560 /* ISO mode */ 1561 #define USBHS_DEVEPTICR_ISO_UNDERFIC_Pos 2 /**< (USBHS_DEVEPTICR) Underflow Interrupt Clear Position */ 1562 #define USBHS_DEVEPTICR_ISO_UNDERFIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_UNDERFIC_Pos) /**< (USBHS_DEVEPTICR) Underflow Interrupt Clear Mask */ 1563 #define USBHS_DEVEPTICR_ISO_UNDERFIC USBHS_DEVEPTICR_ISO_UNDERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_ISO_UNDERFIC_Msk instead */ 1564 #define USBHS_DEVEPTICR_ISO_HBISOINERRIC_Pos 3 /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ 1565 #define USBHS_DEVEPTICR_ISO_HBISOINERRIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_HBISOINERRIC_Pos) /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ 1566 #define USBHS_DEVEPTICR_ISO_HBISOINERRIC USBHS_DEVEPTICR_ISO_HBISOINERRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_ISO_HBISOINERRIC_Msk instead */ 1567 #define USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Pos 4 /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ 1568 #define USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Pos) /**< (USBHS_DEVEPTICR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ 1569 #define USBHS_DEVEPTICR_ISO_HBISOFLUSHIC USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_ISO_HBISOFLUSHIC_Msk instead */ 1570 #define USBHS_DEVEPTICR_ISO_CRCERRIC_Pos 6 /**< (USBHS_DEVEPTICR) CRC Error Interrupt Clear Position */ 1571 #define USBHS_DEVEPTICR_ISO_CRCERRIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_ISO_CRCERRIC_Pos) /**< (USBHS_DEVEPTICR) CRC Error Interrupt Clear Mask */ 1572 #define USBHS_DEVEPTICR_ISO_CRCERRIC USBHS_DEVEPTICR_ISO_CRCERRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_ISO_CRCERRIC_Msk instead */ 1573 #define USBHS_DEVEPTICR_ISO_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTICR_ISO) Register MASK (Use USBHS_DEVEPTICR_ISO_Msk instead) */ 1574 #define USBHS_DEVEPTICR_ISO_Msk _U_(0x5C) /**< (USBHS_DEVEPTICR_ISO) Register Mask */ 1575 1576 /* BLK mode */ 1577 #define USBHS_DEVEPTICR_BLK_RXSTPIC_Pos 2 /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ 1578 #define USBHS_DEVEPTICR_BLK_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ 1579 #define USBHS_DEVEPTICR_BLK_RXSTPIC USBHS_DEVEPTICR_BLK_RXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_BLK_RXSTPIC_Msk instead */ 1580 #define USBHS_DEVEPTICR_BLK_NAKOUTIC_Pos 3 /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ 1581 #define USBHS_DEVEPTICR_BLK_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ 1582 #define USBHS_DEVEPTICR_BLK_NAKOUTIC USBHS_DEVEPTICR_BLK_NAKOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_BLK_NAKOUTIC_Msk instead */ 1583 #define USBHS_DEVEPTICR_BLK_NAKINIC_Pos 4 /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ 1584 #define USBHS_DEVEPTICR_BLK_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ 1585 #define USBHS_DEVEPTICR_BLK_NAKINIC USBHS_DEVEPTICR_BLK_NAKINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_BLK_NAKINIC_Msk instead */ 1586 #define USBHS_DEVEPTICR_BLK_STALLEDIC_Pos 6 /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ 1587 #define USBHS_DEVEPTICR_BLK_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_BLK_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ 1588 #define USBHS_DEVEPTICR_BLK_STALLEDIC USBHS_DEVEPTICR_BLK_STALLEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_BLK_STALLEDIC_Msk instead */ 1589 #define USBHS_DEVEPTICR_BLK_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTICR_BLK) Register MASK (Use USBHS_DEVEPTICR_BLK_Msk instead) */ 1590 #define USBHS_DEVEPTICR_BLK_Msk _U_(0x5C) /**< (USBHS_DEVEPTICR_BLK) Register Mask */ 1591 1592 /* INTRPT mode */ 1593 #define USBHS_DEVEPTICR_INTRPT_RXSTPIC_Pos 2 /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Position */ 1594 #define USBHS_DEVEPTICR_INTRPT_RXSTPIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_RXSTPIC_Pos) /**< (USBHS_DEVEPTICR) Received SETUP Interrupt Clear Mask */ 1595 #define USBHS_DEVEPTICR_INTRPT_RXSTPIC USBHS_DEVEPTICR_INTRPT_RXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_INTRPT_RXSTPIC_Msk instead */ 1596 #define USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Pos 3 /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Position */ 1597 #define USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Pos) /**< (USBHS_DEVEPTICR) NAKed OUT Interrupt Clear Mask */ 1598 #define USBHS_DEVEPTICR_INTRPT_NAKOUTIC USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_INTRPT_NAKOUTIC_Msk instead */ 1599 #define USBHS_DEVEPTICR_INTRPT_NAKINIC_Pos 4 /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Position */ 1600 #define USBHS_DEVEPTICR_INTRPT_NAKINIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_NAKINIC_Pos) /**< (USBHS_DEVEPTICR) NAKed IN Interrupt Clear Mask */ 1601 #define USBHS_DEVEPTICR_INTRPT_NAKINIC USBHS_DEVEPTICR_INTRPT_NAKINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_INTRPT_NAKINIC_Msk instead */ 1602 #define USBHS_DEVEPTICR_INTRPT_STALLEDIC_Pos 6 /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Position */ 1603 #define USBHS_DEVEPTICR_INTRPT_STALLEDIC_Msk (_U_(0x1) << USBHS_DEVEPTICR_INTRPT_STALLEDIC_Pos) /**< (USBHS_DEVEPTICR) STALLed Interrupt Clear Mask */ 1604 #define USBHS_DEVEPTICR_INTRPT_STALLEDIC USBHS_DEVEPTICR_INTRPT_STALLEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTICR_INTRPT_STALLEDIC_Msk instead */ 1605 #define USBHS_DEVEPTICR_INTRPT_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTICR_INTRPT) Register MASK (Use USBHS_DEVEPTICR_INTRPT_Msk instead) */ 1606 #define USBHS_DEVEPTICR_INTRPT_Msk _U_(0x5C) /**< (USBHS_DEVEPTICR_INTRPT) Register Mask */ 1607 1608 1609 /* -------- USBHS_DEVEPTIFR : (USBHS Offset: 0x190) (/W 32) Device Endpoint Interrupt Set Register -------- */ 1610 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1611 #if COMPONENT_TYPEDEF_STYLE == 'N' 1612 typedef union { 1613 struct { 1614 uint32_t TXINIS:1; /**< bit: 0 Transmitted IN Data Interrupt Set */ 1615 uint32_t RXOUTIS:1; /**< bit: 1 Received OUT Data Interrupt Set */ 1616 uint32_t :3; /**< bit: 2..4 Reserved */ 1617 uint32_t OVERFIS:1; /**< bit: 5 Overflow Interrupt Set */ 1618 uint32_t :1; /**< bit: 6 Reserved */ 1619 uint32_t SHORTPACKETS:1; /**< bit: 7 Short Packet Interrupt Set */ 1620 uint32_t :4; /**< bit: 8..11 Reserved */ 1621 uint32_t NBUSYBKS:1; /**< bit: 12 Number of Busy Banks Interrupt Set */ 1622 uint32_t :19; /**< bit: 13..31 Reserved */ 1623 } bit; /**< Structure used for bit access */ 1624 struct { // CTRL mode 1625 uint32_t :2; /**< bit: 0..1 Reserved */ 1626 uint32_t RXSTPIS:1; /**< bit: 2 Received SETUP Interrupt Set */ 1627 uint32_t NAKOUTIS:1; /**< bit: 3 NAKed OUT Interrupt Set */ 1628 uint32_t NAKINIS:1; /**< bit: 4 NAKed IN Interrupt Set */ 1629 uint32_t :1; /**< bit: 5 Reserved */ 1630 uint32_t STALLEDIS:1; /**< bit: 6 STALLed Interrupt Set */ 1631 uint32_t :25; /**< bit: 7..31 Reserved */ 1632 } CTRL; /**< Structure used for CTRL mode access */ 1633 struct { // ISO mode 1634 uint32_t :2; /**< bit: 0..1 Reserved */ 1635 uint32_t UNDERFIS:1; /**< bit: 2 Underflow Interrupt Set */ 1636 uint32_t HBISOINERRIS:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt Set */ 1637 uint32_t HBISOFLUSHIS:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt Set */ 1638 uint32_t :1; /**< bit: 5 Reserved */ 1639 uint32_t CRCERRIS:1; /**< bit: 6 CRC Error Interrupt Set */ 1640 uint32_t :25; /**< bit: 7..31 Reserved */ 1641 } ISO; /**< Structure used for ISO mode access */ 1642 struct { // BLK mode 1643 uint32_t :2; /**< bit: 0..1 Reserved */ 1644 uint32_t RXSTPIS:1; /**< bit: 2 Received SETUP Interrupt Set */ 1645 uint32_t NAKOUTIS:1; /**< bit: 3 NAKed OUT Interrupt Set */ 1646 uint32_t NAKINIS:1; /**< bit: 4 NAKed IN Interrupt Set */ 1647 uint32_t :1; /**< bit: 5 Reserved */ 1648 uint32_t STALLEDIS:1; /**< bit: 6 STALLed Interrupt Set */ 1649 uint32_t :25; /**< bit: 7..31 Reserved */ 1650 } BLK; /**< Structure used for BLK mode access */ 1651 struct { // INTRPT mode 1652 uint32_t :2; /**< bit: 0..1 Reserved */ 1653 uint32_t RXSTPIS:1; /**< bit: 2 Received SETUP Interrupt Set */ 1654 uint32_t NAKOUTIS:1; /**< bit: 3 NAKed OUT Interrupt Set */ 1655 uint32_t NAKINIS:1; /**< bit: 4 NAKed IN Interrupt Set */ 1656 uint32_t :1; /**< bit: 5 Reserved */ 1657 uint32_t STALLEDIS:1; /**< bit: 6 STALLed Interrupt Set */ 1658 uint32_t :25; /**< bit: 7..31 Reserved */ 1659 } INTRPT; /**< Structure used for INTRPT mode access */ 1660 uint32_t reg; /**< Type used for register access */ 1661 } USBHS_DEVEPTIFR_Type; 1662 #endif 1663 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1664 1665 #define USBHS_DEVEPTIFR_OFFSET (0x190) /**< (USBHS_DEVEPTIFR) Device Endpoint Interrupt Set Register Offset */ 1666 1667 #define USBHS_DEVEPTIFR_TXINIS_Pos 0 /**< (USBHS_DEVEPTIFR) Transmitted IN Data Interrupt Set Position */ 1668 #define USBHS_DEVEPTIFR_TXINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_TXINIS_Pos) /**< (USBHS_DEVEPTIFR) Transmitted IN Data Interrupt Set Mask */ 1669 #define USBHS_DEVEPTIFR_TXINIS USBHS_DEVEPTIFR_TXINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_TXINIS_Msk instead */ 1670 #define USBHS_DEVEPTIFR_RXOUTIS_Pos 1 /**< (USBHS_DEVEPTIFR) Received OUT Data Interrupt Set Position */ 1671 #define USBHS_DEVEPTIFR_RXOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_RXOUTIS_Pos) /**< (USBHS_DEVEPTIFR) Received OUT Data Interrupt Set Mask */ 1672 #define USBHS_DEVEPTIFR_RXOUTIS USBHS_DEVEPTIFR_RXOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_RXOUTIS_Msk instead */ 1673 #define USBHS_DEVEPTIFR_OVERFIS_Pos 5 /**< (USBHS_DEVEPTIFR) Overflow Interrupt Set Position */ 1674 #define USBHS_DEVEPTIFR_OVERFIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_OVERFIS_Pos) /**< (USBHS_DEVEPTIFR) Overflow Interrupt Set Mask */ 1675 #define USBHS_DEVEPTIFR_OVERFIS USBHS_DEVEPTIFR_OVERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_OVERFIS_Msk instead */ 1676 #define USBHS_DEVEPTIFR_SHORTPACKETS_Pos 7 /**< (USBHS_DEVEPTIFR) Short Packet Interrupt Set Position */ 1677 #define USBHS_DEVEPTIFR_SHORTPACKETS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_SHORTPACKETS_Pos) /**< (USBHS_DEVEPTIFR) Short Packet Interrupt Set Mask */ 1678 #define USBHS_DEVEPTIFR_SHORTPACKETS USBHS_DEVEPTIFR_SHORTPACKETS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_SHORTPACKETS_Msk instead */ 1679 #define USBHS_DEVEPTIFR_NBUSYBKS_Pos 12 /**< (USBHS_DEVEPTIFR) Number of Busy Banks Interrupt Set Position */ 1680 #define USBHS_DEVEPTIFR_NBUSYBKS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_NBUSYBKS_Pos) /**< (USBHS_DEVEPTIFR) Number of Busy Banks Interrupt Set Mask */ 1681 #define USBHS_DEVEPTIFR_NBUSYBKS USBHS_DEVEPTIFR_NBUSYBKS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_NBUSYBKS_Msk instead */ 1682 #define USBHS_DEVEPTIFR_MASK _U_(0x10A3) /**< \deprecated (USBHS_DEVEPTIFR) Register MASK (Use USBHS_DEVEPTIFR_Msk instead) */ 1683 #define USBHS_DEVEPTIFR_Msk _U_(0x10A3) /**< (USBHS_DEVEPTIFR) Register Mask */ 1684 1685 /* CTRL mode */ 1686 #define USBHS_DEVEPTIFR_CTRL_RXSTPIS_Pos 2 /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ 1687 #define USBHS_DEVEPTIFR_CTRL_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ 1688 #define USBHS_DEVEPTIFR_CTRL_RXSTPIS USBHS_DEVEPTIFR_CTRL_RXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_CTRL_RXSTPIS_Msk instead */ 1689 #define USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Pos 3 /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ 1690 #define USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ 1691 #define USBHS_DEVEPTIFR_CTRL_NAKOUTIS USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_CTRL_NAKOUTIS_Msk instead */ 1692 #define USBHS_DEVEPTIFR_CTRL_NAKINIS_Pos 4 /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ 1693 #define USBHS_DEVEPTIFR_CTRL_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ 1694 #define USBHS_DEVEPTIFR_CTRL_NAKINIS USBHS_DEVEPTIFR_CTRL_NAKINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_CTRL_NAKINIS_Msk instead */ 1695 #define USBHS_DEVEPTIFR_CTRL_STALLEDIS_Pos 6 /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ 1696 #define USBHS_DEVEPTIFR_CTRL_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_CTRL_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ 1697 #define USBHS_DEVEPTIFR_CTRL_STALLEDIS USBHS_DEVEPTIFR_CTRL_STALLEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_CTRL_STALLEDIS_Msk instead */ 1698 #define USBHS_DEVEPTIFR_CTRL_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTIFR_CTRL) Register MASK (Use USBHS_DEVEPTIFR_CTRL_Msk instead) */ 1699 #define USBHS_DEVEPTIFR_CTRL_Msk _U_(0x5C) /**< (USBHS_DEVEPTIFR_CTRL) Register Mask */ 1700 1701 /* ISO mode */ 1702 #define USBHS_DEVEPTIFR_ISO_UNDERFIS_Pos 2 /**< (USBHS_DEVEPTIFR) Underflow Interrupt Set Position */ 1703 #define USBHS_DEVEPTIFR_ISO_UNDERFIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_UNDERFIS_Pos) /**< (USBHS_DEVEPTIFR) Underflow Interrupt Set Mask */ 1704 #define USBHS_DEVEPTIFR_ISO_UNDERFIS USBHS_DEVEPTIFR_ISO_UNDERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_ISO_UNDERFIS_Msk instead */ 1705 #define USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Pos 3 /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Position */ 1706 #define USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Pos) /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Underflow Error Interrupt Set Mask */ 1707 #define USBHS_DEVEPTIFR_ISO_HBISOINERRIS USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_ISO_HBISOINERRIS_Msk instead */ 1708 #define USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Pos 4 /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Position */ 1709 #define USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Pos) /**< (USBHS_DEVEPTIFR) High Bandwidth Isochronous IN Flush Interrupt Set Mask */ 1710 #define USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_ISO_HBISOFLUSHIS_Msk instead */ 1711 #define USBHS_DEVEPTIFR_ISO_CRCERRIS_Pos 6 /**< (USBHS_DEVEPTIFR) CRC Error Interrupt Set Position */ 1712 #define USBHS_DEVEPTIFR_ISO_CRCERRIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_ISO_CRCERRIS_Pos) /**< (USBHS_DEVEPTIFR) CRC Error Interrupt Set Mask */ 1713 #define USBHS_DEVEPTIFR_ISO_CRCERRIS USBHS_DEVEPTIFR_ISO_CRCERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_ISO_CRCERRIS_Msk instead */ 1714 #define USBHS_DEVEPTIFR_ISO_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTIFR_ISO) Register MASK (Use USBHS_DEVEPTIFR_ISO_Msk instead) */ 1715 #define USBHS_DEVEPTIFR_ISO_Msk _U_(0x5C) /**< (USBHS_DEVEPTIFR_ISO) Register Mask */ 1716 1717 /* BLK mode */ 1718 #define USBHS_DEVEPTIFR_BLK_RXSTPIS_Pos 2 /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ 1719 #define USBHS_DEVEPTIFR_BLK_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ 1720 #define USBHS_DEVEPTIFR_BLK_RXSTPIS USBHS_DEVEPTIFR_BLK_RXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_BLK_RXSTPIS_Msk instead */ 1721 #define USBHS_DEVEPTIFR_BLK_NAKOUTIS_Pos 3 /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ 1722 #define USBHS_DEVEPTIFR_BLK_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ 1723 #define USBHS_DEVEPTIFR_BLK_NAKOUTIS USBHS_DEVEPTIFR_BLK_NAKOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_BLK_NAKOUTIS_Msk instead */ 1724 #define USBHS_DEVEPTIFR_BLK_NAKINIS_Pos 4 /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ 1725 #define USBHS_DEVEPTIFR_BLK_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ 1726 #define USBHS_DEVEPTIFR_BLK_NAKINIS USBHS_DEVEPTIFR_BLK_NAKINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_BLK_NAKINIS_Msk instead */ 1727 #define USBHS_DEVEPTIFR_BLK_STALLEDIS_Pos 6 /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ 1728 #define USBHS_DEVEPTIFR_BLK_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_BLK_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ 1729 #define USBHS_DEVEPTIFR_BLK_STALLEDIS USBHS_DEVEPTIFR_BLK_STALLEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_BLK_STALLEDIS_Msk instead */ 1730 #define USBHS_DEVEPTIFR_BLK_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTIFR_BLK) Register MASK (Use USBHS_DEVEPTIFR_BLK_Msk instead) */ 1731 #define USBHS_DEVEPTIFR_BLK_Msk _U_(0x5C) /**< (USBHS_DEVEPTIFR_BLK) Register Mask */ 1732 1733 /* INTRPT mode */ 1734 #define USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Pos 2 /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Position */ 1735 #define USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Pos) /**< (USBHS_DEVEPTIFR) Received SETUP Interrupt Set Mask */ 1736 #define USBHS_DEVEPTIFR_INTRPT_RXSTPIS USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_INTRPT_RXSTPIS_Msk instead */ 1737 #define USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Pos 3 /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Position */ 1738 #define USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed OUT Interrupt Set Mask */ 1739 #define USBHS_DEVEPTIFR_INTRPT_NAKOUTIS USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_INTRPT_NAKOUTIS_Msk instead */ 1740 #define USBHS_DEVEPTIFR_INTRPT_NAKINIS_Pos 4 /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Position */ 1741 #define USBHS_DEVEPTIFR_INTRPT_NAKINIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_NAKINIS_Pos) /**< (USBHS_DEVEPTIFR) NAKed IN Interrupt Set Mask */ 1742 #define USBHS_DEVEPTIFR_INTRPT_NAKINIS USBHS_DEVEPTIFR_INTRPT_NAKINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_INTRPT_NAKINIS_Msk instead */ 1743 #define USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Pos 6 /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Position */ 1744 #define USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Msk (_U_(0x1) << USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Pos) /**< (USBHS_DEVEPTIFR) STALLed Interrupt Set Mask */ 1745 #define USBHS_DEVEPTIFR_INTRPT_STALLEDIS USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIFR_INTRPT_STALLEDIS_Msk instead */ 1746 #define USBHS_DEVEPTIFR_INTRPT_MASK _U_(0x5C) /**< \deprecated (USBHS_DEVEPTIFR_INTRPT) Register MASK (Use USBHS_DEVEPTIFR_INTRPT_Msk instead) */ 1747 #define USBHS_DEVEPTIFR_INTRPT_Msk _U_(0x5C) /**< (USBHS_DEVEPTIFR_INTRPT) Register Mask */ 1748 1749 1750 /* -------- USBHS_DEVEPTIMR : (USBHS Offset: 0x1c0) (R/ 32) Device Endpoint Interrupt Mask Register -------- */ 1751 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1752 #if COMPONENT_TYPEDEF_STYLE == 'N' 1753 typedef union { 1754 struct { 1755 uint32_t TXINE:1; /**< bit: 0 Transmitted IN Data Interrupt */ 1756 uint32_t RXOUTE:1; /**< bit: 1 Received OUT Data Interrupt */ 1757 uint32_t :3; /**< bit: 2..4 Reserved */ 1758 uint32_t OVERFE:1; /**< bit: 5 Overflow Interrupt */ 1759 uint32_t :1; /**< bit: 6 Reserved */ 1760 uint32_t SHORTPACKETE:1; /**< bit: 7 Short Packet Interrupt */ 1761 uint32_t :4; /**< bit: 8..11 Reserved */ 1762 uint32_t NBUSYBKE:1; /**< bit: 12 Number of Busy Banks Interrupt */ 1763 uint32_t KILLBK:1; /**< bit: 13 Kill IN Bank */ 1764 uint32_t FIFOCON:1; /**< bit: 14 FIFO Control */ 1765 uint32_t :1; /**< bit: 15 Reserved */ 1766 uint32_t EPDISHDMA:1; /**< bit: 16 Endpoint Interrupts Disable HDMA Request */ 1767 uint32_t :1; /**< bit: 17 Reserved */ 1768 uint32_t RSTDT:1; /**< bit: 18 Reset Data Toggle */ 1769 uint32_t :13; /**< bit: 19..31 Reserved */ 1770 } bit; /**< Structure used for bit access */ 1771 struct { // CTRL mode 1772 uint32_t :2; /**< bit: 0..1 Reserved */ 1773 uint32_t RXSTPE:1; /**< bit: 2 Received SETUP Interrupt */ 1774 uint32_t NAKOUTE:1; /**< bit: 3 NAKed OUT Interrupt */ 1775 uint32_t NAKINE:1; /**< bit: 4 NAKed IN Interrupt */ 1776 uint32_t :1; /**< bit: 5 Reserved */ 1777 uint32_t STALLEDE:1; /**< bit: 6 STALLed Interrupt */ 1778 uint32_t :10; /**< bit: 7..16 Reserved */ 1779 uint32_t NYETDIS:1; /**< bit: 17 NYET Token Disable */ 1780 uint32_t :1; /**< bit: 18 Reserved */ 1781 uint32_t STALLRQ:1; /**< bit: 19 STALL Request */ 1782 uint32_t :12; /**< bit: 20..31 Reserved */ 1783 } CTRL; /**< Structure used for CTRL mode access */ 1784 struct { // ISO mode 1785 uint32_t :2; /**< bit: 0..1 Reserved */ 1786 uint32_t UNDERFE:1; /**< bit: 2 Underflow Interrupt */ 1787 uint32_t HBISOINERRE:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt */ 1788 uint32_t HBISOFLUSHE:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt */ 1789 uint32_t :1; /**< bit: 5 Reserved */ 1790 uint32_t CRCERRE:1; /**< bit: 6 CRC Error Interrupt */ 1791 uint32_t :1; /**< bit: 7 Reserved */ 1792 uint32_t MDATAE:1; /**< bit: 8 MData Interrupt */ 1793 uint32_t DATAXE:1; /**< bit: 9 DataX Interrupt */ 1794 uint32_t ERRORTRANSE:1; /**< bit: 10 Transaction Error Interrupt */ 1795 uint32_t :21; /**< bit: 11..31 Reserved */ 1796 } ISO; /**< Structure used for ISO mode access */ 1797 struct { // BLK mode 1798 uint32_t :2; /**< bit: 0..1 Reserved */ 1799 uint32_t RXSTPE:1; /**< bit: 2 Received SETUP Interrupt */ 1800 uint32_t NAKOUTE:1; /**< bit: 3 NAKed OUT Interrupt */ 1801 uint32_t NAKINE:1; /**< bit: 4 NAKed IN Interrupt */ 1802 uint32_t :1; /**< bit: 5 Reserved */ 1803 uint32_t STALLEDE:1; /**< bit: 6 STALLed Interrupt */ 1804 uint32_t :10; /**< bit: 7..16 Reserved */ 1805 uint32_t NYETDIS:1; /**< bit: 17 NYET Token Disable */ 1806 uint32_t :1; /**< bit: 18 Reserved */ 1807 uint32_t STALLRQ:1; /**< bit: 19 STALL Request */ 1808 uint32_t :12; /**< bit: 20..31 Reserved */ 1809 } BLK; /**< Structure used for BLK mode access */ 1810 struct { // INTRPT mode 1811 uint32_t :2; /**< bit: 0..1 Reserved */ 1812 uint32_t RXSTPE:1; /**< bit: 2 Received SETUP Interrupt */ 1813 uint32_t NAKOUTE:1; /**< bit: 3 NAKed OUT Interrupt */ 1814 uint32_t NAKINE:1; /**< bit: 4 NAKed IN Interrupt */ 1815 uint32_t :1; /**< bit: 5 Reserved */ 1816 uint32_t STALLEDE:1; /**< bit: 6 STALLed Interrupt */ 1817 uint32_t :10; /**< bit: 7..16 Reserved */ 1818 uint32_t NYETDIS:1; /**< bit: 17 NYET Token Disable */ 1819 uint32_t :1; /**< bit: 18 Reserved */ 1820 uint32_t STALLRQ:1; /**< bit: 19 STALL Request */ 1821 uint32_t :12; /**< bit: 20..31 Reserved */ 1822 } INTRPT; /**< Structure used for INTRPT mode access */ 1823 uint32_t reg; /**< Type used for register access */ 1824 } USBHS_DEVEPTIMR_Type; 1825 #endif 1826 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1827 1828 #define USBHS_DEVEPTIMR_OFFSET (0x1C0) /**< (USBHS_DEVEPTIMR) Device Endpoint Interrupt Mask Register Offset */ 1829 1830 #define USBHS_DEVEPTIMR_TXINE_Pos 0 /**< (USBHS_DEVEPTIMR) Transmitted IN Data Interrupt Position */ 1831 #define USBHS_DEVEPTIMR_TXINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_TXINE_Pos) /**< (USBHS_DEVEPTIMR) Transmitted IN Data Interrupt Mask */ 1832 #define USBHS_DEVEPTIMR_TXINE USBHS_DEVEPTIMR_TXINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_TXINE_Msk instead */ 1833 #define USBHS_DEVEPTIMR_RXOUTE_Pos 1 /**< (USBHS_DEVEPTIMR) Received OUT Data Interrupt Position */ 1834 #define USBHS_DEVEPTIMR_RXOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_RXOUTE_Pos) /**< (USBHS_DEVEPTIMR) Received OUT Data Interrupt Mask */ 1835 #define USBHS_DEVEPTIMR_RXOUTE USBHS_DEVEPTIMR_RXOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_RXOUTE_Msk instead */ 1836 #define USBHS_DEVEPTIMR_OVERFE_Pos 5 /**< (USBHS_DEVEPTIMR) Overflow Interrupt Position */ 1837 #define USBHS_DEVEPTIMR_OVERFE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_OVERFE_Pos) /**< (USBHS_DEVEPTIMR) Overflow Interrupt Mask */ 1838 #define USBHS_DEVEPTIMR_OVERFE USBHS_DEVEPTIMR_OVERFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_OVERFE_Msk instead */ 1839 #define USBHS_DEVEPTIMR_SHORTPACKETE_Pos 7 /**< (USBHS_DEVEPTIMR) Short Packet Interrupt Position */ 1840 #define USBHS_DEVEPTIMR_SHORTPACKETE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_SHORTPACKETE_Pos) /**< (USBHS_DEVEPTIMR) Short Packet Interrupt Mask */ 1841 #define USBHS_DEVEPTIMR_SHORTPACKETE USBHS_DEVEPTIMR_SHORTPACKETE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_SHORTPACKETE_Msk instead */ 1842 #define USBHS_DEVEPTIMR_NBUSYBKE_Pos 12 /**< (USBHS_DEVEPTIMR) Number of Busy Banks Interrupt Position */ 1843 #define USBHS_DEVEPTIMR_NBUSYBKE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_NBUSYBKE_Pos) /**< (USBHS_DEVEPTIMR) Number of Busy Banks Interrupt Mask */ 1844 #define USBHS_DEVEPTIMR_NBUSYBKE USBHS_DEVEPTIMR_NBUSYBKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_NBUSYBKE_Msk instead */ 1845 #define USBHS_DEVEPTIMR_KILLBK_Pos 13 /**< (USBHS_DEVEPTIMR) Kill IN Bank Position */ 1846 #define USBHS_DEVEPTIMR_KILLBK_Msk (_U_(0x1) << USBHS_DEVEPTIMR_KILLBK_Pos) /**< (USBHS_DEVEPTIMR) Kill IN Bank Mask */ 1847 #define USBHS_DEVEPTIMR_KILLBK USBHS_DEVEPTIMR_KILLBK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_KILLBK_Msk instead */ 1848 #define USBHS_DEVEPTIMR_FIFOCON_Pos 14 /**< (USBHS_DEVEPTIMR) FIFO Control Position */ 1849 #define USBHS_DEVEPTIMR_FIFOCON_Msk (_U_(0x1) << USBHS_DEVEPTIMR_FIFOCON_Pos) /**< (USBHS_DEVEPTIMR) FIFO Control Mask */ 1850 #define USBHS_DEVEPTIMR_FIFOCON USBHS_DEVEPTIMR_FIFOCON_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_FIFOCON_Msk instead */ 1851 #define USBHS_DEVEPTIMR_EPDISHDMA_Pos 16 /**< (USBHS_DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Position */ 1852 #define USBHS_DEVEPTIMR_EPDISHDMA_Msk (_U_(0x1) << USBHS_DEVEPTIMR_EPDISHDMA_Pos) /**< (USBHS_DEVEPTIMR) Endpoint Interrupts Disable HDMA Request Mask */ 1853 #define USBHS_DEVEPTIMR_EPDISHDMA USBHS_DEVEPTIMR_EPDISHDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_EPDISHDMA_Msk instead */ 1854 #define USBHS_DEVEPTIMR_RSTDT_Pos 18 /**< (USBHS_DEVEPTIMR) Reset Data Toggle Position */ 1855 #define USBHS_DEVEPTIMR_RSTDT_Msk (_U_(0x1) << USBHS_DEVEPTIMR_RSTDT_Pos) /**< (USBHS_DEVEPTIMR) Reset Data Toggle Mask */ 1856 #define USBHS_DEVEPTIMR_RSTDT USBHS_DEVEPTIMR_RSTDT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_RSTDT_Msk instead */ 1857 #define USBHS_DEVEPTIMR_MASK _U_(0x570A3) /**< \deprecated (USBHS_DEVEPTIMR) Register MASK (Use USBHS_DEVEPTIMR_Msk instead) */ 1858 #define USBHS_DEVEPTIMR_Msk _U_(0x570A3) /**< (USBHS_DEVEPTIMR) Register Mask */ 1859 1860 /* CTRL mode */ 1861 #define USBHS_DEVEPTIMR_CTRL_RXSTPE_Pos 2 /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ 1862 #define USBHS_DEVEPTIMR_CTRL_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ 1863 #define USBHS_DEVEPTIMR_CTRL_RXSTPE USBHS_DEVEPTIMR_CTRL_RXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_RXSTPE_Msk instead */ 1864 #define USBHS_DEVEPTIMR_CTRL_NAKOUTE_Pos 3 /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ 1865 #define USBHS_DEVEPTIMR_CTRL_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ 1866 #define USBHS_DEVEPTIMR_CTRL_NAKOUTE USBHS_DEVEPTIMR_CTRL_NAKOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_NAKOUTE_Msk instead */ 1867 #define USBHS_DEVEPTIMR_CTRL_NAKINE_Pos 4 /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ 1868 #define USBHS_DEVEPTIMR_CTRL_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ 1869 #define USBHS_DEVEPTIMR_CTRL_NAKINE USBHS_DEVEPTIMR_CTRL_NAKINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_NAKINE_Msk instead */ 1870 #define USBHS_DEVEPTIMR_CTRL_STALLEDE_Pos 6 /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ 1871 #define USBHS_DEVEPTIMR_CTRL_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ 1872 #define USBHS_DEVEPTIMR_CTRL_STALLEDE USBHS_DEVEPTIMR_CTRL_STALLEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_STALLEDE_Msk instead */ 1873 #define USBHS_DEVEPTIMR_CTRL_NYETDIS_Pos 17 /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ 1874 #define USBHS_DEVEPTIMR_CTRL_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ 1875 #define USBHS_DEVEPTIMR_CTRL_NYETDIS USBHS_DEVEPTIMR_CTRL_NYETDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_NYETDIS_Msk instead */ 1876 #define USBHS_DEVEPTIMR_CTRL_STALLRQ_Pos 19 /**< (USBHS_DEVEPTIMR) STALL Request Position */ 1877 #define USBHS_DEVEPTIMR_CTRL_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_CTRL_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ 1878 #define USBHS_DEVEPTIMR_CTRL_STALLRQ USBHS_DEVEPTIMR_CTRL_STALLRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_CTRL_STALLRQ_Msk instead */ 1879 #define USBHS_DEVEPTIMR_CTRL_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIMR_CTRL) Register MASK (Use USBHS_DEVEPTIMR_CTRL_Msk instead) */ 1880 #define USBHS_DEVEPTIMR_CTRL_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIMR_CTRL) Register Mask */ 1881 1882 /* ISO mode */ 1883 #define USBHS_DEVEPTIMR_ISO_UNDERFE_Pos 2 /**< (USBHS_DEVEPTIMR) Underflow Interrupt Position */ 1884 #define USBHS_DEVEPTIMR_ISO_UNDERFE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_UNDERFE_Pos) /**< (USBHS_DEVEPTIMR) Underflow Interrupt Mask */ 1885 #define USBHS_DEVEPTIMR_ISO_UNDERFE USBHS_DEVEPTIMR_ISO_UNDERFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_UNDERFE_Msk instead */ 1886 #define USBHS_DEVEPTIMR_ISO_HBISOINERRE_Pos 3 /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Position */ 1887 #define USBHS_DEVEPTIMR_ISO_HBISOINERRE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_HBISOINERRE_Pos) /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Underflow Error Interrupt Mask */ 1888 #define USBHS_DEVEPTIMR_ISO_HBISOINERRE USBHS_DEVEPTIMR_ISO_HBISOINERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_HBISOINERRE_Msk instead */ 1889 #define USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Pos 4 /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Position */ 1890 #define USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Pos) /**< (USBHS_DEVEPTIMR) High Bandwidth Isochronous IN Flush Interrupt Mask */ 1891 #define USBHS_DEVEPTIMR_ISO_HBISOFLUSHE USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_HBISOFLUSHE_Msk instead */ 1892 #define USBHS_DEVEPTIMR_ISO_CRCERRE_Pos 6 /**< (USBHS_DEVEPTIMR) CRC Error Interrupt Position */ 1893 #define USBHS_DEVEPTIMR_ISO_CRCERRE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_CRCERRE_Pos) /**< (USBHS_DEVEPTIMR) CRC Error Interrupt Mask */ 1894 #define USBHS_DEVEPTIMR_ISO_CRCERRE USBHS_DEVEPTIMR_ISO_CRCERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_CRCERRE_Msk instead */ 1895 #define USBHS_DEVEPTIMR_ISO_MDATAE_Pos 8 /**< (USBHS_DEVEPTIMR) MData Interrupt Position */ 1896 #define USBHS_DEVEPTIMR_ISO_MDATAE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_MDATAE_Pos) /**< (USBHS_DEVEPTIMR) MData Interrupt Mask */ 1897 #define USBHS_DEVEPTIMR_ISO_MDATAE USBHS_DEVEPTIMR_ISO_MDATAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_MDATAE_Msk instead */ 1898 #define USBHS_DEVEPTIMR_ISO_DATAXE_Pos 9 /**< (USBHS_DEVEPTIMR) DataX Interrupt Position */ 1899 #define USBHS_DEVEPTIMR_ISO_DATAXE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_DATAXE_Pos) /**< (USBHS_DEVEPTIMR) DataX Interrupt Mask */ 1900 #define USBHS_DEVEPTIMR_ISO_DATAXE USBHS_DEVEPTIMR_ISO_DATAXE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_DATAXE_Msk instead */ 1901 #define USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Pos 10 /**< (USBHS_DEVEPTIMR) Transaction Error Interrupt Position */ 1902 #define USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Pos) /**< (USBHS_DEVEPTIMR) Transaction Error Interrupt Mask */ 1903 #define USBHS_DEVEPTIMR_ISO_ERRORTRANSE USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_ISO_ERRORTRANSE_Msk instead */ 1904 #define USBHS_DEVEPTIMR_ISO_MASK _U_(0x75C) /**< \deprecated (USBHS_DEVEPTIMR_ISO) Register MASK (Use USBHS_DEVEPTIMR_ISO_Msk instead) */ 1905 #define USBHS_DEVEPTIMR_ISO_Msk _U_(0x75C) /**< (USBHS_DEVEPTIMR_ISO) Register Mask */ 1906 1907 /* BLK mode */ 1908 #define USBHS_DEVEPTIMR_BLK_RXSTPE_Pos 2 /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ 1909 #define USBHS_DEVEPTIMR_BLK_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ 1910 #define USBHS_DEVEPTIMR_BLK_RXSTPE USBHS_DEVEPTIMR_BLK_RXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_RXSTPE_Msk instead */ 1911 #define USBHS_DEVEPTIMR_BLK_NAKOUTE_Pos 3 /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ 1912 #define USBHS_DEVEPTIMR_BLK_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ 1913 #define USBHS_DEVEPTIMR_BLK_NAKOUTE USBHS_DEVEPTIMR_BLK_NAKOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_NAKOUTE_Msk instead */ 1914 #define USBHS_DEVEPTIMR_BLK_NAKINE_Pos 4 /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ 1915 #define USBHS_DEVEPTIMR_BLK_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ 1916 #define USBHS_DEVEPTIMR_BLK_NAKINE USBHS_DEVEPTIMR_BLK_NAKINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_NAKINE_Msk instead */ 1917 #define USBHS_DEVEPTIMR_BLK_STALLEDE_Pos 6 /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ 1918 #define USBHS_DEVEPTIMR_BLK_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ 1919 #define USBHS_DEVEPTIMR_BLK_STALLEDE USBHS_DEVEPTIMR_BLK_STALLEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_STALLEDE_Msk instead */ 1920 #define USBHS_DEVEPTIMR_BLK_NYETDIS_Pos 17 /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ 1921 #define USBHS_DEVEPTIMR_BLK_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ 1922 #define USBHS_DEVEPTIMR_BLK_NYETDIS USBHS_DEVEPTIMR_BLK_NYETDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_NYETDIS_Msk instead */ 1923 #define USBHS_DEVEPTIMR_BLK_STALLRQ_Pos 19 /**< (USBHS_DEVEPTIMR) STALL Request Position */ 1924 #define USBHS_DEVEPTIMR_BLK_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_BLK_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ 1925 #define USBHS_DEVEPTIMR_BLK_STALLRQ USBHS_DEVEPTIMR_BLK_STALLRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_BLK_STALLRQ_Msk instead */ 1926 #define USBHS_DEVEPTIMR_BLK_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIMR_BLK) Register MASK (Use USBHS_DEVEPTIMR_BLK_Msk instead) */ 1927 #define USBHS_DEVEPTIMR_BLK_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIMR_BLK) Register Mask */ 1928 1929 /* INTRPT mode */ 1930 #define USBHS_DEVEPTIMR_INTRPT_RXSTPE_Pos 2 /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Position */ 1931 #define USBHS_DEVEPTIMR_INTRPT_RXSTPE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_RXSTPE_Pos) /**< (USBHS_DEVEPTIMR) Received SETUP Interrupt Mask */ 1932 #define USBHS_DEVEPTIMR_INTRPT_RXSTPE USBHS_DEVEPTIMR_INTRPT_RXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_RXSTPE_Msk instead */ 1933 #define USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Pos 3 /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Position */ 1934 #define USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Pos) /**< (USBHS_DEVEPTIMR) NAKed OUT Interrupt Mask */ 1935 #define USBHS_DEVEPTIMR_INTRPT_NAKOUTE USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_NAKOUTE_Msk instead */ 1936 #define USBHS_DEVEPTIMR_INTRPT_NAKINE_Pos 4 /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Position */ 1937 #define USBHS_DEVEPTIMR_INTRPT_NAKINE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_NAKINE_Pos) /**< (USBHS_DEVEPTIMR) NAKed IN Interrupt Mask */ 1938 #define USBHS_DEVEPTIMR_INTRPT_NAKINE USBHS_DEVEPTIMR_INTRPT_NAKINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_NAKINE_Msk instead */ 1939 #define USBHS_DEVEPTIMR_INTRPT_STALLEDE_Pos 6 /**< (USBHS_DEVEPTIMR) STALLed Interrupt Position */ 1940 #define USBHS_DEVEPTIMR_INTRPT_STALLEDE_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_STALLEDE_Pos) /**< (USBHS_DEVEPTIMR) STALLed Interrupt Mask */ 1941 #define USBHS_DEVEPTIMR_INTRPT_STALLEDE USBHS_DEVEPTIMR_INTRPT_STALLEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_STALLEDE_Msk instead */ 1942 #define USBHS_DEVEPTIMR_INTRPT_NYETDIS_Pos 17 /**< (USBHS_DEVEPTIMR) NYET Token Disable Position */ 1943 #define USBHS_DEVEPTIMR_INTRPT_NYETDIS_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_NYETDIS_Pos) /**< (USBHS_DEVEPTIMR) NYET Token Disable Mask */ 1944 #define USBHS_DEVEPTIMR_INTRPT_NYETDIS USBHS_DEVEPTIMR_INTRPT_NYETDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_NYETDIS_Msk instead */ 1945 #define USBHS_DEVEPTIMR_INTRPT_STALLRQ_Pos 19 /**< (USBHS_DEVEPTIMR) STALL Request Position */ 1946 #define USBHS_DEVEPTIMR_INTRPT_STALLRQ_Msk (_U_(0x1) << USBHS_DEVEPTIMR_INTRPT_STALLRQ_Pos) /**< (USBHS_DEVEPTIMR) STALL Request Mask */ 1947 #define USBHS_DEVEPTIMR_INTRPT_STALLRQ USBHS_DEVEPTIMR_INTRPT_STALLRQ_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIMR_INTRPT_STALLRQ_Msk instead */ 1948 #define USBHS_DEVEPTIMR_INTRPT_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIMR_INTRPT) Register MASK (Use USBHS_DEVEPTIMR_INTRPT_Msk instead) */ 1949 #define USBHS_DEVEPTIMR_INTRPT_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIMR_INTRPT) Register Mask */ 1950 1951 1952 /* -------- USBHS_DEVEPTIER : (USBHS Offset: 0x1f0) (/W 32) Device Endpoint Interrupt Enable Register -------- */ 1953 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1954 #if COMPONENT_TYPEDEF_STYLE == 'N' 1955 typedef union { 1956 struct { 1957 uint32_t TXINES:1; /**< bit: 0 Transmitted IN Data Interrupt Enable */ 1958 uint32_t RXOUTES:1; /**< bit: 1 Received OUT Data Interrupt Enable */ 1959 uint32_t :3; /**< bit: 2..4 Reserved */ 1960 uint32_t OVERFES:1; /**< bit: 5 Overflow Interrupt Enable */ 1961 uint32_t :1; /**< bit: 6 Reserved */ 1962 uint32_t SHORTPACKETES:1; /**< bit: 7 Short Packet Interrupt Enable */ 1963 uint32_t :4; /**< bit: 8..11 Reserved */ 1964 uint32_t NBUSYBKES:1; /**< bit: 12 Number of Busy Banks Interrupt Enable */ 1965 uint32_t KILLBKS:1; /**< bit: 13 Kill IN Bank */ 1966 uint32_t FIFOCONS:1; /**< bit: 14 FIFO Control */ 1967 uint32_t :1; /**< bit: 15 Reserved */ 1968 uint32_t EPDISHDMAS:1; /**< bit: 16 Endpoint Interrupts Disable HDMA Request Enable */ 1969 uint32_t :1; /**< bit: 17 Reserved */ 1970 uint32_t RSTDTS:1; /**< bit: 18 Reset Data Toggle Enable */ 1971 uint32_t :13; /**< bit: 19..31 Reserved */ 1972 } bit; /**< Structure used for bit access */ 1973 struct { // CTRL mode 1974 uint32_t :2; /**< bit: 0..1 Reserved */ 1975 uint32_t RXSTPES:1; /**< bit: 2 Received SETUP Interrupt Enable */ 1976 uint32_t NAKOUTES:1; /**< bit: 3 NAKed OUT Interrupt Enable */ 1977 uint32_t NAKINES:1; /**< bit: 4 NAKed IN Interrupt Enable */ 1978 uint32_t :1; /**< bit: 5 Reserved */ 1979 uint32_t STALLEDES:1; /**< bit: 6 STALLed Interrupt Enable */ 1980 uint32_t :10; /**< bit: 7..16 Reserved */ 1981 uint32_t NYETDISS:1; /**< bit: 17 NYET Token Disable Enable */ 1982 uint32_t :1; /**< bit: 18 Reserved */ 1983 uint32_t STALLRQS:1; /**< bit: 19 STALL Request Enable */ 1984 uint32_t :12; /**< bit: 20..31 Reserved */ 1985 } CTRL; /**< Structure used for CTRL mode access */ 1986 struct { // ISO mode 1987 uint32_t :2; /**< bit: 0..1 Reserved */ 1988 uint32_t UNDERFES:1; /**< bit: 2 Underflow Interrupt Enable */ 1989 uint32_t HBISOINERRES:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt Enable */ 1990 uint32_t HBISOFLUSHES:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt Enable */ 1991 uint32_t :1; /**< bit: 5 Reserved */ 1992 uint32_t CRCERRES:1; /**< bit: 6 CRC Error Interrupt Enable */ 1993 uint32_t :1; /**< bit: 7 Reserved */ 1994 uint32_t MDATAES:1; /**< bit: 8 MData Interrupt Enable */ 1995 uint32_t DATAXES:1; /**< bit: 9 DataX Interrupt Enable */ 1996 uint32_t ERRORTRANSES:1; /**< bit: 10 Transaction Error Interrupt Enable */ 1997 uint32_t :21; /**< bit: 11..31 Reserved */ 1998 } ISO; /**< Structure used for ISO mode access */ 1999 struct { // BLK mode 2000 uint32_t :2; /**< bit: 0..1 Reserved */ 2001 uint32_t RXSTPES:1; /**< bit: 2 Received SETUP Interrupt Enable */ 2002 uint32_t NAKOUTES:1; /**< bit: 3 NAKed OUT Interrupt Enable */ 2003 uint32_t NAKINES:1; /**< bit: 4 NAKed IN Interrupt Enable */ 2004 uint32_t :1; /**< bit: 5 Reserved */ 2005 uint32_t STALLEDES:1; /**< bit: 6 STALLed Interrupt Enable */ 2006 uint32_t :10; /**< bit: 7..16 Reserved */ 2007 uint32_t NYETDISS:1; /**< bit: 17 NYET Token Disable Enable */ 2008 uint32_t :1; /**< bit: 18 Reserved */ 2009 uint32_t STALLRQS:1; /**< bit: 19 STALL Request Enable */ 2010 uint32_t :12; /**< bit: 20..31 Reserved */ 2011 } BLK; /**< Structure used for BLK mode access */ 2012 struct { // INTRPT mode 2013 uint32_t :2; /**< bit: 0..1 Reserved */ 2014 uint32_t RXSTPES:1; /**< bit: 2 Received SETUP Interrupt Enable */ 2015 uint32_t NAKOUTES:1; /**< bit: 3 NAKed OUT Interrupt Enable */ 2016 uint32_t NAKINES:1; /**< bit: 4 NAKed IN Interrupt Enable */ 2017 uint32_t :1; /**< bit: 5 Reserved */ 2018 uint32_t STALLEDES:1; /**< bit: 6 STALLed Interrupt Enable */ 2019 uint32_t :10; /**< bit: 7..16 Reserved */ 2020 uint32_t NYETDISS:1; /**< bit: 17 NYET Token Disable Enable */ 2021 uint32_t :1; /**< bit: 18 Reserved */ 2022 uint32_t STALLRQS:1; /**< bit: 19 STALL Request Enable */ 2023 uint32_t :12; /**< bit: 20..31 Reserved */ 2024 } INTRPT; /**< Structure used for INTRPT mode access */ 2025 uint32_t reg; /**< Type used for register access */ 2026 } USBHS_DEVEPTIER_Type; 2027 #endif 2028 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2029 2030 #define USBHS_DEVEPTIER_OFFSET (0x1F0) /**< (USBHS_DEVEPTIER) Device Endpoint Interrupt Enable Register Offset */ 2031 2032 #define USBHS_DEVEPTIER_TXINES_Pos 0 /**< (USBHS_DEVEPTIER) Transmitted IN Data Interrupt Enable Position */ 2033 #define USBHS_DEVEPTIER_TXINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_TXINES_Pos) /**< (USBHS_DEVEPTIER) Transmitted IN Data Interrupt Enable Mask */ 2034 #define USBHS_DEVEPTIER_TXINES USBHS_DEVEPTIER_TXINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_TXINES_Msk instead */ 2035 #define USBHS_DEVEPTIER_RXOUTES_Pos 1 /**< (USBHS_DEVEPTIER) Received OUT Data Interrupt Enable Position */ 2036 #define USBHS_DEVEPTIER_RXOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_RXOUTES_Pos) /**< (USBHS_DEVEPTIER) Received OUT Data Interrupt Enable Mask */ 2037 #define USBHS_DEVEPTIER_RXOUTES USBHS_DEVEPTIER_RXOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_RXOUTES_Msk instead */ 2038 #define USBHS_DEVEPTIER_OVERFES_Pos 5 /**< (USBHS_DEVEPTIER) Overflow Interrupt Enable Position */ 2039 #define USBHS_DEVEPTIER_OVERFES_Msk (_U_(0x1) << USBHS_DEVEPTIER_OVERFES_Pos) /**< (USBHS_DEVEPTIER) Overflow Interrupt Enable Mask */ 2040 #define USBHS_DEVEPTIER_OVERFES USBHS_DEVEPTIER_OVERFES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_OVERFES_Msk instead */ 2041 #define USBHS_DEVEPTIER_SHORTPACKETES_Pos 7 /**< (USBHS_DEVEPTIER) Short Packet Interrupt Enable Position */ 2042 #define USBHS_DEVEPTIER_SHORTPACKETES_Msk (_U_(0x1) << USBHS_DEVEPTIER_SHORTPACKETES_Pos) /**< (USBHS_DEVEPTIER) Short Packet Interrupt Enable Mask */ 2043 #define USBHS_DEVEPTIER_SHORTPACKETES USBHS_DEVEPTIER_SHORTPACKETES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_SHORTPACKETES_Msk instead */ 2044 #define USBHS_DEVEPTIER_NBUSYBKES_Pos 12 /**< (USBHS_DEVEPTIER) Number of Busy Banks Interrupt Enable Position */ 2045 #define USBHS_DEVEPTIER_NBUSYBKES_Msk (_U_(0x1) << USBHS_DEVEPTIER_NBUSYBKES_Pos) /**< (USBHS_DEVEPTIER) Number of Busy Banks Interrupt Enable Mask */ 2046 #define USBHS_DEVEPTIER_NBUSYBKES USBHS_DEVEPTIER_NBUSYBKES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_NBUSYBKES_Msk instead */ 2047 #define USBHS_DEVEPTIER_KILLBKS_Pos 13 /**< (USBHS_DEVEPTIER) Kill IN Bank Position */ 2048 #define USBHS_DEVEPTIER_KILLBKS_Msk (_U_(0x1) << USBHS_DEVEPTIER_KILLBKS_Pos) /**< (USBHS_DEVEPTIER) Kill IN Bank Mask */ 2049 #define USBHS_DEVEPTIER_KILLBKS USBHS_DEVEPTIER_KILLBKS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_KILLBKS_Msk instead */ 2050 #define USBHS_DEVEPTIER_FIFOCONS_Pos 14 /**< (USBHS_DEVEPTIER) FIFO Control Position */ 2051 #define USBHS_DEVEPTIER_FIFOCONS_Msk (_U_(0x1) << USBHS_DEVEPTIER_FIFOCONS_Pos) /**< (USBHS_DEVEPTIER) FIFO Control Mask */ 2052 #define USBHS_DEVEPTIER_FIFOCONS USBHS_DEVEPTIER_FIFOCONS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_FIFOCONS_Msk instead */ 2053 #define USBHS_DEVEPTIER_EPDISHDMAS_Pos 16 /**< (USBHS_DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Position */ 2054 #define USBHS_DEVEPTIER_EPDISHDMAS_Msk (_U_(0x1) << USBHS_DEVEPTIER_EPDISHDMAS_Pos) /**< (USBHS_DEVEPTIER) Endpoint Interrupts Disable HDMA Request Enable Mask */ 2055 #define USBHS_DEVEPTIER_EPDISHDMAS USBHS_DEVEPTIER_EPDISHDMAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_EPDISHDMAS_Msk instead */ 2056 #define USBHS_DEVEPTIER_RSTDTS_Pos 18 /**< (USBHS_DEVEPTIER) Reset Data Toggle Enable Position */ 2057 #define USBHS_DEVEPTIER_RSTDTS_Msk (_U_(0x1) << USBHS_DEVEPTIER_RSTDTS_Pos) /**< (USBHS_DEVEPTIER) Reset Data Toggle Enable Mask */ 2058 #define USBHS_DEVEPTIER_RSTDTS USBHS_DEVEPTIER_RSTDTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_RSTDTS_Msk instead */ 2059 #define USBHS_DEVEPTIER_MASK _U_(0x570A3) /**< \deprecated (USBHS_DEVEPTIER) Register MASK (Use USBHS_DEVEPTIER_Msk instead) */ 2060 #define USBHS_DEVEPTIER_Msk _U_(0x570A3) /**< (USBHS_DEVEPTIER) Register Mask */ 2061 2062 /* CTRL mode */ 2063 #define USBHS_DEVEPTIER_CTRL_RXSTPES_Pos 2 /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ 2064 #define USBHS_DEVEPTIER_CTRL_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ 2065 #define USBHS_DEVEPTIER_CTRL_RXSTPES USBHS_DEVEPTIER_CTRL_RXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_RXSTPES_Msk instead */ 2066 #define USBHS_DEVEPTIER_CTRL_NAKOUTES_Pos 3 /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ 2067 #define USBHS_DEVEPTIER_CTRL_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ 2068 #define USBHS_DEVEPTIER_CTRL_NAKOUTES USBHS_DEVEPTIER_CTRL_NAKOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_NAKOUTES_Msk instead */ 2069 #define USBHS_DEVEPTIER_CTRL_NAKINES_Pos 4 /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ 2070 #define USBHS_DEVEPTIER_CTRL_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ 2071 #define USBHS_DEVEPTIER_CTRL_NAKINES USBHS_DEVEPTIER_CTRL_NAKINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_NAKINES_Msk instead */ 2072 #define USBHS_DEVEPTIER_CTRL_STALLEDES_Pos 6 /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ 2073 #define USBHS_DEVEPTIER_CTRL_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ 2074 #define USBHS_DEVEPTIER_CTRL_STALLEDES USBHS_DEVEPTIER_CTRL_STALLEDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_STALLEDES_Msk instead */ 2075 #define USBHS_DEVEPTIER_CTRL_NYETDISS_Pos 17 /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ 2076 #define USBHS_DEVEPTIER_CTRL_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ 2077 #define USBHS_DEVEPTIER_CTRL_NYETDISS USBHS_DEVEPTIER_CTRL_NYETDISS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_NYETDISS_Msk instead */ 2078 #define USBHS_DEVEPTIER_CTRL_STALLRQS_Pos 19 /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ 2079 #define USBHS_DEVEPTIER_CTRL_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_CTRL_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ 2080 #define USBHS_DEVEPTIER_CTRL_STALLRQS USBHS_DEVEPTIER_CTRL_STALLRQS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_CTRL_STALLRQS_Msk instead */ 2081 #define USBHS_DEVEPTIER_CTRL_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIER_CTRL) Register MASK (Use USBHS_DEVEPTIER_CTRL_Msk instead) */ 2082 #define USBHS_DEVEPTIER_CTRL_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIER_CTRL) Register Mask */ 2083 2084 /* ISO mode */ 2085 #define USBHS_DEVEPTIER_ISO_UNDERFES_Pos 2 /**< (USBHS_DEVEPTIER) Underflow Interrupt Enable Position */ 2086 #define USBHS_DEVEPTIER_ISO_UNDERFES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_UNDERFES_Pos) /**< (USBHS_DEVEPTIER) Underflow Interrupt Enable Mask */ 2087 #define USBHS_DEVEPTIER_ISO_UNDERFES USBHS_DEVEPTIER_ISO_UNDERFES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_UNDERFES_Msk instead */ 2088 #define USBHS_DEVEPTIER_ISO_HBISOINERRES_Pos 3 /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Position */ 2089 #define USBHS_DEVEPTIER_ISO_HBISOINERRES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_HBISOINERRES_Pos) /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Underflow Error Interrupt Enable Mask */ 2090 #define USBHS_DEVEPTIER_ISO_HBISOINERRES USBHS_DEVEPTIER_ISO_HBISOINERRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_HBISOINERRES_Msk instead */ 2091 #define USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Pos 4 /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Position */ 2092 #define USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Pos) /**< (USBHS_DEVEPTIER) High Bandwidth Isochronous IN Flush Interrupt Enable Mask */ 2093 #define USBHS_DEVEPTIER_ISO_HBISOFLUSHES USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_HBISOFLUSHES_Msk instead */ 2094 #define USBHS_DEVEPTIER_ISO_CRCERRES_Pos 6 /**< (USBHS_DEVEPTIER) CRC Error Interrupt Enable Position */ 2095 #define USBHS_DEVEPTIER_ISO_CRCERRES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_CRCERRES_Pos) /**< (USBHS_DEVEPTIER) CRC Error Interrupt Enable Mask */ 2096 #define USBHS_DEVEPTIER_ISO_CRCERRES USBHS_DEVEPTIER_ISO_CRCERRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_CRCERRES_Msk instead */ 2097 #define USBHS_DEVEPTIER_ISO_MDATAES_Pos 8 /**< (USBHS_DEVEPTIER) MData Interrupt Enable Position */ 2098 #define USBHS_DEVEPTIER_ISO_MDATAES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_MDATAES_Pos) /**< (USBHS_DEVEPTIER) MData Interrupt Enable Mask */ 2099 #define USBHS_DEVEPTIER_ISO_MDATAES USBHS_DEVEPTIER_ISO_MDATAES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_MDATAES_Msk instead */ 2100 #define USBHS_DEVEPTIER_ISO_DATAXES_Pos 9 /**< (USBHS_DEVEPTIER) DataX Interrupt Enable Position */ 2101 #define USBHS_DEVEPTIER_ISO_DATAXES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_DATAXES_Pos) /**< (USBHS_DEVEPTIER) DataX Interrupt Enable Mask */ 2102 #define USBHS_DEVEPTIER_ISO_DATAXES USBHS_DEVEPTIER_ISO_DATAXES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_DATAXES_Msk instead */ 2103 #define USBHS_DEVEPTIER_ISO_ERRORTRANSES_Pos 10 /**< (USBHS_DEVEPTIER) Transaction Error Interrupt Enable Position */ 2104 #define USBHS_DEVEPTIER_ISO_ERRORTRANSES_Msk (_U_(0x1) << USBHS_DEVEPTIER_ISO_ERRORTRANSES_Pos) /**< (USBHS_DEVEPTIER) Transaction Error Interrupt Enable Mask */ 2105 #define USBHS_DEVEPTIER_ISO_ERRORTRANSES USBHS_DEVEPTIER_ISO_ERRORTRANSES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_ISO_ERRORTRANSES_Msk instead */ 2106 #define USBHS_DEVEPTIER_ISO_MASK _U_(0x75C) /**< \deprecated (USBHS_DEVEPTIER_ISO) Register MASK (Use USBHS_DEVEPTIER_ISO_Msk instead) */ 2107 #define USBHS_DEVEPTIER_ISO_Msk _U_(0x75C) /**< (USBHS_DEVEPTIER_ISO) Register Mask */ 2108 2109 /* BLK mode */ 2110 #define USBHS_DEVEPTIER_BLK_RXSTPES_Pos 2 /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ 2111 #define USBHS_DEVEPTIER_BLK_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ 2112 #define USBHS_DEVEPTIER_BLK_RXSTPES USBHS_DEVEPTIER_BLK_RXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_RXSTPES_Msk instead */ 2113 #define USBHS_DEVEPTIER_BLK_NAKOUTES_Pos 3 /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ 2114 #define USBHS_DEVEPTIER_BLK_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ 2115 #define USBHS_DEVEPTIER_BLK_NAKOUTES USBHS_DEVEPTIER_BLK_NAKOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_NAKOUTES_Msk instead */ 2116 #define USBHS_DEVEPTIER_BLK_NAKINES_Pos 4 /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ 2117 #define USBHS_DEVEPTIER_BLK_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ 2118 #define USBHS_DEVEPTIER_BLK_NAKINES USBHS_DEVEPTIER_BLK_NAKINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_NAKINES_Msk instead */ 2119 #define USBHS_DEVEPTIER_BLK_STALLEDES_Pos 6 /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ 2120 #define USBHS_DEVEPTIER_BLK_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ 2121 #define USBHS_DEVEPTIER_BLK_STALLEDES USBHS_DEVEPTIER_BLK_STALLEDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_STALLEDES_Msk instead */ 2122 #define USBHS_DEVEPTIER_BLK_NYETDISS_Pos 17 /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ 2123 #define USBHS_DEVEPTIER_BLK_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ 2124 #define USBHS_DEVEPTIER_BLK_NYETDISS USBHS_DEVEPTIER_BLK_NYETDISS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_NYETDISS_Msk instead */ 2125 #define USBHS_DEVEPTIER_BLK_STALLRQS_Pos 19 /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ 2126 #define USBHS_DEVEPTIER_BLK_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_BLK_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ 2127 #define USBHS_DEVEPTIER_BLK_STALLRQS USBHS_DEVEPTIER_BLK_STALLRQS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_BLK_STALLRQS_Msk instead */ 2128 #define USBHS_DEVEPTIER_BLK_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIER_BLK) Register MASK (Use USBHS_DEVEPTIER_BLK_Msk instead) */ 2129 #define USBHS_DEVEPTIER_BLK_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIER_BLK) Register Mask */ 2130 2131 /* INTRPT mode */ 2132 #define USBHS_DEVEPTIER_INTRPT_RXSTPES_Pos 2 /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Position */ 2133 #define USBHS_DEVEPTIER_INTRPT_RXSTPES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_RXSTPES_Pos) /**< (USBHS_DEVEPTIER) Received SETUP Interrupt Enable Mask */ 2134 #define USBHS_DEVEPTIER_INTRPT_RXSTPES USBHS_DEVEPTIER_INTRPT_RXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_RXSTPES_Msk instead */ 2135 #define USBHS_DEVEPTIER_INTRPT_NAKOUTES_Pos 3 /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Position */ 2136 #define USBHS_DEVEPTIER_INTRPT_NAKOUTES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_NAKOUTES_Pos) /**< (USBHS_DEVEPTIER) NAKed OUT Interrupt Enable Mask */ 2137 #define USBHS_DEVEPTIER_INTRPT_NAKOUTES USBHS_DEVEPTIER_INTRPT_NAKOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_NAKOUTES_Msk instead */ 2138 #define USBHS_DEVEPTIER_INTRPT_NAKINES_Pos 4 /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Position */ 2139 #define USBHS_DEVEPTIER_INTRPT_NAKINES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_NAKINES_Pos) /**< (USBHS_DEVEPTIER) NAKed IN Interrupt Enable Mask */ 2140 #define USBHS_DEVEPTIER_INTRPT_NAKINES USBHS_DEVEPTIER_INTRPT_NAKINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_NAKINES_Msk instead */ 2141 #define USBHS_DEVEPTIER_INTRPT_STALLEDES_Pos 6 /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Position */ 2142 #define USBHS_DEVEPTIER_INTRPT_STALLEDES_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_STALLEDES_Pos) /**< (USBHS_DEVEPTIER) STALLed Interrupt Enable Mask */ 2143 #define USBHS_DEVEPTIER_INTRPT_STALLEDES USBHS_DEVEPTIER_INTRPT_STALLEDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_STALLEDES_Msk instead */ 2144 #define USBHS_DEVEPTIER_INTRPT_NYETDISS_Pos 17 /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Position */ 2145 #define USBHS_DEVEPTIER_INTRPT_NYETDISS_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_NYETDISS_Pos) /**< (USBHS_DEVEPTIER) NYET Token Disable Enable Mask */ 2146 #define USBHS_DEVEPTIER_INTRPT_NYETDISS USBHS_DEVEPTIER_INTRPT_NYETDISS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_NYETDISS_Msk instead */ 2147 #define USBHS_DEVEPTIER_INTRPT_STALLRQS_Pos 19 /**< (USBHS_DEVEPTIER) STALL Request Enable Position */ 2148 #define USBHS_DEVEPTIER_INTRPT_STALLRQS_Msk (_U_(0x1) << USBHS_DEVEPTIER_INTRPT_STALLRQS_Pos) /**< (USBHS_DEVEPTIER) STALL Request Enable Mask */ 2149 #define USBHS_DEVEPTIER_INTRPT_STALLRQS USBHS_DEVEPTIER_INTRPT_STALLRQS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIER_INTRPT_STALLRQS_Msk instead */ 2150 #define USBHS_DEVEPTIER_INTRPT_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIER_INTRPT) Register MASK (Use USBHS_DEVEPTIER_INTRPT_Msk instead) */ 2151 #define USBHS_DEVEPTIER_INTRPT_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIER_INTRPT) Register Mask */ 2152 2153 2154 /* -------- USBHS_DEVEPTIDR : (USBHS Offset: 0x220) (/W 32) Device Endpoint Interrupt Disable Register -------- */ 2155 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2156 #if COMPONENT_TYPEDEF_STYLE == 'N' 2157 typedef union { 2158 struct { 2159 uint32_t TXINEC:1; /**< bit: 0 Transmitted IN Interrupt Clear */ 2160 uint32_t RXOUTEC:1; /**< bit: 1 Received OUT Data Interrupt Clear */ 2161 uint32_t :3; /**< bit: 2..4 Reserved */ 2162 uint32_t OVERFEC:1; /**< bit: 5 Overflow Interrupt Clear */ 2163 uint32_t :1; /**< bit: 6 Reserved */ 2164 uint32_t SHORTPACKETEC:1; /**< bit: 7 Shortpacket Interrupt Clear */ 2165 uint32_t :4; /**< bit: 8..11 Reserved */ 2166 uint32_t NBUSYBKEC:1; /**< bit: 12 Number of Busy Banks Interrupt Clear */ 2167 uint32_t :1; /**< bit: 13 Reserved */ 2168 uint32_t FIFOCONC:1; /**< bit: 14 FIFO Control Clear */ 2169 uint32_t :1; /**< bit: 15 Reserved */ 2170 uint32_t EPDISHDMAC:1; /**< bit: 16 Endpoint Interrupts Disable HDMA Request Clear */ 2171 uint32_t :15; /**< bit: 17..31 Reserved */ 2172 } bit; /**< Structure used for bit access */ 2173 struct { // CTRL mode 2174 uint32_t :2; /**< bit: 0..1 Reserved */ 2175 uint32_t RXSTPEC:1; /**< bit: 2 Received SETUP Interrupt Clear */ 2176 uint32_t NAKOUTEC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ 2177 uint32_t NAKINEC:1; /**< bit: 4 NAKed IN Interrupt Clear */ 2178 uint32_t :1; /**< bit: 5 Reserved */ 2179 uint32_t STALLEDEC:1; /**< bit: 6 STALLed Interrupt Clear */ 2180 uint32_t :10; /**< bit: 7..16 Reserved */ 2181 uint32_t NYETDISC:1; /**< bit: 17 NYET Token Disable Clear */ 2182 uint32_t :1; /**< bit: 18 Reserved */ 2183 uint32_t STALLRQC:1; /**< bit: 19 STALL Request Clear */ 2184 uint32_t :12; /**< bit: 20..31 Reserved */ 2185 } CTRL; /**< Structure used for CTRL mode access */ 2186 struct { // ISO mode 2187 uint32_t :2; /**< bit: 0..1 Reserved */ 2188 uint32_t UNDERFEC:1; /**< bit: 2 Underflow Interrupt Clear */ 2189 uint32_t HBISOINERREC:1; /**< bit: 3 High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ 2190 uint32_t HBISOFLUSHEC:1; /**< bit: 4 High Bandwidth Isochronous IN Flush Interrupt Clear */ 2191 uint32_t :3; /**< bit: 5..7 Reserved */ 2192 uint32_t MDATAEC:1; /**< bit: 8 MData Interrupt Clear */ 2193 uint32_t DATAXEC:1; /**< bit: 9 DataX Interrupt Clear */ 2194 uint32_t ERRORTRANSEC:1; /**< bit: 10 Transaction Error Interrupt Clear */ 2195 uint32_t :21; /**< bit: 11..31 Reserved */ 2196 } ISO; /**< Structure used for ISO mode access */ 2197 struct { // BLK mode 2198 uint32_t :2; /**< bit: 0..1 Reserved */ 2199 uint32_t RXSTPEC:1; /**< bit: 2 Received SETUP Interrupt Clear */ 2200 uint32_t NAKOUTEC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ 2201 uint32_t NAKINEC:1; /**< bit: 4 NAKed IN Interrupt Clear */ 2202 uint32_t :1; /**< bit: 5 Reserved */ 2203 uint32_t STALLEDEC:1; /**< bit: 6 STALLed Interrupt Clear */ 2204 uint32_t :10; /**< bit: 7..16 Reserved */ 2205 uint32_t NYETDISC:1; /**< bit: 17 NYET Token Disable Clear */ 2206 uint32_t :1; /**< bit: 18 Reserved */ 2207 uint32_t STALLRQC:1; /**< bit: 19 STALL Request Clear */ 2208 uint32_t :12; /**< bit: 20..31 Reserved */ 2209 } BLK; /**< Structure used for BLK mode access */ 2210 struct { // INTRPT mode 2211 uint32_t :2; /**< bit: 0..1 Reserved */ 2212 uint32_t RXSTPEC:1; /**< bit: 2 Received SETUP Interrupt Clear */ 2213 uint32_t NAKOUTEC:1; /**< bit: 3 NAKed OUT Interrupt Clear */ 2214 uint32_t NAKINEC:1; /**< bit: 4 NAKed IN Interrupt Clear */ 2215 uint32_t :1; /**< bit: 5 Reserved */ 2216 uint32_t STALLEDEC:1; /**< bit: 6 STALLed Interrupt Clear */ 2217 uint32_t :10; /**< bit: 7..16 Reserved */ 2218 uint32_t NYETDISC:1; /**< bit: 17 NYET Token Disable Clear */ 2219 uint32_t :1; /**< bit: 18 Reserved */ 2220 uint32_t STALLRQC:1; /**< bit: 19 STALL Request Clear */ 2221 uint32_t :12; /**< bit: 20..31 Reserved */ 2222 } INTRPT; /**< Structure used for INTRPT mode access */ 2223 uint32_t reg; /**< Type used for register access */ 2224 } USBHS_DEVEPTIDR_Type; 2225 #endif 2226 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2227 2228 #define USBHS_DEVEPTIDR_OFFSET (0x220) /**< (USBHS_DEVEPTIDR) Device Endpoint Interrupt Disable Register Offset */ 2229 2230 #define USBHS_DEVEPTIDR_TXINEC_Pos 0 /**< (USBHS_DEVEPTIDR) Transmitted IN Interrupt Clear Position */ 2231 #define USBHS_DEVEPTIDR_TXINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_TXINEC_Pos) /**< (USBHS_DEVEPTIDR) Transmitted IN Interrupt Clear Mask */ 2232 #define USBHS_DEVEPTIDR_TXINEC USBHS_DEVEPTIDR_TXINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_TXINEC_Msk instead */ 2233 #define USBHS_DEVEPTIDR_RXOUTEC_Pos 1 /**< (USBHS_DEVEPTIDR) Received OUT Data Interrupt Clear Position */ 2234 #define USBHS_DEVEPTIDR_RXOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_RXOUTEC_Pos) /**< (USBHS_DEVEPTIDR) Received OUT Data Interrupt Clear Mask */ 2235 #define USBHS_DEVEPTIDR_RXOUTEC USBHS_DEVEPTIDR_RXOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_RXOUTEC_Msk instead */ 2236 #define USBHS_DEVEPTIDR_OVERFEC_Pos 5 /**< (USBHS_DEVEPTIDR) Overflow Interrupt Clear Position */ 2237 #define USBHS_DEVEPTIDR_OVERFEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_OVERFEC_Pos) /**< (USBHS_DEVEPTIDR) Overflow Interrupt Clear Mask */ 2238 #define USBHS_DEVEPTIDR_OVERFEC USBHS_DEVEPTIDR_OVERFEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_OVERFEC_Msk instead */ 2239 #define USBHS_DEVEPTIDR_SHORTPACKETEC_Pos 7 /**< (USBHS_DEVEPTIDR) Shortpacket Interrupt Clear Position */ 2240 #define USBHS_DEVEPTIDR_SHORTPACKETEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_SHORTPACKETEC_Pos) /**< (USBHS_DEVEPTIDR) Shortpacket Interrupt Clear Mask */ 2241 #define USBHS_DEVEPTIDR_SHORTPACKETEC USBHS_DEVEPTIDR_SHORTPACKETEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_SHORTPACKETEC_Msk instead */ 2242 #define USBHS_DEVEPTIDR_NBUSYBKEC_Pos 12 /**< (USBHS_DEVEPTIDR) Number of Busy Banks Interrupt Clear Position */ 2243 #define USBHS_DEVEPTIDR_NBUSYBKEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_NBUSYBKEC_Pos) /**< (USBHS_DEVEPTIDR) Number of Busy Banks Interrupt Clear Mask */ 2244 #define USBHS_DEVEPTIDR_NBUSYBKEC USBHS_DEVEPTIDR_NBUSYBKEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_NBUSYBKEC_Msk instead */ 2245 #define USBHS_DEVEPTIDR_FIFOCONC_Pos 14 /**< (USBHS_DEVEPTIDR) FIFO Control Clear Position */ 2246 #define USBHS_DEVEPTIDR_FIFOCONC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_FIFOCONC_Pos) /**< (USBHS_DEVEPTIDR) FIFO Control Clear Mask */ 2247 #define USBHS_DEVEPTIDR_FIFOCONC USBHS_DEVEPTIDR_FIFOCONC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_FIFOCONC_Msk instead */ 2248 #define USBHS_DEVEPTIDR_EPDISHDMAC_Pos 16 /**< (USBHS_DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Position */ 2249 #define USBHS_DEVEPTIDR_EPDISHDMAC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_EPDISHDMAC_Pos) /**< (USBHS_DEVEPTIDR) Endpoint Interrupts Disable HDMA Request Clear Mask */ 2250 #define USBHS_DEVEPTIDR_EPDISHDMAC USBHS_DEVEPTIDR_EPDISHDMAC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_EPDISHDMAC_Msk instead */ 2251 #define USBHS_DEVEPTIDR_MASK _U_(0x150A3) /**< \deprecated (USBHS_DEVEPTIDR) Register MASK (Use USBHS_DEVEPTIDR_Msk instead) */ 2252 #define USBHS_DEVEPTIDR_Msk _U_(0x150A3) /**< (USBHS_DEVEPTIDR) Register Mask */ 2253 2254 /* CTRL mode */ 2255 #define USBHS_DEVEPTIDR_CTRL_RXSTPEC_Pos 2 /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ 2256 #define USBHS_DEVEPTIDR_CTRL_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ 2257 #define USBHS_DEVEPTIDR_CTRL_RXSTPEC USBHS_DEVEPTIDR_CTRL_RXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_RXSTPEC_Msk instead */ 2258 #define USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Pos 3 /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ 2259 #define USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ 2260 #define USBHS_DEVEPTIDR_CTRL_NAKOUTEC USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_NAKOUTEC_Msk instead */ 2261 #define USBHS_DEVEPTIDR_CTRL_NAKINEC_Pos 4 /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ 2262 #define USBHS_DEVEPTIDR_CTRL_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ 2263 #define USBHS_DEVEPTIDR_CTRL_NAKINEC USBHS_DEVEPTIDR_CTRL_NAKINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_NAKINEC_Msk instead */ 2264 #define USBHS_DEVEPTIDR_CTRL_STALLEDEC_Pos 6 /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ 2265 #define USBHS_DEVEPTIDR_CTRL_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ 2266 #define USBHS_DEVEPTIDR_CTRL_STALLEDEC USBHS_DEVEPTIDR_CTRL_STALLEDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_STALLEDEC_Msk instead */ 2267 #define USBHS_DEVEPTIDR_CTRL_NYETDISC_Pos 17 /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ 2268 #define USBHS_DEVEPTIDR_CTRL_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ 2269 #define USBHS_DEVEPTIDR_CTRL_NYETDISC USBHS_DEVEPTIDR_CTRL_NYETDISC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_NYETDISC_Msk instead */ 2270 #define USBHS_DEVEPTIDR_CTRL_STALLRQC_Pos 19 /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ 2271 #define USBHS_DEVEPTIDR_CTRL_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_CTRL_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ 2272 #define USBHS_DEVEPTIDR_CTRL_STALLRQC USBHS_DEVEPTIDR_CTRL_STALLRQC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_CTRL_STALLRQC_Msk instead */ 2273 #define USBHS_DEVEPTIDR_CTRL_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIDR_CTRL) Register MASK (Use USBHS_DEVEPTIDR_CTRL_Msk instead) */ 2274 #define USBHS_DEVEPTIDR_CTRL_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIDR_CTRL) Register Mask */ 2275 2276 /* ISO mode */ 2277 #define USBHS_DEVEPTIDR_ISO_UNDERFEC_Pos 2 /**< (USBHS_DEVEPTIDR) Underflow Interrupt Clear Position */ 2278 #define USBHS_DEVEPTIDR_ISO_UNDERFEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_UNDERFEC_Pos) /**< (USBHS_DEVEPTIDR) Underflow Interrupt Clear Mask */ 2279 #define USBHS_DEVEPTIDR_ISO_UNDERFEC USBHS_DEVEPTIDR_ISO_UNDERFEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_UNDERFEC_Msk instead */ 2280 #define USBHS_DEVEPTIDR_ISO_HBISOINERREC_Pos 3 /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Position */ 2281 #define USBHS_DEVEPTIDR_ISO_HBISOINERREC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_HBISOINERREC_Pos) /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Underflow Error Interrupt Clear Mask */ 2282 #define USBHS_DEVEPTIDR_ISO_HBISOINERREC USBHS_DEVEPTIDR_ISO_HBISOINERREC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_HBISOINERREC_Msk instead */ 2283 #define USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Pos 4 /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Position */ 2284 #define USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Pos) /**< (USBHS_DEVEPTIDR) High Bandwidth Isochronous IN Flush Interrupt Clear Mask */ 2285 #define USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_HBISOFLUSHEC_Msk instead */ 2286 #define USBHS_DEVEPTIDR_ISO_MDATAEC_Pos 8 /**< (USBHS_DEVEPTIDR) MData Interrupt Clear Position */ 2287 #define USBHS_DEVEPTIDR_ISO_MDATAEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_MDATAEC_Pos) /**< (USBHS_DEVEPTIDR) MData Interrupt Clear Mask */ 2288 #define USBHS_DEVEPTIDR_ISO_MDATAEC USBHS_DEVEPTIDR_ISO_MDATAEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_MDATAEC_Msk instead */ 2289 #define USBHS_DEVEPTIDR_ISO_DATAXEC_Pos 9 /**< (USBHS_DEVEPTIDR) DataX Interrupt Clear Position */ 2290 #define USBHS_DEVEPTIDR_ISO_DATAXEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_DATAXEC_Pos) /**< (USBHS_DEVEPTIDR) DataX Interrupt Clear Mask */ 2291 #define USBHS_DEVEPTIDR_ISO_DATAXEC USBHS_DEVEPTIDR_ISO_DATAXEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_DATAXEC_Msk instead */ 2292 #define USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Pos 10 /**< (USBHS_DEVEPTIDR) Transaction Error Interrupt Clear Position */ 2293 #define USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Pos) /**< (USBHS_DEVEPTIDR) Transaction Error Interrupt Clear Mask */ 2294 #define USBHS_DEVEPTIDR_ISO_ERRORTRANSEC USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_ISO_ERRORTRANSEC_Msk instead */ 2295 #define USBHS_DEVEPTIDR_ISO_MASK _U_(0x71C) /**< \deprecated (USBHS_DEVEPTIDR_ISO) Register MASK (Use USBHS_DEVEPTIDR_ISO_Msk instead) */ 2296 #define USBHS_DEVEPTIDR_ISO_Msk _U_(0x71C) /**< (USBHS_DEVEPTIDR_ISO) Register Mask */ 2297 2298 /* BLK mode */ 2299 #define USBHS_DEVEPTIDR_BLK_RXSTPEC_Pos 2 /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ 2300 #define USBHS_DEVEPTIDR_BLK_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ 2301 #define USBHS_DEVEPTIDR_BLK_RXSTPEC USBHS_DEVEPTIDR_BLK_RXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_RXSTPEC_Msk instead */ 2302 #define USBHS_DEVEPTIDR_BLK_NAKOUTEC_Pos 3 /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ 2303 #define USBHS_DEVEPTIDR_BLK_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ 2304 #define USBHS_DEVEPTIDR_BLK_NAKOUTEC USBHS_DEVEPTIDR_BLK_NAKOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_NAKOUTEC_Msk instead */ 2305 #define USBHS_DEVEPTIDR_BLK_NAKINEC_Pos 4 /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ 2306 #define USBHS_DEVEPTIDR_BLK_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ 2307 #define USBHS_DEVEPTIDR_BLK_NAKINEC USBHS_DEVEPTIDR_BLK_NAKINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_NAKINEC_Msk instead */ 2308 #define USBHS_DEVEPTIDR_BLK_STALLEDEC_Pos 6 /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ 2309 #define USBHS_DEVEPTIDR_BLK_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ 2310 #define USBHS_DEVEPTIDR_BLK_STALLEDEC USBHS_DEVEPTIDR_BLK_STALLEDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_STALLEDEC_Msk instead */ 2311 #define USBHS_DEVEPTIDR_BLK_NYETDISC_Pos 17 /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ 2312 #define USBHS_DEVEPTIDR_BLK_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ 2313 #define USBHS_DEVEPTIDR_BLK_NYETDISC USBHS_DEVEPTIDR_BLK_NYETDISC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_NYETDISC_Msk instead */ 2314 #define USBHS_DEVEPTIDR_BLK_STALLRQC_Pos 19 /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ 2315 #define USBHS_DEVEPTIDR_BLK_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_BLK_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ 2316 #define USBHS_DEVEPTIDR_BLK_STALLRQC USBHS_DEVEPTIDR_BLK_STALLRQC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_BLK_STALLRQC_Msk instead */ 2317 #define USBHS_DEVEPTIDR_BLK_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIDR_BLK) Register MASK (Use USBHS_DEVEPTIDR_BLK_Msk instead) */ 2318 #define USBHS_DEVEPTIDR_BLK_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIDR_BLK) Register Mask */ 2319 2320 /* INTRPT mode */ 2321 #define USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Pos 2 /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Position */ 2322 #define USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Pos) /**< (USBHS_DEVEPTIDR) Received SETUP Interrupt Clear Mask */ 2323 #define USBHS_DEVEPTIDR_INTRPT_RXSTPEC USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_RXSTPEC_Msk instead */ 2324 #define USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Pos 3 /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Position */ 2325 #define USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed OUT Interrupt Clear Mask */ 2326 #define USBHS_DEVEPTIDR_INTRPT_NAKOUTEC USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_NAKOUTEC_Msk instead */ 2327 #define USBHS_DEVEPTIDR_INTRPT_NAKINEC_Pos 4 /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Position */ 2328 #define USBHS_DEVEPTIDR_INTRPT_NAKINEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_NAKINEC_Pos) /**< (USBHS_DEVEPTIDR) NAKed IN Interrupt Clear Mask */ 2329 #define USBHS_DEVEPTIDR_INTRPT_NAKINEC USBHS_DEVEPTIDR_INTRPT_NAKINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_NAKINEC_Msk instead */ 2330 #define USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Pos 6 /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Position */ 2331 #define USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Pos) /**< (USBHS_DEVEPTIDR) STALLed Interrupt Clear Mask */ 2332 #define USBHS_DEVEPTIDR_INTRPT_STALLEDEC USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_STALLEDEC_Msk instead */ 2333 #define USBHS_DEVEPTIDR_INTRPT_NYETDISC_Pos 17 /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Position */ 2334 #define USBHS_DEVEPTIDR_INTRPT_NYETDISC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_NYETDISC_Pos) /**< (USBHS_DEVEPTIDR) NYET Token Disable Clear Mask */ 2335 #define USBHS_DEVEPTIDR_INTRPT_NYETDISC USBHS_DEVEPTIDR_INTRPT_NYETDISC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_NYETDISC_Msk instead */ 2336 #define USBHS_DEVEPTIDR_INTRPT_STALLRQC_Pos 19 /**< (USBHS_DEVEPTIDR) STALL Request Clear Position */ 2337 #define USBHS_DEVEPTIDR_INTRPT_STALLRQC_Msk (_U_(0x1) << USBHS_DEVEPTIDR_INTRPT_STALLRQC_Pos) /**< (USBHS_DEVEPTIDR) STALL Request Clear Mask */ 2338 #define USBHS_DEVEPTIDR_INTRPT_STALLRQC USBHS_DEVEPTIDR_INTRPT_STALLRQC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_DEVEPTIDR_INTRPT_STALLRQC_Msk instead */ 2339 #define USBHS_DEVEPTIDR_INTRPT_MASK _U_(0xA005C) /**< \deprecated (USBHS_DEVEPTIDR_INTRPT) Register MASK (Use USBHS_DEVEPTIDR_INTRPT_Msk instead) */ 2340 #define USBHS_DEVEPTIDR_INTRPT_Msk _U_(0xA005C) /**< (USBHS_DEVEPTIDR_INTRPT) Register Mask */ 2341 2342 2343 /* -------- USBHS_HSTCTRL : (USBHS Offset: 0x400) (R/W 32) Host General Control Register -------- */ 2344 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2345 #if COMPONENT_TYPEDEF_STYLE == 'N' 2346 typedef union { 2347 struct { 2348 uint32_t :8; /**< bit: 0..7 Reserved */ 2349 uint32_t SOFE:1; /**< bit: 8 Start of Frame Generation Enable */ 2350 uint32_t RESET:1; /**< bit: 9 Send USB Reset */ 2351 uint32_t RESUME:1; /**< bit: 10 Send USB Resume */ 2352 uint32_t :1; /**< bit: 11 Reserved */ 2353 uint32_t SPDCONF:2; /**< bit: 12..13 Mode Configuration */ 2354 uint32_t :18; /**< bit: 14..31 Reserved */ 2355 } bit; /**< Structure used for bit access */ 2356 uint32_t reg; /**< Type used for register access */ 2357 } USBHS_HSTCTRL_Type; 2358 #endif 2359 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2360 2361 #define USBHS_HSTCTRL_OFFSET (0x400) /**< (USBHS_HSTCTRL) Host General Control Register Offset */ 2362 2363 #define USBHS_HSTCTRL_SOFE_Pos 8 /**< (USBHS_HSTCTRL) Start of Frame Generation Enable Position */ 2364 #define USBHS_HSTCTRL_SOFE_Msk (_U_(0x1) << USBHS_HSTCTRL_SOFE_Pos) /**< (USBHS_HSTCTRL) Start of Frame Generation Enable Mask */ 2365 #define USBHS_HSTCTRL_SOFE USBHS_HSTCTRL_SOFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTCTRL_SOFE_Msk instead */ 2366 #define USBHS_HSTCTRL_RESET_Pos 9 /**< (USBHS_HSTCTRL) Send USB Reset Position */ 2367 #define USBHS_HSTCTRL_RESET_Msk (_U_(0x1) << USBHS_HSTCTRL_RESET_Pos) /**< (USBHS_HSTCTRL) Send USB Reset Mask */ 2368 #define USBHS_HSTCTRL_RESET USBHS_HSTCTRL_RESET_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTCTRL_RESET_Msk instead */ 2369 #define USBHS_HSTCTRL_RESUME_Pos 10 /**< (USBHS_HSTCTRL) Send USB Resume Position */ 2370 #define USBHS_HSTCTRL_RESUME_Msk (_U_(0x1) << USBHS_HSTCTRL_RESUME_Pos) /**< (USBHS_HSTCTRL) Send USB Resume Mask */ 2371 #define USBHS_HSTCTRL_RESUME USBHS_HSTCTRL_RESUME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTCTRL_RESUME_Msk instead */ 2372 #define USBHS_HSTCTRL_SPDCONF_Pos 12 /**< (USBHS_HSTCTRL) Mode Configuration Position */ 2373 #define USBHS_HSTCTRL_SPDCONF_Msk (_U_(0x3) << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) Mode Configuration Mask */ 2374 #define USBHS_HSTCTRL_SPDCONF(value) (USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos)) 2375 #define USBHS_HSTCTRL_SPDCONF_NORMAL_Val _U_(0x0) /**< (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ 2376 #define USBHS_HSTCTRL_SPDCONF_LOW_POWER_Val _U_(0x1) /**< (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ 2377 #define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED_Val _U_(0x2) /**< (USBHS_HSTCTRL) Forced high speed. */ 2378 #define USBHS_HSTCTRL_SPDCONF_FORCED_FS_Val _U_(0x3) /**< (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ 2379 #define USBHS_HSTCTRL_SPDCONF_NORMAL (USBHS_HSTCTRL_SPDCONF_NORMAL_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. Position */ 2380 #define USBHS_HSTCTRL_SPDCONF_LOW_POWER (USBHS_HSTCTRL_SPDCONF_LOW_POWER_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. Position */ 2381 #define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (USBHS_HSTCTRL_SPDCONF_HIGH_SPEED_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) Forced high speed. Position */ 2382 #define USBHS_HSTCTRL_SPDCONF_FORCED_FS (USBHS_HSTCTRL_SPDCONF_FORCED_FS_Val << USBHS_HSTCTRL_SPDCONF_Pos) /**< (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. Position */ 2383 #define USBHS_HSTCTRL_MASK _U_(0x3700) /**< \deprecated (USBHS_HSTCTRL) Register MASK (Use USBHS_HSTCTRL_Msk instead) */ 2384 #define USBHS_HSTCTRL_Msk _U_(0x3700) /**< (USBHS_HSTCTRL) Register Mask */ 2385 2386 2387 /* -------- USBHS_HSTISR : (USBHS Offset: 0x404) (R/ 32) Host Global Interrupt Status Register -------- */ 2388 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2389 #if COMPONENT_TYPEDEF_STYLE == 'N' 2390 typedef union { 2391 struct { 2392 uint32_t DCONNI:1; /**< bit: 0 Device Connection Interrupt */ 2393 uint32_t DDISCI:1; /**< bit: 1 Device Disconnection Interrupt */ 2394 uint32_t RSTI:1; /**< bit: 2 USB Reset Sent Interrupt */ 2395 uint32_t RSMEDI:1; /**< bit: 3 Downstream Resume Sent Interrupt */ 2396 uint32_t RXRSMI:1; /**< bit: 4 Upstream Resume Received Interrupt */ 2397 uint32_t HSOFI:1; /**< bit: 5 Host Start of Frame Interrupt */ 2398 uint32_t HWUPI:1; /**< bit: 6 Host Wake-Up Interrupt */ 2399 uint32_t :1; /**< bit: 7 Reserved */ 2400 uint32_t PEP_0:1; /**< bit: 8 Pipe 0 Interrupt */ 2401 uint32_t PEP_1:1; /**< bit: 9 Pipe 1 Interrupt */ 2402 uint32_t PEP_2:1; /**< bit: 10 Pipe 2 Interrupt */ 2403 uint32_t PEP_3:1; /**< bit: 11 Pipe 3 Interrupt */ 2404 uint32_t PEP_4:1; /**< bit: 12 Pipe 4 Interrupt */ 2405 uint32_t PEP_5:1; /**< bit: 13 Pipe 5 Interrupt */ 2406 uint32_t PEP_6:1; /**< bit: 14 Pipe 6 Interrupt */ 2407 uint32_t PEP_7:1; /**< bit: 15 Pipe 7 Interrupt */ 2408 uint32_t PEP_8:1; /**< bit: 16 Pipe 8 Interrupt */ 2409 uint32_t PEP_9:1; /**< bit: 17 Pipe 9 Interrupt */ 2410 uint32_t :7; /**< bit: 18..24 Reserved */ 2411 uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt */ 2412 uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt */ 2413 uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt */ 2414 uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt */ 2415 uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt */ 2416 uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt */ 2417 uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt */ 2418 } bit; /**< Structure used for bit access */ 2419 struct { 2420 uint32_t :8; /**< bit: 0..7 Reserved */ 2421 uint32_t PEP_:10; /**< bit: 8..17 Pipe x Interrupt */ 2422 uint32_t :7; /**< bit: 18..24 Reserved */ 2423 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt */ 2424 } vec; /**< Structure used for vec access */ 2425 uint32_t reg; /**< Type used for register access */ 2426 } USBHS_HSTISR_Type; 2427 #endif 2428 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2429 2430 #define USBHS_HSTISR_OFFSET (0x404) /**< (USBHS_HSTISR) Host Global Interrupt Status Register Offset */ 2431 2432 #define USBHS_HSTISR_DCONNI_Pos 0 /**< (USBHS_HSTISR) Device Connection Interrupt Position */ 2433 #define USBHS_HSTISR_DCONNI_Msk (_U_(0x1) << USBHS_HSTISR_DCONNI_Pos) /**< (USBHS_HSTISR) Device Connection Interrupt Mask */ 2434 #define USBHS_HSTISR_DCONNI USBHS_HSTISR_DCONNI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DCONNI_Msk instead */ 2435 #define USBHS_HSTISR_DDISCI_Pos 1 /**< (USBHS_HSTISR) Device Disconnection Interrupt Position */ 2436 #define USBHS_HSTISR_DDISCI_Msk (_U_(0x1) << USBHS_HSTISR_DDISCI_Pos) /**< (USBHS_HSTISR) Device Disconnection Interrupt Mask */ 2437 #define USBHS_HSTISR_DDISCI USBHS_HSTISR_DDISCI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DDISCI_Msk instead */ 2438 #define USBHS_HSTISR_RSTI_Pos 2 /**< (USBHS_HSTISR) USB Reset Sent Interrupt Position */ 2439 #define USBHS_HSTISR_RSTI_Msk (_U_(0x1) << USBHS_HSTISR_RSTI_Pos) /**< (USBHS_HSTISR) USB Reset Sent Interrupt Mask */ 2440 #define USBHS_HSTISR_RSTI USBHS_HSTISR_RSTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_RSTI_Msk instead */ 2441 #define USBHS_HSTISR_RSMEDI_Pos 3 /**< (USBHS_HSTISR) Downstream Resume Sent Interrupt Position */ 2442 #define USBHS_HSTISR_RSMEDI_Msk (_U_(0x1) << USBHS_HSTISR_RSMEDI_Pos) /**< (USBHS_HSTISR) Downstream Resume Sent Interrupt Mask */ 2443 #define USBHS_HSTISR_RSMEDI USBHS_HSTISR_RSMEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_RSMEDI_Msk instead */ 2444 #define USBHS_HSTISR_RXRSMI_Pos 4 /**< (USBHS_HSTISR) Upstream Resume Received Interrupt Position */ 2445 #define USBHS_HSTISR_RXRSMI_Msk (_U_(0x1) << USBHS_HSTISR_RXRSMI_Pos) /**< (USBHS_HSTISR) Upstream Resume Received Interrupt Mask */ 2446 #define USBHS_HSTISR_RXRSMI USBHS_HSTISR_RXRSMI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_RXRSMI_Msk instead */ 2447 #define USBHS_HSTISR_HSOFI_Pos 5 /**< (USBHS_HSTISR) Host Start of Frame Interrupt Position */ 2448 #define USBHS_HSTISR_HSOFI_Msk (_U_(0x1) << USBHS_HSTISR_HSOFI_Pos) /**< (USBHS_HSTISR) Host Start of Frame Interrupt Mask */ 2449 #define USBHS_HSTISR_HSOFI USBHS_HSTISR_HSOFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_HSOFI_Msk instead */ 2450 #define USBHS_HSTISR_HWUPI_Pos 6 /**< (USBHS_HSTISR) Host Wake-Up Interrupt Position */ 2451 #define USBHS_HSTISR_HWUPI_Msk (_U_(0x1) << USBHS_HSTISR_HWUPI_Pos) /**< (USBHS_HSTISR) Host Wake-Up Interrupt Mask */ 2452 #define USBHS_HSTISR_HWUPI USBHS_HSTISR_HWUPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_HWUPI_Msk instead */ 2453 #define USBHS_HSTISR_PEP_0_Pos 8 /**< (USBHS_HSTISR) Pipe 0 Interrupt Position */ 2454 #define USBHS_HSTISR_PEP_0_Msk (_U_(0x1) << USBHS_HSTISR_PEP_0_Pos) /**< (USBHS_HSTISR) Pipe 0 Interrupt Mask */ 2455 #define USBHS_HSTISR_PEP_0 USBHS_HSTISR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_0_Msk instead */ 2456 #define USBHS_HSTISR_PEP_1_Pos 9 /**< (USBHS_HSTISR) Pipe 1 Interrupt Position */ 2457 #define USBHS_HSTISR_PEP_1_Msk (_U_(0x1) << USBHS_HSTISR_PEP_1_Pos) /**< (USBHS_HSTISR) Pipe 1 Interrupt Mask */ 2458 #define USBHS_HSTISR_PEP_1 USBHS_HSTISR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_1_Msk instead */ 2459 #define USBHS_HSTISR_PEP_2_Pos 10 /**< (USBHS_HSTISR) Pipe 2 Interrupt Position */ 2460 #define USBHS_HSTISR_PEP_2_Msk (_U_(0x1) << USBHS_HSTISR_PEP_2_Pos) /**< (USBHS_HSTISR) Pipe 2 Interrupt Mask */ 2461 #define USBHS_HSTISR_PEP_2 USBHS_HSTISR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_2_Msk instead */ 2462 #define USBHS_HSTISR_PEP_3_Pos 11 /**< (USBHS_HSTISR) Pipe 3 Interrupt Position */ 2463 #define USBHS_HSTISR_PEP_3_Msk (_U_(0x1) << USBHS_HSTISR_PEP_3_Pos) /**< (USBHS_HSTISR) Pipe 3 Interrupt Mask */ 2464 #define USBHS_HSTISR_PEP_3 USBHS_HSTISR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_3_Msk instead */ 2465 #define USBHS_HSTISR_PEP_4_Pos 12 /**< (USBHS_HSTISR) Pipe 4 Interrupt Position */ 2466 #define USBHS_HSTISR_PEP_4_Msk (_U_(0x1) << USBHS_HSTISR_PEP_4_Pos) /**< (USBHS_HSTISR) Pipe 4 Interrupt Mask */ 2467 #define USBHS_HSTISR_PEP_4 USBHS_HSTISR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_4_Msk instead */ 2468 #define USBHS_HSTISR_PEP_5_Pos 13 /**< (USBHS_HSTISR) Pipe 5 Interrupt Position */ 2469 #define USBHS_HSTISR_PEP_5_Msk (_U_(0x1) << USBHS_HSTISR_PEP_5_Pos) /**< (USBHS_HSTISR) Pipe 5 Interrupt Mask */ 2470 #define USBHS_HSTISR_PEP_5 USBHS_HSTISR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_5_Msk instead */ 2471 #define USBHS_HSTISR_PEP_6_Pos 14 /**< (USBHS_HSTISR) Pipe 6 Interrupt Position */ 2472 #define USBHS_HSTISR_PEP_6_Msk (_U_(0x1) << USBHS_HSTISR_PEP_6_Pos) /**< (USBHS_HSTISR) Pipe 6 Interrupt Mask */ 2473 #define USBHS_HSTISR_PEP_6 USBHS_HSTISR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_6_Msk instead */ 2474 #define USBHS_HSTISR_PEP_7_Pos 15 /**< (USBHS_HSTISR) Pipe 7 Interrupt Position */ 2475 #define USBHS_HSTISR_PEP_7_Msk (_U_(0x1) << USBHS_HSTISR_PEP_7_Pos) /**< (USBHS_HSTISR) Pipe 7 Interrupt Mask */ 2476 #define USBHS_HSTISR_PEP_7 USBHS_HSTISR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_7_Msk instead */ 2477 #define USBHS_HSTISR_PEP_8_Pos 16 /**< (USBHS_HSTISR) Pipe 8 Interrupt Position */ 2478 #define USBHS_HSTISR_PEP_8_Msk (_U_(0x1) << USBHS_HSTISR_PEP_8_Pos) /**< (USBHS_HSTISR) Pipe 8 Interrupt Mask */ 2479 #define USBHS_HSTISR_PEP_8 USBHS_HSTISR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_8_Msk instead */ 2480 #define USBHS_HSTISR_PEP_9_Pos 17 /**< (USBHS_HSTISR) Pipe 9 Interrupt Position */ 2481 #define USBHS_HSTISR_PEP_9_Msk (_U_(0x1) << USBHS_HSTISR_PEP_9_Pos) /**< (USBHS_HSTISR) Pipe 9 Interrupt Mask */ 2482 #define USBHS_HSTISR_PEP_9 USBHS_HSTISR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_PEP_9_Msk instead */ 2483 #define USBHS_HSTISR_DMA_0_Pos 25 /**< (USBHS_HSTISR) DMA Channel 0 Interrupt Position */ 2484 #define USBHS_HSTISR_DMA_0_Msk (_U_(0x1) << USBHS_HSTISR_DMA_0_Pos) /**< (USBHS_HSTISR) DMA Channel 0 Interrupt Mask */ 2485 #define USBHS_HSTISR_DMA_0 USBHS_HSTISR_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_0_Msk instead */ 2486 #define USBHS_HSTISR_DMA_1_Pos 26 /**< (USBHS_HSTISR) DMA Channel 1 Interrupt Position */ 2487 #define USBHS_HSTISR_DMA_1_Msk (_U_(0x1) << USBHS_HSTISR_DMA_1_Pos) /**< (USBHS_HSTISR) DMA Channel 1 Interrupt Mask */ 2488 #define USBHS_HSTISR_DMA_1 USBHS_HSTISR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_1_Msk instead */ 2489 #define USBHS_HSTISR_DMA_2_Pos 27 /**< (USBHS_HSTISR) DMA Channel 2 Interrupt Position */ 2490 #define USBHS_HSTISR_DMA_2_Msk (_U_(0x1) << USBHS_HSTISR_DMA_2_Pos) /**< (USBHS_HSTISR) DMA Channel 2 Interrupt Mask */ 2491 #define USBHS_HSTISR_DMA_2 USBHS_HSTISR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_2_Msk instead */ 2492 #define USBHS_HSTISR_DMA_3_Pos 28 /**< (USBHS_HSTISR) DMA Channel 3 Interrupt Position */ 2493 #define USBHS_HSTISR_DMA_3_Msk (_U_(0x1) << USBHS_HSTISR_DMA_3_Pos) /**< (USBHS_HSTISR) DMA Channel 3 Interrupt Mask */ 2494 #define USBHS_HSTISR_DMA_3 USBHS_HSTISR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_3_Msk instead */ 2495 #define USBHS_HSTISR_DMA_4_Pos 29 /**< (USBHS_HSTISR) DMA Channel 4 Interrupt Position */ 2496 #define USBHS_HSTISR_DMA_4_Msk (_U_(0x1) << USBHS_HSTISR_DMA_4_Pos) /**< (USBHS_HSTISR) DMA Channel 4 Interrupt Mask */ 2497 #define USBHS_HSTISR_DMA_4 USBHS_HSTISR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_4_Msk instead */ 2498 #define USBHS_HSTISR_DMA_5_Pos 30 /**< (USBHS_HSTISR) DMA Channel 5 Interrupt Position */ 2499 #define USBHS_HSTISR_DMA_5_Msk (_U_(0x1) << USBHS_HSTISR_DMA_5_Pos) /**< (USBHS_HSTISR) DMA Channel 5 Interrupt Mask */ 2500 #define USBHS_HSTISR_DMA_5 USBHS_HSTISR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_5_Msk instead */ 2501 #define USBHS_HSTISR_DMA_6_Pos 31 /**< (USBHS_HSTISR) DMA Channel 6 Interrupt Position */ 2502 #define USBHS_HSTISR_DMA_6_Msk (_U_(0x1) << USBHS_HSTISR_DMA_6_Pos) /**< (USBHS_HSTISR) DMA Channel 6 Interrupt Mask */ 2503 #define USBHS_HSTISR_DMA_6 USBHS_HSTISR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTISR_DMA_6_Msk instead */ 2504 #define USBHS_HSTISR_MASK _U_(0xFE03FF7F) /**< \deprecated (USBHS_HSTISR) Register MASK (Use USBHS_HSTISR_Msk instead) */ 2505 #define USBHS_HSTISR_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTISR) Register Mask */ 2506 2507 #define USBHS_HSTISR_PEP__Pos 8 /**< (USBHS_HSTISR Position) Pipe x Interrupt */ 2508 #define USBHS_HSTISR_PEP__Msk (_U_(0x3FF) << USBHS_HSTISR_PEP__Pos) /**< (USBHS_HSTISR Mask) PEP_ */ 2509 #define USBHS_HSTISR_PEP_(value) (USBHS_HSTISR_PEP__Msk & ((value) << USBHS_HSTISR_PEP__Pos)) 2510 #define USBHS_HSTISR_DMA__Pos 25 /**< (USBHS_HSTISR Position) DMA Channel 6 Interrupt */ 2511 #define USBHS_HSTISR_DMA__Msk (_U_(0x7F) << USBHS_HSTISR_DMA__Pos) /**< (USBHS_HSTISR Mask) DMA_ */ 2512 #define USBHS_HSTISR_DMA_(value) (USBHS_HSTISR_DMA__Msk & ((value) << USBHS_HSTISR_DMA__Pos)) 2513 2514 /* -------- USBHS_HSTICR : (USBHS Offset: 0x408) (/W 32) Host Global Interrupt Clear Register -------- */ 2515 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2516 #if COMPONENT_TYPEDEF_STYLE == 'N' 2517 typedef union { 2518 struct { 2519 uint32_t DCONNIC:1; /**< bit: 0 Device Connection Interrupt Clear */ 2520 uint32_t DDISCIC:1; /**< bit: 1 Device Disconnection Interrupt Clear */ 2521 uint32_t RSTIC:1; /**< bit: 2 USB Reset Sent Interrupt Clear */ 2522 uint32_t RSMEDIC:1; /**< bit: 3 Downstream Resume Sent Interrupt Clear */ 2523 uint32_t RXRSMIC:1; /**< bit: 4 Upstream Resume Received Interrupt Clear */ 2524 uint32_t HSOFIC:1; /**< bit: 5 Host Start of Frame Interrupt Clear */ 2525 uint32_t HWUPIC:1; /**< bit: 6 Host Wake-Up Interrupt Clear */ 2526 uint32_t :25; /**< bit: 7..31 Reserved */ 2527 } bit; /**< Structure used for bit access */ 2528 uint32_t reg; /**< Type used for register access */ 2529 } USBHS_HSTICR_Type; 2530 #endif 2531 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2532 2533 #define USBHS_HSTICR_OFFSET (0x408) /**< (USBHS_HSTICR) Host Global Interrupt Clear Register Offset */ 2534 2535 #define USBHS_HSTICR_DCONNIC_Pos 0 /**< (USBHS_HSTICR) Device Connection Interrupt Clear Position */ 2536 #define USBHS_HSTICR_DCONNIC_Msk (_U_(0x1) << USBHS_HSTICR_DCONNIC_Pos) /**< (USBHS_HSTICR) Device Connection Interrupt Clear Mask */ 2537 #define USBHS_HSTICR_DCONNIC USBHS_HSTICR_DCONNIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_DCONNIC_Msk instead */ 2538 #define USBHS_HSTICR_DDISCIC_Pos 1 /**< (USBHS_HSTICR) Device Disconnection Interrupt Clear Position */ 2539 #define USBHS_HSTICR_DDISCIC_Msk (_U_(0x1) << USBHS_HSTICR_DDISCIC_Pos) /**< (USBHS_HSTICR) Device Disconnection Interrupt Clear Mask */ 2540 #define USBHS_HSTICR_DDISCIC USBHS_HSTICR_DDISCIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_DDISCIC_Msk instead */ 2541 #define USBHS_HSTICR_RSTIC_Pos 2 /**< (USBHS_HSTICR) USB Reset Sent Interrupt Clear Position */ 2542 #define USBHS_HSTICR_RSTIC_Msk (_U_(0x1) << USBHS_HSTICR_RSTIC_Pos) /**< (USBHS_HSTICR) USB Reset Sent Interrupt Clear Mask */ 2543 #define USBHS_HSTICR_RSTIC USBHS_HSTICR_RSTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_RSTIC_Msk instead */ 2544 #define USBHS_HSTICR_RSMEDIC_Pos 3 /**< (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear Position */ 2545 #define USBHS_HSTICR_RSMEDIC_Msk (_U_(0x1) << USBHS_HSTICR_RSMEDIC_Pos) /**< (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear Mask */ 2546 #define USBHS_HSTICR_RSMEDIC USBHS_HSTICR_RSMEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_RSMEDIC_Msk instead */ 2547 #define USBHS_HSTICR_RXRSMIC_Pos 4 /**< (USBHS_HSTICR) Upstream Resume Received Interrupt Clear Position */ 2548 #define USBHS_HSTICR_RXRSMIC_Msk (_U_(0x1) << USBHS_HSTICR_RXRSMIC_Pos) /**< (USBHS_HSTICR) Upstream Resume Received Interrupt Clear Mask */ 2549 #define USBHS_HSTICR_RXRSMIC USBHS_HSTICR_RXRSMIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_RXRSMIC_Msk instead */ 2550 #define USBHS_HSTICR_HSOFIC_Pos 5 /**< (USBHS_HSTICR) Host Start of Frame Interrupt Clear Position */ 2551 #define USBHS_HSTICR_HSOFIC_Msk (_U_(0x1) << USBHS_HSTICR_HSOFIC_Pos) /**< (USBHS_HSTICR) Host Start of Frame Interrupt Clear Mask */ 2552 #define USBHS_HSTICR_HSOFIC USBHS_HSTICR_HSOFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_HSOFIC_Msk instead */ 2553 #define USBHS_HSTICR_HWUPIC_Pos 6 /**< (USBHS_HSTICR) Host Wake-Up Interrupt Clear Position */ 2554 #define USBHS_HSTICR_HWUPIC_Msk (_U_(0x1) << USBHS_HSTICR_HWUPIC_Pos) /**< (USBHS_HSTICR) Host Wake-Up Interrupt Clear Mask */ 2555 #define USBHS_HSTICR_HWUPIC USBHS_HSTICR_HWUPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTICR_HWUPIC_Msk instead */ 2556 #define USBHS_HSTICR_MASK _U_(0x7F) /**< \deprecated (USBHS_HSTICR) Register MASK (Use USBHS_HSTICR_Msk instead) */ 2557 #define USBHS_HSTICR_Msk _U_(0x7F) /**< (USBHS_HSTICR) Register Mask */ 2558 2559 2560 /* -------- USBHS_HSTIFR : (USBHS Offset: 0x40c) (/W 32) Host Global Interrupt Set Register -------- */ 2561 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2562 #if COMPONENT_TYPEDEF_STYLE == 'N' 2563 typedef union { 2564 struct { 2565 uint32_t DCONNIS:1; /**< bit: 0 Device Connection Interrupt Set */ 2566 uint32_t DDISCIS:1; /**< bit: 1 Device Disconnection Interrupt Set */ 2567 uint32_t RSTIS:1; /**< bit: 2 USB Reset Sent Interrupt Set */ 2568 uint32_t RSMEDIS:1; /**< bit: 3 Downstream Resume Sent Interrupt Set */ 2569 uint32_t RXRSMIS:1; /**< bit: 4 Upstream Resume Received Interrupt Set */ 2570 uint32_t HSOFIS:1; /**< bit: 5 Host Start of Frame Interrupt Set */ 2571 uint32_t HWUPIS:1; /**< bit: 6 Host Wake-Up Interrupt Set */ 2572 uint32_t :18; /**< bit: 7..24 Reserved */ 2573 uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt Set */ 2574 uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt Set */ 2575 uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt Set */ 2576 uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt Set */ 2577 uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt Set */ 2578 uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt Set */ 2579 uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt Set */ 2580 } bit; /**< Structure used for bit access */ 2581 struct { 2582 uint32_t :25; /**< bit: 0..24 Reserved */ 2583 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt Set */ 2584 } vec; /**< Structure used for vec access */ 2585 uint32_t reg; /**< Type used for register access */ 2586 } USBHS_HSTIFR_Type; 2587 #endif 2588 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2589 2590 #define USBHS_HSTIFR_OFFSET (0x40C) /**< (USBHS_HSTIFR) Host Global Interrupt Set Register Offset */ 2591 2592 #define USBHS_HSTIFR_DCONNIS_Pos 0 /**< (USBHS_HSTIFR) Device Connection Interrupt Set Position */ 2593 #define USBHS_HSTIFR_DCONNIS_Msk (_U_(0x1) << USBHS_HSTIFR_DCONNIS_Pos) /**< (USBHS_HSTIFR) Device Connection Interrupt Set Mask */ 2594 #define USBHS_HSTIFR_DCONNIS USBHS_HSTIFR_DCONNIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DCONNIS_Msk instead */ 2595 #define USBHS_HSTIFR_DDISCIS_Pos 1 /**< (USBHS_HSTIFR) Device Disconnection Interrupt Set Position */ 2596 #define USBHS_HSTIFR_DDISCIS_Msk (_U_(0x1) << USBHS_HSTIFR_DDISCIS_Pos) /**< (USBHS_HSTIFR) Device Disconnection Interrupt Set Mask */ 2597 #define USBHS_HSTIFR_DDISCIS USBHS_HSTIFR_DDISCIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DDISCIS_Msk instead */ 2598 #define USBHS_HSTIFR_RSTIS_Pos 2 /**< (USBHS_HSTIFR) USB Reset Sent Interrupt Set Position */ 2599 #define USBHS_HSTIFR_RSTIS_Msk (_U_(0x1) << USBHS_HSTIFR_RSTIS_Pos) /**< (USBHS_HSTIFR) USB Reset Sent Interrupt Set Mask */ 2600 #define USBHS_HSTIFR_RSTIS USBHS_HSTIFR_RSTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_RSTIS_Msk instead */ 2601 #define USBHS_HSTIFR_RSMEDIS_Pos 3 /**< (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set Position */ 2602 #define USBHS_HSTIFR_RSMEDIS_Msk (_U_(0x1) << USBHS_HSTIFR_RSMEDIS_Pos) /**< (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set Mask */ 2603 #define USBHS_HSTIFR_RSMEDIS USBHS_HSTIFR_RSMEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_RSMEDIS_Msk instead */ 2604 #define USBHS_HSTIFR_RXRSMIS_Pos 4 /**< (USBHS_HSTIFR) Upstream Resume Received Interrupt Set Position */ 2605 #define USBHS_HSTIFR_RXRSMIS_Msk (_U_(0x1) << USBHS_HSTIFR_RXRSMIS_Pos) /**< (USBHS_HSTIFR) Upstream Resume Received Interrupt Set Mask */ 2606 #define USBHS_HSTIFR_RXRSMIS USBHS_HSTIFR_RXRSMIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_RXRSMIS_Msk instead */ 2607 #define USBHS_HSTIFR_HSOFIS_Pos 5 /**< (USBHS_HSTIFR) Host Start of Frame Interrupt Set Position */ 2608 #define USBHS_HSTIFR_HSOFIS_Msk (_U_(0x1) << USBHS_HSTIFR_HSOFIS_Pos) /**< (USBHS_HSTIFR) Host Start of Frame Interrupt Set Mask */ 2609 #define USBHS_HSTIFR_HSOFIS USBHS_HSTIFR_HSOFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_HSOFIS_Msk instead */ 2610 #define USBHS_HSTIFR_HWUPIS_Pos 6 /**< (USBHS_HSTIFR) Host Wake-Up Interrupt Set Position */ 2611 #define USBHS_HSTIFR_HWUPIS_Msk (_U_(0x1) << USBHS_HSTIFR_HWUPIS_Pos) /**< (USBHS_HSTIFR) Host Wake-Up Interrupt Set Mask */ 2612 #define USBHS_HSTIFR_HWUPIS USBHS_HSTIFR_HWUPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_HWUPIS_Msk instead */ 2613 #define USBHS_HSTIFR_DMA_0_Pos 25 /**< (USBHS_HSTIFR) DMA Channel 0 Interrupt Set Position */ 2614 #define USBHS_HSTIFR_DMA_0_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_0_Pos) /**< (USBHS_HSTIFR) DMA Channel 0 Interrupt Set Mask */ 2615 #define USBHS_HSTIFR_DMA_0 USBHS_HSTIFR_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_0_Msk instead */ 2616 #define USBHS_HSTIFR_DMA_1_Pos 26 /**< (USBHS_HSTIFR) DMA Channel 1 Interrupt Set Position */ 2617 #define USBHS_HSTIFR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_1_Pos) /**< (USBHS_HSTIFR) DMA Channel 1 Interrupt Set Mask */ 2618 #define USBHS_HSTIFR_DMA_1 USBHS_HSTIFR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_1_Msk instead */ 2619 #define USBHS_HSTIFR_DMA_2_Pos 27 /**< (USBHS_HSTIFR) DMA Channel 2 Interrupt Set Position */ 2620 #define USBHS_HSTIFR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_2_Pos) /**< (USBHS_HSTIFR) DMA Channel 2 Interrupt Set Mask */ 2621 #define USBHS_HSTIFR_DMA_2 USBHS_HSTIFR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_2_Msk instead */ 2622 #define USBHS_HSTIFR_DMA_3_Pos 28 /**< (USBHS_HSTIFR) DMA Channel 3 Interrupt Set Position */ 2623 #define USBHS_HSTIFR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_3_Pos) /**< (USBHS_HSTIFR) DMA Channel 3 Interrupt Set Mask */ 2624 #define USBHS_HSTIFR_DMA_3 USBHS_HSTIFR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_3_Msk instead */ 2625 #define USBHS_HSTIFR_DMA_4_Pos 29 /**< (USBHS_HSTIFR) DMA Channel 4 Interrupt Set Position */ 2626 #define USBHS_HSTIFR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_4_Pos) /**< (USBHS_HSTIFR) DMA Channel 4 Interrupt Set Mask */ 2627 #define USBHS_HSTIFR_DMA_4 USBHS_HSTIFR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_4_Msk instead */ 2628 #define USBHS_HSTIFR_DMA_5_Pos 30 /**< (USBHS_HSTIFR) DMA Channel 5 Interrupt Set Position */ 2629 #define USBHS_HSTIFR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_5_Pos) /**< (USBHS_HSTIFR) DMA Channel 5 Interrupt Set Mask */ 2630 #define USBHS_HSTIFR_DMA_5 USBHS_HSTIFR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_5_Msk instead */ 2631 #define USBHS_HSTIFR_DMA_6_Pos 31 /**< (USBHS_HSTIFR) DMA Channel 6 Interrupt Set Position */ 2632 #define USBHS_HSTIFR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIFR_DMA_6_Pos) /**< (USBHS_HSTIFR) DMA Channel 6 Interrupt Set Mask */ 2633 #define USBHS_HSTIFR_DMA_6 USBHS_HSTIFR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIFR_DMA_6_Msk instead */ 2634 #define USBHS_HSTIFR_MASK _U_(0xFE00007F) /**< \deprecated (USBHS_HSTIFR) Register MASK (Use USBHS_HSTIFR_Msk instead) */ 2635 #define USBHS_HSTIFR_Msk _U_(0xFE00007F) /**< (USBHS_HSTIFR) Register Mask */ 2636 2637 #define USBHS_HSTIFR_DMA__Pos 25 /**< (USBHS_HSTIFR Position) DMA Channel 6 Interrupt Set */ 2638 #define USBHS_HSTIFR_DMA__Msk (_U_(0x7F) << USBHS_HSTIFR_DMA__Pos) /**< (USBHS_HSTIFR Mask) DMA_ */ 2639 #define USBHS_HSTIFR_DMA_(value) (USBHS_HSTIFR_DMA__Msk & ((value) << USBHS_HSTIFR_DMA__Pos)) 2640 2641 /* -------- USBHS_HSTIMR : (USBHS Offset: 0x410) (R/ 32) Host Global Interrupt Mask Register -------- */ 2642 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2643 #if COMPONENT_TYPEDEF_STYLE == 'N' 2644 typedef union { 2645 struct { 2646 uint32_t DCONNIE:1; /**< bit: 0 Device Connection Interrupt Enable */ 2647 uint32_t DDISCIE:1; /**< bit: 1 Device Disconnection Interrupt Enable */ 2648 uint32_t RSTIE:1; /**< bit: 2 USB Reset Sent Interrupt Enable */ 2649 uint32_t RSMEDIE:1; /**< bit: 3 Downstream Resume Sent Interrupt Enable */ 2650 uint32_t RXRSMIE:1; /**< bit: 4 Upstream Resume Received Interrupt Enable */ 2651 uint32_t HSOFIE:1; /**< bit: 5 Host Start of Frame Interrupt Enable */ 2652 uint32_t HWUPIE:1; /**< bit: 6 Host Wake-Up Interrupt Enable */ 2653 uint32_t :1; /**< bit: 7 Reserved */ 2654 uint32_t PEP_0:1; /**< bit: 8 Pipe 0 Interrupt Enable */ 2655 uint32_t PEP_1:1; /**< bit: 9 Pipe 1 Interrupt Enable */ 2656 uint32_t PEP_2:1; /**< bit: 10 Pipe 2 Interrupt Enable */ 2657 uint32_t PEP_3:1; /**< bit: 11 Pipe 3 Interrupt Enable */ 2658 uint32_t PEP_4:1; /**< bit: 12 Pipe 4 Interrupt Enable */ 2659 uint32_t PEP_5:1; /**< bit: 13 Pipe 5 Interrupt Enable */ 2660 uint32_t PEP_6:1; /**< bit: 14 Pipe 6 Interrupt Enable */ 2661 uint32_t PEP_7:1; /**< bit: 15 Pipe 7 Interrupt Enable */ 2662 uint32_t PEP_8:1; /**< bit: 16 Pipe 8 Interrupt Enable */ 2663 uint32_t PEP_9:1; /**< bit: 17 Pipe 9 Interrupt Enable */ 2664 uint32_t :7; /**< bit: 18..24 Reserved */ 2665 uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt Enable */ 2666 uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt Enable */ 2667 uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt Enable */ 2668 uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt Enable */ 2669 uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt Enable */ 2670 uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt Enable */ 2671 uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt Enable */ 2672 } bit; /**< Structure used for bit access */ 2673 struct { 2674 uint32_t :8; /**< bit: 0..7 Reserved */ 2675 uint32_t PEP_:10; /**< bit: 8..17 Pipe x Interrupt Enable */ 2676 uint32_t :7; /**< bit: 18..24 Reserved */ 2677 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt Enable */ 2678 } vec; /**< Structure used for vec access */ 2679 uint32_t reg; /**< Type used for register access */ 2680 } USBHS_HSTIMR_Type; 2681 #endif 2682 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2683 2684 #define USBHS_HSTIMR_OFFSET (0x410) /**< (USBHS_HSTIMR) Host Global Interrupt Mask Register Offset */ 2685 2686 #define USBHS_HSTIMR_DCONNIE_Pos 0 /**< (USBHS_HSTIMR) Device Connection Interrupt Enable Position */ 2687 #define USBHS_HSTIMR_DCONNIE_Msk (_U_(0x1) << USBHS_HSTIMR_DCONNIE_Pos) /**< (USBHS_HSTIMR) Device Connection Interrupt Enable Mask */ 2688 #define USBHS_HSTIMR_DCONNIE USBHS_HSTIMR_DCONNIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DCONNIE_Msk instead */ 2689 #define USBHS_HSTIMR_DDISCIE_Pos 1 /**< (USBHS_HSTIMR) Device Disconnection Interrupt Enable Position */ 2690 #define USBHS_HSTIMR_DDISCIE_Msk (_U_(0x1) << USBHS_HSTIMR_DDISCIE_Pos) /**< (USBHS_HSTIMR) Device Disconnection Interrupt Enable Mask */ 2691 #define USBHS_HSTIMR_DDISCIE USBHS_HSTIMR_DDISCIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DDISCIE_Msk instead */ 2692 #define USBHS_HSTIMR_RSTIE_Pos 2 /**< (USBHS_HSTIMR) USB Reset Sent Interrupt Enable Position */ 2693 #define USBHS_HSTIMR_RSTIE_Msk (_U_(0x1) << USBHS_HSTIMR_RSTIE_Pos) /**< (USBHS_HSTIMR) USB Reset Sent Interrupt Enable Mask */ 2694 #define USBHS_HSTIMR_RSTIE USBHS_HSTIMR_RSTIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_RSTIE_Msk instead */ 2695 #define USBHS_HSTIMR_RSMEDIE_Pos 3 /**< (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable Position */ 2696 #define USBHS_HSTIMR_RSMEDIE_Msk (_U_(0x1) << USBHS_HSTIMR_RSMEDIE_Pos) /**< (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable Mask */ 2697 #define USBHS_HSTIMR_RSMEDIE USBHS_HSTIMR_RSMEDIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_RSMEDIE_Msk instead */ 2698 #define USBHS_HSTIMR_RXRSMIE_Pos 4 /**< (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable Position */ 2699 #define USBHS_HSTIMR_RXRSMIE_Msk (_U_(0x1) << USBHS_HSTIMR_RXRSMIE_Pos) /**< (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable Mask */ 2700 #define USBHS_HSTIMR_RXRSMIE USBHS_HSTIMR_RXRSMIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_RXRSMIE_Msk instead */ 2701 #define USBHS_HSTIMR_HSOFIE_Pos 5 /**< (USBHS_HSTIMR) Host Start of Frame Interrupt Enable Position */ 2702 #define USBHS_HSTIMR_HSOFIE_Msk (_U_(0x1) << USBHS_HSTIMR_HSOFIE_Pos) /**< (USBHS_HSTIMR) Host Start of Frame Interrupt Enable Mask */ 2703 #define USBHS_HSTIMR_HSOFIE USBHS_HSTIMR_HSOFIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_HSOFIE_Msk instead */ 2704 #define USBHS_HSTIMR_HWUPIE_Pos 6 /**< (USBHS_HSTIMR) Host Wake-Up Interrupt Enable Position */ 2705 #define USBHS_HSTIMR_HWUPIE_Msk (_U_(0x1) << USBHS_HSTIMR_HWUPIE_Pos) /**< (USBHS_HSTIMR) Host Wake-Up Interrupt Enable Mask */ 2706 #define USBHS_HSTIMR_HWUPIE USBHS_HSTIMR_HWUPIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_HWUPIE_Msk instead */ 2707 #define USBHS_HSTIMR_PEP_0_Pos 8 /**< (USBHS_HSTIMR) Pipe 0 Interrupt Enable Position */ 2708 #define USBHS_HSTIMR_PEP_0_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_0_Pos) /**< (USBHS_HSTIMR) Pipe 0 Interrupt Enable Mask */ 2709 #define USBHS_HSTIMR_PEP_0 USBHS_HSTIMR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_0_Msk instead */ 2710 #define USBHS_HSTIMR_PEP_1_Pos 9 /**< (USBHS_HSTIMR) Pipe 1 Interrupt Enable Position */ 2711 #define USBHS_HSTIMR_PEP_1_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_1_Pos) /**< (USBHS_HSTIMR) Pipe 1 Interrupt Enable Mask */ 2712 #define USBHS_HSTIMR_PEP_1 USBHS_HSTIMR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_1_Msk instead */ 2713 #define USBHS_HSTIMR_PEP_2_Pos 10 /**< (USBHS_HSTIMR) Pipe 2 Interrupt Enable Position */ 2714 #define USBHS_HSTIMR_PEP_2_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_2_Pos) /**< (USBHS_HSTIMR) Pipe 2 Interrupt Enable Mask */ 2715 #define USBHS_HSTIMR_PEP_2 USBHS_HSTIMR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_2_Msk instead */ 2716 #define USBHS_HSTIMR_PEP_3_Pos 11 /**< (USBHS_HSTIMR) Pipe 3 Interrupt Enable Position */ 2717 #define USBHS_HSTIMR_PEP_3_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_3_Pos) /**< (USBHS_HSTIMR) Pipe 3 Interrupt Enable Mask */ 2718 #define USBHS_HSTIMR_PEP_3 USBHS_HSTIMR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_3_Msk instead */ 2719 #define USBHS_HSTIMR_PEP_4_Pos 12 /**< (USBHS_HSTIMR) Pipe 4 Interrupt Enable Position */ 2720 #define USBHS_HSTIMR_PEP_4_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_4_Pos) /**< (USBHS_HSTIMR) Pipe 4 Interrupt Enable Mask */ 2721 #define USBHS_HSTIMR_PEP_4 USBHS_HSTIMR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_4_Msk instead */ 2722 #define USBHS_HSTIMR_PEP_5_Pos 13 /**< (USBHS_HSTIMR) Pipe 5 Interrupt Enable Position */ 2723 #define USBHS_HSTIMR_PEP_5_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_5_Pos) /**< (USBHS_HSTIMR) Pipe 5 Interrupt Enable Mask */ 2724 #define USBHS_HSTIMR_PEP_5 USBHS_HSTIMR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_5_Msk instead */ 2725 #define USBHS_HSTIMR_PEP_6_Pos 14 /**< (USBHS_HSTIMR) Pipe 6 Interrupt Enable Position */ 2726 #define USBHS_HSTIMR_PEP_6_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_6_Pos) /**< (USBHS_HSTIMR) Pipe 6 Interrupt Enable Mask */ 2727 #define USBHS_HSTIMR_PEP_6 USBHS_HSTIMR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_6_Msk instead */ 2728 #define USBHS_HSTIMR_PEP_7_Pos 15 /**< (USBHS_HSTIMR) Pipe 7 Interrupt Enable Position */ 2729 #define USBHS_HSTIMR_PEP_7_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_7_Pos) /**< (USBHS_HSTIMR) Pipe 7 Interrupt Enable Mask */ 2730 #define USBHS_HSTIMR_PEP_7 USBHS_HSTIMR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_7_Msk instead */ 2731 #define USBHS_HSTIMR_PEP_8_Pos 16 /**< (USBHS_HSTIMR) Pipe 8 Interrupt Enable Position */ 2732 #define USBHS_HSTIMR_PEP_8_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_8_Pos) /**< (USBHS_HSTIMR) Pipe 8 Interrupt Enable Mask */ 2733 #define USBHS_HSTIMR_PEP_8 USBHS_HSTIMR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_8_Msk instead */ 2734 #define USBHS_HSTIMR_PEP_9_Pos 17 /**< (USBHS_HSTIMR) Pipe 9 Interrupt Enable Position */ 2735 #define USBHS_HSTIMR_PEP_9_Msk (_U_(0x1) << USBHS_HSTIMR_PEP_9_Pos) /**< (USBHS_HSTIMR) Pipe 9 Interrupt Enable Mask */ 2736 #define USBHS_HSTIMR_PEP_9 USBHS_HSTIMR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_PEP_9_Msk instead */ 2737 #define USBHS_HSTIMR_DMA_0_Pos 25 /**< (USBHS_HSTIMR) DMA Channel 0 Interrupt Enable Position */ 2738 #define USBHS_HSTIMR_DMA_0_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_0_Pos) /**< (USBHS_HSTIMR) DMA Channel 0 Interrupt Enable Mask */ 2739 #define USBHS_HSTIMR_DMA_0 USBHS_HSTIMR_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_0_Msk instead */ 2740 #define USBHS_HSTIMR_DMA_1_Pos 26 /**< (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable Position */ 2741 #define USBHS_HSTIMR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_1_Pos) /**< (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable Mask */ 2742 #define USBHS_HSTIMR_DMA_1 USBHS_HSTIMR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_1_Msk instead */ 2743 #define USBHS_HSTIMR_DMA_2_Pos 27 /**< (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable Position */ 2744 #define USBHS_HSTIMR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_2_Pos) /**< (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable Mask */ 2745 #define USBHS_HSTIMR_DMA_2 USBHS_HSTIMR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_2_Msk instead */ 2746 #define USBHS_HSTIMR_DMA_3_Pos 28 /**< (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable Position */ 2747 #define USBHS_HSTIMR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_3_Pos) /**< (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable Mask */ 2748 #define USBHS_HSTIMR_DMA_3 USBHS_HSTIMR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_3_Msk instead */ 2749 #define USBHS_HSTIMR_DMA_4_Pos 29 /**< (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable Position */ 2750 #define USBHS_HSTIMR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_4_Pos) /**< (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable Mask */ 2751 #define USBHS_HSTIMR_DMA_4 USBHS_HSTIMR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_4_Msk instead */ 2752 #define USBHS_HSTIMR_DMA_5_Pos 30 /**< (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable Position */ 2753 #define USBHS_HSTIMR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_5_Pos) /**< (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable Mask */ 2754 #define USBHS_HSTIMR_DMA_5 USBHS_HSTIMR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_5_Msk instead */ 2755 #define USBHS_HSTIMR_DMA_6_Pos 31 /**< (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable Position */ 2756 #define USBHS_HSTIMR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIMR_DMA_6_Pos) /**< (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable Mask */ 2757 #define USBHS_HSTIMR_DMA_6 USBHS_HSTIMR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIMR_DMA_6_Msk instead */ 2758 #define USBHS_HSTIMR_MASK _U_(0xFE03FF7F) /**< \deprecated (USBHS_HSTIMR) Register MASK (Use USBHS_HSTIMR_Msk instead) */ 2759 #define USBHS_HSTIMR_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTIMR) Register Mask */ 2760 2761 #define USBHS_HSTIMR_PEP__Pos 8 /**< (USBHS_HSTIMR Position) Pipe x Interrupt Enable */ 2762 #define USBHS_HSTIMR_PEP__Msk (_U_(0x3FF) << USBHS_HSTIMR_PEP__Pos) /**< (USBHS_HSTIMR Mask) PEP_ */ 2763 #define USBHS_HSTIMR_PEP_(value) (USBHS_HSTIMR_PEP__Msk & ((value) << USBHS_HSTIMR_PEP__Pos)) 2764 #define USBHS_HSTIMR_DMA__Pos 25 /**< (USBHS_HSTIMR Position) DMA Channel 6 Interrupt Enable */ 2765 #define USBHS_HSTIMR_DMA__Msk (_U_(0x7F) << USBHS_HSTIMR_DMA__Pos) /**< (USBHS_HSTIMR Mask) DMA_ */ 2766 #define USBHS_HSTIMR_DMA_(value) (USBHS_HSTIMR_DMA__Msk & ((value) << USBHS_HSTIMR_DMA__Pos)) 2767 2768 /* -------- USBHS_HSTIDR : (USBHS Offset: 0x414) (/W 32) Host Global Interrupt Disable Register -------- */ 2769 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2770 #if COMPONENT_TYPEDEF_STYLE == 'N' 2771 typedef union { 2772 struct { 2773 uint32_t DCONNIEC:1; /**< bit: 0 Device Connection Interrupt Disable */ 2774 uint32_t DDISCIEC:1; /**< bit: 1 Device Disconnection Interrupt Disable */ 2775 uint32_t RSTIEC:1; /**< bit: 2 USB Reset Sent Interrupt Disable */ 2776 uint32_t RSMEDIEC:1; /**< bit: 3 Downstream Resume Sent Interrupt Disable */ 2777 uint32_t RXRSMIEC:1; /**< bit: 4 Upstream Resume Received Interrupt Disable */ 2778 uint32_t HSOFIEC:1; /**< bit: 5 Host Start of Frame Interrupt Disable */ 2779 uint32_t HWUPIEC:1; /**< bit: 6 Host Wake-Up Interrupt Disable */ 2780 uint32_t :1; /**< bit: 7 Reserved */ 2781 uint32_t PEP_0:1; /**< bit: 8 Pipe 0 Interrupt Disable */ 2782 uint32_t PEP_1:1; /**< bit: 9 Pipe 1 Interrupt Disable */ 2783 uint32_t PEP_2:1; /**< bit: 10 Pipe 2 Interrupt Disable */ 2784 uint32_t PEP_3:1; /**< bit: 11 Pipe 3 Interrupt Disable */ 2785 uint32_t PEP_4:1; /**< bit: 12 Pipe 4 Interrupt Disable */ 2786 uint32_t PEP_5:1; /**< bit: 13 Pipe 5 Interrupt Disable */ 2787 uint32_t PEP_6:1; /**< bit: 14 Pipe 6 Interrupt Disable */ 2788 uint32_t PEP_7:1; /**< bit: 15 Pipe 7 Interrupt Disable */ 2789 uint32_t PEP_8:1; /**< bit: 16 Pipe 8 Interrupt Disable */ 2790 uint32_t PEP_9:1; /**< bit: 17 Pipe 9 Interrupt Disable */ 2791 uint32_t :7; /**< bit: 18..24 Reserved */ 2792 uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt Disable */ 2793 uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt Disable */ 2794 uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt Disable */ 2795 uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt Disable */ 2796 uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt Disable */ 2797 uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt Disable */ 2798 uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt Disable */ 2799 } bit; /**< Structure used for bit access */ 2800 struct { 2801 uint32_t :8; /**< bit: 0..7 Reserved */ 2802 uint32_t PEP_:10; /**< bit: 8..17 Pipe x Interrupt Disable */ 2803 uint32_t :7; /**< bit: 18..24 Reserved */ 2804 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt Disable */ 2805 } vec; /**< Structure used for vec access */ 2806 uint32_t reg; /**< Type used for register access */ 2807 } USBHS_HSTIDR_Type; 2808 #endif 2809 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2810 2811 #define USBHS_HSTIDR_OFFSET (0x414) /**< (USBHS_HSTIDR) Host Global Interrupt Disable Register Offset */ 2812 2813 #define USBHS_HSTIDR_DCONNIEC_Pos 0 /**< (USBHS_HSTIDR) Device Connection Interrupt Disable Position */ 2814 #define USBHS_HSTIDR_DCONNIEC_Msk (_U_(0x1) << USBHS_HSTIDR_DCONNIEC_Pos) /**< (USBHS_HSTIDR) Device Connection Interrupt Disable Mask */ 2815 #define USBHS_HSTIDR_DCONNIEC USBHS_HSTIDR_DCONNIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DCONNIEC_Msk instead */ 2816 #define USBHS_HSTIDR_DDISCIEC_Pos 1 /**< (USBHS_HSTIDR) Device Disconnection Interrupt Disable Position */ 2817 #define USBHS_HSTIDR_DDISCIEC_Msk (_U_(0x1) << USBHS_HSTIDR_DDISCIEC_Pos) /**< (USBHS_HSTIDR) Device Disconnection Interrupt Disable Mask */ 2818 #define USBHS_HSTIDR_DDISCIEC USBHS_HSTIDR_DDISCIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DDISCIEC_Msk instead */ 2819 #define USBHS_HSTIDR_RSTIEC_Pos 2 /**< (USBHS_HSTIDR) USB Reset Sent Interrupt Disable Position */ 2820 #define USBHS_HSTIDR_RSTIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RSTIEC_Pos) /**< (USBHS_HSTIDR) USB Reset Sent Interrupt Disable Mask */ 2821 #define USBHS_HSTIDR_RSTIEC USBHS_HSTIDR_RSTIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_RSTIEC_Msk instead */ 2822 #define USBHS_HSTIDR_RSMEDIEC_Pos 3 /**< (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable Position */ 2823 #define USBHS_HSTIDR_RSMEDIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RSMEDIEC_Pos) /**< (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable Mask */ 2824 #define USBHS_HSTIDR_RSMEDIEC USBHS_HSTIDR_RSMEDIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_RSMEDIEC_Msk instead */ 2825 #define USBHS_HSTIDR_RXRSMIEC_Pos 4 /**< (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable Position */ 2826 #define USBHS_HSTIDR_RXRSMIEC_Msk (_U_(0x1) << USBHS_HSTIDR_RXRSMIEC_Pos) /**< (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable Mask */ 2827 #define USBHS_HSTIDR_RXRSMIEC USBHS_HSTIDR_RXRSMIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_RXRSMIEC_Msk instead */ 2828 #define USBHS_HSTIDR_HSOFIEC_Pos 5 /**< (USBHS_HSTIDR) Host Start of Frame Interrupt Disable Position */ 2829 #define USBHS_HSTIDR_HSOFIEC_Msk (_U_(0x1) << USBHS_HSTIDR_HSOFIEC_Pos) /**< (USBHS_HSTIDR) Host Start of Frame Interrupt Disable Mask */ 2830 #define USBHS_HSTIDR_HSOFIEC USBHS_HSTIDR_HSOFIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_HSOFIEC_Msk instead */ 2831 #define USBHS_HSTIDR_HWUPIEC_Pos 6 /**< (USBHS_HSTIDR) Host Wake-Up Interrupt Disable Position */ 2832 #define USBHS_HSTIDR_HWUPIEC_Msk (_U_(0x1) << USBHS_HSTIDR_HWUPIEC_Pos) /**< (USBHS_HSTIDR) Host Wake-Up Interrupt Disable Mask */ 2833 #define USBHS_HSTIDR_HWUPIEC USBHS_HSTIDR_HWUPIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_HWUPIEC_Msk instead */ 2834 #define USBHS_HSTIDR_PEP_0_Pos 8 /**< (USBHS_HSTIDR) Pipe 0 Interrupt Disable Position */ 2835 #define USBHS_HSTIDR_PEP_0_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_0_Pos) /**< (USBHS_HSTIDR) Pipe 0 Interrupt Disable Mask */ 2836 #define USBHS_HSTIDR_PEP_0 USBHS_HSTIDR_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_0_Msk instead */ 2837 #define USBHS_HSTIDR_PEP_1_Pos 9 /**< (USBHS_HSTIDR) Pipe 1 Interrupt Disable Position */ 2838 #define USBHS_HSTIDR_PEP_1_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_1_Pos) /**< (USBHS_HSTIDR) Pipe 1 Interrupt Disable Mask */ 2839 #define USBHS_HSTIDR_PEP_1 USBHS_HSTIDR_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_1_Msk instead */ 2840 #define USBHS_HSTIDR_PEP_2_Pos 10 /**< (USBHS_HSTIDR) Pipe 2 Interrupt Disable Position */ 2841 #define USBHS_HSTIDR_PEP_2_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_2_Pos) /**< (USBHS_HSTIDR) Pipe 2 Interrupt Disable Mask */ 2842 #define USBHS_HSTIDR_PEP_2 USBHS_HSTIDR_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_2_Msk instead */ 2843 #define USBHS_HSTIDR_PEP_3_Pos 11 /**< (USBHS_HSTIDR) Pipe 3 Interrupt Disable Position */ 2844 #define USBHS_HSTIDR_PEP_3_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_3_Pos) /**< (USBHS_HSTIDR) Pipe 3 Interrupt Disable Mask */ 2845 #define USBHS_HSTIDR_PEP_3 USBHS_HSTIDR_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_3_Msk instead */ 2846 #define USBHS_HSTIDR_PEP_4_Pos 12 /**< (USBHS_HSTIDR) Pipe 4 Interrupt Disable Position */ 2847 #define USBHS_HSTIDR_PEP_4_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_4_Pos) /**< (USBHS_HSTIDR) Pipe 4 Interrupt Disable Mask */ 2848 #define USBHS_HSTIDR_PEP_4 USBHS_HSTIDR_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_4_Msk instead */ 2849 #define USBHS_HSTIDR_PEP_5_Pos 13 /**< (USBHS_HSTIDR) Pipe 5 Interrupt Disable Position */ 2850 #define USBHS_HSTIDR_PEP_5_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_5_Pos) /**< (USBHS_HSTIDR) Pipe 5 Interrupt Disable Mask */ 2851 #define USBHS_HSTIDR_PEP_5 USBHS_HSTIDR_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_5_Msk instead */ 2852 #define USBHS_HSTIDR_PEP_6_Pos 14 /**< (USBHS_HSTIDR) Pipe 6 Interrupt Disable Position */ 2853 #define USBHS_HSTIDR_PEP_6_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_6_Pos) /**< (USBHS_HSTIDR) Pipe 6 Interrupt Disable Mask */ 2854 #define USBHS_HSTIDR_PEP_6 USBHS_HSTIDR_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_6_Msk instead */ 2855 #define USBHS_HSTIDR_PEP_7_Pos 15 /**< (USBHS_HSTIDR) Pipe 7 Interrupt Disable Position */ 2856 #define USBHS_HSTIDR_PEP_7_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_7_Pos) /**< (USBHS_HSTIDR) Pipe 7 Interrupt Disable Mask */ 2857 #define USBHS_HSTIDR_PEP_7 USBHS_HSTIDR_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_7_Msk instead */ 2858 #define USBHS_HSTIDR_PEP_8_Pos 16 /**< (USBHS_HSTIDR) Pipe 8 Interrupt Disable Position */ 2859 #define USBHS_HSTIDR_PEP_8_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_8_Pos) /**< (USBHS_HSTIDR) Pipe 8 Interrupt Disable Mask */ 2860 #define USBHS_HSTIDR_PEP_8 USBHS_HSTIDR_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_8_Msk instead */ 2861 #define USBHS_HSTIDR_PEP_9_Pos 17 /**< (USBHS_HSTIDR) Pipe 9 Interrupt Disable Position */ 2862 #define USBHS_HSTIDR_PEP_9_Msk (_U_(0x1) << USBHS_HSTIDR_PEP_9_Pos) /**< (USBHS_HSTIDR) Pipe 9 Interrupt Disable Mask */ 2863 #define USBHS_HSTIDR_PEP_9 USBHS_HSTIDR_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_PEP_9_Msk instead */ 2864 #define USBHS_HSTIDR_DMA_0_Pos 25 /**< (USBHS_HSTIDR) DMA Channel 0 Interrupt Disable Position */ 2865 #define USBHS_HSTIDR_DMA_0_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_0_Pos) /**< (USBHS_HSTIDR) DMA Channel 0 Interrupt Disable Mask */ 2866 #define USBHS_HSTIDR_DMA_0 USBHS_HSTIDR_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_0_Msk instead */ 2867 #define USBHS_HSTIDR_DMA_1_Pos 26 /**< (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable Position */ 2868 #define USBHS_HSTIDR_DMA_1_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_1_Pos) /**< (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable Mask */ 2869 #define USBHS_HSTIDR_DMA_1 USBHS_HSTIDR_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_1_Msk instead */ 2870 #define USBHS_HSTIDR_DMA_2_Pos 27 /**< (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable Position */ 2871 #define USBHS_HSTIDR_DMA_2_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_2_Pos) /**< (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable Mask */ 2872 #define USBHS_HSTIDR_DMA_2 USBHS_HSTIDR_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_2_Msk instead */ 2873 #define USBHS_HSTIDR_DMA_3_Pos 28 /**< (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable Position */ 2874 #define USBHS_HSTIDR_DMA_3_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_3_Pos) /**< (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable Mask */ 2875 #define USBHS_HSTIDR_DMA_3 USBHS_HSTIDR_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_3_Msk instead */ 2876 #define USBHS_HSTIDR_DMA_4_Pos 29 /**< (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable Position */ 2877 #define USBHS_HSTIDR_DMA_4_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_4_Pos) /**< (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable Mask */ 2878 #define USBHS_HSTIDR_DMA_4 USBHS_HSTIDR_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_4_Msk instead */ 2879 #define USBHS_HSTIDR_DMA_5_Pos 30 /**< (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable Position */ 2880 #define USBHS_HSTIDR_DMA_5_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_5_Pos) /**< (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable Mask */ 2881 #define USBHS_HSTIDR_DMA_5 USBHS_HSTIDR_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_5_Msk instead */ 2882 #define USBHS_HSTIDR_DMA_6_Pos 31 /**< (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable Position */ 2883 #define USBHS_HSTIDR_DMA_6_Msk (_U_(0x1) << USBHS_HSTIDR_DMA_6_Pos) /**< (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable Mask */ 2884 #define USBHS_HSTIDR_DMA_6 USBHS_HSTIDR_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIDR_DMA_6_Msk instead */ 2885 #define USBHS_HSTIDR_MASK _U_(0xFE03FF7F) /**< \deprecated (USBHS_HSTIDR) Register MASK (Use USBHS_HSTIDR_Msk instead) */ 2886 #define USBHS_HSTIDR_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTIDR) Register Mask */ 2887 2888 #define USBHS_HSTIDR_PEP__Pos 8 /**< (USBHS_HSTIDR Position) Pipe x Interrupt Disable */ 2889 #define USBHS_HSTIDR_PEP__Msk (_U_(0x3FF) << USBHS_HSTIDR_PEP__Pos) /**< (USBHS_HSTIDR Mask) PEP_ */ 2890 #define USBHS_HSTIDR_PEP_(value) (USBHS_HSTIDR_PEP__Msk & ((value) << USBHS_HSTIDR_PEP__Pos)) 2891 #define USBHS_HSTIDR_DMA__Pos 25 /**< (USBHS_HSTIDR Position) DMA Channel 6 Interrupt Disable */ 2892 #define USBHS_HSTIDR_DMA__Msk (_U_(0x7F) << USBHS_HSTIDR_DMA__Pos) /**< (USBHS_HSTIDR Mask) DMA_ */ 2893 #define USBHS_HSTIDR_DMA_(value) (USBHS_HSTIDR_DMA__Msk & ((value) << USBHS_HSTIDR_DMA__Pos)) 2894 2895 /* -------- USBHS_HSTIER : (USBHS Offset: 0x418) (/W 32) Host Global Interrupt Enable Register -------- */ 2896 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2897 #if COMPONENT_TYPEDEF_STYLE == 'N' 2898 typedef union { 2899 struct { 2900 uint32_t DCONNIES:1; /**< bit: 0 Device Connection Interrupt Enable */ 2901 uint32_t DDISCIES:1; /**< bit: 1 Device Disconnection Interrupt Enable */ 2902 uint32_t RSTIES:1; /**< bit: 2 USB Reset Sent Interrupt Enable */ 2903 uint32_t RSMEDIES:1; /**< bit: 3 Downstream Resume Sent Interrupt Enable */ 2904 uint32_t RXRSMIES:1; /**< bit: 4 Upstream Resume Received Interrupt Enable */ 2905 uint32_t HSOFIES:1; /**< bit: 5 Host Start of Frame Interrupt Enable */ 2906 uint32_t HWUPIES:1; /**< bit: 6 Host Wake-Up Interrupt Enable */ 2907 uint32_t :1; /**< bit: 7 Reserved */ 2908 uint32_t PEP_0:1; /**< bit: 8 Pipe 0 Interrupt Enable */ 2909 uint32_t PEP_1:1; /**< bit: 9 Pipe 1 Interrupt Enable */ 2910 uint32_t PEP_2:1; /**< bit: 10 Pipe 2 Interrupt Enable */ 2911 uint32_t PEP_3:1; /**< bit: 11 Pipe 3 Interrupt Enable */ 2912 uint32_t PEP_4:1; /**< bit: 12 Pipe 4 Interrupt Enable */ 2913 uint32_t PEP_5:1; /**< bit: 13 Pipe 5 Interrupt Enable */ 2914 uint32_t PEP_6:1; /**< bit: 14 Pipe 6 Interrupt Enable */ 2915 uint32_t PEP_7:1; /**< bit: 15 Pipe 7 Interrupt Enable */ 2916 uint32_t PEP_8:1; /**< bit: 16 Pipe 8 Interrupt Enable */ 2917 uint32_t PEP_9:1; /**< bit: 17 Pipe 9 Interrupt Enable */ 2918 uint32_t :7; /**< bit: 18..24 Reserved */ 2919 uint32_t DMA_0:1; /**< bit: 25 DMA Channel 0 Interrupt Enable */ 2920 uint32_t DMA_1:1; /**< bit: 26 DMA Channel 1 Interrupt Enable */ 2921 uint32_t DMA_2:1; /**< bit: 27 DMA Channel 2 Interrupt Enable */ 2922 uint32_t DMA_3:1; /**< bit: 28 DMA Channel 3 Interrupt Enable */ 2923 uint32_t DMA_4:1; /**< bit: 29 DMA Channel 4 Interrupt Enable */ 2924 uint32_t DMA_5:1; /**< bit: 30 DMA Channel 5 Interrupt Enable */ 2925 uint32_t DMA_6:1; /**< bit: 31 DMA Channel 6 Interrupt Enable */ 2926 } bit; /**< Structure used for bit access */ 2927 struct { 2928 uint32_t :8; /**< bit: 0..7 Reserved */ 2929 uint32_t PEP_:10; /**< bit: 8..17 Pipe x Interrupt Enable */ 2930 uint32_t :7; /**< bit: 18..24 Reserved */ 2931 uint32_t DMA_:7; /**< bit: 25..31 DMA Channel 6 Interrupt Enable */ 2932 } vec; /**< Structure used for vec access */ 2933 uint32_t reg; /**< Type used for register access */ 2934 } USBHS_HSTIER_Type; 2935 #endif 2936 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2937 2938 #define USBHS_HSTIER_OFFSET (0x418) /**< (USBHS_HSTIER) Host Global Interrupt Enable Register Offset */ 2939 2940 #define USBHS_HSTIER_DCONNIES_Pos 0 /**< (USBHS_HSTIER) Device Connection Interrupt Enable Position */ 2941 #define USBHS_HSTIER_DCONNIES_Msk (_U_(0x1) << USBHS_HSTIER_DCONNIES_Pos) /**< (USBHS_HSTIER) Device Connection Interrupt Enable Mask */ 2942 #define USBHS_HSTIER_DCONNIES USBHS_HSTIER_DCONNIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DCONNIES_Msk instead */ 2943 #define USBHS_HSTIER_DDISCIES_Pos 1 /**< (USBHS_HSTIER) Device Disconnection Interrupt Enable Position */ 2944 #define USBHS_HSTIER_DDISCIES_Msk (_U_(0x1) << USBHS_HSTIER_DDISCIES_Pos) /**< (USBHS_HSTIER) Device Disconnection Interrupt Enable Mask */ 2945 #define USBHS_HSTIER_DDISCIES USBHS_HSTIER_DDISCIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DDISCIES_Msk instead */ 2946 #define USBHS_HSTIER_RSTIES_Pos 2 /**< (USBHS_HSTIER) USB Reset Sent Interrupt Enable Position */ 2947 #define USBHS_HSTIER_RSTIES_Msk (_U_(0x1) << USBHS_HSTIER_RSTIES_Pos) /**< (USBHS_HSTIER) USB Reset Sent Interrupt Enable Mask */ 2948 #define USBHS_HSTIER_RSTIES USBHS_HSTIER_RSTIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_RSTIES_Msk instead */ 2949 #define USBHS_HSTIER_RSMEDIES_Pos 3 /**< (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable Position */ 2950 #define USBHS_HSTIER_RSMEDIES_Msk (_U_(0x1) << USBHS_HSTIER_RSMEDIES_Pos) /**< (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable Mask */ 2951 #define USBHS_HSTIER_RSMEDIES USBHS_HSTIER_RSMEDIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_RSMEDIES_Msk instead */ 2952 #define USBHS_HSTIER_RXRSMIES_Pos 4 /**< (USBHS_HSTIER) Upstream Resume Received Interrupt Enable Position */ 2953 #define USBHS_HSTIER_RXRSMIES_Msk (_U_(0x1) << USBHS_HSTIER_RXRSMIES_Pos) /**< (USBHS_HSTIER) Upstream Resume Received Interrupt Enable Mask */ 2954 #define USBHS_HSTIER_RXRSMIES USBHS_HSTIER_RXRSMIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_RXRSMIES_Msk instead */ 2955 #define USBHS_HSTIER_HSOFIES_Pos 5 /**< (USBHS_HSTIER) Host Start of Frame Interrupt Enable Position */ 2956 #define USBHS_HSTIER_HSOFIES_Msk (_U_(0x1) << USBHS_HSTIER_HSOFIES_Pos) /**< (USBHS_HSTIER) Host Start of Frame Interrupt Enable Mask */ 2957 #define USBHS_HSTIER_HSOFIES USBHS_HSTIER_HSOFIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_HSOFIES_Msk instead */ 2958 #define USBHS_HSTIER_HWUPIES_Pos 6 /**< (USBHS_HSTIER) Host Wake-Up Interrupt Enable Position */ 2959 #define USBHS_HSTIER_HWUPIES_Msk (_U_(0x1) << USBHS_HSTIER_HWUPIES_Pos) /**< (USBHS_HSTIER) Host Wake-Up Interrupt Enable Mask */ 2960 #define USBHS_HSTIER_HWUPIES USBHS_HSTIER_HWUPIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_HWUPIES_Msk instead */ 2961 #define USBHS_HSTIER_PEP_0_Pos 8 /**< (USBHS_HSTIER) Pipe 0 Interrupt Enable Position */ 2962 #define USBHS_HSTIER_PEP_0_Msk (_U_(0x1) << USBHS_HSTIER_PEP_0_Pos) /**< (USBHS_HSTIER) Pipe 0 Interrupt Enable Mask */ 2963 #define USBHS_HSTIER_PEP_0 USBHS_HSTIER_PEP_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_0_Msk instead */ 2964 #define USBHS_HSTIER_PEP_1_Pos 9 /**< (USBHS_HSTIER) Pipe 1 Interrupt Enable Position */ 2965 #define USBHS_HSTIER_PEP_1_Msk (_U_(0x1) << USBHS_HSTIER_PEP_1_Pos) /**< (USBHS_HSTIER) Pipe 1 Interrupt Enable Mask */ 2966 #define USBHS_HSTIER_PEP_1 USBHS_HSTIER_PEP_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_1_Msk instead */ 2967 #define USBHS_HSTIER_PEP_2_Pos 10 /**< (USBHS_HSTIER) Pipe 2 Interrupt Enable Position */ 2968 #define USBHS_HSTIER_PEP_2_Msk (_U_(0x1) << USBHS_HSTIER_PEP_2_Pos) /**< (USBHS_HSTIER) Pipe 2 Interrupt Enable Mask */ 2969 #define USBHS_HSTIER_PEP_2 USBHS_HSTIER_PEP_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_2_Msk instead */ 2970 #define USBHS_HSTIER_PEP_3_Pos 11 /**< (USBHS_HSTIER) Pipe 3 Interrupt Enable Position */ 2971 #define USBHS_HSTIER_PEP_3_Msk (_U_(0x1) << USBHS_HSTIER_PEP_3_Pos) /**< (USBHS_HSTIER) Pipe 3 Interrupt Enable Mask */ 2972 #define USBHS_HSTIER_PEP_3 USBHS_HSTIER_PEP_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_3_Msk instead */ 2973 #define USBHS_HSTIER_PEP_4_Pos 12 /**< (USBHS_HSTIER) Pipe 4 Interrupt Enable Position */ 2974 #define USBHS_HSTIER_PEP_4_Msk (_U_(0x1) << USBHS_HSTIER_PEP_4_Pos) /**< (USBHS_HSTIER) Pipe 4 Interrupt Enable Mask */ 2975 #define USBHS_HSTIER_PEP_4 USBHS_HSTIER_PEP_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_4_Msk instead */ 2976 #define USBHS_HSTIER_PEP_5_Pos 13 /**< (USBHS_HSTIER) Pipe 5 Interrupt Enable Position */ 2977 #define USBHS_HSTIER_PEP_5_Msk (_U_(0x1) << USBHS_HSTIER_PEP_5_Pos) /**< (USBHS_HSTIER) Pipe 5 Interrupt Enable Mask */ 2978 #define USBHS_HSTIER_PEP_5 USBHS_HSTIER_PEP_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_5_Msk instead */ 2979 #define USBHS_HSTIER_PEP_6_Pos 14 /**< (USBHS_HSTIER) Pipe 6 Interrupt Enable Position */ 2980 #define USBHS_HSTIER_PEP_6_Msk (_U_(0x1) << USBHS_HSTIER_PEP_6_Pos) /**< (USBHS_HSTIER) Pipe 6 Interrupt Enable Mask */ 2981 #define USBHS_HSTIER_PEP_6 USBHS_HSTIER_PEP_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_6_Msk instead */ 2982 #define USBHS_HSTIER_PEP_7_Pos 15 /**< (USBHS_HSTIER) Pipe 7 Interrupt Enable Position */ 2983 #define USBHS_HSTIER_PEP_7_Msk (_U_(0x1) << USBHS_HSTIER_PEP_7_Pos) /**< (USBHS_HSTIER) Pipe 7 Interrupt Enable Mask */ 2984 #define USBHS_HSTIER_PEP_7 USBHS_HSTIER_PEP_7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_7_Msk instead */ 2985 #define USBHS_HSTIER_PEP_8_Pos 16 /**< (USBHS_HSTIER) Pipe 8 Interrupt Enable Position */ 2986 #define USBHS_HSTIER_PEP_8_Msk (_U_(0x1) << USBHS_HSTIER_PEP_8_Pos) /**< (USBHS_HSTIER) Pipe 8 Interrupt Enable Mask */ 2987 #define USBHS_HSTIER_PEP_8 USBHS_HSTIER_PEP_8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_8_Msk instead */ 2988 #define USBHS_HSTIER_PEP_9_Pos 17 /**< (USBHS_HSTIER) Pipe 9 Interrupt Enable Position */ 2989 #define USBHS_HSTIER_PEP_9_Msk (_U_(0x1) << USBHS_HSTIER_PEP_9_Pos) /**< (USBHS_HSTIER) Pipe 9 Interrupt Enable Mask */ 2990 #define USBHS_HSTIER_PEP_9 USBHS_HSTIER_PEP_9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_PEP_9_Msk instead */ 2991 #define USBHS_HSTIER_DMA_0_Pos 25 /**< (USBHS_HSTIER) DMA Channel 0 Interrupt Enable Position */ 2992 #define USBHS_HSTIER_DMA_0_Msk (_U_(0x1) << USBHS_HSTIER_DMA_0_Pos) /**< (USBHS_HSTIER) DMA Channel 0 Interrupt Enable Mask */ 2993 #define USBHS_HSTIER_DMA_0 USBHS_HSTIER_DMA_0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_0_Msk instead */ 2994 #define USBHS_HSTIER_DMA_1_Pos 26 /**< (USBHS_HSTIER) DMA Channel 1 Interrupt Enable Position */ 2995 #define USBHS_HSTIER_DMA_1_Msk (_U_(0x1) << USBHS_HSTIER_DMA_1_Pos) /**< (USBHS_HSTIER) DMA Channel 1 Interrupt Enable Mask */ 2996 #define USBHS_HSTIER_DMA_1 USBHS_HSTIER_DMA_1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_1_Msk instead */ 2997 #define USBHS_HSTIER_DMA_2_Pos 27 /**< (USBHS_HSTIER) DMA Channel 2 Interrupt Enable Position */ 2998 #define USBHS_HSTIER_DMA_2_Msk (_U_(0x1) << USBHS_HSTIER_DMA_2_Pos) /**< (USBHS_HSTIER) DMA Channel 2 Interrupt Enable Mask */ 2999 #define USBHS_HSTIER_DMA_2 USBHS_HSTIER_DMA_2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_2_Msk instead */ 3000 #define USBHS_HSTIER_DMA_3_Pos 28 /**< (USBHS_HSTIER) DMA Channel 3 Interrupt Enable Position */ 3001 #define USBHS_HSTIER_DMA_3_Msk (_U_(0x1) << USBHS_HSTIER_DMA_3_Pos) /**< (USBHS_HSTIER) DMA Channel 3 Interrupt Enable Mask */ 3002 #define USBHS_HSTIER_DMA_3 USBHS_HSTIER_DMA_3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_3_Msk instead */ 3003 #define USBHS_HSTIER_DMA_4_Pos 29 /**< (USBHS_HSTIER) DMA Channel 4 Interrupt Enable Position */ 3004 #define USBHS_HSTIER_DMA_4_Msk (_U_(0x1) << USBHS_HSTIER_DMA_4_Pos) /**< (USBHS_HSTIER) DMA Channel 4 Interrupt Enable Mask */ 3005 #define USBHS_HSTIER_DMA_4 USBHS_HSTIER_DMA_4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_4_Msk instead */ 3006 #define USBHS_HSTIER_DMA_5_Pos 30 /**< (USBHS_HSTIER) DMA Channel 5 Interrupt Enable Position */ 3007 #define USBHS_HSTIER_DMA_5_Msk (_U_(0x1) << USBHS_HSTIER_DMA_5_Pos) /**< (USBHS_HSTIER) DMA Channel 5 Interrupt Enable Mask */ 3008 #define USBHS_HSTIER_DMA_5 USBHS_HSTIER_DMA_5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_5_Msk instead */ 3009 #define USBHS_HSTIER_DMA_6_Pos 31 /**< (USBHS_HSTIER) DMA Channel 6 Interrupt Enable Position */ 3010 #define USBHS_HSTIER_DMA_6_Msk (_U_(0x1) << USBHS_HSTIER_DMA_6_Pos) /**< (USBHS_HSTIER) DMA Channel 6 Interrupt Enable Mask */ 3011 #define USBHS_HSTIER_DMA_6 USBHS_HSTIER_DMA_6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTIER_DMA_6_Msk instead */ 3012 #define USBHS_HSTIER_MASK _U_(0xFE03FF7F) /**< \deprecated (USBHS_HSTIER) Register MASK (Use USBHS_HSTIER_Msk instead) */ 3013 #define USBHS_HSTIER_Msk _U_(0xFE03FF7F) /**< (USBHS_HSTIER) Register Mask */ 3014 3015 #define USBHS_HSTIER_PEP__Pos 8 /**< (USBHS_HSTIER Position) Pipe x Interrupt Enable */ 3016 #define USBHS_HSTIER_PEP__Msk (_U_(0x3FF) << USBHS_HSTIER_PEP__Pos) /**< (USBHS_HSTIER Mask) PEP_ */ 3017 #define USBHS_HSTIER_PEP_(value) (USBHS_HSTIER_PEP__Msk & ((value) << USBHS_HSTIER_PEP__Pos)) 3018 #define USBHS_HSTIER_DMA__Pos 25 /**< (USBHS_HSTIER Position) DMA Channel 6 Interrupt Enable */ 3019 #define USBHS_HSTIER_DMA__Msk (_U_(0x7F) << USBHS_HSTIER_DMA__Pos) /**< (USBHS_HSTIER Mask) DMA_ */ 3020 #define USBHS_HSTIER_DMA_(value) (USBHS_HSTIER_DMA__Msk & ((value) << USBHS_HSTIER_DMA__Pos)) 3021 3022 /* -------- USBHS_HSTPIP : (USBHS Offset: 0x41c) (R/W 32) Host Pipe Register -------- */ 3023 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3024 #if COMPONENT_TYPEDEF_STYLE == 'N' 3025 typedef union { 3026 struct { 3027 uint32_t PEN0:1; /**< bit: 0 Pipe 0 Enable */ 3028 uint32_t PEN1:1; /**< bit: 1 Pipe 1 Enable */ 3029 uint32_t PEN2:1; /**< bit: 2 Pipe 2 Enable */ 3030 uint32_t PEN3:1; /**< bit: 3 Pipe 3 Enable */ 3031 uint32_t PEN4:1; /**< bit: 4 Pipe 4 Enable */ 3032 uint32_t PEN5:1; /**< bit: 5 Pipe 5 Enable */ 3033 uint32_t PEN6:1; /**< bit: 6 Pipe 6 Enable */ 3034 uint32_t PEN7:1; /**< bit: 7 Pipe 7 Enable */ 3035 uint32_t PEN8:1; /**< bit: 8 Pipe 8 Enable */ 3036 uint32_t :7; /**< bit: 9..15 Reserved */ 3037 uint32_t PRST0:1; /**< bit: 16 Pipe 0 Reset */ 3038 uint32_t PRST1:1; /**< bit: 17 Pipe 1 Reset */ 3039 uint32_t PRST2:1; /**< bit: 18 Pipe 2 Reset */ 3040 uint32_t PRST3:1; /**< bit: 19 Pipe 3 Reset */ 3041 uint32_t PRST4:1; /**< bit: 20 Pipe 4 Reset */ 3042 uint32_t PRST5:1; /**< bit: 21 Pipe 5 Reset */ 3043 uint32_t PRST6:1; /**< bit: 22 Pipe 6 Reset */ 3044 uint32_t PRST7:1; /**< bit: 23 Pipe 7 Reset */ 3045 uint32_t PRST8:1; /**< bit: 24 Pipe 8 Reset */ 3046 uint32_t :7; /**< bit: 25..31 Reserved */ 3047 } bit; /**< Structure used for bit access */ 3048 struct { 3049 uint32_t PEN:9; /**< bit: 0..8 Pipe x Enable */ 3050 uint32_t :7; /**< bit: 9..15 Reserved */ 3051 uint32_t PRST:9; /**< bit: 16..24 Pipe 8 Reset */ 3052 uint32_t :7; /**< bit: 25..31 Reserved */ 3053 } vec; /**< Structure used for vec access */ 3054 uint32_t reg; /**< Type used for register access */ 3055 } USBHS_HSTPIP_Type; 3056 #endif 3057 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3058 3059 #define USBHS_HSTPIP_OFFSET (0x41C) /**< (USBHS_HSTPIP) Host Pipe Register Offset */ 3060 3061 #define USBHS_HSTPIP_PEN0_Pos 0 /**< (USBHS_HSTPIP) Pipe 0 Enable Position */ 3062 #define USBHS_HSTPIP_PEN0_Msk (_U_(0x1) << USBHS_HSTPIP_PEN0_Pos) /**< (USBHS_HSTPIP) Pipe 0 Enable Mask */ 3063 #define USBHS_HSTPIP_PEN0 USBHS_HSTPIP_PEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN0_Msk instead */ 3064 #define USBHS_HSTPIP_PEN1_Pos 1 /**< (USBHS_HSTPIP) Pipe 1 Enable Position */ 3065 #define USBHS_HSTPIP_PEN1_Msk (_U_(0x1) << USBHS_HSTPIP_PEN1_Pos) /**< (USBHS_HSTPIP) Pipe 1 Enable Mask */ 3066 #define USBHS_HSTPIP_PEN1 USBHS_HSTPIP_PEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN1_Msk instead */ 3067 #define USBHS_HSTPIP_PEN2_Pos 2 /**< (USBHS_HSTPIP) Pipe 2 Enable Position */ 3068 #define USBHS_HSTPIP_PEN2_Msk (_U_(0x1) << USBHS_HSTPIP_PEN2_Pos) /**< (USBHS_HSTPIP) Pipe 2 Enable Mask */ 3069 #define USBHS_HSTPIP_PEN2 USBHS_HSTPIP_PEN2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN2_Msk instead */ 3070 #define USBHS_HSTPIP_PEN3_Pos 3 /**< (USBHS_HSTPIP) Pipe 3 Enable Position */ 3071 #define USBHS_HSTPIP_PEN3_Msk (_U_(0x1) << USBHS_HSTPIP_PEN3_Pos) /**< (USBHS_HSTPIP) Pipe 3 Enable Mask */ 3072 #define USBHS_HSTPIP_PEN3 USBHS_HSTPIP_PEN3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN3_Msk instead */ 3073 #define USBHS_HSTPIP_PEN4_Pos 4 /**< (USBHS_HSTPIP) Pipe 4 Enable Position */ 3074 #define USBHS_HSTPIP_PEN4_Msk (_U_(0x1) << USBHS_HSTPIP_PEN4_Pos) /**< (USBHS_HSTPIP) Pipe 4 Enable Mask */ 3075 #define USBHS_HSTPIP_PEN4 USBHS_HSTPIP_PEN4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN4_Msk instead */ 3076 #define USBHS_HSTPIP_PEN5_Pos 5 /**< (USBHS_HSTPIP) Pipe 5 Enable Position */ 3077 #define USBHS_HSTPIP_PEN5_Msk (_U_(0x1) << USBHS_HSTPIP_PEN5_Pos) /**< (USBHS_HSTPIP) Pipe 5 Enable Mask */ 3078 #define USBHS_HSTPIP_PEN5 USBHS_HSTPIP_PEN5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN5_Msk instead */ 3079 #define USBHS_HSTPIP_PEN6_Pos 6 /**< (USBHS_HSTPIP) Pipe 6 Enable Position */ 3080 #define USBHS_HSTPIP_PEN6_Msk (_U_(0x1) << USBHS_HSTPIP_PEN6_Pos) /**< (USBHS_HSTPIP) Pipe 6 Enable Mask */ 3081 #define USBHS_HSTPIP_PEN6 USBHS_HSTPIP_PEN6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN6_Msk instead */ 3082 #define USBHS_HSTPIP_PEN7_Pos 7 /**< (USBHS_HSTPIP) Pipe 7 Enable Position */ 3083 #define USBHS_HSTPIP_PEN7_Msk (_U_(0x1) << USBHS_HSTPIP_PEN7_Pos) /**< (USBHS_HSTPIP) Pipe 7 Enable Mask */ 3084 #define USBHS_HSTPIP_PEN7 USBHS_HSTPIP_PEN7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN7_Msk instead */ 3085 #define USBHS_HSTPIP_PEN8_Pos 8 /**< (USBHS_HSTPIP) Pipe 8 Enable Position */ 3086 #define USBHS_HSTPIP_PEN8_Msk (_U_(0x1) << USBHS_HSTPIP_PEN8_Pos) /**< (USBHS_HSTPIP) Pipe 8 Enable Mask */ 3087 #define USBHS_HSTPIP_PEN8 USBHS_HSTPIP_PEN8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PEN8_Msk instead */ 3088 #define USBHS_HSTPIP_PRST0_Pos 16 /**< (USBHS_HSTPIP) Pipe 0 Reset Position */ 3089 #define USBHS_HSTPIP_PRST0_Msk (_U_(0x1) << USBHS_HSTPIP_PRST0_Pos) /**< (USBHS_HSTPIP) Pipe 0 Reset Mask */ 3090 #define USBHS_HSTPIP_PRST0 USBHS_HSTPIP_PRST0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST0_Msk instead */ 3091 #define USBHS_HSTPIP_PRST1_Pos 17 /**< (USBHS_HSTPIP) Pipe 1 Reset Position */ 3092 #define USBHS_HSTPIP_PRST1_Msk (_U_(0x1) << USBHS_HSTPIP_PRST1_Pos) /**< (USBHS_HSTPIP) Pipe 1 Reset Mask */ 3093 #define USBHS_HSTPIP_PRST1 USBHS_HSTPIP_PRST1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST1_Msk instead */ 3094 #define USBHS_HSTPIP_PRST2_Pos 18 /**< (USBHS_HSTPIP) Pipe 2 Reset Position */ 3095 #define USBHS_HSTPIP_PRST2_Msk (_U_(0x1) << USBHS_HSTPIP_PRST2_Pos) /**< (USBHS_HSTPIP) Pipe 2 Reset Mask */ 3096 #define USBHS_HSTPIP_PRST2 USBHS_HSTPIP_PRST2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST2_Msk instead */ 3097 #define USBHS_HSTPIP_PRST3_Pos 19 /**< (USBHS_HSTPIP) Pipe 3 Reset Position */ 3098 #define USBHS_HSTPIP_PRST3_Msk (_U_(0x1) << USBHS_HSTPIP_PRST3_Pos) /**< (USBHS_HSTPIP) Pipe 3 Reset Mask */ 3099 #define USBHS_HSTPIP_PRST3 USBHS_HSTPIP_PRST3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST3_Msk instead */ 3100 #define USBHS_HSTPIP_PRST4_Pos 20 /**< (USBHS_HSTPIP) Pipe 4 Reset Position */ 3101 #define USBHS_HSTPIP_PRST4_Msk (_U_(0x1) << USBHS_HSTPIP_PRST4_Pos) /**< (USBHS_HSTPIP) Pipe 4 Reset Mask */ 3102 #define USBHS_HSTPIP_PRST4 USBHS_HSTPIP_PRST4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST4_Msk instead */ 3103 #define USBHS_HSTPIP_PRST5_Pos 21 /**< (USBHS_HSTPIP) Pipe 5 Reset Position */ 3104 #define USBHS_HSTPIP_PRST5_Msk (_U_(0x1) << USBHS_HSTPIP_PRST5_Pos) /**< (USBHS_HSTPIP) Pipe 5 Reset Mask */ 3105 #define USBHS_HSTPIP_PRST5 USBHS_HSTPIP_PRST5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST5_Msk instead */ 3106 #define USBHS_HSTPIP_PRST6_Pos 22 /**< (USBHS_HSTPIP) Pipe 6 Reset Position */ 3107 #define USBHS_HSTPIP_PRST6_Msk (_U_(0x1) << USBHS_HSTPIP_PRST6_Pos) /**< (USBHS_HSTPIP) Pipe 6 Reset Mask */ 3108 #define USBHS_HSTPIP_PRST6 USBHS_HSTPIP_PRST6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST6_Msk instead */ 3109 #define USBHS_HSTPIP_PRST7_Pos 23 /**< (USBHS_HSTPIP) Pipe 7 Reset Position */ 3110 #define USBHS_HSTPIP_PRST7_Msk (_U_(0x1) << USBHS_HSTPIP_PRST7_Pos) /**< (USBHS_HSTPIP) Pipe 7 Reset Mask */ 3111 #define USBHS_HSTPIP_PRST7 USBHS_HSTPIP_PRST7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST7_Msk instead */ 3112 #define USBHS_HSTPIP_PRST8_Pos 24 /**< (USBHS_HSTPIP) Pipe 8 Reset Position */ 3113 #define USBHS_HSTPIP_PRST8_Msk (_U_(0x1) << USBHS_HSTPIP_PRST8_Pos) /**< (USBHS_HSTPIP) Pipe 8 Reset Mask */ 3114 #define USBHS_HSTPIP_PRST8 USBHS_HSTPIP_PRST8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIP_PRST8_Msk instead */ 3115 #define USBHS_HSTPIP_MASK _U_(0x1FF01FF) /**< \deprecated (USBHS_HSTPIP) Register MASK (Use USBHS_HSTPIP_Msk instead) */ 3116 #define USBHS_HSTPIP_Msk _U_(0x1FF01FF) /**< (USBHS_HSTPIP) Register Mask */ 3117 3118 #define USBHS_HSTPIP_PEN_Pos 0 /**< (USBHS_HSTPIP Position) Pipe x Enable */ 3119 #define USBHS_HSTPIP_PEN_Msk (_U_(0x1FF) << USBHS_HSTPIP_PEN_Pos) /**< (USBHS_HSTPIP Mask) PEN */ 3120 #define USBHS_HSTPIP_PEN(value) (USBHS_HSTPIP_PEN_Msk & ((value) << USBHS_HSTPIP_PEN_Pos)) 3121 #define USBHS_HSTPIP_PRST_Pos 16 /**< (USBHS_HSTPIP Position) Pipe 8 Reset */ 3122 #define USBHS_HSTPIP_PRST_Msk (_U_(0x1FF) << USBHS_HSTPIP_PRST_Pos) /**< (USBHS_HSTPIP Mask) PRST */ 3123 #define USBHS_HSTPIP_PRST(value) (USBHS_HSTPIP_PRST_Msk & ((value) << USBHS_HSTPIP_PRST_Pos)) 3124 3125 /* -------- USBHS_HSTFNUM : (USBHS Offset: 0x420) (R/W 32) Host Frame Number Register -------- */ 3126 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3127 #if COMPONENT_TYPEDEF_STYLE == 'N' 3128 typedef union { 3129 struct { 3130 uint32_t MFNUM:3; /**< bit: 0..2 Micro Frame Number */ 3131 uint32_t FNUM:11; /**< bit: 3..13 Frame Number */ 3132 uint32_t :2; /**< bit: 14..15 Reserved */ 3133 uint32_t FLENHIGH:8; /**< bit: 16..23 Frame Length */ 3134 uint32_t :8; /**< bit: 24..31 Reserved */ 3135 } bit; /**< Structure used for bit access */ 3136 uint32_t reg; /**< Type used for register access */ 3137 } USBHS_HSTFNUM_Type; 3138 #endif 3139 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3140 3141 #define USBHS_HSTFNUM_OFFSET (0x420) /**< (USBHS_HSTFNUM) Host Frame Number Register Offset */ 3142 3143 #define USBHS_HSTFNUM_MFNUM_Pos 0 /**< (USBHS_HSTFNUM) Micro Frame Number Position */ 3144 #define USBHS_HSTFNUM_MFNUM_Msk (_U_(0x7) << USBHS_HSTFNUM_MFNUM_Pos) /**< (USBHS_HSTFNUM) Micro Frame Number Mask */ 3145 #define USBHS_HSTFNUM_MFNUM(value) (USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos)) 3146 #define USBHS_HSTFNUM_FNUM_Pos 3 /**< (USBHS_HSTFNUM) Frame Number Position */ 3147 #define USBHS_HSTFNUM_FNUM_Msk (_U_(0x7FF) << USBHS_HSTFNUM_FNUM_Pos) /**< (USBHS_HSTFNUM) Frame Number Mask */ 3148 #define USBHS_HSTFNUM_FNUM(value) (USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos)) 3149 #define USBHS_HSTFNUM_FLENHIGH_Pos 16 /**< (USBHS_HSTFNUM) Frame Length Position */ 3150 #define USBHS_HSTFNUM_FLENHIGH_Msk (_U_(0xFF) << USBHS_HSTFNUM_FLENHIGH_Pos) /**< (USBHS_HSTFNUM) Frame Length Mask */ 3151 #define USBHS_HSTFNUM_FLENHIGH(value) (USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos)) 3152 #define USBHS_HSTFNUM_MASK _U_(0xFF3FFF) /**< \deprecated (USBHS_HSTFNUM) Register MASK (Use USBHS_HSTFNUM_Msk instead) */ 3153 #define USBHS_HSTFNUM_Msk _U_(0xFF3FFF) /**< (USBHS_HSTFNUM) Register Mask */ 3154 3155 3156 /* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x424) (R/W 32) Host Address 1 Register -------- */ 3157 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3158 #if COMPONENT_TYPEDEF_STYLE == 'N' 3159 typedef union { 3160 struct { 3161 uint32_t HSTADDRP0:7; /**< bit: 0..6 USB Host Address */ 3162 uint32_t :1; /**< bit: 7 Reserved */ 3163 uint32_t HSTADDRP1:7; /**< bit: 8..14 USB Host Address */ 3164 uint32_t :1; /**< bit: 15 Reserved */ 3165 uint32_t HSTADDRP2:7; /**< bit: 16..22 USB Host Address */ 3166 uint32_t :1; /**< bit: 23 Reserved */ 3167 uint32_t HSTADDRP3:7; /**< bit: 24..30 USB Host Address */ 3168 uint32_t :1; /**< bit: 31 Reserved */ 3169 } bit; /**< Structure used for bit access */ 3170 uint32_t reg; /**< Type used for register access */ 3171 } USBHS_HSTADDR1_Type; 3172 #endif 3173 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3174 3175 #define USBHS_HSTADDR1_OFFSET (0x424) /**< (USBHS_HSTADDR1) Host Address 1 Register Offset */ 3176 3177 #define USBHS_HSTADDR1_HSTADDRP0_Pos 0 /**< (USBHS_HSTADDR1) USB Host Address Position */ 3178 #define USBHS_HSTADDR1_HSTADDRP0_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ 3179 #define USBHS_HSTADDR1_HSTADDRP0(value) (USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos)) 3180 #define USBHS_HSTADDR1_HSTADDRP1_Pos 8 /**< (USBHS_HSTADDR1) USB Host Address Position */ 3181 #define USBHS_HSTADDR1_HSTADDRP1_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ 3182 #define USBHS_HSTADDR1_HSTADDRP1(value) (USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos)) 3183 #define USBHS_HSTADDR1_HSTADDRP2_Pos 16 /**< (USBHS_HSTADDR1) USB Host Address Position */ 3184 #define USBHS_HSTADDR1_HSTADDRP2_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ 3185 #define USBHS_HSTADDR1_HSTADDRP2(value) (USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos)) 3186 #define USBHS_HSTADDR1_HSTADDRP3_Pos 24 /**< (USBHS_HSTADDR1) USB Host Address Position */ 3187 #define USBHS_HSTADDR1_HSTADDRP3_Msk (_U_(0x7F) << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< (USBHS_HSTADDR1) USB Host Address Mask */ 3188 #define USBHS_HSTADDR1_HSTADDRP3(value) (USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos)) 3189 #define USBHS_HSTADDR1_MASK _U_(0x7F7F7F7F) /**< \deprecated (USBHS_HSTADDR1) Register MASK (Use USBHS_HSTADDR1_Msk instead) */ 3190 #define USBHS_HSTADDR1_Msk _U_(0x7F7F7F7F) /**< (USBHS_HSTADDR1) Register Mask */ 3191 3192 3193 /* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x428) (R/W 32) Host Address 2 Register -------- */ 3194 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3195 #if COMPONENT_TYPEDEF_STYLE == 'N' 3196 typedef union { 3197 struct { 3198 uint32_t HSTADDRP4:7; /**< bit: 0..6 USB Host Address */ 3199 uint32_t :1; /**< bit: 7 Reserved */ 3200 uint32_t HSTADDRP5:7; /**< bit: 8..14 USB Host Address */ 3201 uint32_t :1; /**< bit: 15 Reserved */ 3202 uint32_t HSTADDRP6:7; /**< bit: 16..22 USB Host Address */ 3203 uint32_t :1; /**< bit: 23 Reserved */ 3204 uint32_t HSTADDRP7:7; /**< bit: 24..30 USB Host Address */ 3205 uint32_t :1; /**< bit: 31 Reserved */ 3206 } bit; /**< Structure used for bit access */ 3207 uint32_t reg; /**< Type used for register access */ 3208 } USBHS_HSTADDR2_Type; 3209 #endif 3210 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3211 3212 #define USBHS_HSTADDR2_OFFSET (0x428) /**< (USBHS_HSTADDR2) Host Address 2 Register Offset */ 3213 3214 #define USBHS_HSTADDR2_HSTADDRP4_Pos 0 /**< (USBHS_HSTADDR2) USB Host Address Position */ 3215 #define USBHS_HSTADDR2_HSTADDRP4_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ 3216 #define USBHS_HSTADDR2_HSTADDRP4(value) (USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos)) 3217 #define USBHS_HSTADDR2_HSTADDRP5_Pos 8 /**< (USBHS_HSTADDR2) USB Host Address Position */ 3218 #define USBHS_HSTADDR2_HSTADDRP5_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ 3219 #define USBHS_HSTADDR2_HSTADDRP5(value) (USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos)) 3220 #define USBHS_HSTADDR2_HSTADDRP6_Pos 16 /**< (USBHS_HSTADDR2) USB Host Address Position */ 3221 #define USBHS_HSTADDR2_HSTADDRP6_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ 3222 #define USBHS_HSTADDR2_HSTADDRP6(value) (USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos)) 3223 #define USBHS_HSTADDR2_HSTADDRP7_Pos 24 /**< (USBHS_HSTADDR2) USB Host Address Position */ 3224 #define USBHS_HSTADDR2_HSTADDRP7_Msk (_U_(0x7F) << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< (USBHS_HSTADDR2) USB Host Address Mask */ 3225 #define USBHS_HSTADDR2_HSTADDRP7(value) (USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos)) 3226 #define USBHS_HSTADDR2_MASK _U_(0x7F7F7F7F) /**< \deprecated (USBHS_HSTADDR2) Register MASK (Use USBHS_HSTADDR2_Msk instead) */ 3227 #define USBHS_HSTADDR2_Msk _U_(0x7F7F7F7F) /**< (USBHS_HSTADDR2) Register Mask */ 3228 3229 3230 /* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x42c) (R/W 32) Host Address 3 Register -------- */ 3231 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3232 #if COMPONENT_TYPEDEF_STYLE == 'N' 3233 typedef union { 3234 struct { 3235 uint32_t HSTADDRP8:7; /**< bit: 0..6 USB Host Address */ 3236 uint32_t :1; /**< bit: 7 Reserved */ 3237 uint32_t HSTADDRP9:7; /**< bit: 8..14 USB Host Address */ 3238 uint32_t :17; /**< bit: 15..31 Reserved */ 3239 } bit; /**< Structure used for bit access */ 3240 uint32_t reg; /**< Type used for register access */ 3241 } USBHS_HSTADDR3_Type; 3242 #endif 3243 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3244 3245 #define USBHS_HSTADDR3_OFFSET (0x42C) /**< (USBHS_HSTADDR3) Host Address 3 Register Offset */ 3246 3247 #define USBHS_HSTADDR3_HSTADDRP8_Pos 0 /**< (USBHS_HSTADDR3) USB Host Address Position */ 3248 #define USBHS_HSTADDR3_HSTADDRP8_Msk (_U_(0x7F) << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< (USBHS_HSTADDR3) USB Host Address Mask */ 3249 #define USBHS_HSTADDR3_HSTADDRP8(value) (USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos)) 3250 #define USBHS_HSTADDR3_HSTADDRP9_Pos 8 /**< (USBHS_HSTADDR3) USB Host Address Position */ 3251 #define USBHS_HSTADDR3_HSTADDRP9_Msk (_U_(0x7F) << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< (USBHS_HSTADDR3) USB Host Address Mask */ 3252 #define USBHS_HSTADDR3_HSTADDRP9(value) (USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos)) 3253 #define USBHS_HSTADDR3_MASK _U_(0x7F7F) /**< \deprecated (USBHS_HSTADDR3) Register MASK (Use USBHS_HSTADDR3_Msk instead) */ 3254 #define USBHS_HSTADDR3_Msk _U_(0x7F7F) /**< (USBHS_HSTADDR3) Register Mask */ 3255 3256 3257 /* -------- USBHS_HSTPIPCFG : (USBHS Offset: 0x500) (R/W 32) Host Pipe Configuration Register -------- */ 3258 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3259 #if COMPONENT_TYPEDEF_STYLE == 'N' 3260 typedef union { 3261 struct { 3262 uint32_t :1; /**< bit: 0 Reserved */ 3263 uint32_t ALLOC:1; /**< bit: 1 Pipe Memory Allocate */ 3264 uint32_t PBK:2; /**< bit: 2..3 Pipe Banks */ 3265 uint32_t PSIZE:3; /**< bit: 4..6 Pipe Size */ 3266 uint32_t :1; /**< bit: 7 Reserved */ 3267 uint32_t PTOKEN:2; /**< bit: 8..9 Pipe Token */ 3268 uint32_t AUTOSW:1; /**< bit: 10 Automatic Switch */ 3269 uint32_t :1; /**< bit: 11 Reserved */ 3270 uint32_t PTYPE:2; /**< bit: 12..13 Pipe Type */ 3271 uint32_t :2; /**< bit: 14..15 Reserved */ 3272 uint32_t PEPNUM:4; /**< bit: 16..19 Pipe Endpoint Number */ 3273 uint32_t :4; /**< bit: 20..23 Reserved */ 3274 uint32_t INTFRQ:8; /**< bit: 24..31 Pipe Interrupt Request Frequency */ 3275 } bit; /**< Structure used for bit access */ 3276 struct { // CTRL_BULK mode 3277 uint32_t :20; /**< bit: 0..19 Reserved */ 3278 uint32_t PINGEN:1; /**< bit: 20 Ping Enable */ 3279 uint32_t :3; /**< bit: 21..23 Reserved */ 3280 uint32_t BINTERVAL:8; /**< bit: 24..31 bInterval Parameter for the Bulk-Out/Ping Transaction */ 3281 } CTRL_BULK; /**< Structure used for CTRL_BULK mode access */ 3282 uint32_t reg; /**< Type used for register access */ 3283 } USBHS_HSTPIPCFG_Type; 3284 #endif 3285 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3286 3287 #define USBHS_HSTPIPCFG_OFFSET (0x500) /**< (USBHS_HSTPIPCFG) Host Pipe Configuration Register Offset */ 3288 3289 #define USBHS_HSTPIPCFG_ALLOC_Pos 1 /**< (USBHS_HSTPIPCFG) Pipe Memory Allocate Position */ 3290 #define USBHS_HSTPIPCFG_ALLOC_Msk (_U_(0x1) << USBHS_HSTPIPCFG_ALLOC_Pos) /**< (USBHS_HSTPIPCFG) Pipe Memory Allocate Mask */ 3291 #define USBHS_HSTPIPCFG_ALLOC USBHS_HSTPIPCFG_ALLOC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPCFG_ALLOC_Msk instead */ 3292 #define USBHS_HSTPIPCFG_PBK_Pos 2 /**< (USBHS_HSTPIPCFG) Pipe Banks Position */ 3293 #define USBHS_HSTPIPCFG_PBK_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Pipe Banks Mask */ 3294 #define USBHS_HSTPIPCFG_PBK(value) (USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos)) 3295 #define USBHS_HSTPIPCFG_PBK_1_BANK_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) Single-bank pipe */ 3296 #define USBHS_HSTPIPCFG_PBK_2_BANK_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) Double-bank pipe */ 3297 #define USBHS_HSTPIPCFG_PBK_3_BANK_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) Triple-bank pipe */ 3298 #define USBHS_HSTPIPCFG_PBK_1_BANK (USBHS_HSTPIPCFG_PBK_1_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Single-bank pipe Position */ 3299 #define USBHS_HSTPIPCFG_PBK_2_BANK (USBHS_HSTPIPCFG_PBK_2_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Double-bank pipe Position */ 3300 #define USBHS_HSTPIPCFG_PBK_3_BANK (USBHS_HSTPIPCFG_PBK_3_BANK_Val << USBHS_HSTPIPCFG_PBK_Pos) /**< (USBHS_HSTPIPCFG) Triple-bank pipe Position */ 3301 #define USBHS_HSTPIPCFG_PSIZE_Pos 4 /**< (USBHS_HSTPIPCFG) Pipe Size Position */ 3302 #define USBHS_HSTPIPCFG_PSIZE_Msk (_U_(0x7) << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) Pipe Size Mask */ 3303 #define USBHS_HSTPIPCFG_PSIZE(value) (USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos)) 3304 #define USBHS_HSTPIPCFG_PSIZE_8_BYTE_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) 8 bytes */ 3305 #define USBHS_HSTPIPCFG_PSIZE_16_BYTE_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) 16 bytes */ 3306 #define USBHS_HSTPIPCFG_PSIZE_32_BYTE_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) 32 bytes */ 3307 #define USBHS_HSTPIPCFG_PSIZE_64_BYTE_Val _U_(0x3) /**< (USBHS_HSTPIPCFG) 64 bytes */ 3308 #define USBHS_HSTPIPCFG_PSIZE_128_BYTE_Val _U_(0x4) /**< (USBHS_HSTPIPCFG) 128 bytes */ 3309 #define USBHS_HSTPIPCFG_PSIZE_256_BYTE_Val _U_(0x5) /**< (USBHS_HSTPIPCFG) 256 bytes */ 3310 #define USBHS_HSTPIPCFG_PSIZE_512_BYTE_Val _U_(0x6) /**< (USBHS_HSTPIPCFG) 512 bytes */ 3311 #define USBHS_HSTPIPCFG_PSIZE_1024_BYTE_Val _U_(0x7) /**< (USBHS_HSTPIPCFG) 1024 bytes */ 3312 #define USBHS_HSTPIPCFG_PSIZE_8_BYTE (USBHS_HSTPIPCFG_PSIZE_8_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 8 bytes Position */ 3313 #define USBHS_HSTPIPCFG_PSIZE_16_BYTE (USBHS_HSTPIPCFG_PSIZE_16_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 16 bytes Position */ 3314 #define USBHS_HSTPIPCFG_PSIZE_32_BYTE (USBHS_HSTPIPCFG_PSIZE_32_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 32 bytes Position */ 3315 #define USBHS_HSTPIPCFG_PSIZE_64_BYTE (USBHS_HSTPIPCFG_PSIZE_64_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 64 bytes Position */ 3316 #define USBHS_HSTPIPCFG_PSIZE_128_BYTE (USBHS_HSTPIPCFG_PSIZE_128_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 128 bytes Position */ 3317 #define USBHS_HSTPIPCFG_PSIZE_256_BYTE (USBHS_HSTPIPCFG_PSIZE_256_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 256 bytes Position */ 3318 #define USBHS_HSTPIPCFG_PSIZE_512_BYTE (USBHS_HSTPIPCFG_PSIZE_512_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 512 bytes Position */ 3319 #define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (USBHS_HSTPIPCFG_PSIZE_1024_BYTE_Val << USBHS_HSTPIPCFG_PSIZE_Pos) /**< (USBHS_HSTPIPCFG) 1024 bytes Position */ 3320 #define USBHS_HSTPIPCFG_PTOKEN_Pos 8 /**< (USBHS_HSTPIPCFG) Pipe Token Position */ 3321 #define USBHS_HSTPIPCFG_PTOKEN_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) Pipe Token Mask */ 3322 #define USBHS_HSTPIPCFG_PTOKEN(value) (USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos)) 3323 #define USBHS_HSTPIPCFG_PTOKEN_SETUP_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) SETUP */ 3324 #define USBHS_HSTPIPCFG_PTOKEN_IN_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) IN */ 3325 #define USBHS_HSTPIPCFG_PTOKEN_OUT_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) OUT */ 3326 #define USBHS_HSTPIPCFG_PTOKEN_SETUP (USBHS_HSTPIPCFG_PTOKEN_SETUP_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) SETUP Position */ 3327 #define USBHS_HSTPIPCFG_PTOKEN_IN (USBHS_HSTPIPCFG_PTOKEN_IN_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) IN Position */ 3328 #define USBHS_HSTPIPCFG_PTOKEN_OUT (USBHS_HSTPIPCFG_PTOKEN_OUT_Val << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< (USBHS_HSTPIPCFG) OUT Position */ 3329 #define USBHS_HSTPIPCFG_AUTOSW_Pos 10 /**< (USBHS_HSTPIPCFG) Automatic Switch Position */ 3330 #define USBHS_HSTPIPCFG_AUTOSW_Msk (_U_(0x1) << USBHS_HSTPIPCFG_AUTOSW_Pos) /**< (USBHS_HSTPIPCFG) Automatic Switch Mask */ 3331 #define USBHS_HSTPIPCFG_AUTOSW USBHS_HSTPIPCFG_AUTOSW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPCFG_AUTOSW_Msk instead */ 3332 #define USBHS_HSTPIPCFG_PTYPE_Pos 12 /**< (USBHS_HSTPIPCFG) Pipe Type Position */ 3333 #define USBHS_HSTPIPCFG_PTYPE_Msk (_U_(0x3) << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Pipe Type Mask */ 3334 #define USBHS_HSTPIPCFG_PTYPE(value) (USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos)) 3335 #define USBHS_HSTPIPCFG_PTYPE_CTRL_Val _U_(0x0) /**< (USBHS_HSTPIPCFG) Control */ 3336 #define USBHS_HSTPIPCFG_PTYPE_ISO_Val _U_(0x1) /**< (USBHS_HSTPIPCFG) Isochronous */ 3337 #define USBHS_HSTPIPCFG_PTYPE_BLK_Val _U_(0x2) /**< (USBHS_HSTPIPCFG) Bulk */ 3338 #define USBHS_HSTPIPCFG_PTYPE_INTRPT_Val _U_(0x3) /**< (USBHS_HSTPIPCFG) Interrupt */ 3339 #define USBHS_HSTPIPCFG_PTYPE_CTRL (USBHS_HSTPIPCFG_PTYPE_CTRL_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Control Position */ 3340 #define USBHS_HSTPIPCFG_PTYPE_ISO (USBHS_HSTPIPCFG_PTYPE_ISO_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Isochronous Position */ 3341 #define USBHS_HSTPIPCFG_PTYPE_BLK (USBHS_HSTPIPCFG_PTYPE_BLK_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Bulk Position */ 3342 #define USBHS_HSTPIPCFG_PTYPE_INTRPT (USBHS_HSTPIPCFG_PTYPE_INTRPT_Val << USBHS_HSTPIPCFG_PTYPE_Pos) /**< (USBHS_HSTPIPCFG) Interrupt Position */ 3343 #define USBHS_HSTPIPCFG_PEPNUM_Pos 16 /**< (USBHS_HSTPIPCFG) Pipe Endpoint Number Position */ 3344 #define USBHS_HSTPIPCFG_PEPNUM_Msk (_U_(0xF) << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< (USBHS_HSTPIPCFG) Pipe Endpoint Number Mask */ 3345 #define USBHS_HSTPIPCFG_PEPNUM(value) (USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos)) 3346 #define USBHS_HSTPIPCFG_INTFRQ_Pos 24 /**< (USBHS_HSTPIPCFG) Pipe Interrupt Request Frequency Position */ 3347 #define USBHS_HSTPIPCFG_INTFRQ_Msk (_U_(0xFF) << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< (USBHS_HSTPIPCFG) Pipe Interrupt Request Frequency Mask */ 3348 #define USBHS_HSTPIPCFG_INTFRQ(value) (USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos)) 3349 #define USBHS_HSTPIPCFG_MASK _U_(0xFF0F377E) /**< \deprecated (USBHS_HSTPIPCFG) Register MASK (Use USBHS_HSTPIPCFG_Msk instead) */ 3350 #define USBHS_HSTPIPCFG_Msk _U_(0xFF0F377E) /**< (USBHS_HSTPIPCFG) Register Mask */ 3351 3352 /* CTRL_BULK mode */ 3353 #define USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Pos 20 /**< (USBHS_HSTPIPCFG) Ping Enable Position */ 3354 #define USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Msk (_U_(0x1) << USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Pos) /**< (USBHS_HSTPIPCFG) Ping Enable Mask */ 3355 #define USBHS_HSTPIPCFG_CTRL_BULK_PINGEN USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPCFG_CTRL_BULK_PINGEN_Msk instead */ 3356 #define USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos 24 /**< (USBHS_HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Position */ 3357 #define USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Msk (_U_(0xFF) << USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos) /**< (USBHS_HSTPIPCFG) bInterval Parameter for the Bulk-Out/Ping Transaction Mask */ 3358 #define USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL(value) (USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_CTRL_BULK_BINTERVAL_Pos)) 3359 #define USBHS_HSTPIPCFG_CTRL_BULK_MASK _U_(0xFF100000) /**< \deprecated (USBHS_HSTPIPCFG_CTRL_BULK) Register MASK (Use USBHS_HSTPIPCFG_CTRL_BULK_Msk instead) */ 3360 #define USBHS_HSTPIPCFG_CTRL_BULK_Msk _U_(0xFF100000) /**< (USBHS_HSTPIPCFG_CTRL_BULK) Register Mask */ 3361 3362 3363 /* -------- USBHS_HSTPIPISR : (USBHS Offset: 0x530) (R/ 32) Host Pipe Status Register -------- */ 3364 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3365 #if COMPONENT_TYPEDEF_STYLE == 'N' 3366 typedef union { 3367 struct { 3368 uint32_t RXINI:1; /**< bit: 0 Received IN Data Interrupt */ 3369 uint32_t TXOUTI:1; /**< bit: 1 Transmitted OUT Data Interrupt */ 3370 uint32_t :1; /**< bit: 2 Reserved */ 3371 uint32_t PERRI:1; /**< bit: 3 Pipe Error Interrupt */ 3372 uint32_t NAKEDI:1; /**< bit: 4 NAKed Interrupt */ 3373 uint32_t OVERFI:1; /**< bit: 5 Overflow Interrupt */ 3374 uint32_t :1; /**< bit: 6 Reserved */ 3375 uint32_t SHORTPACKETI:1; /**< bit: 7 Short Packet Interrupt */ 3376 uint32_t DTSEQ:2; /**< bit: 8..9 Data Toggle Sequence */ 3377 uint32_t :2; /**< bit: 10..11 Reserved */ 3378 uint32_t NBUSYBK:2; /**< bit: 12..13 Number of Busy Banks */ 3379 uint32_t CURRBK:2; /**< bit: 14..15 Current Bank */ 3380 uint32_t RWALL:1; /**< bit: 16 Read/Write Allowed */ 3381 uint32_t :1; /**< bit: 17 Reserved */ 3382 uint32_t CFGOK:1; /**< bit: 18 Configuration OK Status */ 3383 uint32_t :1; /**< bit: 19 Reserved */ 3384 uint32_t PBYCT:11; /**< bit: 20..30 Pipe Byte Count */ 3385 uint32_t :1; /**< bit: 31 Reserved */ 3386 } bit; /**< Structure used for bit access */ 3387 struct { // CTRL mode 3388 uint32_t :2; /**< bit: 0..1 Reserved */ 3389 uint32_t TXSTPI:1; /**< bit: 2 Transmitted SETUP Interrupt */ 3390 uint32_t :3; /**< bit: 3..5 Reserved */ 3391 uint32_t RXSTALLDI:1; /**< bit: 6 Received STALLed Interrupt */ 3392 uint32_t :25; /**< bit: 7..31 Reserved */ 3393 } CTRL; /**< Structure used for CTRL mode access */ 3394 struct { // ISO mode 3395 uint32_t :2; /**< bit: 0..1 Reserved */ 3396 uint32_t UNDERFI:1; /**< bit: 2 Underflow Interrupt */ 3397 uint32_t :3; /**< bit: 3..5 Reserved */ 3398 uint32_t CRCERRI:1; /**< bit: 6 CRC Error Interrupt */ 3399 uint32_t :25; /**< bit: 7..31 Reserved */ 3400 } ISO; /**< Structure used for ISO mode access */ 3401 struct { // BLK mode 3402 uint32_t :2; /**< bit: 0..1 Reserved */ 3403 uint32_t TXSTPI:1; /**< bit: 2 Transmitted SETUP Interrupt */ 3404 uint32_t :3; /**< bit: 3..5 Reserved */ 3405 uint32_t RXSTALLDI:1; /**< bit: 6 Received STALLed Interrupt */ 3406 uint32_t :25; /**< bit: 7..31 Reserved */ 3407 } BLK; /**< Structure used for BLK mode access */ 3408 struct { // INTRPT mode 3409 uint32_t :2; /**< bit: 0..1 Reserved */ 3410 uint32_t UNDERFI:1; /**< bit: 2 Underflow Interrupt */ 3411 uint32_t :3; /**< bit: 3..5 Reserved */ 3412 uint32_t RXSTALLDI:1; /**< bit: 6 Received STALLed Interrupt */ 3413 uint32_t :25; /**< bit: 7..31 Reserved */ 3414 } INTRPT; /**< Structure used for INTRPT mode access */ 3415 uint32_t reg; /**< Type used for register access */ 3416 } USBHS_HSTPIPISR_Type; 3417 #endif 3418 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3419 3420 #define USBHS_HSTPIPISR_OFFSET (0x530) /**< (USBHS_HSTPIPISR) Host Pipe Status Register Offset */ 3421 3422 #define USBHS_HSTPIPISR_RXINI_Pos 0 /**< (USBHS_HSTPIPISR) Received IN Data Interrupt Position */ 3423 #define USBHS_HSTPIPISR_RXINI_Msk (_U_(0x1) << USBHS_HSTPIPISR_RXINI_Pos) /**< (USBHS_HSTPIPISR) Received IN Data Interrupt Mask */ 3424 #define USBHS_HSTPIPISR_RXINI USBHS_HSTPIPISR_RXINI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_RXINI_Msk instead */ 3425 #define USBHS_HSTPIPISR_TXOUTI_Pos 1 /**< (USBHS_HSTPIPISR) Transmitted OUT Data Interrupt Position */ 3426 #define USBHS_HSTPIPISR_TXOUTI_Msk (_U_(0x1) << USBHS_HSTPIPISR_TXOUTI_Pos) /**< (USBHS_HSTPIPISR) Transmitted OUT Data Interrupt Mask */ 3427 #define USBHS_HSTPIPISR_TXOUTI USBHS_HSTPIPISR_TXOUTI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_TXOUTI_Msk instead */ 3428 #define USBHS_HSTPIPISR_PERRI_Pos 3 /**< (USBHS_HSTPIPISR) Pipe Error Interrupt Position */ 3429 #define USBHS_HSTPIPISR_PERRI_Msk (_U_(0x1) << USBHS_HSTPIPISR_PERRI_Pos) /**< (USBHS_HSTPIPISR) Pipe Error Interrupt Mask */ 3430 #define USBHS_HSTPIPISR_PERRI USBHS_HSTPIPISR_PERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_PERRI_Msk instead */ 3431 #define USBHS_HSTPIPISR_NAKEDI_Pos 4 /**< (USBHS_HSTPIPISR) NAKed Interrupt Position */ 3432 #define USBHS_HSTPIPISR_NAKEDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_NAKEDI_Pos) /**< (USBHS_HSTPIPISR) NAKed Interrupt Mask */ 3433 #define USBHS_HSTPIPISR_NAKEDI USBHS_HSTPIPISR_NAKEDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_NAKEDI_Msk instead */ 3434 #define USBHS_HSTPIPISR_OVERFI_Pos 5 /**< (USBHS_HSTPIPISR) Overflow Interrupt Position */ 3435 #define USBHS_HSTPIPISR_OVERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_OVERFI_Pos) /**< (USBHS_HSTPIPISR) Overflow Interrupt Mask */ 3436 #define USBHS_HSTPIPISR_OVERFI USBHS_HSTPIPISR_OVERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_OVERFI_Msk instead */ 3437 #define USBHS_HSTPIPISR_SHORTPACKETI_Pos 7 /**< (USBHS_HSTPIPISR) Short Packet Interrupt Position */ 3438 #define USBHS_HSTPIPISR_SHORTPACKETI_Msk (_U_(0x1) << USBHS_HSTPIPISR_SHORTPACKETI_Pos) /**< (USBHS_HSTPIPISR) Short Packet Interrupt Mask */ 3439 #define USBHS_HSTPIPISR_SHORTPACKETI USBHS_HSTPIPISR_SHORTPACKETI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_SHORTPACKETI_Msk instead */ 3440 #define USBHS_HSTPIPISR_DTSEQ_Pos 8 /**< (USBHS_HSTPIPISR) Data Toggle Sequence Position */ 3441 #define USBHS_HSTPIPISR_DTSEQ_Msk (_U_(0x3) << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data Toggle Sequence Mask */ 3442 #define USBHS_HSTPIPISR_DTSEQ(value) (USBHS_HSTPIPISR_DTSEQ_Msk & ((value) << USBHS_HSTPIPISR_DTSEQ_Pos)) 3443 #define USBHS_HSTPIPISR_DTSEQ_DATA0_Val _U_(0x0) /**< (USBHS_HSTPIPISR) Data0 toggle sequence */ 3444 #define USBHS_HSTPIPISR_DTSEQ_DATA1_Val _U_(0x1) /**< (USBHS_HSTPIPISR) Data1 toggle sequence */ 3445 #define USBHS_HSTPIPISR_DTSEQ_DATA0 (USBHS_HSTPIPISR_DTSEQ_DATA0_Val << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data0 toggle sequence Position */ 3446 #define USBHS_HSTPIPISR_DTSEQ_DATA1 (USBHS_HSTPIPISR_DTSEQ_DATA1_Val << USBHS_HSTPIPISR_DTSEQ_Pos) /**< (USBHS_HSTPIPISR) Data1 toggle sequence Position */ 3447 #define USBHS_HSTPIPISR_NBUSYBK_Pos 12 /**< (USBHS_HSTPIPISR) Number of Busy Banks Position */ 3448 #define USBHS_HSTPIPISR_NBUSYBK_Msk (_U_(0x3) << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) Number of Busy Banks Mask */ 3449 #define USBHS_HSTPIPISR_NBUSYBK(value) (USBHS_HSTPIPISR_NBUSYBK_Msk & ((value) << USBHS_HSTPIPISR_NBUSYBK_Pos)) 3450 #define USBHS_HSTPIPISR_NBUSYBK_0_BUSY_Val _U_(0x0) /**< (USBHS_HSTPIPISR) 0 busy bank (all banks free) */ 3451 #define USBHS_HSTPIPISR_NBUSYBK_1_BUSY_Val _U_(0x1) /**< (USBHS_HSTPIPISR) 1 busy bank */ 3452 #define USBHS_HSTPIPISR_NBUSYBK_2_BUSY_Val _U_(0x2) /**< (USBHS_HSTPIPISR) 2 busy banks */ 3453 #define USBHS_HSTPIPISR_NBUSYBK_3_BUSY_Val _U_(0x3) /**< (USBHS_HSTPIPISR) 3 busy banks */ 3454 #define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (USBHS_HSTPIPISR_NBUSYBK_0_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 0 busy bank (all banks free) Position */ 3455 #define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (USBHS_HSTPIPISR_NBUSYBK_1_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 1 busy bank Position */ 3456 #define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (USBHS_HSTPIPISR_NBUSYBK_2_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 2 busy banks Position */ 3457 #define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (USBHS_HSTPIPISR_NBUSYBK_3_BUSY_Val << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< (USBHS_HSTPIPISR) 3 busy banks Position */ 3458 #define USBHS_HSTPIPISR_CURRBK_Pos 14 /**< (USBHS_HSTPIPISR) Current Bank Position */ 3459 #define USBHS_HSTPIPISR_CURRBK_Msk (_U_(0x3) << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current Bank Mask */ 3460 #define USBHS_HSTPIPISR_CURRBK(value) (USBHS_HSTPIPISR_CURRBK_Msk & ((value) << USBHS_HSTPIPISR_CURRBK_Pos)) 3461 #define USBHS_HSTPIPISR_CURRBK_BANK0_Val _U_(0x0) /**< (USBHS_HSTPIPISR) Current bank is bank0 */ 3462 #define USBHS_HSTPIPISR_CURRBK_BANK1_Val _U_(0x1) /**< (USBHS_HSTPIPISR) Current bank is bank1 */ 3463 #define USBHS_HSTPIPISR_CURRBK_BANK2_Val _U_(0x2) /**< (USBHS_HSTPIPISR) Current bank is bank2 */ 3464 #define USBHS_HSTPIPISR_CURRBK_BANK0 (USBHS_HSTPIPISR_CURRBK_BANK0_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank0 Position */ 3465 #define USBHS_HSTPIPISR_CURRBK_BANK1 (USBHS_HSTPIPISR_CURRBK_BANK1_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank1 Position */ 3466 #define USBHS_HSTPIPISR_CURRBK_BANK2 (USBHS_HSTPIPISR_CURRBK_BANK2_Val << USBHS_HSTPIPISR_CURRBK_Pos) /**< (USBHS_HSTPIPISR) Current bank is bank2 Position */ 3467 #define USBHS_HSTPIPISR_RWALL_Pos 16 /**< (USBHS_HSTPIPISR) Read/Write Allowed Position */ 3468 #define USBHS_HSTPIPISR_RWALL_Msk (_U_(0x1) << USBHS_HSTPIPISR_RWALL_Pos) /**< (USBHS_HSTPIPISR) Read/Write Allowed Mask */ 3469 #define USBHS_HSTPIPISR_RWALL USBHS_HSTPIPISR_RWALL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_RWALL_Msk instead */ 3470 #define USBHS_HSTPIPISR_CFGOK_Pos 18 /**< (USBHS_HSTPIPISR) Configuration OK Status Position */ 3471 #define USBHS_HSTPIPISR_CFGOK_Msk (_U_(0x1) << USBHS_HSTPIPISR_CFGOK_Pos) /**< (USBHS_HSTPIPISR) Configuration OK Status Mask */ 3472 #define USBHS_HSTPIPISR_CFGOK USBHS_HSTPIPISR_CFGOK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_CFGOK_Msk instead */ 3473 #define USBHS_HSTPIPISR_PBYCT_Pos 20 /**< (USBHS_HSTPIPISR) Pipe Byte Count Position */ 3474 #define USBHS_HSTPIPISR_PBYCT_Msk (_U_(0x7FF) << USBHS_HSTPIPISR_PBYCT_Pos) /**< (USBHS_HSTPIPISR) Pipe Byte Count Mask */ 3475 #define USBHS_HSTPIPISR_PBYCT(value) (USBHS_HSTPIPISR_PBYCT_Msk & ((value) << USBHS_HSTPIPISR_PBYCT_Pos)) 3476 #define USBHS_HSTPIPISR_MASK _U_(0x7FF5F3BB) /**< \deprecated (USBHS_HSTPIPISR) Register MASK (Use USBHS_HSTPIPISR_Msk instead) */ 3477 #define USBHS_HSTPIPISR_Msk _U_(0x7FF5F3BB) /**< (USBHS_HSTPIPISR) Register Mask */ 3478 3479 /* CTRL mode */ 3480 #define USBHS_HSTPIPISR_CTRL_TXSTPI_Pos 2 /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Position */ 3481 #define USBHS_HSTPIPISR_CTRL_TXSTPI_Msk (_U_(0x1) << USBHS_HSTPIPISR_CTRL_TXSTPI_Pos) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Mask */ 3482 #define USBHS_HSTPIPISR_CTRL_TXSTPI USBHS_HSTPIPISR_CTRL_TXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_CTRL_TXSTPI_Msk instead */ 3483 #define USBHS_HSTPIPISR_CTRL_RXSTALLDI_Pos 6 /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ 3484 #define USBHS_HSTPIPISR_CTRL_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_CTRL_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ 3485 #define USBHS_HSTPIPISR_CTRL_RXSTALLDI USBHS_HSTPIPISR_CTRL_RXSTALLDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_CTRL_RXSTALLDI_Msk instead */ 3486 #define USBHS_HSTPIPISR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPISR_CTRL) Register MASK (Use USBHS_HSTPIPISR_CTRL_Msk instead) */ 3487 #define USBHS_HSTPIPISR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPISR_CTRL) Register Mask */ 3488 3489 /* ISO mode */ 3490 #define USBHS_HSTPIPISR_ISO_UNDERFI_Pos 2 /**< (USBHS_HSTPIPISR) Underflow Interrupt Position */ 3491 #define USBHS_HSTPIPISR_ISO_UNDERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_ISO_UNDERFI_Pos) /**< (USBHS_HSTPIPISR) Underflow Interrupt Mask */ 3492 #define USBHS_HSTPIPISR_ISO_UNDERFI USBHS_HSTPIPISR_ISO_UNDERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_ISO_UNDERFI_Msk instead */ 3493 #define USBHS_HSTPIPISR_ISO_CRCERRI_Pos 6 /**< (USBHS_HSTPIPISR) CRC Error Interrupt Position */ 3494 #define USBHS_HSTPIPISR_ISO_CRCERRI_Msk (_U_(0x1) << USBHS_HSTPIPISR_ISO_CRCERRI_Pos) /**< (USBHS_HSTPIPISR) CRC Error Interrupt Mask */ 3495 #define USBHS_HSTPIPISR_ISO_CRCERRI USBHS_HSTPIPISR_ISO_CRCERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_ISO_CRCERRI_Msk instead */ 3496 #define USBHS_HSTPIPISR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPISR_ISO) Register MASK (Use USBHS_HSTPIPISR_ISO_Msk instead) */ 3497 #define USBHS_HSTPIPISR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPISR_ISO) Register Mask */ 3498 3499 /* BLK mode */ 3500 #define USBHS_HSTPIPISR_BLK_TXSTPI_Pos 2 /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Position */ 3501 #define USBHS_HSTPIPISR_BLK_TXSTPI_Msk (_U_(0x1) << USBHS_HSTPIPISR_BLK_TXSTPI_Pos) /**< (USBHS_HSTPIPISR) Transmitted SETUP Interrupt Mask */ 3502 #define USBHS_HSTPIPISR_BLK_TXSTPI USBHS_HSTPIPISR_BLK_TXSTPI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_BLK_TXSTPI_Msk instead */ 3503 #define USBHS_HSTPIPISR_BLK_RXSTALLDI_Pos 6 /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ 3504 #define USBHS_HSTPIPISR_BLK_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_BLK_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ 3505 #define USBHS_HSTPIPISR_BLK_RXSTALLDI USBHS_HSTPIPISR_BLK_RXSTALLDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_BLK_RXSTALLDI_Msk instead */ 3506 #define USBHS_HSTPIPISR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPISR_BLK) Register MASK (Use USBHS_HSTPIPISR_BLK_Msk instead) */ 3507 #define USBHS_HSTPIPISR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPISR_BLK) Register Mask */ 3508 3509 /* INTRPT mode */ 3510 #define USBHS_HSTPIPISR_INTRPT_UNDERFI_Pos 2 /**< (USBHS_HSTPIPISR) Underflow Interrupt Position */ 3511 #define USBHS_HSTPIPISR_INTRPT_UNDERFI_Msk (_U_(0x1) << USBHS_HSTPIPISR_INTRPT_UNDERFI_Pos) /**< (USBHS_HSTPIPISR) Underflow Interrupt Mask */ 3512 #define USBHS_HSTPIPISR_INTRPT_UNDERFI USBHS_HSTPIPISR_INTRPT_UNDERFI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_INTRPT_UNDERFI_Msk instead */ 3513 #define USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Pos 6 /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Position */ 3514 #define USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Msk (_U_(0x1) << USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Pos) /**< (USBHS_HSTPIPISR) Received STALLed Interrupt Mask */ 3515 #define USBHS_HSTPIPISR_INTRPT_RXSTALLDI USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPISR_INTRPT_RXSTALLDI_Msk instead */ 3516 #define USBHS_HSTPIPISR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPISR_INTRPT) Register MASK (Use USBHS_HSTPIPISR_INTRPT_Msk instead) */ 3517 #define USBHS_HSTPIPISR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPISR_INTRPT) Register Mask */ 3518 3519 3520 /* -------- USBHS_HSTPIPICR : (USBHS Offset: 0x560) (/W 32) Host Pipe Clear Register -------- */ 3521 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3522 #if COMPONENT_TYPEDEF_STYLE == 'N' 3523 typedef union { 3524 struct { 3525 uint32_t RXINIC:1; /**< bit: 0 Received IN Data Interrupt Clear */ 3526 uint32_t TXOUTIC:1; /**< bit: 1 Transmitted OUT Data Interrupt Clear */ 3527 uint32_t :2; /**< bit: 2..3 Reserved */ 3528 uint32_t NAKEDIC:1; /**< bit: 4 NAKed Interrupt Clear */ 3529 uint32_t OVERFIC:1; /**< bit: 5 Overflow Interrupt Clear */ 3530 uint32_t :1; /**< bit: 6 Reserved */ 3531 uint32_t SHORTPACKETIC:1; /**< bit: 7 Short Packet Interrupt Clear */ 3532 uint32_t :24; /**< bit: 8..31 Reserved */ 3533 } bit; /**< Structure used for bit access */ 3534 struct { // CTRL mode 3535 uint32_t :2; /**< bit: 0..1 Reserved */ 3536 uint32_t TXSTPIC:1; /**< bit: 2 Transmitted SETUP Interrupt Clear */ 3537 uint32_t :3; /**< bit: 3..5 Reserved */ 3538 uint32_t RXSTALLDIC:1; /**< bit: 6 Received STALLed Interrupt Clear */ 3539 uint32_t :25; /**< bit: 7..31 Reserved */ 3540 } CTRL; /**< Structure used for CTRL mode access */ 3541 struct { // ISO mode 3542 uint32_t :2; /**< bit: 0..1 Reserved */ 3543 uint32_t UNDERFIC:1; /**< bit: 2 Underflow Interrupt Clear */ 3544 uint32_t :3; /**< bit: 3..5 Reserved */ 3545 uint32_t CRCERRIC:1; /**< bit: 6 CRC Error Interrupt Clear */ 3546 uint32_t :25; /**< bit: 7..31 Reserved */ 3547 } ISO; /**< Structure used for ISO mode access */ 3548 struct { // BLK mode 3549 uint32_t :2; /**< bit: 0..1 Reserved */ 3550 uint32_t TXSTPIC:1; /**< bit: 2 Transmitted SETUP Interrupt Clear */ 3551 uint32_t :3; /**< bit: 3..5 Reserved */ 3552 uint32_t RXSTALLDIC:1; /**< bit: 6 Received STALLed Interrupt Clear */ 3553 uint32_t :25; /**< bit: 7..31 Reserved */ 3554 } BLK; /**< Structure used for BLK mode access */ 3555 struct { // INTRPT mode 3556 uint32_t :2; /**< bit: 0..1 Reserved */ 3557 uint32_t UNDERFIC:1; /**< bit: 2 Underflow Interrupt Clear */ 3558 uint32_t :3; /**< bit: 3..5 Reserved */ 3559 uint32_t RXSTALLDIC:1; /**< bit: 6 Received STALLed Interrupt Clear */ 3560 uint32_t :25; /**< bit: 7..31 Reserved */ 3561 } INTRPT; /**< Structure used for INTRPT mode access */ 3562 uint32_t reg; /**< Type used for register access */ 3563 } USBHS_HSTPIPICR_Type; 3564 #endif 3565 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3566 3567 #define USBHS_HSTPIPICR_OFFSET (0x560) /**< (USBHS_HSTPIPICR) Host Pipe Clear Register Offset */ 3568 3569 #define USBHS_HSTPIPICR_RXINIC_Pos 0 /**< (USBHS_HSTPIPICR) Received IN Data Interrupt Clear Position */ 3570 #define USBHS_HSTPIPICR_RXINIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_RXINIC_Pos) /**< (USBHS_HSTPIPICR) Received IN Data Interrupt Clear Mask */ 3571 #define USBHS_HSTPIPICR_RXINIC USBHS_HSTPIPICR_RXINIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_RXINIC_Msk instead */ 3572 #define USBHS_HSTPIPICR_TXOUTIC_Pos 1 /**< (USBHS_HSTPIPICR) Transmitted OUT Data Interrupt Clear Position */ 3573 #define USBHS_HSTPIPICR_TXOUTIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_TXOUTIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted OUT Data Interrupt Clear Mask */ 3574 #define USBHS_HSTPIPICR_TXOUTIC USBHS_HSTPIPICR_TXOUTIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_TXOUTIC_Msk instead */ 3575 #define USBHS_HSTPIPICR_NAKEDIC_Pos 4 /**< (USBHS_HSTPIPICR) NAKed Interrupt Clear Position */ 3576 #define USBHS_HSTPIPICR_NAKEDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_NAKEDIC_Pos) /**< (USBHS_HSTPIPICR) NAKed Interrupt Clear Mask */ 3577 #define USBHS_HSTPIPICR_NAKEDIC USBHS_HSTPIPICR_NAKEDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_NAKEDIC_Msk instead */ 3578 #define USBHS_HSTPIPICR_OVERFIC_Pos 5 /**< (USBHS_HSTPIPICR) Overflow Interrupt Clear Position */ 3579 #define USBHS_HSTPIPICR_OVERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_OVERFIC_Pos) /**< (USBHS_HSTPIPICR) Overflow Interrupt Clear Mask */ 3580 #define USBHS_HSTPIPICR_OVERFIC USBHS_HSTPIPICR_OVERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_OVERFIC_Msk instead */ 3581 #define USBHS_HSTPIPICR_SHORTPACKETIC_Pos 7 /**< (USBHS_HSTPIPICR) Short Packet Interrupt Clear Position */ 3582 #define USBHS_HSTPIPICR_SHORTPACKETIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_SHORTPACKETIC_Pos) /**< (USBHS_HSTPIPICR) Short Packet Interrupt Clear Mask */ 3583 #define USBHS_HSTPIPICR_SHORTPACKETIC USBHS_HSTPIPICR_SHORTPACKETIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_SHORTPACKETIC_Msk instead */ 3584 #define USBHS_HSTPIPICR_MASK _U_(0xB3) /**< \deprecated (USBHS_HSTPIPICR) Register MASK (Use USBHS_HSTPIPICR_Msk instead) */ 3585 #define USBHS_HSTPIPICR_Msk _U_(0xB3) /**< (USBHS_HSTPIPICR) Register Mask */ 3586 3587 /* CTRL mode */ 3588 #define USBHS_HSTPIPICR_CTRL_TXSTPIC_Pos 2 /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ 3589 #define USBHS_HSTPIPICR_CTRL_TXSTPIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_CTRL_TXSTPIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ 3590 #define USBHS_HSTPIPICR_CTRL_TXSTPIC USBHS_HSTPIPICR_CTRL_TXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_CTRL_TXSTPIC_Msk instead */ 3591 #define USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Pos 6 /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ 3592 #define USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ 3593 #define USBHS_HSTPIPICR_CTRL_RXSTALLDIC USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_CTRL_RXSTALLDIC_Msk instead */ 3594 #define USBHS_HSTPIPICR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPICR_CTRL) Register MASK (Use USBHS_HSTPIPICR_CTRL_Msk instead) */ 3595 #define USBHS_HSTPIPICR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPICR_CTRL) Register Mask */ 3596 3597 /* ISO mode */ 3598 #define USBHS_HSTPIPICR_ISO_UNDERFIC_Pos 2 /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Position */ 3599 #define USBHS_HSTPIPICR_ISO_UNDERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_ISO_UNDERFIC_Pos) /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Mask */ 3600 #define USBHS_HSTPIPICR_ISO_UNDERFIC USBHS_HSTPIPICR_ISO_UNDERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_ISO_UNDERFIC_Msk instead */ 3601 #define USBHS_HSTPIPICR_ISO_CRCERRIC_Pos 6 /**< (USBHS_HSTPIPICR) CRC Error Interrupt Clear Position */ 3602 #define USBHS_HSTPIPICR_ISO_CRCERRIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_ISO_CRCERRIC_Pos) /**< (USBHS_HSTPIPICR) CRC Error Interrupt Clear Mask */ 3603 #define USBHS_HSTPIPICR_ISO_CRCERRIC USBHS_HSTPIPICR_ISO_CRCERRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_ISO_CRCERRIC_Msk instead */ 3604 #define USBHS_HSTPIPICR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPICR_ISO) Register MASK (Use USBHS_HSTPIPICR_ISO_Msk instead) */ 3605 #define USBHS_HSTPIPICR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPICR_ISO) Register Mask */ 3606 3607 /* BLK mode */ 3608 #define USBHS_HSTPIPICR_BLK_TXSTPIC_Pos 2 /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Position */ 3609 #define USBHS_HSTPIPICR_BLK_TXSTPIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_BLK_TXSTPIC_Pos) /**< (USBHS_HSTPIPICR) Transmitted SETUP Interrupt Clear Mask */ 3610 #define USBHS_HSTPIPICR_BLK_TXSTPIC USBHS_HSTPIPICR_BLK_TXSTPIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_BLK_TXSTPIC_Msk instead */ 3611 #define USBHS_HSTPIPICR_BLK_RXSTALLDIC_Pos 6 /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ 3612 #define USBHS_HSTPIPICR_BLK_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_BLK_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ 3613 #define USBHS_HSTPIPICR_BLK_RXSTALLDIC USBHS_HSTPIPICR_BLK_RXSTALLDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_BLK_RXSTALLDIC_Msk instead */ 3614 #define USBHS_HSTPIPICR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPICR_BLK) Register MASK (Use USBHS_HSTPIPICR_BLK_Msk instead) */ 3615 #define USBHS_HSTPIPICR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPICR_BLK) Register Mask */ 3616 3617 /* INTRPT mode */ 3618 #define USBHS_HSTPIPICR_INTRPT_UNDERFIC_Pos 2 /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Position */ 3619 #define USBHS_HSTPIPICR_INTRPT_UNDERFIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_INTRPT_UNDERFIC_Pos) /**< (USBHS_HSTPIPICR) Underflow Interrupt Clear Mask */ 3620 #define USBHS_HSTPIPICR_INTRPT_UNDERFIC USBHS_HSTPIPICR_INTRPT_UNDERFIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_INTRPT_UNDERFIC_Msk instead */ 3621 #define USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Pos 6 /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Position */ 3622 #define USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Msk (_U_(0x1) << USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Pos) /**< (USBHS_HSTPIPICR) Received STALLed Interrupt Clear Mask */ 3623 #define USBHS_HSTPIPICR_INTRPT_RXSTALLDIC USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPICR_INTRPT_RXSTALLDIC_Msk instead */ 3624 #define USBHS_HSTPIPICR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPICR_INTRPT) Register MASK (Use USBHS_HSTPIPICR_INTRPT_Msk instead) */ 3625 #define USBHS_HSTPIPICR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPICR_INTRPT) Register Mask */ 3626 3627 3628 /* -------- USBHS_HSTPIPIFR : (USBHS Offset: 0x590) (/W 32) Host Pipe Set Register -------- */ 3629 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3630 #if COMPONENT_TYPEDEF_STYLE == 'N' 3631 typedef union { 3632 struct { 3633 uint32_t RXINIS:1; /**< bit: 0 Received IN Data Interrupt Set */ 3634 uint32_t TXOUTIS:1; /**< bit: 1 Transmitted OUT Data Interrupt Set */ 3635 uint32_t :1; /**< bit: 2 Reserved */ 3636 uint32_t PERRIS:1; /**< bit: 3 Pipe Error Interrupt Set */ 3637 uint32_t NAKEDIS:1; /**< bit: 4 NAKed Interrupt Set */ 3638 uint32_t OVERFIS:1; /**< bit: 5 Overflow Interrupt Set */ 3639 uint32_t :1; /**< bit: 6 Reserved */ 3640 uint32_t SHORTPACKETIS:1; /**< bit: 7 Short Packet Interrupt Set */ 3641 uint32_t :4; /**< bit: 8..11 Reserved */ 3642 uint32_t NBUSYBKS:1; /**< bit: 12 Number of Busy Banks Set */ 3643 uint32_t :19; /**< bit: 13..31 Reserved */ 3644 } bit; /**< Structure used for bit access */ 3645 struct { // CTRL mode 3646 uint32_t :2; /**< bit: 0..1 Reserved */ 3647 uint32_t TXSTPIS:1; /**< bit: 2 Transmitted SETUP Interrupt Set */ 3648 uint32_t :3; /**< bit: 3..5 Reserved */ 3649 uint32_t RXSTALLDIS:1; /**< bit: 6 Received STALLed Interrupt Set */ 3650 uint32_t :25; /**< bit: 7..31 Reserved */ 3651 } CTRL; /**< Structure used for CTRL mode access */ 3652 struct { // ISO mode 3653 uint32_t :2; /**< bit: 0..1 Reserved */ 3654 uint32_t UNDERFIS:1; /**< bit: 2 Underflow Interrupt Set */ 3655 uint32_t :3; /**< bit: 3..5 Reserved */ 3656 uint32_t CRCERRIS:1; /**< bit: 6 CRC Error Interrupt Set */ 3657 uint32_t :25; /**< bit: 7..31 Reserved */ 3658 } ISO; /**< Structure used for ISO mode access */ 3659 struct { // BLK mode 3660 uint32_t :2; /**< bit: 0..1 Reserved */ 3661 uint32_t TXSTPIS:1; /**< bit: 2 Transmitted SETUP Interrupt Set */ 3662 uint32_t :3; /**< bit: 3..5 Reserved */ 3663 uint32_t RXSTALLDIS:1; /**< bit: 6 Received STALLed Interrupt Set */ 3664 uint32_t :25; /**< bit: 7..31 Reserved */ 3665 } BLK; /**< Structure used for BLK mode access */ 3666 struct { // INTRPT mode 3667 uint32_t :2; /**< bit: 0..1 Reserved */ 3668 uint32_t UNDERFIS:1; /**< bit: 2 Underflow Interrupt Set */ 3669 uint32_t :3; /**< bit: 3..5 Reserved */ 3670 uint32_t RXSTALLDIS:1; /**< bit: 6 Received STALLed Interrupt Set */ 3671 uint32_t :25; /**< bit: 7..31 Reserved */ 3672 } INTRPT; /**< Structure used for INTRPT mode access */ 3673 uint32_t reg; /**< Type used for register access */ 3674 } USBHS_HSTPIPIFR_Type; 3675 #endif 3676 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3677 3678 #define USBHS_HSTPIPIFR_OFFSET (0x590) /**< (USBHS_HSTPIPIFR) Host Pipe Set Register Offset */ 3679 3680 #define USBHS_HSTPIPIFR_RXINIS_Pos 0 /**< (USBHS_HSTPIPIFR) Received IN Data Interrupt Set Position */ 3681 #define USBHS_HSTPIPIFR_RXINIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_RXINIS_Pos) /**< (USBHS_HSTPIPIFR) Received IN Data Interrupt Set Mask */ 3682 #define USBHS_HSTPIPIFR_RXINIS USBHS_HSTPIPIFR_RXINIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_RXINIS_Msk instead */ 3683 #define USBHS_HSTPIPIFR_TXOUTIS_Pos 1 /**< (USBHS_HSTPIPIFR) Transmitted OUT Data Interrupt Set Position */ 3684 #define USBHS_HSTPIPIFR_TXOUTIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_TXOUTIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted OUT Data Interrupt Set Mask */ 3685 #define USBHS_HSTPIPIFR_TXOUTIS USBHS_HSTPIPIFR_TXOUTIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_TXOUTIS_Msk instead */ 3686 #define USBHS_HSTPIPIFR_PERRIS_Pos 3 /**< (USBHS_HSTPIPIFR) Pipe Error Interrupt Set Position */ 3687 #define USBHS_HSTPIPIFR_PERRIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_PERRIS_Pos) /**< (USBHS_HSTPIPIFR) Pipe Error Interrupt Set Mask */ 3688 #define USBHS_HSTPIPIFR_PERRIS USBHS_HSTPIPIFR_PERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_PERRIS_Msk instead */ 3689 #define USBHS_HSTPIPIFR_NAKEDIS_Pos 4 /**< (USBHS_HSTPIPIFR) NAKed Interrupt Set Position */ 3690 #define USBHS_HSTPIPIFR_NAKEDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_NAKEDIS_Pos) /**< (USBHS_HSTPIPIFR) NAKed Interrupt Set Mask */ 3691 #define USBHS_HSTPIPIFR_NAKEDIS USBHS_HSTPIPIFR_NAKEDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_NAKEDIS_Msk instead */ 3692 #define USBHS_HSTPIPIFR_OVERFIS_Pos 5 /**< (USBHS_HSTPIPIFR) Overflow Interrupt Set Position */ 3693 #define USBHS_HSTPIPIFR_OVERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_OVERFIS_Pos) /**< (USBHS_HSTPIPIFR) Overflow Interrupt Set Mask */ 3694 #define USBHS_HSTPIPIFR_OVERFIS USBHS_HSTPIPIFR_OVERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_OVERFIS_Msk instead */ 3695 #define USBHS_HSTPIPIFR_SHORTPACKETIS_Pos 7 /**< (USBHS_HSTPIPIFR) Short Packet Interrupt Set Position */ 3696 #define USBHS_HSTPIPIFR_SHORTPACKETIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_SHORTPACKETIS_Pos) /**< (USBHS_HSTPIPIFR) Short Packet Interrupt Set Mask */ 3697 #define USBHS_HSTPIPIFR_SHORTPACKETIS USBHS_HSTPIPIFR_SHORTPACKETIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_SHORTPACKETIS_Msk instead */ 3698 #define USBHS_HSTPIPIFR_NBUSYBKS_Pos 12 /**< (USBHS_HSTPIPIFR) Number of Busy Banks Set Position */ 3699 #define USBHS_HSTPIPIFR_NBUSYBKS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_NBUSYBKS_Pos) /**< (USBHS_HSTPIPIFR) Number of Busy Banks Set Mask */ 3700 #define USBHS_HSTPIPIFR_NBUSYBKS USBHS_HSTPIPIFR_NBUSYBKS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_NBUSYBKS_Msk instead */ 3701 #define USBHS_HSTPIPIFR_MASK _U_(0x10BB) /**< \deprecated (USBHS_HSTPIPIFR) Register MASK (Use USBHS_HSTPIPIFR_Msk instead) */ 3702 #define USBHS_HSTPIPIFR_Msk _U_(0x10BB) /**< (USBHS_HSTPIPIFR) Register Mask */ 3703 3704 /* CTRL mode */ 3705 #define USBHS_HSTPIPIFR_CTRL_TXSTPIS_Pos 2 /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ 3706 #define USBHS_HSTPIPIFR_CTRL_TXSTPIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_CTRL_TXSTPIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ 3707 #define USBHS_HSTPIPIFR_CTRL_TXSTPIS USBHS_HSTPIPIFR_CTRL_TXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_CTRL_TXSTPIS_Msk instead */ 3708 #define USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Pos 6 /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ 3709 #define USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ 3710 #define USBHS_HSTPIPIFR_CTRL_RXSTALLDIS USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_CTRL_RXSTALLDIS_Msk instead */ 3711 #define USBHS_HSTPIPIFR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIFR_CTRL) Register MASK (Use USBHS_HSTPIPIFR_CTRL_Msk instead) */ 3712 #define USBHS_HSTPIPIFR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPIFR_CTRL) Register Mask */ 3713 3714 /* ISO mode */ 3715 #define USBHS_HSTPIPIFR_ISO_UNDERFIS_Pos 2 /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Position */ 3716 #define USBHS_HSTPIPIFR_ISO_UNDERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_ISO_UNDERFIS_Pos) /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Mask */ 3717 #define USBHS_HSTPIPIFR_ISO_UNDERFIS USBHS_HSTPIPIFR_ISO_UNDERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_ISO_UNDERFIS_Msk instead */ 3718 #define USBHS_HSTPIPIFR_ISO_CRCERRIS_Pos 6 /**< (USBHS_HSTPIPIFR) CRC Error Interrupt Set Position */ 3719 #define USBHS_HSTPIPIFR_ISO_CRCERRIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_ISO_CRCERRIS_Pos) /**< (USBHS_HSTPIPIFR) CRC Error Interrupt Set Mask */ 3720 #define USBHS_HSTPIPIFR_ISO_CRCERRIS USBHS_HSTPIPIFR_ISO_CRCERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_ISO_CRCERRIS_Msk instead */ 3721 #define USBHS_HSTPIPIFR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIFR_ISO) Register MASK (Use USBHS_HSTPIPIFR_ISO_Msk instead) */ 3722 #define USBHS_HSTPIPIFR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPIFR_ISO) Register Mask */ 3723 3724 /* BLK mode */ 3725 #define USBHS_HSTPIPIFR_BLK_TXSTPIS_Pos 2 /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Position */ 3726 #define USBHS_HSTPIPIFR_BLK_TXSTPIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_BLK_TXSTPIS_Pos) /**< (USBHS_HSTPIPIFR) Transmitted SETUP Interrupt Set Mask */ 3727 #define USBHS_HSTPIPIFR_BLK_TXSTPIS USBHS_HSTPIPIFR_BLK_TXSTPIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_BLK_TXSTPIS_Msk instead */ 3728 #define USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Pos 6 /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ 3729 #define USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ 3730 #define USBHS_HSTPIPIFR_BLK_RXSTALLDIS USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_BLK_RXSTALLDIS_Msk instead */ 3731 #define USBHS_HSTPIPIFR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIFR_BLK) Register MASK (Use USBHS_HSTPIPIFR_BLK_Msk instead) */ 3732 #define USBHS_HSTPIPIFR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPIFR_BLK) Register Mask */ 3733 3734 /* INTRPT mode */ 3735 #define USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Pos 2 /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Position */ 3736 #define USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Pos) /**< (USBHS_HSTPIPIFR) Underflow Interrupt Set Mask */ 3737 #define USBHS_HSTPIPIFR_INTRPT_UNDERFIS USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_INTRPT_UNDERFIS_Msk instead */ 3738 #define USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Pos 6 /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Position */ 3739 #define USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Msk (_U_(0x1) << USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Pos) /**< (USBHS_HSTPIPIFR) Received STALLed Interrupt Set Mask */ 3740 #define USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIFR_INTRPT_RXSTALLDIS_Msk instead */ 3741 #define USBHS_HSTPIPIFR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIFR_INTRPT) Register MASK (Use USBHS_HSTPIPIFR_INTRPT_Msk instead) */ 3742 #define USBHS_HSTPIPIFR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPIFR_INTRPT) Register Mask */ 3743 3744 3745 /* -------- USBHS_HSTPIPIMR : (USBHS Offset: 0x5c0) (R/ 32) Host Pipe Mask Register -------- */ 3746 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3747 #if COMPONENT_TYPEDEF_STYLE == 'N' 3748 typedef union { 3749 struct { 3750 uint32_t RXINE:1; /**< bit: 0 Received IN Data Interrupt Enable */ 3751 uint32_t TXOUTE:1; /**< bit: 1 Transmitted OUT Data Interrupt Enable */ 3752 uint32_t :1; /**< bit: 2 Reserved */ 3753 uint32_t PERRE:1; /**< bit: 3 Pipe Error Interrupt Enable */ 3754 uint32_t NAKEDE:1; /**< bit: 4 NAKed Interrupt Enable */ 3755 uint32_t OVERFIE:1; /**< bit: 5 Overflow Interrupt Enable */ 3756 uint32_t :1; /**< bit: 6 Reserved */ 3757 uint32_t SHORTPACKETIE:1; /**< bit: 7 Short Packet Interrupt Enable */ 3758 uint32_t :4; /**< bit: 8..11 Reserved */ 3759 uint32_t NBUSYBKE:1; /**< bit: 12 Number of Busy Banks Interrupt Enable */ 3760 uint32_t :1; /**< bit: 13 Reserved */ 3761 uint32_t FIFOCON:1; /**< bit: 14 FIFO Control */ 3762 uint32_t :1; /**< bit: 15 Reserved */ 3763 uint32_t PDISHDMA:1; /**< bit: 16 Pipe Interrupts Disable HDMA Request Enable */ 3764 uint32_t PFREEZE:1; /**< bit: 17 Pipe Freeze */ 3765 uint32_t RSTDT:1; /**< bit: 18 Reset Data Toggle */ 3766 uint32_t :13; /**< bit: 19..31 Reserved */ 3767 } bit; /**< Structure used for bit access */ 3768 struct { // CTRL mode 3769 uint32_t :2; /**< bit: 0..1 Reserved */ 3770 uint32_t TXSTPE:1; /**< bit: 2 Transmitted SETUP Interrupt Enable */ 3771 uint32_t :3; /**< bit: 3..5 Reserved */ 3772 uint32_t RXSTALLDE:1; /**< bit: 6 Received STALLed Interrupt Enable */ 3773 uint32_t :25; /**< bit: 7..31 Reserved */ 3774 } CTRL; /**< Structure used for CTRL mode access */ 3775 struct { // ISO mode 3776 uint32_t :2; /**< bit: 0..1 Reserved */ 3777 uint32_t UNDERFIE:1; /**< bit: 2 Underflow Interrupt Enable */ 3778 uint32_t :3; /**< bit: 3..5 Reserved */ 3779 uint32_t CRCERRE:1; /**< bit: 6 CRC Error Interrupt Enable */ 3780 uint32_t :25; /**< bit: 7..31 Reserved */ 3781 } ISO; /**< Structure used for ISO mode access */ 3782 struct { // BLK mode 3783 uint32_t :2; /**< bit: 0..1 Reserved */ 3784 uint32_t TXSTPE:1; /**< bit: 2 Transmitted SETUP Interrupt Enable */ 3785 uint32_t :3; /**< bit: 3..5 Reserved */ 3786 uint32_t RXSTALLDE:1; /**< bit: 6 Received STALLed Interrupt Enable */ 3787 uint32_t :25; /**< bit: 7..31 Reserved */ 3788 } BLK; /**< Structure used for BLK mode access */ 3789 struct { // INTRPT mode 3790 uint32_t :2; /**< bit: 0..1 Reserved */ 3791 uint32_t UNDERFIE:1; /**< bit: 2 Underflow Interrupt Enable */ 3792 uint32_t :3; /**< bit: 3..5 Reserved */ 3793 uint32_t RXSTALLDE:1; /**< bit: 6 Received STALLed Interrupt Enable */ 3794 uint32_t :25; /**< bit: 7..31 Reserved */ 3795 } INTRPT; /**< Structure used for INTRPT mode access */ 3796 uint32_t reg; /**< Type used for register access */ 3797 } USBHS_HSTPIPIMR_Type; 3798 #endif 3799 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3800 3801 #define USBHS_HSTPIPIMR_OFFSET (0x5C0) /**< (USBHS_HSTPIPIMR) Host Pipe Mask Register Offset */ 3802 3803 #define USBHS_HSTPIPIMR_RXINE_Pos 0 /**< (USBHS_HSTPIPIMR) Received IN Data Interrupt Enable Position */ 3804 #define USBHS_HSTPIPIMR_RXINE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_RXINE_Pos) /**< (USBHS_HSTPIPIMR) Received IN Data Interrupt Enable Mask */ 3805 #define USBHS_HSTPIPIMR_RXINE USBHS_HSTPIPIMR_RXINE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_RXINE_Msk instead */ 3806 #define USBHS_HSTPIPIMR_TXOUTE_Pos 1 /**< (USBHS_HSTPIPIMR) Transmitted OUT Data Interrupt Enable Position */ 3807 #define USBHS_HSTPIPIMR_TXOUTE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_TXOUTE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted OUT Data Interrupt Enable Mask */ 3808 #define USBHS_HSTPIPIMR_TXOUTE USBHS_HSTPIPIMR_TXOUTE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_TXOUTE_Msk instead */ 3809 #define USBHS_HSTPIPIMR_PERRE_Pos 3 /**< (USBHS_HSTPIPIMR) Pipe Error Interrupt Enable Position */ 3810 #define USBHS_HSTPIPIMR_PERRE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PERRE_Pos) /**< (USBHS_HSTPIPIMR) Pipe Error Interrupt Enable Mask */ 3811 #define USBHS_HSTPIPIMR_PERRE USBHS_HSTPIPIMR_PERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_PERRE_Msk instead */ 3812 #define USBHS_HSTPIPIMR_NAKEDE_Pos 4 /**< (USBHS_HSTPIPIMR) NAKed Interrupt Enable Position */ 3813 #define USBHS_HSTPIPIMR_NAKEDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_NAKEDE_Pos) /**< (USBHS_HSTPIPIMR) NAKed Interrupt Enable Mask */ 3814 #define USBHS_HSTPIPIMR_NAKEDE USBHS_HSTPIPIMR_NAKEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_NAKEDE_Msk instead */ 3815 #define USBHS_HSTPIPIMR_OVERFIE_Pos 5 /**< (USBHS_HSTPIPIMR) Overflow Interrupt Enable Position */ 3816 #define USBHS_HSTPIPIMR_OVERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_OVERFIE_Pos) /**< (USBHS_HSTPIPIMR) Overflow Interrupt Enable Mask */ 3817 #define USBHS_HSTPIPIMR_OVERFIE USBHS_HSTPIPIMR_OVERFIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_OVERFIE_Msk instead */ 3818 #define USBHS_HSTPIPIMR_SHORTPACKETIE_Pos 7 /**< (USBHS_HSTPIPIMR) Short Packet Interrupt Enable Position */ 3819 #define USBHS_HSTPIPIMR_SHORTPACKETIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_SHORTPACKETIE_Pos) /**< (USBHS_HSTPIPIMR) Short Packet Interrupt Enable Mask */ 3820 #define USBHS_HSTPIPIMR_SHORTPACKETIE USBHS_HSTPIPIMR_SHORTPACKETIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_SHORTPACKETIE_Msk instead */ 3821 #define USBHS_HSTPIPIMR_NBUSYBKE_Pos 12 /**< (USBHS_HSTPIPIMR) Number of Busy Banks Interrupt Enable Position */ 3822 #define USBHS_HSTPIPIMR_NBUSYBKE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_NBUSYBKE_Pos) /**< (USBHS_HSTPIPIMR) Number of Busy Banks Interrupt Enable Mask */ 3823 #define USBHS_HSTPIPIMR_NBUSYBKE USBHS_HSTPIPIMR_NBUSYBKE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_NBUSYBKE_Msk instead */ 3824 #define USBHS_HSTPIPIMR_FIFOCON_Pos 14 /**< (USBHS_HSTPIPIMR) FIFO Control Position */ 3825 #define USBHS_HSTPIPIMR_FIFOCON_Msk (_U_(0x1) << USBHS_HSTPIPIMR_FIFOCON_Pos) /**< (USBHS_HSTPIPIMR) FIFO Control Mask */ 3826 #define USBHS_HSTPIPIMR_FIFOCON USBHS_HSTPIPIMR_FIFOCON_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_FIFOCON_Msk instead */ 3827 #define USBHS_HSTPIPIMR_PDISHDMA_Pos 16 /**< (USBHS_HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Position */ 3828 #define USBHS_HSTPIPIMR_PDISHDMA_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PDISHDMA_Pos) /**< (USBHS_HSTPIPIMR) Pipe Interrupts Disable HDMA Request Enable Mask */ 3829 #define USBHS_HSTPIPIMR_PDISHDMA USBHS_HSTPIPIMR_PDISHDMA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_PDISHDMA_Msk instead */ 3830 #define USBHS_HSTPIPIMR_PFREEZE_Pos 17 /**< (USBHS_HSTPIPIMR) Pipe Freeze Position */ 3831 #define USBHS_HSTPIPIMR_PFREEZE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_PFREEZE_Pos) /**< (USBHS_HSTPIPIMR) Pipe Freeze Mask */ 3832 #define USBHS_HSTPIPIMR_PFREEZE USBHS_HSTPIPIMR_PFREEZE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_PFREEZE_Msk instead */ 3833 #define USBHS_HSTPIPIMR_RSTDT_Pos 18 /**< (USBHS_HSTPIPIMR) Reset Data Toggle Position */ 3834 #define USBHS_HSTPIPIMR_RSTDT_Msk (_U_(0x1) << USBHS_HSTPIPIMR_RSTDT_Pos) /**< (USBHS_HSTPIPIMR) Reset Data Toggle Mask */ 3835 #define USBHS_HSTPIPIMR_RSTDT USBHS_HSTPIPIMR_RSTDT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_RSTDT_Msk instead */ 3836 #define USBHS_HSTPIPIMR_MASK _U_(0x750BB) /**< \deprecated (USBHS_HSTPIPIMR) Register MASK (Use USBHS_HSTPIPIMR_Msk instead) */ 3837 #define USBHS_HSTPIPIMR_Msk _U_(0x750BB) /**< (USBHS_HSTPIPIMR) Register Mask */ 3838 3839 /* CTRL mode */ 3840 #define USBHS_HSTPIPIMR_CTRL_TXSTPE_Pos 2 /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ 3841 #define USBHS_HSTPIPIMR_CTRL_TXSTPE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_CTRL_TXSTPE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ 3842 #define USBHS_HSTPIPIMR_CTRL_TXSTPE USBHS_HSTPIPIMR_CTRL_TXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_CTRL_TXSTPE_Msk instead */ 3843 #define USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Pos 6 /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ 3844 #define USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ 3845 #define USBHS_HSTPIPIMR_CTRL_RXSTALLDE USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_CTRL_RXSTALLDE_Msk instead */ 3846 #define USBHS_HSTPIPIMR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIMR_CTRL) Register MASK (Use USBHS_HSTPIPIMR_CTRL_Msk instead) */ 3847 #define USBHS_HSTPIPIMR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPIMR_CTRL) Register Mask */ 3848 3849 /* ISO mode */ 3850 #define USBHS_HSTPIPIMR_ISO_UNDERFIE_Pos 2 /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Position */ 3851 #define USBHS_HSTPIPIMR_ISO_UNDERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_ISO_UNDERFIE_Pos) /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Mask */ 3852 #define USBHS_HSTPIPIMR_ISO_UNDERFIE USBHS_HSTPIPIMR_ISO_UNDERFIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_ISO_UNDERFIE_Msk instead */ 3853 #define USBHS_HSTPIPIMR_ISO_CRCERRE_Pos 6 /**< (USBHS_HSTPIPIMR) CRC Error Interrupt Enable Position */ 3854 #define USBHS_HSTPIPIMR_ISO_CRCERRE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_ISO_CRCERRE_Pos) /**< (USBHS_HSTPIPIMR) CRC Error Interrupt Enable Mask */ 3855 #define USBHS_HSTPIPIMR_ISO_CRCERRE USBHS_HSTPIPIMR_ISO_CRCERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_ISO_CRCERRE_Msk instead */ 3856 #define USBHS_HSTPIPIMR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIMR_ISO) Register MASK (Use USBHS_HSTPIPIMR_ISO_Msk instead) */ 3857 #define USBHS_HSTPIPIMR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPIMR_ISO) Register Mask */ 3858 3859 /* BLK mode */ 3860 #define USBHS_HSTPIPIMR_BLK_TXSTPE_Pos 2 /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Position */ 3861 #define USBHS_HSTPIPIMR_BLK_TXSTPE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_BLK_TXSTPE_Pos) /**< (USBHS_HSTPIPIMR) Transmitted SETUP Interrupt Enable Mask */ 3862 #define USBHS_HSTPIPIMR_BLK_TXSTPE USBHS_HSTPIPIMR_BLK_TXSTPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_BLK_TXSTPE_Msk instead */ 3863 #define USBHS_HSTPIPIMR_BLK_RXSTALLDE_Pos 6 /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ 3864 #define USBHS_HSTPIPIMR_BLK_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_BLK_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ 3865 #define USBHS_HSTPIPIMR_BLK_RXSTALLDE USBHS_HSTPIPIMR_BLK_RXSTALLDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_BLK_RXSTALLDE_Msk instead */ 3866 #define USBHS_HSTPIPIMR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIMR_BLK) Register MASK (Use USBHS_HSTPIPIMR_BLK_Msk instead) */ 3867 #define USBHS_HSTPIPIMR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPIMR_BLK) Register Mask */ 3868 3869 /* INTRPT mode */ 3870 #define USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Pos 2 /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Position */ 3871 #define USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Pos) /**< (USBHS_HSTPIPIMR) Underflow Interrupt Enable Mask */ 3872 #define USBHS_HSTPIPIMR_INTRPT_UNDERFIE USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_INTRPT_UNDERFIE_Msk instead */ 3873 #define USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Pos 6 /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Position */ 3874 #define USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Msk (_U_(0x1) << USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Pos) /**< (USBHS_HSTPIPIMR) Received STALLed Interrupt Enable Mask */ 3875 #define USBHS_HSTPIPIMR_INTRPT_RXSTALLDE USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIMR_INTRPT_RXSTALLDE_Msk instead */ 3876 #define USBHS_HSTPIPIMR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIMR_INTRPT) Register MASK (Use USBHS_HSTPIPIMR_INTRPT_Msk instead) */ 3877 #define USBHS_HSTPIPIMR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPIMR_INTRPT) Register Mask */ 3878 3879 3880 /* -------- USBHS_HSTPIPIER : (USBHS Offset: 0x5f0) (/W 32) Host Pipe Enable Register -------- */ 3881 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3882 #if COMPONENT_TYPEDEF_STYLE == 'N' 3883 typedef union { 3884 struct { 3885 uint32_t RXINES:1; /**< bit: 0 Received IN Data Interrupt Enable */ 3886 uint32_t TXOUTES:1; /**< bit: 1 Transmitted OUT Data Interrupt Enable */ 3887 uint32_t :1; /**< bit: 2 Reserved */ 3888 uint32_t PERRES:1; /**< bit: 3 Pipe Error Interrupt Enable */ 3889 uint32_t NAKEDES:1; /**< bit: 4 NAKed Interrupt Enable */ 3890 uint32_t OVERFIES:1; /**< bit: 5 Overflow Interrupt Enable */ 3891 uint32_t :1; /**< bit: 6 Reserved */ 3892 uint32_t SHORTPACKETIES:1; /**< bit: 7 Short Packet Interrupt Enable */ 3893 uint32_t :4; /**< bit: 8..11 Reserved */ 3894 uint32_t NBUSYBKES:1; /**< bit: 12 Number of Busy Banks Enable */ 3895 uint32_t :3; /**< bit: 13..15 Reserved */ 3896 uint32_t PDISHDMAS:1; /**< bit: 16 Pipe Interrupts Disable HDMA Request Enable */ 3897 uint32_t PFREEZES:1; /**< bit: 17 Pipe Freeze Enable */ 3898 uint32_t RSTDTS:1; /**< bit: 18 Reset Data Toggle Enable */ 3899 uint32_t :13; /**< bit: 19..31 Reserved */ 3900 } bit; /**< Structure used for bit access */ 3901 struct { // CTRL mode 3902 uint32_t :2; /**< bit: 0..1 Reserved */ 3903 uint32_t TXSTPES:1; /**< bit: 2 Transmitted SETUP Interrupt Enable */ 3904 uint32_t :3; /**< bit: 3..5 Reserved */ 3905 uint32_t RXSTALLDES:1; /**< bit: 6 Received STALLed Interrupt Enable */ 3906 uint32_t :25; /**< bit: 7..31 Reserved */ 3907 } CTRL; /**< Structure used for CTRL mode access */ 3908 struct { // ISO mode 3909 uint32_t :2; /**< bit: 0..1 Reserved */ 3910 uint32_t UNDERFIES:1; /**< bit: 2 Underflow Interrupt Enable */ 3911 uint32_t :3; /**< bit: 3..5 Reserved */ 3912 uint32_t CRCERRES:1; /**< bit: 6 CRC Error Interrupt Enable */ 3913 uint32_t :25; /**< bit: 7..31 Reserved */ 3914 } ISO; /**< Structure used for ISO mode access */ 3915 struct { // BLK mode 3916 uint32_t :2; /**< bit: 0..1 Reserved */ 3917 uint32_t TXSTPES:1; /**< bit: 2 Transmitted SETUP Interrupt Enable */ 3918 uint32_t :3; /**< bit: 3..5 Reserved */ 3919 uint32_t RXSTALLDES:1; /**< bit: 6 Received STALLed Interrupt Enable */ 3920 uint32_t :25; /**< bit: 7..31 Reserved */ 3921 } BLK; /**< Structure used for BLK mode access */ 3922 struct { // INTRPT mode 3923 uint32_t :2; /**< bit: 0..1 Reserved */ 3924 uint32_t UNDERFIES:1; /**< bit: 2 Underflow Interrupt Enable */ 3925 uint32_t :3; /**< bit: 3..5 Reserved */ 3926 uint32_t RXSTALLDES:1; /**< bit: 6 Received STALLed Interrupt Enable */ 3927 uint32_t :25; /**< bit: 7..31 Reserved */ 3928 } INTRPT; /**< Structure used for INTRPT mode access */ 3929 uint32_t reg; /**< Type used for register access */ 3930 } USBHS_HSTPIPIER_Type; 3931 #endif 3932 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3933 3934 #define USBHS_HSTPIPIER_OFFSET (0x5F0) /**< (USBHS_HSTPIPIER) Host Pipe Enable Register Offset */ 3935 3936 #define USBHS_HSTPIPIER_RXINES_Pos 0 /**< (USBHS_HSTPIPIER) Received IN Data Interrupt Enable Position */ 3937 #define USBHS_HSTPIPIER_RXINES_Msk (_U_(0x1) << USBHS_HSTPIPIER_RXINES_Pos) /**< (USBHS_HSTPIPIER) Received IN Data Interrupt Enable Mask */ 3938 #define USBHS_HSTPIPIER_RXINES USBHS_HSTPIPIER_RXINES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_RXINES_Msk instead */ 3939 #define USBHS_HSTPIPIER_TXOUTES_Pos 1 /**< (USBHS_HSTPIPIER) Transmitted OUT Data Interrupt Enable Position */ 3940 #define USBHS_HSTPIPIER_TXOUTES_Msk (_U_(0x1) << USBHS_HSTPIPIER_TXOUTES_Pos) /**< (USBHS_HSTPIPIER) Transmitted OUT Data Interrupt Enable Mask */ 3941 #define USBHS_HSTPIPIER_TXOUTES USBHS_HSTPIPIER_TXOUTES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_TXOUTES_Msk instead */ 3942 #define USBHS_HSTPIPIER_PERRES_Pos 3 /**< (USBHS_HSTPIPIER) Pipe Error Interrupt Enable Position */ 3943 #define USBHS_HSTPIPIER_PERRES_Msk (_U_(0x1) << USBHS_HSTPIPIER_PERRES_Pos) /**< (USBHS_HSTPIPIER) Pipe Error Interrupt Enable Mask */ 3944 #define USBHS_HSTPIPIER_PERRES USBHS_HSTPIPIER_PERRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_PERRES_Msk instead */ 3945 #define USBHS_HSTPIPIER_NAKEDES_Pos 4 /**< (USBHS_HSTPIPIER) NAKed Interrupt Enable Position */ 3946 #define USBHS_HSTPIPIER_NAKEDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_NAKEDES_Pos) /**< (USBHS_HSTPIPIER) NAKed Interrupt Enable Mask */ 3947 #define USBHS_HSTPIPIER_NAKEDES USBHS_HSTPIPIER_NAKEDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_NAKEDES_Msk instead */ 3948 #define USBHS_HSTPIPIER_OVERFIES_Pos 5 /**< (USBHS_HSTPIPIER) Overflow Interrupt Enable Position */ 3949 #define USBHS_HSTPIPIER_OVERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_OVERFIES_Pos) /**< (USBHS_HSTPIPIER) Overflow Interrupt Enable Mask */ 3950 #define USBHS_HSTPIPIER_OVERFIES USBHS_HSTPIPIER_OVERFIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_OVERFIES_Msk instead */ 3951 #define USBHS_HSTPIPIER_SHORTPACKETIES_Pos 7 /**< (USBHS_HSTPIPIER) Short Packet Interrupt Enable Position */ 3952 #define USBHS_HSTPIPIER_SHORTPACKETIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_SHORTPACKETIES_Pos) /**< (USBHS_HSTPIPIER) Short Packet Interrupt Enable Mask */ 3953 #define USBHS_HSTPIPIER_SHORTPACKETIES USBHS_HSTPIPIER_SHORTPACKETIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_SHORTPACKETIES_Msk instead */ 3954 #define USBHS_HSTPIPIER_NBUSYBKES_Pos 12 /**< (USBHS_HSTPIPIER) Number of Busy Banks Enable Position */ 3955 #define USBHS_HSTPIPIER_NBUSYBKES_Msk (_U_(0x1) << USBHS_HSTPIPIER_NBUSYBKES_Pos) /**< (USBHS_HSTPIPIER) Number of Busy Banks Enable Mask */ 3956 #define USBHS_HSTPIPIER_NBUSYBKES USBHS_HSTPIPIER_NBUSYBKES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_NBUSYBKES_Msk instead */ 3957 #define USBHS_HSTPIPIER_PDISHDMAS_Pos 16 /**< (USBHS_HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Position */ 3958 #define USBHS_HSTPIPIER_PDISHDMAS_Msk (_U_(0x1) << USBHS_HSTPIPIER_PDISHDMAS_Pos) /**< (USBHS_HSTPIPIER) Pipe Interrupts Disable HDMA Request Enable Mask */ 3959 #define USBHS_HSTPIPIER_PDISHDMAS USBHS_HSTPIPIER_PDISHDMAS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_PDISHDMAS_Msk instead */ 3960 #define USBHS_HSTPIPIER_PFREEZES_Pos 17 /**< (USBHS_HSTPIPIER) Pipe Freeze Enable Position */ 3961 #define USBHS_HSTPIPIER_PFREEZES_Msk (_U_(0x1) << USBHS_HSTPIPIER_PFREEZES_Pos) /**< (USBHS_HSTPIPIER) Pipe Freeze Enable Mask */ 3962 #define USBHS_HSTPIPIER_PFREEZES USBHS_HSTPIPIER_PFREEZES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_PFREEZES_Msk instead */ 3963 #define USBHS_HSTPIPIER_RSTDTS_Pos 18 /**< (USBHS_HSTPIPIER) Reset Data Toggle Enable Position */ 3964 #define USBHS_HSTPIPIER_RSTDTS_Msk (_U_(0x1) << USBHS_HSTPIPIER_RSTDTS_Pos) /**< (USBHS_HSTPIPIER) Reset Data Toggle Enable Mask */ 3965 #define USBHS_HSTPIPIER_RSTDTS USBHS_HSTPIPIER_RSTDTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_RSTDTS_Msk instead */ 3966 #define USBHS_HSTPIPIER_MASK _U_(0x710BB) /**< \deprecated (USBHS_HSTPIPIER) Register MASK (Use USBHS_HSTPIPIER_Msk instead) */ 3967 #define USBHS_HSTPIPIER_Msk _U_(0x710BB) /**< (USBHS_HSTPIPIER) Register Mask */ 3968 3969 /* CTRL mode */ 3970 #define USBHS_HSTPIPIER_CTRL_TXSTPES_Pos 2 /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ 3971 #define USBHS_HSTPIPIER_CTRL_TXSTPES_Msk (_U_(0x1) << USBHS_HSTPIPIER_CTRL_TXSTPES_Pos) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ 3972 #define USBHS_HSTPIPIER_CTRL_TXSTPES USBHS_HSTPIPIER_CTRL_TXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_CTRL_TXSTPES_Msk instead */ 3973 #define USBHS_HSTPIPIER_CTRL_RXSTALLDES_Pos 6 /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ 3974 #define USBHS_HSTPIPIER_CTRL_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_CTRL_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ 3975 #define USBHS_HSTPIPIER_CTRL_RXSTALLDES USBHS_HSTPIPIER_CTRL_RXSTALLDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_CTRL_RXSTALLDES_Msk instead */ 3976 #define USBHS_HSTPIPIER_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIER_CTRL) Register MASK (Use USBHS_HSTPIPIER_CTRL_Msk instead) */ 3977 #define USBHS_HSTPIPIER_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPIER_CTRL) Register Mask */ 3978 3979 /* ISO mode */ 3980 #define USBHS_HSTPIPIER_ISO_UNDERFIES_Pos 2 /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Position */ 3981 #define USBHS_HSTPIPIER_ISO_UNDERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_ISO_UNDERFIES_Pos) /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Mask */ 3982 #define USBHS_HSTPIPIER_ISO_UNDERFIES USBHS_HSTPIPIER_ISO_UNDERFIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_ISO_UNDERFIES_Msk instead */ 3983 #define USBHS_HSTPIPIER_ISO_CRCERRES_Pos 6 /**< (USBHS_HSTPIPIER) CRC Error Interrupt Enable Position */ 3984 #define USBHS_HSTPIPIER_ISO_CRCERRES_Msk (_U_(0x1) << USBHS_HSTPIPIER_ISO_CRCERRES_Pos) /**< (USBHS_HSTPIPIER) CRC Error Interrupt Enable Mask */ 3985 #define USBHS_HSTPIPIER_ISO_CRCERRES USBHS_HSTPIPIER_ISO_CRCERRES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_ISO_CRCERRES_Msk instead */ 3986 #define USBHS_HSTPIPIER_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIER_ISO) Register MASK (Use USBHS_HSTPIPIER_ISO_Msk instead) */ 3987 #define USBHS_HSTPIPIER_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPIER_ISO) Register Mask */ 3988 3989 /* BLK mode */ 3990 #define USBHS_HSTPIPIER_BLK_TXSTPES_Pos 2 /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Position */ 3991 #define USBHS_HSTPIPIER_BLK_TXSTPES_Msk (_U_(0x1) << USBHS_HSTPIPIER_BLK_TXSTPES_Pos) /**< (USBHS_HSTPIPIER) Transmitted SETUP Interrupt Enable Mask */ 3992 #define USBHS_HSTPIPIER_BLK_TXSTPES USBHS_HSTPIPIER_BLK_TXSTPES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_BLK_TXSTPES_Msk instead */ 3993 #define USBHS_HSTPIPIER_BLK_RXSTALLDES_Pos 6 /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ 3994 #define USBHS_HSTPIPIER_BLK_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_BLK_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ 3995 #define USBHS_HSTPIPIER_BLK_RXSTALLDES USBHS_HSTPIPIER_BLK_RXSTALLDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_BLK_RXSTALLDES_Msk instead */ 3996 #define USBHS_HSTPIPIER_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIER_BLK) Register MASK (Use USBHS_HSTPIPIER_BLK_Msk instead) */ 3997 #define USBHS_HSTPIPIER_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPIER_BLK) Register Mask */ 3998 3999 /* INTRPT mode */ 4000 #define USBHS_HSTPIPIER_INTRPT_UNDERFIES_Pos 2 /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Position */ 4001 #define USBHS_HSTPIPIER_INTRPT_UNDERFIES_Msk (_U_(0x1) << USBHS_HSTPIPIER_INTRPT_UNDERFIES_Pos) /**< (USBHS_HSTPIPIER) Underflow Interrupt Enable Mask */ 4002 #define USBHS_HSTPIPIER_INTRPT_UNDERFIES USBHS_HSTPIPIER_INTRPT_UNDERFIES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_INTRPT_UNDERFIES_Msk instead */ 4003 #define USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Pos 6 /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Position */ 4004 #define USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Msk (_U_(0x1) << USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Pos) /**< (USBHS_HSTPIPIER) Received STALLed Interrupt Enable Mask */ 4005 #define USBHS_HSTPIPIER_INTRPT_RXSTALLDES USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIER_INTRPT_RXSTALLDES_Msk instead */ 4006 #define USBHS_HSTPIPIER_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIER_INTRPT) Register MASK (Use USBHS_HSTPIPIER_INTRPT_Msk instead) */ 4007 #define USBHS_HSTPIPIER_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPIER_INTRPT) Register Mask */ 4008 4009 4010 /* -------- USBHS_HSTPIPIDR : (USBHS Offset: 0x620) (/W 32) Host Pipe Disable Register -------- */ 4011 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4012 #if COMPONENT_TYPEDEF_STYLE == 'N' 4013 typedef union { 4014 struct { 4015 uint32_t RXINEC:1; /**< bit: 0 Received IN Data Interrupt Disable */ 4016 uint32_t TXOUTEC:1; /**< bit: 1 Transmitted OUT Data Interrupt Disable */ 4017 uint32_t :1; /**< bit: 2 Reserved */ 4018 uint32_t PERREC:1; /**< bit: 3 Pipe Error Interrupt Disable */ 4019 uint32_t NAKEDEC:1; /**< bit: 4 NAKed Interrupt Disable */ 4020 uint32_t OVERFIEC:1; /**< bit: 5 Overflow Interrupt Disable */ 4021 uint32_t :1; /**< bit: 6 Reserved */ 4022 uint32_t SHORTPACKETIEC:1; /**< bit: 7 Short Packet Interrupt Disable */ 4023 uint32_t :4; /**< bit: 8..11 Reserved */ 4024 uint32_t NBUSYBKEC:1; /**< bit: 12 Number of Busy Banks Disable */ 4025 uint32_t :1; /**< bit: 13 Reserved */ 4026 uint32_t FIFOCONC:1; /**< bit: 14 FIFO Control Disable */ 4027 uint32_t :1; /**< bit: 15 Reserved */ 4028 uint32_t PDISHDMAC:1; /**< bit: 16 Pipe Interrupts Disable HDMA Request Disable */ 4029 uint32_t PFREEZEC:1; /**< bit: 17 Pipe Freeze Disable */ 4030 uint32_t :14; /**< bit: 18..31 Reserved */ 4031 } bit; /**< Structure used for bit access */ 4032 struct { // CTRL mode 4033 uint32_t :2; /**< bit: 0..1 Reserved */ 4034 uint32_t TXSTPEC:1; /**< bit: 2 Transmitted SETUP Interrupt Disable */ 4035 uint32_t :3; /**< bit: 3..5 Reserved */ 4036 uint32_t RXSTALLDEC:1; /**< bit: 6 Received STALLed Interrupt Disable */ 4037 uint32_t :25; /**< bit: 7..31 Reserved */ 4038 } CTRL; /**< Structure used for CTRL mode access */ 4039 struct { // ISO mode 4040 uint32_t :2; /**< bit: 0..1 Reserved */ 4041 uint32_t UNDERFIEC:1; /**< bit: 2 Underflow Interrupt Disable */ 4042 uint32_t :3; /**< bit: 3..5 Reserved */ 4043 uint32_t CRCERREC:1; /**< bit: 6 CRC Error Interrupt Disable */ 4044 uint32_t :25; /**< bit: 7..31 Reserved */ 4045 } ISO; /**< Structure used for ISO mode access */ 4046 struct { // BLK mode 4047 uint32_t :2; /**< bit: 0..1 Reserved */ 4048 uint32_t TXSTPEC:1; /**< bit: 2 Transmitted SETUP Interrupt Disable */ 4049 uint32_t :3; /**< bit: 3..5 Reserved */ 4050 uint32_t RXSTALLDEC:1; /**< bit: 6 Received STALLed Interrupt Disable */ 4051 uint32_t :25; /**< bit: 7..31 Reserved */ 4052 } BLK; /**< Structure used for BLK mode access */ 4053 struct { // INTRPT mode 4054 uint32_t :2; /**< bit: 0..1 Reserved */ 4055 uint32_t UNDERFIEC:1; /**< bit: 2 Underflow Interrupt Disable */ 4056 uint32_t :3; /**< bit: 3..5 Reserved */ 4057 uint32_t RXSTALLDEC:1; /**< bit: 6 Received STALLed Interrupt Disable */ 4058 uint32_t :25; /**< bit: 7..31 Reserved */ 4059 } INTRPT; /**< Structure used for INTRPT mode access */ 4060 uint32_t reg; /**< Type used for register access */ 4061 } USBHS_HSTPIPIDR_Type; 4062 #endif 4063 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4064 4065 #define USBHS_HSTPIPIDR_OFFSET (0x620) /**< (USBHS_HSTPIPIDR) Host Pipe Disable Register Offset */ 4066 4067 #define USBHS_HSTPIPIDR_RXINEC_Pos 0 /**< (USBHS_HSTPIPIDR) Received IN Data Interrupt Disable Position */ 4068 #define USBHS_HSTPIPIDR_RXINEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_RXINEC_Pos) /**< (USBHS_HSTPIPIDR) Received IN Data Interrupt Disable Mask */ 4069 #define USBHS_HSTPIPIDR_RXINEC USBHS_HSTPIPIDR_RXINEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_RXINEC_Msk instead */ 4070 #define USBHS_HSTPIPIDR_TXOUTEC_Pos 1 /**< (USBHS_HSTPIPIDR) Transmitted OUT Data Interrupt Disable Position */ 4071 #define USBHS_HSTPIPIDR_TXOUTEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_TXOUTEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted OUT Data Interrupt Disable Mask */ 4072 #define USBHS_HSTPIPIDR_TXOUTEC USBHS_HSTPIPIDR_TXOUTEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_TXOUTEC_Msk instead */ 4073 #define USBHS_HSTPIPIDR_PERREC_Pos 3 /**< (USBHS_HSTPIPIDR) Pipe Error Interrupt Disable Position */ 4074 #define USBHS_HSTPIPIDR_PERREC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PERREC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Error Interrupt Disable Mask */ 4075 #define USBHS_HSTPIPIDR_PERREC USBHS_HSTPIPIDR_PERREC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_PERREC_Msk instead */ 4076 #define USBHS_HSTPIPIDR_NAKEDEC_Pos 4 /**< (USBHS_HSTPIPIDR) NAKed Interrupt Disable Position */ 4077 #define USBHS_HSTPIPIDR_NAKEDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_NAKEDEC_Pos) /**< (USBHS_HSTPIPIDR) NAKed Interrupt Disable Mask */ 4078 #define USBHS_HSTPIPIDR_NAKEDEC USBHS_HSTPIPIDR_NAKEDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_NAKEDEC_Msk instead */ 4079 #define USBHS_HSTPIPIDR_OVERFIEC_Pos 5 /**< (USBHS_HSTPIPIDR) Overflow Interrupt Disable Position */ 4080 #define USBHS_HSTPIPIDR_OVERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_OVERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Overflow Interrupt Disable Mask */ 4081 #define USBHS_HSTPIPIDR_OVERFIEC USBHS_HSTPIPIDR_OVERFIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_OVERFIEC_Msk instead */ 4082 #define USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos 7 /**< (USBHS_HSTPIPIDR) Short Packet Interrupt Disable Position */ 4083 #define USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_SHORTPACKETIEC_Pos) /**< (USBHS_HSTPIPIDR) Short Packet Interrupt Disable Mask */ 4084 #define USBHS_HSTPIPIDR_SHORTPACKETIEC USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_SHORTPACKETIEC_Msk instead */ 4085 #define USBHS_HSTPIPIDR_NBUSYBKEC_Pos 12 /**< (USBHS_HSTPIPIDR) Number of Busy Banks Disable Position */ 4086 #define USBHS_HSTPIPIDR_NBUSYBKEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_NBUSYBKEC_Pos) /**< (USBHS_HSTPIPIDR) Number of Busy Banks Disable Mask */ 4087 #define USBHS_HSTPIPIDR_NBUSYBKEC USBHS_HSTPIPIDR_NBUSYBKEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_NBUSYBKEC_Msk instead */ 4088 #define USBHS_HSTPIPIDR_FIFOCONC_Pos 14 /**< (USBHS_HSTPIPIDR) FIFO Control Disable Position */ 4089 #define USBHS_HSTPIPIDR_FIFOCONC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_FIFOCONC_Pos) /**< (USBHS_HSTPIPIDR) FIFO Control Disable Mask */ 4090 #define USBHS_HSTPIPIDR_FIFOCONC USBHS_HSTPIPIDR_FIFOCONC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_FIFOCONC_Msk instead */ 4091 #define USBHS_HSTPIPIDR_PDISHDMAC_Pos 16 /**< (USBHS_HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Position */ 4092 #define USBHS_HSTPIPIDR_PDISHDMAC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PDISHDMAC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Interrupts Disable HDMA Request Disable Mask */ 4093 #define USBHS_HSTPIPIDR_PDISHDMAC USBHS_HSTPIPIDR_PDISHDMAC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_PDISHDMAC_Msk instead */ 4094 #define USBHS_HSTPIPIDR_PFREEZEC_Pos 17 /**< (USBHS_HSTPIPIDR) Pipe Freeze Disable Position */ 4095 #define USBHS_HSTPIPIDR_PFREEZEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_PFREEZEC_Pos) /**< (USBHS_HSTPIPIDR) Pipe Freeze Disable Mask */ 4096 #define USBHS_HSTPIPIDR_PFREEZEC USBHS_HSTPIPIDR_PFREEZEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_PFREEZEC_Msk instead */ 4097 #define USBHS_HSTPIPIDR_MASK _U_(0x350BB) /**< \deprecated (USBHS_HSTPIPIDR) Register MASK (Use USBHS_HSTPIPIDR_Msk instead) */ 4098 #define USBHS_HSTPIPIDR_Msk _U_(0x350BB) /**< (USBHS_HSTPIPIDR) Register Mask */ 4099 4100 /* CTRL mode */ 4101 #define USBHS_HSTPIPIDR_CTRL_TXSTPEC_Pos 2 /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ 4102 #define USBHS_HSTPIPIDR_CTRL_TXSTPEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_CTRL_TXSTPEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ 4103 #define USBHS_HSTPIPIDR_CTRL_TXSTPEC USBHS_HSTPIPIDR_CTRL_TXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_CTRL_TXSTPEC_Msk instead */ 4104 #define USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Pos 6 /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ 4105 #define USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ 4106 #define USBHS_HSTPIPIDR_CTRL_RXSTALLDEC USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_CTRL_RXSTALLDEC_Msk instead */ 4107 #define USBHS_HSTPIPIDR_CTRL_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIDR_CTRL) Register MASK (Use USBHS_HSTPIPIDR_CTRL_Msk instead) */ 4108 #define USBHS_HSTPIPIDR_CTRL_Msk _U_(0x44) /**< (USBHS_HSTPIPIDR_CTRL) Register Mask */ 4109 4110 /* ISO mode */ 4111 #define USBHS_HSTPIPIDR_ISO_UNDERFIEC_Pos 2 /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Position */ 4112 #define USBHS_HSTPIPIDR_ISO_UNDERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_ISO_UNDERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Mask */ 4113 #define USBHS_HSTPIPIDR_ISO_UNDERFIEC USBHS_HSTPIPIDR_ISO_UNDERFIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_ISO_UNDERFIEC_Msk instead */ 4114 #define USBHS_HSTPIPIDR_ISO_CRCERREC_Pos 6 /**< (USBHS_HSTPIPIDR) CRC Error Interrupt Disable Position */ 4115 #define USBHS_HSTPIPIDR_ISO_CRCERREC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_ISO_CRCERREC_Pos) /**< (USBHS_HSTPIPIDR) CRC Error Interrupt Disable Mask */ 4116 #define USBHS_HSTPIPIDR_ISO_CRCERREC USBHS_HSTPIPIDR_ISO_CRCERREC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_ISO_CRCERREC_Msk instead */ 4117 #define USBHS_HSTPIPIDR_ISO_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIDR_ISO) Register MASK (Use USBHS_HSTPIPIDR_ISO_Msk instead) */ 4118 #define USBHS_HSTPIPIDR_ISO_Msk _U_(0x44) /**< (USBHS_HSTPIPIDR_ISO) Register Mask */ 4119 4120 /* BLK mode */ 4121 #define USBHS_HSTPIPIDR_BLK_TXSTPEC_Pos 2 /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Position */ 4122 #define USBHS_HSTPIPIDR_BLK_TXSTPEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_BLK_TXSTPEC_Pos) /**< (USBHS_HSTPIPIDR) Transmitted SETUP Interrupt Disable Mask */ 4123 #define USBHS_HSTPIPIDR_BLK_TXSTPEC USBHS_HSTPIPIDR_BLK_TXSTPEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_BLK_TXSTPEC_Msk instead */ 4124 #define USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Pos 6 /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ 4125 #define USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ 4126 #define USBHS_HSTPIPIDR_BLK_RXSTALLDEC USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_BLK_RXSTALLDEC_Msk instead */ 4127 #define USBHS_HSTPIPIDR_BLK_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIDR_BLK) Register MASK (Use USBHS_HSTPIPIDR_BLK_Msk instead) */ 4128 #define USBHS_HSTPIPIDR_BLK_Msk _U_(0x44) /**< (USBHS_HSTPIPIDR_BLK) Register Mask */ 4129 4130 /* INTRPT mode */ 4131 #define USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Pos 2 /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Position */ 4132 #define USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Pos) /**< (USBHS_HSTPIPIDR) Underflow Interrupt Disable Mask */ 4133 #define USBHS_HSTPIPIDR_INTRPT_UNDERFIEC USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_INTRPT_UNDERFIEC_Msk instead */ 4134 #define USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Pos 6 /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Position */ 4135 #define USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Msk (_U_(0x1) << USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Pos) /**< (USBHS_HSTPIPIDR) Received STALLed Interrupt Disable Mask */ 4136 #define USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPIDR_INTRPT_RXSTALLDEC_Msk instead */ 4137 #define USBHS_HSTPIPIDR_INTRPT_MASK _U_(0x44) /**< \deprecated (USBHS_HSTPIPIDR_INTRPT) Register MASK (Use USBHS_HSTPIPIDR_INTRPT_Msk instead) */ 4138 #define USBHS_HSTPIPIDR_INTRPT_Msk _U_(0x44) /**< (USBHS_HSTPIPIDR_INTRPT) Register Mask */ 4139 4140 4141 /* -------- USBHS_HSTPIPINRQ : (USBHS Offset: 0x650) (R/W 32) Host Pipe IN Request Register -------- */ 4142 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4143 #if COMPONENT_TYPEDEF_STYLE == 'N' 4144 typedef union { 4145 struct { 4146 uint32_t INRQ:8; /**< bit: 0..7 IN Request Number before Freeze */ 4147 uint32_t INMODE:1; /**< bit: 8 IN Request Mode */ 4148 uint32_t :23; /**< bit: 9..31 Reserved */ 4149 } bit; /**< Structure used for bit access */ 4150 uint32_t reg; /**< Type used for register access */ 4151 } USBHS_HSTPIPINRQ_Type; 4152 #endif 4153 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4154 4155 #define USBHS_HSTPIPINRQ_OFFSET (0x650) /**< (USBHS_HSTPIPINRQ) Host Pipe IN Request Register Offset */ 4156 4157 #define USBHS_HSTPIPINRQ_INRQ_Pos 0 /**< (USBHS_HSTPIPINRQ) IN Request Number before Freeze Position */ 4158 #define USBHS_HSTPIPINRQ_INRQ_Msk (_U_(0xFF) << USBHS_HSTPIPINRQ_INRQ_Pos) /**< (USBHS_HSTPIPINRQ) IN Request Number before Freeze Mask */ 4159 #define USBHS_HSTPIPINRQ_INRQ(value) (USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos)) 4160 #define USBHS_HSTPIPINRQ_INMODE_Pos 8 /**< (USBHS_HSTPIPINRQ) IN Request Mode Position */ 4161 #define USBHS_HSTPIPINRQ_INMODE_Msk (_U_(0x1) << USBHS_HSTPIPINRQ_INMODE_Pos) /**< (USBHS_HSTPIPINRQ) IN Request Mode Mask */ 4162 #define USBHS_HSTPIPINRQ_INMODE USBHS_HSTPIPINRQ_INMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPINRQ_INMODE_Msk instead */ 4163 #define USBHS_HSTPIPINRQ_MASK _U_(0x1FF) /**< \deprecated (USBHS_HSTPIPINRQ) Register MASK (Use USBHS_HSTPIPINRQ_Msk instead) */ 4164 #define USBHS_HSTPIPINRQ_Msk _U_(0x1FF) /**< (USBHS_HSTPIPINRQ) Register Mask */ 4165 4166 4167 /* -------- USBHS_HSTPIPERR : (USBHS Offset: 0x680) (R/W 32) Host Pipe Error Register -------- */ 4168 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4169 #if COMPONENT_TYPEDEF_STYLE == 'N' 4170 typedef union { 4171 struct { 4172 uint32_t DATATGL:1; /**< bit: 0 Data Toggle Error */ 4173 uint32_t DATAPID:1; /**< bit: 1 Data PID Error */ 4174 uint32_t PID:1; /**< bit: 2 Data PID Error */ 4175 uint32_t TIMEOUT:1; /**< bit: 3 Time-Out Error */ 4176 uint32_t CRC16:1; /**< bit: 4 CRC16 Error */ 4177 uint32_t COUNTER:2; /**< bit: 5..6 Error Counter */ 4178 uint32_t :25; /**< bit: 7..31 Reserved */ 4179 } bit; /**< Structure used for bit access */ 4180 struct { 4181 uint32_t :4; /**< bit: 0..3 Reserved */ 4182 uint32_t CRC:1; /**< bit: 4 CRCx6 Error */ 4183 uint32_t :27; /**< bit: 5..31 Reserved */ 4184 } vec; /**< Structure used for vec access */ 4185 uint32_t reg; /**< Type used for register access */ 4186 } USBHS_HSTPIPERR_Type; 4187 #endif 4188 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4189 4190 #define USBHS_HSTPIPERR_OFFSET (0x680) /**< (USBHS_HSTPIPERR) Host Pipe Error Register Offset */ 4191 4192 #define USBHS_HSTPIPERR_DATATGL_Pos 0 /**< (USBHS_HSTPIPERR) Data Toggle Error Position */ 4193 #define USBHS_HSTPIPERR_DATATGL_Msk (_U_(0x1) << USBHS_HSTPIPERR_DATATGL_Pos) /**< (USBHS_HSTPIPERR) Data Toggle Error Mask */ 4194 #define USBHS_HSTPIPERR_DATATGL USBHS_HSTPIPERR_DATATGL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_DATATGL_Msk instead */ 4195 #define USBHS_HSTPIPERR_DATAPID_Pos 1 /**< (USBHS_HSTPIPERR) Data PID Error Position */ 4196 #define USBHS_HSTPIPERR_DATAPID_Msk (_U_(0x1) << USBHS_HSTPIPERR_DATAPID_Pos) /**< (USBHS_HSTPIPERR) Data PID Error Mask */ 4197 #define USBHS_HSTPIPERR_DATAPID USBHS_HSTPIPERR_DATAPID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_DATAPID_Msk instead */ 4198 #define USBHS_HSTPIPERR_PID_Pos 2 /**< (USBHS_HSTPIPERR) Data PID Error Position */ 4199 #define USBHS_HSTPIPERR_PID_Msk (_U_(0x1) << USBHS_HSTPIPERR_PID_Pos) /**< (USBHS_HSTPIPERR) Data PID Error Mask */ 4200 #define USBHS_HSTPIPERR_PID USBHS_HSTPIPERR_PID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_PID_Msk instead */ 4201 #define USBHS_HSTPIPERR_TIMEOUT_Pos 3 /**< (USBHS_HSTPIPERR) Time-Out Error Position */ 4202 #define USBHS_HSTPIPERR_TIMEOUT_Msk (_U_(0x1) << USBHS_HSTPIPERR_TIMEOUT_Pos) /**< (USBHS_HSTPIPERR) Time-Out Error Mask */ 4203 #define USBHS_HSTPIPERR_TIMEOUT USBHS_HSTPIPERR_TIMEOUT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_TIMEOUT_Msk instead */ 4204 #define USBHS_HSTPIPERR_CRC16_Pos 4 /**< (USBHS_HSTPIPERR) CRC16 Error Position */ 4205 #define USBHS_HSTPIPERR_CRC16_Msk (_U_(0x1) << USBHS_HSTPIPERR_CRC16_Pos) /**< (USBHS_HSTPIPERR) CRC16 Error Mask */ 4206 #define USBHS_HSTPIPERR_CRC16 USBHS_HSTPIPERR_CRC16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_HSTPIPERR_CRC16_Msk instead */ 4207 #define USBHS_HSTPIPERR_COUNTER_Pos 5 /**< (USBHS_HSTPIPERR) Error Counter Position */ 4208 #define USBHS_HSTPIPERR_COUNTER_Msk (_U_(0x3) << USBHS_HSTPIPERR_COUNTER_Pos) /**< (USBHS_HSTPIPERR) Error Counter Mask */ 4209 #define USBHS_HSTPIPERR_COUNTER(value) (USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos)) 4210 #define USBHS_HSTPIPERR_MASK _U_(0x7F) /**< \deprecated (USBHS_HSTPIPERR) Register MASK (Use USBHS_HSTPIPERR_Msk instead) */ 4211 #define USBHS_HSTPIPERR_Msk _U_(0x7F) /**< (USBHS_HSTPIPERR) Register Mask */ 4212 4213 #define USBHS_HSTPIPERR_CRC_Pos 4 /**< (USBHS_HSTPIPERR Position) CRCx6 Error */ 4214 #define USBHS_HSTPIPERR_CRC_Msk (_U_(0x1) << USBHS_HSTPIPERR_CRC_Pos) /**< (USBHS_HSTPIPERR Mask) CRC */ 4215 #define USBHS_HSTPIPERR_CRC(value) (USBHS_HSTPIPERR_CRC_Msk & ((value) << USBHS_HSTPIPERR_CRC_Pos)) 4216 4217 /* -------- USBHS_CTRL : (USBHS Offset: 0x800) (R/W 32) General Control Register -------- */ 4218 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4219 #if COMPONENT_TYPEDEF_STYLE == 'N' 4220 typedef union { 4221 struct { 4222 uint32_t :4; /**< bit: 0..3 Reserved */ 4223 uint32_t RDERRE:1; /**< bit: 4 Remote Device Connection Error Interrupt Enable */ 4224 uint32_t :3; /**< bit: 5..7 Reserved */ 4225 uint32_t VBUSHWC:1; /**< bit: 8 VBUS Hardware Control */ 4226 uint32_t :5; /**< bit: 9..13 Reserved */ 4227 uint32_t FRZCLK:1; /**< bit: 14 Freeze USB Clock */ 4228 uint32_t USBE:1; /**< bit: 15 USBHS Enable */ 4229 uint32_t :8; /**< bit: 16..23 Reserved */ 4230 uint32_t UID:1; /**< bit: 24 UID Pin Enable */ 4231 uint32_t UIMOD:1; /**< bit: 25 USBHS Mode */ 4232 uint32_t :6; /**< bit: 26..31 Reserved */ 4233 } bit; /**< Structure used for bit access */ 4234 uint32_t reg; /**< Type used for register access */ 4235 } USBHS_CTRL_Type; 4236 #endif 4237 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4238 4239 #define USBHS_CTRL_OFFSET (0x800) /**< (USBHS_CTRL) General Control Register Offset */ 4240 4241 #define USBHS_CTRL_RDERRE_Pos 4 /**< (USBHS_CTRL) Remote Device Connection Error Interrupt Enable Position */ 4242 #define USBHS_CTRL_RDERRE_Msk (_U_(0x1) << USBHS_CTRL_RDERRE_Pos) /**< (USBHS_CTRL) Remote Device Connection Error Interrupt Enable Mask */ 4243 #define USBHS_CTRL_RDERRE USBHS_CTRL_RDERRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_RDERRE_Msk instead */ 4244 #define USBHS_CTRL_VBUSHWC_Pos 8 /**< (USBHS_CTRL) VBUS Hardware Control Position */ 4245 #define USBHS_CTRL_VBUSHWC_Msk (_U_(0x1) << USBHS_CTRL_VBUSHWC_Pos) /**< (USBHS_CTRL) VBUS Hardware Control Mask */ 4246 #define USBHS_CTRL_VBUSHWC USBHS_CTRL_VBUSHWC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_VBUSHWC_Msk instead */ 4247 #define USBHS_CTRL_FRZCLK_Pos 14 /**< (USBHS_CTRL) Freeze USB Clock Position */ 4248 #define USBHS_CTRL_FRZCLK_Msk (_U_(0x1) << USBHS_CTRL_FRZCLK_Pos) /**< (USBHS_CTRL) Freeze USB Clock Mask */ 4249 #define USBHS_CTRL_FRZCLK USBHS_CTRL_FRZCLK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_FRZCLK_Msk instead */ 4250 #define USBHS_CTRL_USBE_Pos 15 /**< (USBHS_CTRL) USBHS Enable Position */ 4251 #define USBHS_CTRL_USBE_Msk (_U_(0x1) << USBHS_CTRL_USBE_Pos) /**< (USBHS_CTRL) USBHS Enable Mask */ 4252 #define USBHS_CTRL_USBE USBHS_CTRL_USBE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_USBE_Msk instead */ 4253 #define USBHS_CTRL_UID_Pos 24 /**< (USBHS_CTRL) UID Pin Enable Position */ 4254 #define USBHS_CTRL_UID_Msk (_U_(0x1) << USBHS_CTRL_UID_Pos) /**< (USBHS_CTRL) UID Pin Enable Mask */ 4255 #define USBHS_CTRL_UID USBHS_CTRL_UID_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_UID_Msk instead */ 4256 #define USBHS_CTRL_UIMOD_Pos 25 /**< (USBHS_CTRL) USBHS Mode Position */ 4257 #define USBHS_CTRL_UIMOD_Msk (_U_(0x1) << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) USBHS Mode Mask */ 4258 #define USBHS_CTRL_UIMOD USBHS_CTRL_UIMOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_CTRL_UIMOD_Msk instead */ 4259 #define USBHS_CTRL_UIMOD_HOST_Val _U_(0x0) /**< (USBHS_CTRL) The module is in USB Host mode. */ 4260 #define USBHS_CTRL_UIMOD_DEVICE_Val _U_(0x1) /**< (USBHS_CTRL) The module is in USB Device mode. */ 4261 #define USBHS_CTRL_UIMOD_HOST (USBHS_CTRL_UIMOD_HOST_Val << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) The module is in USB Host mode. Position */ 4262 #define USBHS_CTRL_UIMOD_DEVICE (USBHS_CTRL_UIMOD_DEVICE_Val << USBHS_CTRL_UIMOD_Pos) /**< (USBHS_CTRL) The module is in USB Device mode. Position */ 4263 #define USBHS_CTRL_MASK _U_(0x300C110) /**< \deprecated (USBHS_CTRL) Register MASK (Use USBHS_CTRL_Msk instead) */ 4264 #define USBHS_CTRL_Msk _U_(0x300C110) /**< (USBHS_CTRL) Register Mask */ 4265 4266 4267 /* -------- USBHS_SR : (USBHS Offset: 0x804) (R/ 32) General Status Register -------- */ 4268 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4269 #if COMPONENT_TYPEDEF_STYLE == 'N' 4270 typedef union { 4271 struct { 4272 uint32_t :4; /**< bit: 0..3 Reserved */ 4273 uint32_t RDERRI:1; /**< bit: 4 Remote Device Connection Error Interrupt (Host mode only) */ 4274 uint32_t :7; /**< bit: 5..11 Reserved */ 4275 uint32_t SPEED:2; /**< bit: 12..13 Speed Status (Device mode only) */ 4276 uint32_t CLKUSABLE:1; /**< bit: 14 UTMI Clock Usable */ 4277 uint32_t :17; /**< bit: 15..31 Reserved */ 4278 } bit; /**< Structure used for bit access */ 4279 uint32_t reg; /**< Type used for register access */ 4280 } USBHS_SR_Type; 4281 #endif 4282 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4283 4284 #define USBHS_SR_OFFSET (0x804) /**< (USBHS_SR) General Status Register Offset */ 4285 4286 #define USBHS_SR_RDERRI_Pos 4 /**< (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) Position */ 4287 #define USBHS_SR_RDERRI_Msk (_U_(0x1) << USBHS_SR_RDERRI_Pos) /**< (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) Mask */ 4288 #define USBHS_SR_RDERRI USBHS_SR_RDERRI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SR_RDERRI_Msk instead */ 4289 #define USBHS_SR_SPEED_Pos 12 /**< (USBHS_SR) Speed Status (Device mode only) Position */ 4290 #define USBHS_SR_SPEED_Msk (_U_(0x3) << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Speed Status (Device mode only) Mask */ 4291 #define USBHS_SR_SPEED(value) (USBHS_SR_SPEED_Msk & ((value) << USBHS_SR_SPEED_Pos)) 4292 #define USBHS_SR_SPEED_FULL_SPEED_Val _U_(0x0) /**< (USBHS_SR) Full-Speed mode */ 4293 #define USBHS_SR_SPEED_HIGH_SPEED_Val _U_(0x1) /**< (USBHS_SR) High-Speed mode */ 4294 #define USBHS_SR_SPEED_LOW_SPEED_Val _U_(0x2) /**< (USBHS_SR) Low-Speed mode */ 4295 #define USBHS_SR_SPEED_FULL_SPEED (USBHS_SR_SPEED_FULL_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Full-Speed mode Position */ 4296 #define USBHS_SR_SPEED_HIGH_SPEED (USBHS_SR_SPEED_HIGH_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) High-Speed mode Position */ 4297 #define USBHS_SR_SPEED_LOW_SPEED (USBHS_SR_SPEED_LOW_SPEED_Val << USBHS_SR_SPEED_Pos) /**< (USBHS_SR) Low-Speed mode Position */ 4298 #define USBHS_SR_CLKUSABLE_Pos 14 /**< (USBHS_SR) UTMI Clock Usable Position */ 4299 #define USBHS_SR_CLKUSABLE_Msk (_U_(0x1) << USBHS_SR_CLKUSABLE_Pos) /**< (USBHS_SR) UTMI Clock Usable Mask */ 4300 #define USBHS_SR_CLKUSABLE USBHS_SR_CLKUSABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SR_CLKUSABLE_Msk instead */ 4301 #define USBHS_SR_MASK _U_(0x7010) /**< \deprecated (USBHS_SR) Register MASK (Use USBHS_SR_Msk instead) */ 4302 #define USBHS_SR_Msk _U_(0x7010) /**< (USBHS_SR) Register Mask */ 4303 4304 4305 /* -------- USBHS_SCR : (USBHS Offset: 0x808) (/W 32) General Status Clear Register -------- */ 4306 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4307 #if COMPONENT_TYPEDEF_STYLE == 'N' 4308 typedef union { 4309 struct { 4310 uint32_t :4; /**< bit: 0..3 Reserved */ 4311 uint32_t RDERRIC:1; /**< bit: 4 Remote Device Connection Error Interrupt Clear */ 4312 uint32_t :27; /**< bit: 5..31 Reserved */ 4313 } bit; /**< Structure used for bit access */ 4314 uint32_t reg; /**< Type used for register access */ 4315 } USBHS_SCR_Type; 4316 #endif 4317 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4318 4319 #define USBHS_SCR_OFFSET (0x808) /**< (USBHS_SCR) General Status Clear Register Offset */ 4320 4321 #define USBHS_SCR_RDERRIC_Pos 4 /**< (USBHS_SCR) Remote Device Connection Error Interrupt Clear Position */ 4322 #define USBHS_SCR_RDERRIC_Msk (_U_(0x1) << USBHS_SCR_RDERRIC_Pos) /**< (USBHS_SCR) Remote Device Connection Error Interrupt Clear Mask */ 4323 #define USBHS_SCR_RDERRIC USBHS_SCR_RDERRIC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SCR_RDERRIC_Msk instead */ 4324 #define USBHS_SCR_MASK _U_(0x10) /**< \deprecated (USBHS_SCR) Register MASK (Use USBHS_SCR_Msk instead) */ 4325 #define USBHS_SCR_Msk _U_(0x10) /**< (USBHS_SCR) Register Mask */ 4326 4327 4328 /* -------- USBHS_SFR : (USBHS Offset: 0x80c) (/W 32) General Status Set Register -------- */ 4329 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4330 #if COMPONENT_TYPEDEF_STYLE == 'N' 4331 typedef union { 4332 struct { 4333 uint32_t :4; /**< bit: 0..3 Reserved */ 4334 uint32_t RDERRIS:1; /**< bit: 4 Remote Device Connection Error Interrupt Set */ 4335 uint32_t :4; /**< bit: 5..8 Reserved */ 4336 uint32_t VBUSRQS:1; /**< bit: 9 VBUS Request Set */ 4337 uint32_t :22; /**< bit: 10..31 Reserved */ 4338 } bit; /**< Structure used for bit access */ 4339 uint32_t reg; /**< Type used for register access */ 4340 } USBHS_SFR_Type; 4341 #endif 4342 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4343 4344 #define USBHS_SFR_OFFSET (0x80C) /**< (USBHS_SFR) General Status Set Register Offset */ 4345 4346 #define USBHS_SFR_RDERRIS_Pos 4 /**< (USBHS_SFR) Remote Device Connection Error Interrupt Set Position */ 4347 #define USBHS_SFR_RDERRIS_Msk (_U_(0x1) << USBHS_SFR_RDERRIS_Pos) /**< (USBHS_SFR) Remote Device Connection Error Interrupt Set Mask */ 4348 #define USBHS_SFR_RDERRIS USBHS_SFR_RDERRIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SFR_RDERRIS_Msk instead */ 4349 #define USBHS_SFR_VBUSRQS_Pos 9 /**< (USBHS_SFR) VBUS Request Set Position */ 4350 #define USBHS_SFR_VBUSRQS_Msk (_U_(0x1) << USBHS_SFR_VBUSRQS_Pos) /**< (USBHS_SFR) VBUS Request Set Mask */ 4351 #define USBHS_SFR_VBUSRQS USBHS_SFR_VBUSRQS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use USBHS_SFR_VBUSRQS_Msk instead */ 4352 #define USBHS_SFR_MASK _U_(0x210) /**< \deprecated (USBHS_SFR) Register MASK (Use USBHS_SFR_Msk instead) */ 4353 #define USBHS_SFR_Msk _U_(0x210) /**< (USBHS_SFR) Register Mask */ 4354 4355 4356 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 4357 #if COMPONENT_TYPEDEF_STYLE == 'R' 4358 /** \brief USBHS_DEVDMA hardware registers */ 4359 typedef struct { 4360 __IO uint32_t USBHS_DEVDMANXTDSC; /**< (USBHS_DEVDMA Offset: 0x00) Device DMA Channel Next Descriptor Address Register */ 4361 __IO uint32_t USBHS_DEVDMAADDRESS; /**< (USBHS_DEVDMA Offset: 0x04) Device DMA Channel Address Register */ 4362 __IO uint32_t USBHS_DEVDMACONTROL; /**< (USBHS_DEVDMA Offset: 0x08) Device DMA Channel Control Register */ 4363 __IO uint32_t USBHS_DEVDMASTATUS; /**< (USBHS_DEVDMA Offset: 0x0C) Device DMA Channel Status Register */ 4364 } UsbhsDevdma; 4365 4366 /** \brief USBHS_HSTDMA hardware registers */ 4367 typedef struct { 4368 __IO uint32_t USBHS_HSTDMANXTDSC; /**< (USBHS_HSTDMA Offset: 0x00) Host DMA Channel Next Descriptor Address Register */ 4369 __IO uint32_t USBHS_HSTDMAADDRESS; /**< (USBHS_HSTDMA Offset: 0x04) Host DMA Channel Address Register */ 4370 __IO uint32_t USBHS_HSTDMACONTROL; /**< (USBHS_HSTDMA Offset: 0x08) Host DMA Channel Control Register */ 4371 __IO uint32_t USBHS_HSTDMASTATUS; /**< (USBHS_HSTDMA Offset: 0x0C) Host DMA Channel Status Register */ 4372 } UsbhsHstdma; 4373 4374 #define USBHSDEVDMA_NUMBER 7 4375 #define USBHSHSTDMA_NUMBER 7 4376 /** \brief USBHS hardware registers */ 4377 typedef struct { 4378 __IO uint32_t USBHS_DEVCTRL; /**< (USBHS Offset: 0x00) Device General Control Register */ 4379 __I uint32_t USBHS_DEVISR; /**< (USBHS Offset: 0x04) Device Global Interrupt Status Register */ 4380 __O uint32_t USBHS_DEVICR; /**< (USBHS Offset: 0x08) Device Global Interrupt Clear Register */ 4381 __O uint32_t USBHS_DEVIFR; /**< (USBHS Offset: 0x0C) Device Global Interrupt Set Register */ 4382 __I uint32_t USBHS_DEVIMR; /**< (USBHS Offset: 0x10) Device Global Interrupt Mask Register */ 4383 __O uint32_t USBHS_DEVIDR; /**< (USBHS Offset: 0x14) Device Global Interrupt Disable Register */ 4384 __O uint32_t USBHS_DEVIER; /**< (USBHS Offset: 0x18) Device Global Interrupt Enable Register */ 4385 __IO uint32_t USBHS_DEVEPT; /**< (USBHS Offset: 0x1C) Device Endpoint Register */ 4386 __I uint32_t USBHS_DEVFNUM; /**< (USBHS Offset: 0x20) Device Frame Number Register */ 4387 __I uint8_t Reserved1[220]; 4388 __IO uint32_t USBHS_DEVEPTCFG[10]; /**< (USBHS Offset: 0x100) Device Endpoint Configuration Register */ 4389 __I uint8_t Reserved2[8]; 4390 __I uint32_t USBHS_DEVEPTISR[10]; /**< (USBHS Offset: 0x130) Device Endpoint Interrupt Status Register */ 4391 __I uint8_t Reserved3[8]; 4392 __O uint32_t USBHS_DEVEPTICR[10]; /**< (USBHS Offset: 0x160) Device Endpoint Interrupt Clear Register */ 4393 __I uint8_t Reserved4[8]; 4394 __O uint32_t USBHS_DEVEPTIFR[10]; /**< (USBHS Offset: 0x190) Device Endpoint Interrupt Set Register */ 4395 __I uint8_t Reserved5[8]; 4396 __I uint32_t USBHS_DEVEPTIMR[10]; /**< (USBHS Offset: 0x1C0) Device Endpoint Interrupt Mask Register */ 4397 __I uint8_t Reserved6[8]; 4398 __O uint32_t USBHS_DEVEPTIER[10]; /**< (USBHS Offset: 0x1F0) Device Endpoint Interrupt Enable Register */ 4399 __I uint8_t Reserved7[8]; 4400 __O uint32_t USBHS_DEVEPTIDR[10]; /**< (USBHS Offset: 0x220) Device Endpoint Interrupt Disable Register */ 4401 __I uint8_t Reserved8[200]; 4402 UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register */ 4403 __I uint8_t Reserved9[128]; 4404 __IO uint32_t USBHS_HSTCTRL; /**< (USBHS Offset: 0x400) Host General Control Register */ 4405 __I uint32_t USBHS_HSTISR; /**< (USBHS Offset: 0x404) Host Global Interrupt Status Register */ 4406 __O uint32_t USBHS_HSTICR; /**< (USBHS Offset: 0x408) Host Global Interrupt Clear Register */ 4407 __O uint32_t USBHS_HSTIFR; /**< (USBHS Offset: 0x40C) Host Global Interrupt Set Register */ 4408 __I uint32_t USBHS_HSTIMR; /**< (USBHS Offset: 0x410) Host Global Interrupt Mask Register */ 4409 __O uint32_t USBHS_HSTIDR; /**< (USBHS Offset: 0x414) Host Global Interrupt Disable Register */ 4410 __O uint32_t USBHS_HSTIER; /**< (USBHS Offset: 0x418) Host Global Interrupt Enable Register */ 4411 __IO uint32_t USBHS_HSTPIP; /**< (USBHS Offset: 0x41C) Host Pipe Register */ 4412 __IO uint32_t USBHS_HSTFNUM; /**< (USBHS Offset: 0x420) Host Frame Number Register */ 4413 __IO uint32_t USBHS_HSTADDR1; /**< (USBHS Offset: 0x424) Host Address 1 Register */ 4414 __IO uint32_t USBHS_HSTADDR2; /**< (USBHS Offset: 0x428) Host Address 2 Register */ 4415 __IO uint32_t USBHS_HSTADDR3; /**< (USBHS Offset: 0x42C) Host Address 3 Register */ 4416 __I uint8_t Reserved10[208]; 4417 __IO uint32_t USBHS_HSTPIPCFG[10]; /**< (USBHS Offset: 0x500) Host Pipe Configuration Register */ 4418 __I uint8_t Reserved11[8]; 4419 __I uint32_t USBHS_HSTPIPISR[10]; /**< (USBHS Offset: 0x530) Host Pipe Status Register */ 4420 __I uint8_t Reserved12[8]; 4421 __O uint32_t USBHS_HSTPIPICR[10]; /**< (USBHS Offset: 0x560) Host Pipe Clear Register */ 4422 __I uint8_t Reserved13[8]; 4423 __O uint32_t USBHS_HSTPIPIFR[10]; /**< (USBHS Offset: 0x590) Host Pipe Set Register */ 4424 __I uint8_t Reserved14[8]; 4425 __I uint32_t USBHS_HSTPIPIMR[10]; /**< (USBHS Offset: 0x5C0) Host Pipe Mask Register */ 4426 __I uint8_t Reserved15[8]; 4427 __O uint32_t USBHS_HSTPIPIER[10]; /**< (USBHS Offset: 0x5F0) Host Pipe Enable Register */ 4428 __I uint8_t Reserved16[8]; 4429 __O uint32_t USBHS_HSTPIPIDR[10]; /**< (USBHS Offset: 0x620) Host Pipe Disable Register */ 4430 __I uint8_t Reserved17[8]; 4431 __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< (USBHS Offset: 0x650) Host Pipe IN Request Register */ 4432 __I uint8_t Reserved18[8]; 4433 __IO uint32_t USBHS_HSTPIPERR[10]; /**< (USBHS Offset: 0x680) Host Pipe Error Register */ 4434 __I uint8_t Reserved19[104]; 4435 UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register */ 4436 __I uint8_t Reserved20[128]; 4437 __IO uint32_t USBHS_CTRL; /**< (USBHS Offset: 0x800) General Control Register */ 4438 __I uint32_t USBHS_SR; /**< (USBHS Offset: 0x804) General Status Register */ 4439 __O uint32_t USBHS_SCR; /**< (USBHS Offset: 0x808) General Status Clear Register */ 4440 __O uint32_t USBHS_SFR; /**< (USBHS Offset: 0x80C) General Status Set Register */ 4441 } Usbhs; 4442 4443 #elif COMPONENT_TYPEDEF_STYLE == 'N' 4444 /** \brief USBHS_DEVDMA hardware registers */ 4445 typedef struct { 4446 __IO USBHS_DEVDMANXTDSC_Type USBHS_DEVDMANXTDSC; /**< Offset: 0x00 (R/W 32) Device DMA Channel Next Descriptor Address Register */ 4447 __IO USBHS_DEVDMAADDRESS_Type USBHS_DEVDMAADDRESS; /**< Offset: 0x04 (R/W 32) Device DMA Channel Address Register */ 4448 __IO USBHS_DEVDMACONTROL_Type USBHS_DEVDMACONTROL; /**< Offset: 0x08 (R/W 32) Device DMA Channel Control Register */ 4449 __IO USBHS_DEVDMASTATUS_Type USBHS_DEVDMASTATUS; /**< Offset: 0x0C (R/W 32) Device DMA Channel Status Register */ 4450 } UsbhsDevdma; 4451 4452 /** \brief USBHS_HSTDMA hardware registers */ 4453 typedef struct { 4454 __IO USBHS_HSTDMANXTDSC_Type USBHS_HSTDMANXTDSC; /**< Offset: 0x00 (R/W 32) Host DMA Channel Next Descriptor Address Register */ 4455 __IO USBHS_HSTDMAADDRESS_Type USBHS_HSTDMAADDRESS; /**< Offset: 0x04 (R/W 32) Host DMA Channel Address Register */ 4456 __IO USBHS_HSTDMACONTROL_Type USBHS_HSTDMACONTROL; /**< Offset: 0x08 (R/W 32) Host DMA Channel Control Register */ 4457 __IO USBHS_HSTDMASTATUS_Type USBHS_HSTDMASTATUS; /**< Offset: 0x0C (R/W 32) Host DMA Channel Status Register */ 4458 } UsbhsHstdma; 4459 4460 /** \brief USBHS hardware registers */ 4461 typedef struct { 4462 __IO USBHS_DEVCTRL_Type USBHS_DEVCTRL; /**< Offset: 0x00 (R/W 32) Device General Control Register */ 4463 __I USBHS_DEVISR_Type USBHS_DEVISR; /**< Offset: 0x04 (R/ 32) Device Global Interrupt Status Register */ 4464 __O USBHS_DEVICR_Type USBHS_DEVICR; /**< Offset: 0x08 ( /W 32) Device Global Interrupt Clear Register */ 4465 __O USBHS_DEVIFR_Type USBHS_DEVIFR; /**< Offset: 0x0C ( /W 32) Device Global Interrupt Set Register */ 4466 __I USBHS_DEVIMR_Type USBHS_DEVIMR; /**< Offset: 0x10 (R/ 32) Device Global Interrupt Mask Register */ 4467 __O USBHS_DEVIDR_Type USBHS_DEVIDR; /**< Offset: 0x14 ( /W 32) Device Global Interrupt Disable Register */ 4468 __O USBHS_DEVIER_Type USBHS_DEVIER; /**< Offset: 0x18 ( /W 32) Device Global Interrupt Enable Register */ 4469 __IO USBHS_DEVEPT_Type USBHS_DEVEPT; /**< Offset: 0x1C (R/W 32) Device Endpoint Register */ 4470 __I USBHS_DEVFNUM_Type USBHS_DEVFNUM; /**< Offset: 0x20 (R/ 32) Device Frame Number Register */ 4471 __I uint8_t Reserved1[220]; 4472 __IO USBHS_DEVEPTCFG_Type USBHS_DEVEPTCFG[10]; /**< Offset: 0x100 (R/W 32) Device Endpoint Configuration Register */ 4473 __I uint8_t Reserved2[8]; 4474 __I USBHS_DEVEPTISR_Type USBHS_DEVEPTISR[10]; /**< Offset: 0x130 (R/ 32) Device Endpoint Interrupt Status Register */ 4475 __I uint8_t Reserved3[8]; 4476 __O USBHS_DEVEPTICR_Type USBHS_DEVEPTICR[10]; /**< Offset: 0x160 ( /W 32) Device Endpoint Interrupt Clear Register */ 4477 __I uint8_t Reserved4[8]; 4478 __O USBHS_DEVEPTIFR_Type USBHS_DEVEPTIFR[10]; /**< Offset: 0x190 ( /W 32) Device Endpoint Interrupt Set Register */ 4479 __I uint8_t Reserved5[8]; 4480 __I USBHS_DEVEPTIMR_Type USBHS_DEVEPTIMR[10]; /**< Offset: 0x1C0 (R/ 32) Device Endpoint Interrupt Mask Register */ 4481 __I uint8_t Reserved6[8]; 4482 __O USBHS_DEVEPTIER_Type USBHS_DEVEPTIER[10]; /**< Offset: 0x1F0 ( /W 32) Device Endpoint Interrupt Enable Register */ 4483 __I uint8_t Reserved7[8]; 4484 __O USBHS_DEVEPTIDR_Type USBHS_DEVEPTIDR[10]; /**< Offset: 0x220 ( /W 32) Device Endpoint Interrupt Disable Register */ 4485 __I uint8_t Reserved8[200]; 4486 UsbhsDevdma USBHS_DEVDMA[7]; /**< Offset: 0x310 Device DMA Channel Next Descriptor Address Register */ 4487 __I uint8_t Reserved9[128]; 4488 __IO USBHS_HSTCTRL_Type USBHS_HSTCTRL; /**< Offset: 0x400 (R/W 32) Host General Control Register */ 4489 __I USBHS_HSTISR_Type USBHS_HSTISR; /**< Offset: 0x404 (R/ 32) Host Global Interrupt Status Register */ 4490 __O USBHS_HSTICR_Type USBHS_HSTICR; /**< Offset: 0x408 ( /W 32) Host Global Interrupt Clear Register */ 4491 __O USBHS_HSTIFR_Type USBHS_HSTIFR; /**< Offset: 0x40C ( /W 32) Host Global Interrupt Set Register */ 4492 __I USBHS_HSTIMR_Type USBHS_HSTIMR; /**< Offset: 0x410 (R/ 32) Host Global Interrupt Mask Register */ 4493 __O USBHS_HSTIDR_Type USBHS_HSTIDR; /**< Offset: 0x414 ( /W 32) Host Global Interrupt Disable Register */ 4494 __O USBHS_HSTIER_Type USBHS_HSTIER; /**< Offset: 0x418 ( /W 32) Host Global Interrupt Enable Register */ 4495 __IO USBHS_HSTPIP_Type USBHS_HSTPIP; /**< Offset: 0x41C (R/W 32) Host Pipe Register */ 4496 __IO USBHS_HSTFNUM_Type USBHS_HSTFNUM; /**< Offset: 0x420 (R/W 32) Host Frame Number Register */ 4497 __IO USBHS_HSTADDR1_Type USBHS_HSTADDR1; /**< Offset: 0x424 (R/W 32) Host Address 1 Register */ 4498 __IO USBHS_HSTADDR2_Type USBHS_HSTADDR2; /**< Offset: 0x428 (R/W 32) Host Address 2 Register */ 4499 __IO USBHS_HSTADDR3_Type USBHS_HSTADDR3; /**< Offset: 0x42C (R/W 32) Host Address 3 Register */ 4500 __I uint8_t Reserved10[208]; 4501 __IO USBHS_HSTPIPCFG_Type USBHS_HSTPIPCFG[10]; /**< Offset: 0x500 (R/W 32) Host Pipe Configuration Register */ 4502 __I uint8_t Reserved11[8]; 4503 __I USBHS_HSTPIPISR_Type USBHS_HSTPIPISR[10]; /**< Offset: 0x530 (R/ 32) Host Pipe Status Register */ 4504 __I uint8_t Reserved12[8]; 4505 __O USBHS_HSTPIPICR_Type USBHS_HSTPIPICR[10]; /**< Offset: 0x560 ( /W 32) Host Pipe Clear Register */ 4506 __I uint8_t Reserved13[8]; 4507 __O USBHS_HSTPIPIFR_Type USBHS_HSTPIPIFR[10]; /**< Offset: 0x590 ( /W 32) Host Pipe Set Register */ 4508 __I uint8_t Reserved14[8]; 4509 __I USBHS_HSTPIPIMR_Type USBHS_HSTPIPIMR[10]; /**< Offset: 0x5C0 (R/ 32) Host Pipe Mask Register */ 4510 __I uint8_t Reserved15[8]; 4511 __O USBHS_HSTPIPIER_Type USBHS_HSTPIPIER[10]; /**< Offset: 0x5F0 ( /W 32) Host Pipe Enable Register */ 4512 __I uint8_t Reserved16[8]; 4513 __O USBHS_HSTPIPIDR_Type USBHS_HSTPIPIDR[10]; /**< Offset: 0x620 ( /W 32) Host Pipe Disable Register */ 4514 __I uint8_t Reserved17[8]; 4515 __IO USBHS_HSTPIPINRQ_Type USBHS_HSTPIPINRQ[10]; /**< Offset: 0x650 (R/W 32) Host Pipe IN Request Register */ 4516 __I uint8_t Reserved18[8]; 4517 __IO USBHS_HSTPIPERR_Type USBHS_HSTPIPERR[10]; /**< Offset: 0x680 (R/W 32) Host Pipe Error Register */ 4518 __I uint8_t Reserved19[104]; 4519 UsbhsHstdma USBHS_HSTDMA[7]; /**< Offset: 0x710 Host DMA Channel Next Descriptor Address Register */ 4520 __I uint8_t Reserved20[128]; 4521 __IO USBHS_CTRL_Type USBHS_CTRL; /**< Offset: 0x800 (R/W 32) General Control Register */ 4522 __I USBHS_SR_Type USBHS_SR; /**< Offset: 0x804 (R/ 32) General Status Register */ 4523 __O USBHS_SCR_Type USBHS_SCR; /**< Offset: 0x808 ( /W 32) General Status Clear Register */ 4524 __O USBHS_SFR_Type USBHS_SFR; /**< Offset: 0x80C ( /W 32) General Status Set Register */ 4525 } Usbhs; 4526 4527 #else /* COMPONENT_TYPEDEF_STYLE */ 4528 #error Unknown component typedef style 4529 #endif /* COMPONENT_TYPEDEF_STYLE */ 4530 4531 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4532 /** @} end of USB High-Speed Interface */ 4533 4534 #if !(defined(DO_NOT_USE_DEPRECATED_MACROS)) 4535 #include "deprecated/usbhs.h" 4536 #endif /* DO_NOT_USE_DEPRECATED_MACROS */ 4537 #endif /* _SAME70_USBHS_COMPONENT_H_ */ 4538
