1 /** 2 * \file 3 * 4 * \brief Component description for UART 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:19:59Z */ 31 #ifndef _SAME70_UART_COMPONENT_H_ 32 #define _SAME70_UART_COMPONENT_H_ 33 #define _SAME70_UART_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 Universal Asynchronous Receiver Transmitter 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR UART */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define UART_6418 /**< (UART) Module ID */ 46 #define REV_UART R /**< (UART) Module revision */ 47 48 /* -------- UART_CR : (UART Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t :2; /**< bit: 0..1 Reserved */ 54 uint32_t RSTRX:1; /**< bit: 2 Reset Receiver */ 55 uint32_t RSTTX:1; /**< bit: 3 Reset Transmitter */ 56 uint32_t RXEN:1; /**< bit: 4 Receiver Enable */ 57 uint32_t RXDIS:1; /**< bit: 5 Receiver Disable */ 58 uint32_t TXEN:1; /**< bit: 6 Transmitter Enable */ 59 uint32_t TXDIS:1; /**< bit: 7 Transmitter Disable */ 60 uint32_t RSTSTA:1; /**< bit: 8 Reset Status */ 61 uint32_t :3; /**< bit: 9..11 Reserved */ 62 uint32_t REQCLR:1; /**< bit: 12 Request Clear */ 63 uint32_t :19; /**< bit: 13..31 Reserved */ 64 } bit; /**< Structure used for bit access */ 65 uint32_t reg; /**< Type used for register access */ 66 } UART_CR_Type; 67 #endif 68 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 #define UART_CR_OFFSET (0x00) /**< (UART_CR) Control Register Offset */ 71 72 #define UART_CR_RSTRX_Pos 2 /**< (UART_CR) Reset Receiver Position */ 73 #define UART_CR_RSTRX_Msk (_U_(0x1) << UART_CR_RSTRX_Pos) /**< (UART_CR) Reset Receiver Mask */ 74 #define UART_CR_RSTRX UART_CR_RSTRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RSTRX_Msk instead */ 75 #define UART_CR_RSTTX_Pos 3 /**< (UART_CR) Reset Transmitter Position */ 76 #define UART_CR_RSTTX_Msk (_U_(0x1) << UART_CR_RSTTX_Pos) /**< (UART_CR) Reset Transmitter Mask */ 77 #define UART_CR_RSTTX UART_CR_RSTTX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RSTTX_Msk instead */ 78 #define UART_CR_RXEN_Pos 4 /**< (UART_CR) Receiver Enable Position */ 79 #define UART_CR_RXEN_Msk (_U_(0x1) << UART_CR_RXEN_Pos) /**< (UART_CR) Receiver Enable Mask */ 80 #define UART_CR_RXEN UART_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RXEN_Msk instead */ 81 #define UART_CR_RXDIS_Pos 5 /**< (UART_CR) Receiver Disable Position */ 82 #define UART_CR_RXDIS_Msk (_U_(0x1) << UART_CR_RXDIS_Pos) /**< (UART_CR) Receiver Disable Mask */ 83 #define UART_CR_RXDIS UART_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RXDIS_Msk instead */ 84 #define UART_CR_TXEN_Pos 6 /**< (UART_CR) Transmitter Enable Position */ 85 #define UART_CR_TXEN_Msk (_U_(0x1) << UART_CR_TXEN_Pos) /**< (UART_CR) Transmitter Enable Mask */ 86 #define UART_CR_TXEN UART_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_TXEN_Msk instead */ 87 #define UART_CR_TXDIS_Pos 7 /**< (UART_CR) Transmitter Disable Position */ 88 #define UART_CR_TXDIS_Msk (_U_(0x1) << UART_CR_TXDIS_Pos) /**< (UART_CR) Transmitter Disable Mask */ 89 #define UART_CR_TXDIS UART_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_TXDIS_Msk instead */ 90 #define UART_CR_RSTSTA_Pos 8 /**< (UART_CR) Reset Status Position */ 91 #define UART_CR_RSTSTA_Msk (_U_(0x1) << UART_CR_RSTSTA_Pos) /**< (UART_CR) Reset Status Mask */ 92 #define UART_CR_RSTSTA UART_CR_RSTSTA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_RSTSTA_Msk instead */ 93 #define UART_CR_REQCLR_Pos 12 /**< (UART_CR) Request Clear Position */ 94 #define UART_CR_REQCLR_Msk (_U_(0x1) << UART_CR_REQCLR_Pos) /**< (UART_CR) Request Clear Mask */ 95 #define UART_CR_REQCLR UART_CR_REQCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CR_REQCLR_Msk instead */ 96 #define UART_CR_MASK _U_(0x11FC) /**< \deprecated (UART_CR) Register MASK (Use UART_CR_Msk instead) */ 97 #define UART_CR_Msk _U_(0x11FC) /**< (UART_CR) Register Mask */ 98 99 100 /* -------- UART_MR : (UART Offset: 0x04) (R/W 32) Mode Register -------- */ 101 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 102 #if COMPONENT_TYPEDEF_STYLE == 'N' 103 typedef union { 104 struct { 105 uint32_t :4; /**< bit: 0..3 Reserved */ 106 uint32_t FILTER:1; /**< bit: 4 Receiver Digital Filter */ 107 uint32_t :4; /**< bit: 5..8 Reserved */ 108 uint32_t PAR:3; /**< bit: 9..11 Parity Type */ 109 uint32_t BRSRCCK:1; /**< bit: 12 Baud Rate Source Clock */ 110 uint32_t :1; /**< bit: 13 Reserved */ 111 uint32_t CHMODE:2; /**< bit: 14..15 Channel Mode */ 112 uint32_t :16; /**< bit: 16..31 Reserved */ 113 } bit; /**< Structure used for bit access */ 114 uint32_t reg; /**< Type used for register access */ 115 } UART_MR_Type; 116 #endif 117 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 118 119 #define UART_MR_OFFSET (0x04) /**< (UART_MR) Mode Register Offset */ 120 121 #define UART_MR_FILTER_Pos 4 /**< (UART_MR) Receiver Digital Filter Position */ 122 #define UART_MR_FILTER_Msk (_U_(0x1) << UART_MR_FILTER_Pos) /**< (UART_MR) Receiver Digital Filter Mask */ 123 #define UART_MR_FILTER UART_MR_FILTER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_MR_FILTER_Msk instead */ 124 #define UART_MR_FILTER_DISABLED_Val _U_(0x0) /**< (UART_MR) UART does not filter the receive line. */ 125 #define UART_MR_FILTER_ENABLED_Val _U_(0x1) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ 126 #define UART_MR_FILTER_DISABLED (UART_MR_FILTER_DISABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART does not filter the receive line. Position */ 127 #define UART_MR_FILTER_ENABLED (UART_MR_FILTER_ENABLED_Val << UART_MR_FILTER_Pos) /**< (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). Position */ 128 #define UART_MR_PAR_Pos 9 /**< (UART_MR) Parity Type Position */ 129 #define UART_MR_PAR_Msk (_U_(0x7) << UART_MR_PAR_Pos) /**< (UART_MR) Parity Type Mask */ 130 #define UART_MR_PAR(value) (UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos)) 131 #define UART_MR_PAR_EVEN_Val _U_(0x0) /**< (UART_MR) Even Parity */ 132 #define UART_MR_PAR_ODD_Val _U_(0x1) /**< (UART_MR) Odd Parity */ 133 #define UART_MR_PAR_SPACE_Val _U_(0x2) /**< (UART_MR) Space: parity forced to 0 */ 134 #define UART_MR_PAR_MARK_Val _U_(0x3) /**< (UART_MR) Mark: parity forced to 1 */ 135 #define UART_MR_PAR_NO_Val _U_(0x4) /**< (UART_MR) No parity */ 136 #define UART_MR_PAR_EVEN (UART_MR_PAR_EVEN_Val << UART_MR_PAR_Pos) /**< (UART_MR) Even Parity Position */ 137 #define UART_MR_PAR_ODD (UART_MR_PAR_ODD_Val << UART_MR_PAR_Pos) /**< (UART_MR) Odd Parity Position */ 138 #define UART_MR_PAR_SPACE (UART_MR_PAR_SPACE_Val << UART_MR_PAR_Pos) /**< (UART_MR) Space: parity forced to 0 Position */ 139 #define UART_MR_PAR_MARK (UART_MR_PAR_MARK_Val << UART_MR_PAR_Pos) /**< (UART_MR) Mark: parity forced to 1 Position */ 140 #define UART_MR_PAR_NO (UART_MR_PAR_NO_Val << UART_MR_PAR_Pos) /**< (UART_MR) No parity Position */ 141 #define UART_MR_BRSRCCK_Pos 12 /**< (UART_MR) Baud Rate Source Clock Position */ 142 #define UART_MR_BRSRCCK_Msk (_U_(0x1) << UART_MR_BRSRCCK_Pos) /**< (UART_MR) Baud Rate Source Clock Mask */ 143 #define UART_MR_BRSRCCK UART_MR_BRSRCCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_MR_BRSRCCK_Msk instead */ 144 #define UART_MR_BRSRCCK_PERIPH_CLK_Val _U_(0x0) /**< (UART_MR) The baud rate is driven by the peripheral clock */ 145 #define UART_MR_BRSRCCK_PMC_PCK_Val _U_(0x1) /**< (UART_MR) The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). */ 146 #define UART_MR_BRSRCCK_PERIPH_CLK (UART_MR_BRSRCCK_PERIPH_CLK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by the peripheral clock Position */ 147 #define UART_MR_BRSRCCK_PMC_PCK (UART_MR_BRSRCCK_PMC_PCK_Val << UART_MR_BRSRCCK_Pos) /**< (UART_MR) The baud rate is driven by a PMC-programmable clock PCK (see section Power Management Controller (PMC)). Position */ 148 #define UART_MR_CHMODE_Pos 14 /**< (UART_MR) Channel Mode Position */ 149 #define UART_MR_CHMODE_Msk (_U_(0x3) << UART_MR_CHMODE_Pos) /**< (UART_MR) Channel Mode Mask */ 150 #define UART_MR_CHMODE(value) (UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos)) 151 #define UART_MR_CHMODE_NORMAL_Val _U_(0x0) /**< (UART_MR) Normal mode */ 152 #define UART_MR_CHMODE_AUTOMATIC_Val _U_(0x1) /**< (UART_MR) Automatic echo */ 153 #define UART_MR_CHMODE_LOCAL_LOOPBACK_Val _U_(0x2) /**< (UART_MR) Local loopback */ 154 #define UART_MR_CHMODE_REMOTE_LOOPBACK_Val _U_(0x3) /**< (UART_MR) Remote loopback */ 155 #define UART_MR_CHMODE_NORMAL (UART_MR_CHMODE_NORMAL_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Normal mode Position */ 156 #define UART_MR_CHMODE_AUTOMATIC (UART_MR_CHMODE_AUTOMATIC_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Automatic echo Position */ 157 #define UART_MR_CHMODE_LOCAL_LOOPBACK (UART_MR_CHMODE_LOCAL_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Local loopback Position */ 158 #define UART_MR_CHMODE_REMOTE_LOOPBACK (UART_MR_CHMODE_REMOTE_LOOPBACK_Val << UART_MR_CHMODE_Pos) /**< (UART_MR) Remote loopback Position */ 159 #define UART_MR_MASK _U_(0xDE10) /**< \deprecated (UART_MR) Register MASK (Use UART_MR_Msk instead) */ 160 #define UART_MR_Msk _U_(0xDE10) /**< (UART_MR) Register Mask */ 161 162 163 /* -------- UART_IER : (UART Offset: 0x08) (/W 32) Interrupt Enable Register -------- */ 164 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 165 #if COMPONENT_TYPEDEF_STYLE == 'N' 166 typedef union { 167 struct { 168 uint32_t RXRDY:1; /**< bit: 0 Enable RXRDY Interrupt */ 169 uint32_t TXRDY:1; /**< bit: 1 Enable TXRDY Interrupt */ 170 uint32_t :3; /**< bit: 2..4 Reserved */ 171 uint32_t OVRE:1; /**< bit: 5 Enable Overrun Error Interrupt */ 172 uint32_t FRAME:1; /**< bit: 6 Enable Framing Error Interrupt */ 173 uint32_t PARE:1; /**< bit: 7 Enable Parity Error Interrupt */ 174 uint32_t :1; /**< bit: 8 Reserved */ 175 uint32_t TXEMPTY:1; /**< bit: 9 Enable TXEMPTY Interrupt */ 176 uint32_t :5; /**< bit: 10..14 Reserved */ 177 uint32_t CMP:1; /**< bit: 15 Enable Comparison Interrupt */ 178 uint32_t :16; /**< bit: 16..31 Reserved */ 179 } bit; /**< Structure used for bit access */ 180 uint32_t reg; /**< Type used for register access */ 181 } UART_IER_Type; 182 #endif 183 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 184 185 #define UART_IER_OFFSET (0x08) /**< (UART_IER) Interrupt Enable Register Offset */ 186 187 #define UART_IER_RXRDY_Pos 0 /**< (UART_IER) Enable RXRDY Interrupt Position */ 188 #define UART_IER_RXRDY_Msk (_U_(0x1) << UART_IER_RXRDY_Pos) /**< (UART_IER) Enable RXRDY Interrupt Mask */ 189 #define UART_IER_RXRDY UART_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_RXRDY_Msk instead */ 190 #define UART_IER_TXRDY_Pos 1 /**< (UART_IER) Enable TXRDY Interrupt Position */ 191 #define UART_IER_TXRDY_Msk (_U_(0x1) << UART_IER_TXRDY_Pos) /**< (UART_IER) Enable TXRDY Interrupt Mask */ 192 #define UART_IER_TXRDY UART_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_TXRDY_Msk instead */ 193 #define UART_IER_OVRE_Pos 5 /**< (UART_IER) Enable Overrun Error Interrupt Position */ 194 #define UART_IER_OVRE_Msk (_U_(0x1) << UART_IER_OVRE_Pos) /**< (UART_IER) Enable Overrun Error Interrupt Mask */ 195 #define UART_IER_OVRE UART_IER_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_OVRE_Msk instead */ 196 #define UART_IER_FRAME_Pos 6 /**< (UART_IER) Enable Framing Error Interrupt Position */ 197 #define UART_IER_FRAME_Msk (_U_(0x1) << UART_IER_FRAME_Pos) /**< (UART_IER) Enable Framing Error Interrupt Mask */ 198 #define UART_IER_FRAME UART_IER_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_FRAME_Msk instead */ 199 #define UART_IER_PARE_Pos 7 /**< (UART_IER) Enable Parity Error Interrupt Position */ 200 #define UART_IER_PARE_Msk (_U_(0x1) << UART_IER_PARE_Pos) /**< (UART_IER) Enable Parity Error Interrupt Mask */ 201 #define UART_IER_PARE UART_IER_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_PARE_Msk instead */ 202 #define UART_IER_TXEMPTY_Pos 9 /**< (UART_IER) Enable TXEMPTY Interrupt Position */ 203 #define UART_IER_TXEMPTY_Msk (_U_(0x1) << UART_IER_TXEMPTY_Pos) /**< (UART_IER) Enable TXEMPTY Interrupt Mask */ 204 #define UART_IER_TXEMPTY UART_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_TXEMPTY_Msk instead */ 205 #define UART_IER_CMP_Pos 15 /**< (UART_IER) Enable Comparison Interrupt Position */ 206 #define UART_IER_CMP_Msk (_U_(0x1) << UART_IER_CMP_Pos) /**< (UART_IER) Enable Comparison Interrupt Mask */ 207 #define UART_IER_CMP UART_IER_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IER_CMP_Msk instead */ 208 #define UART_IER_MASK _U_(0x82E3) /**< \deprecated (UART_IER) Register MASK (Use UART_IER_Msk instead) */ 209 #define UART_IER_Msk _U_(0x82E3) /**< (UART_IER) Register Mask */ 210 211 212 /* -------- UART_IDR : (UART Offset: 0x0c) (/W 32) Interrupt Disable Register -------- */ 213 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 214 #if COMPONENT_TYPEDEF_STYLE == 'N' 215 typedef union { 216 struct { 217 uint32_t RXRDY:1; /**< bit: 0 Disable RXRDY Interrupt */ 218 uint32_t TXRDY:1; /**< bit: 1 Disable TXRDY Interrupt */ 219 uint32_t :3; /**< bit: 2..4 Reserved */ 220 uint32_t OVRE:1; /**< bit: 5 Disable Overrun Error Interrupt */ 221 uint32_t FRAME:1; /**< bit: 6 Disable Framing Error Interrupt */ 222 uint32_t PARE:1; /**< bit: 7 Disable Parity Error Interrupt */ 223 uint32_t :1; /**< bit: 8 Reserved */ 224 uint32_t TXEMPTY:1; /**< bit: 9 Disable TXEMPTY Interrupt */ 225 uint32_t :5; /**< bit: 10..14 Reserved */ 226 uint32_t CMP:1; /**< bit: 15 Disable Comparison Interrupt */ 227 uint32_t :16; /**< bit: 16..31 Reserved */ 228 } bit; /**< Structure used for bit access */ 229 uint32_t reg; /**< Type used for register access */ 230 } UART_IDR_Type; 231 #endif 232 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 233 234 #define UART_IDR_OFFSET (0x0C) /**< (UART_IDR) Interrupt Disable Register Offset */ 235 236 #define UART_IDR_RXRDY_Pos 0 /**< (UART_IDR) Disable RXRDY Interrupt Position */ 237 #define UART_IDR_RXRDY_Msk (_U_(0x1) << UART_IDR_RXRDY_Pos) /**< (UART_IDR) Disable RXRDY Interrupt Mask */ 238 #define UART_IDR_RXRDY UART_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_RXRDY_Msk instead */ 239 #define UART_IDR_TXRDY_Pos 1 /**< (UART_IDR) Disable TXRDY Interrupt Position */ 240 #define UART_IDR_TXRDY_Msk (_U_(0x1) << UART_IDR_TXRDY_Pos) /**< (UART_IDR) Disable TXRDY Interrupt Mask */ 241 #define UART_IDR_TXRDY UART_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_TXRDY_Msk instead */ 242 #define UART_IDR_OVRE_Pos 5 /**< (UART_IDR) Disable Overrun Error Interrupt Position */ 243 #define UART_IDR_OVRE_Msk (_U_(0x1) << UART_IDR_OVRE_Pos) /**< (UART_IDR) Disable Overrun Error Interrupt Mask */ 244 #define UART_IDR_OVRE UART_IDR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_OVRE_Msk instead */ 245 #define UART_IDR_FRAME_Pos 6 /**< (UART_IDR) Disable Framing Error Interrupt Position */ 246 #define UART_IDR_FRAME_Msk (_U_(0x1) << UART_IDR_FRAME_Pos) /**< (UART_IDR) Disable Framing Error Interrupt Mask */ 247 #define UART_IDR_FRAME UART_IDR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_FRAME_Msk instead */ 248 #define UART_IDR_PARE_Pos 7 /**< (UART_IDR) Disable Parity Error Interrupt Position */ 249 #define UART_IDR_PARE_Msk (_U_(0x1) << UART_IDR_PARE_Pos) /**< (UART_IDR) Disable Parity Error Interrupt Mask */ 250 #define UART_IDR_PARE UART_IDR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_PARE_Msk instead */ 251 #define UART_IDR_TXEMPTY_Pos 9 /**< (UART_IDR) Disable TXEMPTY Interrupt Position */ 252 #define UART_IDR_TXEMPTY_Msk (_U_(0x1) << UART_IDR_TXEMPTY_Pos) /**< (UART_IDR) Disable TXEMPTY Interrupt Mask */ 253 #define UART_IDR_TXEMPTY UART_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_TXEMPTY_Msk instead */ 254 #define UART_IDR_CMP_Pos 15 /**< (UART_IDR) Disable Comparison Interrupt Position */ 255 #define UART_IDR_CMP_Msk (_U_(0x1) << UART_IDR_CMP_Pos) /**< (UART_IDR) Disable Comparison Interrupt Mask */ 256 #define UART_IDR_CMP UART_IDR_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IDR_CMP_Msk instead */ 257 #define UART_IDR_MASK _U_(0x82E3) /**< \deprecated (UART_IDR) Register MASK (Use UART_IDR_Msk instead) */ 258 #define UART_IDR_Msk _U_(0x82E3) /**< (UART_IDR) Register Mask */ 259 260 261 /* -------- UART_IMR : (UART Offset: 0x10) (R/ 32) Interrupt Mask Register -------- */ 262 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 263 #if COMPONENT_TYPEDEF_STYLE == 'N' 264 typedef union { 265 struct { 266 uint32_t RXRDY:1; /**< bit: 0 Mask RXRDY Interrupt */ 267 uint32_t TXRDY:1; /**< bit: 1 Disable TXRDY Interrupt */ 268 uint32_t :3; /**< bit: 2..4 Reserved */ 269 uint32_t OVRE:1; /**< bit: 5 Mask Overrun Error Interrupt */ 270 uint32_t FRAME:1; /**< bit: 6 Mask Framing Error Interrupt */ 271 uint32_t PARE:1; /**< bit: 7 Mask Parity Error Interrupt */ 272 uint32_t :1; /**< bit: 8 Reserved */ 273 uint32_t TXEMPTY:1; /**< bit: 9 Mask TXEMPTY Interrupt */ 274 uint32_t :5; /**< bit: 10..14 Reserved */ 275 uint32_t CMP:1; /**< bit: 15 Mask Comparison Interrupt */ 276 uint32_t :16; /**< bit: 16..31 Reserved */ 277 } bit; /**< Structure used for bit access */ 278 uint32_t reg; /**< Type used for register access */ 279 } UART_IMR_Type; 280 #endif 281 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 282 283 #define UART_IMR_OFFSET (0x10) /**< (UART_IMR) Interrupt Mask Register Offset */ 284 285 #define UART_IMR_RXRDY_Pos 0 /**< (UART_IMR) Mask RXRDY Interrupt Position */ 286 #define UART_IMR_RXRDY_Msk (_U_(0x1) << UART_IMR_RXRDY_Pos) /**< (UART_IMR) Mask RXRDY Interrupt Mask */ 287 #define UART_IMR_RXRDY UART_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_RXRDY_Msk instead */ 288 #define UART_IMR_TXRDY_Pos 1 /**< (UART_IMR) Disable TXRDY Interrupt Position */ 289 #define UART_IMR_TXRDY_Msk (_U_(0x1) << UART_IMR_TXRDY_Pos) /**< (UART_IMR) Disable TXRDY Interrupt Mask */ 290 #define UART_IMR_TXRDY UART_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_TXRDY_Msk instead */ 291 #define UART_IMR_OVRE_Pos 5 /**< (UART_IMR) Mask Overrun Error Interrupt Position */ 292 #define UART_IMR_OVRE_Msk (_U_(0x1) << UART_IMR_OVRE_Pos) /**< (UART_IMR) Mask Overrun Error Interrupt Mask */ 293 #define UART_IMR_OVRE UART_IMR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_OVRE_Msk instead */ 294 #define UART_IMR_FRAME_Pos 6 /**< (UART_IMR) Mask Framing Error Interrupt Position */ 295 #define UART_IMR_FRAME_Msk (_U_(0x1) << UART_IMR_FRAME_Pos) /**< (UART_IMR) Mask Framing Error Interrupt Mask */ 296 #define UART_IMR_FRAME UART_IMR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_FRAME_Msk instead */ 297 #define UART_IMR_PARE_Pos 7 /**< (UART_IMR) Mask Parity Error Interrupt Position */ 298 #define UART_IMR_PARE_Msk (_U_(0x1) << UART_IMR_PARE_Pos) /**< (UART_IMR) Mask Parity Error Interrupt Mask */ 299 #define UART_IMR_PARE UART_IMR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_PARE_Msk instead */ 300 #define UART_IMR_TXEMPTY_Pos 9 /**< (UART_IMR) Mask TXEMPTY Interrupt Position */ 301 #define UART_IMR_TXEMPTY_Msk (_U_(0x1) << UART_IMR_TXEMPTY_Pos) /**< (UART_IMR) Mask TXEMPTY Interrupt Mask */ 302 #define UART_IMR_TXEMPTY UART_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_TXEMPTY_Msk instead */ 303 #define UART_IMR_CMP_Pos 15 /**< (UART_IMR) Mask Comparison Interrupt Position */ 304 #define UART_IMR_CMP_Msk (_U_(0x1) << UART_IMR_CMP_Pos) /**< (UART_IMR) Mask Comparison Interrupt Mask */ 305 #define UART_IMR_CMP UART_IMR_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_IMR_CMP_Msk instead */ 306 #define UART_IMR_MASK _U_(0x82E3) /**< \deprecated (UART_IMR) Register MASK (Use UART_IMR_Msk instead) */ 307 #define UART_IMR_Msk _U_(0x82E3) /**< (UART_IMR) Register Mask */ 308 309 310 /* -------- UART_SR : (UART Offset: 0x14) (R/ 32) Status Register -------- */ 311 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 312 #if COMPONENT_TYPEDEF_STYLE == 'N' 313 typedef union { 314 struct { 315 uint32_t RXRDY:1; /**< bit: 0 Receiver Ready */ 316 uint32_t TXRDY:1; /**< bit: 1 Transmitter Ready */ 317 uint32_t :3; /**< bit: 2..4 Reserved */ 318 uint32_t OVRE:1; /**< bit: 5 Overrun Error */ 319 uint32_t FRAME:1; /**< bit: 6 Framing Error */ 320 uint32_t PARE:1; /**< bit: 7 Parity Error */ 321 uint32_t :1; /**< bit: 8 Reserved */ 322 uint32_t TXEMPTY:1; /**< bit: 9 Transmitter Empty */ 323 uint32_t :5; /**< bit: 10..14 Reserved */ 324 uint32_t CMP:1; /**< bit: 15 Comparison Match */ 325 uint32_t :16; /**< bit: 16..31 Reserved */ 326 } bit; /**< Structure used for bit access */ 327 uint32_t reg; /**< Type used for register access */ 328 } UART_SR_Type; 329 #endif 330 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 331 332 #define UART_SR_OFFSET (0x14) /**< (UART_SR) Status Register Offset */ 333 334 #define UART_SR_RXRDY_Pos 0 /**< (UART_SR) Receiver Ready Position */ 335 #define UART_SR_RXRDY_Msk (_U_(0x1) << UART_SR_RXRDY_Pos) /**< (UART_SR) Receiver Ready Mask */ 336 #define UART_SR_RXRDY UART_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_RXRDY_Msk instead */ 337 #define UART_SR_TXRDY_Pos 1 /**< (UART_SR) Transmitter Ready Position */ 338 #define UART_SR_TXRDY_Msk (_U_(0x1) << UART_SR_TXRDY_Pos) /**< (UART_SR) Transmitter Ready Mask */ 339 #define UART_SR_TXRDY UART_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_TXRDY_Msk instead */ 340 #define UART_SR_OVRE_Pos 5 /**< (UART_SR) Overrun Error Position */ 341 #define UART_SR_OVRE_Msk (_U_(0x1) << UART_SR_OVRE_Pos) /**< (UART_SR) Overrun Error Mask */ 342 #define UART_SR_OVRE UART_SR_OVRE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_OVRE_Msk instead */ 343 #define UART_SR_FRAME_Pos 6 /**< (UART_SR) Framing Error Position */ 344 #define UART_SR_FRAME_Msk (_U_(0x1) << UART_SR_FRAME_Pos) /**< (UART_SR) Framing Error Mask */ 345 #define UART_SR_FRAME UART_SR_FRAME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_FRAME_Msk instead */ 346 #define UART_SR_PARE_Pos 7 /**< (UART_SR) Parity Error Position */ 347 #define UART_SR_PARE_Msk (_U_(0x1) << UART_SR_PARE_Pos) /**< (UART_SR) Parity Error Mask */ 348 #define UART_SR_PARE UART_SR_PARE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_PARE_Msk instead */ 349 #define UART_SR_TXEMPTY_Pos 9 /**< (UART_SR) Transmitter Empty Position */ 350 #define UART_SR_TXEMPTY_Msk (_U_(0x1) << UART_SR_TXEMPTY_Pos) /**< (UART_SR) Transmitter Empty Mask */ 351 #define UART_SR_TXEMPTY UART_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_TXEMPTY_Msk instead */ 352 #define UART_SR_CMP_Pos 15 /**< (UART_SR) Comparison Match Position */ 353 #define UART_SR_CMP_Msk (_U_(0x1) << UART_SR_CMP_Pos) /**< (UART_SR) Comparison Match Mask */ 354 #define UART_SR_CMP UART_SR_CMP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_SR_CMP_Msk instead */ 355 #define UART_SR_MASK _U_(0x82E3) /**< \deprecated (UART_SR) Register MASK (Use UART_SR_Msk instead) */ 356 #define UART_SR_Msk _U_(0x82E3) /**< (UART_SR) Register Mask */ 357 358 359 /* -------- UART_RHR : (UART Offset: 0x18) (R/ 32) Receive Holding Register -------- */ 360 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 361 #if COMPONENT_TYPEDEF_STYLE == 'N' 362 typedef union { 363 struct { 364 uint32_t RXCHR:8; /**< bit: 0..7 Received Character */ 365 uint32_t :24; /**< bit: 8..31 Reserved */ 366 } bit; /**< Structure used for bit access */ 367 uint32_t reg; /**< Type used for register access */ 368 } UART_RHR_Type; 369 #endif 370 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 371 372 #define UART_RHR_OFFSET (0x18) /**< (UART_RHR) Receive Holding Register Offset */ 373 374 #define UART_RHR_RXCHR_Pos 0 /**< (UART_RHR) Received Character Position */ 375 #define UART_RHR_RXCHR_Msk (_U_(0xFF) << UART_RHR_RXCHR_Pos) /**< (UART_RHR) Received Character Mask */ 376 #define UART_RHR_RXCHR(value) (UART_RHR_RXCHR_Msk & ((value) << UART_RHR_RXCHR_Pos)) 377 #define UART_RHR_MASK _U_(0xFF) /**< \deprecated (UART_RHR) Register MASK (Use UART_RHR_Msk instead) */ 378 #define UART_RHR_Msk _U_(0xFF) /**< (UART_RHR) Register Mask */ 379 380 381 /* -------- UART_THR : (UART Offset: 0x1c) (/W 32) Transmit Holding Register -------- */ 382 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 383 #if COMPONENT_TYPEDEF_STYLE == 'N' 384 typedef union { 385 struct { 386 uint32_t TXCHR:8; /**< bit: 0..7 Character to be Transmitted */ 387 uint32_t :24; /**< bit: 8..31 Reserved */ 388 } bit; /**< Structure used for bit access */ 389 uint32_t reg; /**< Type used for register access */ 390 } UART_THR_Type; 391 #endif 392 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 393 394 #define UART_THR_OFFSET (0x1C) /**< (UART_THR) Transmit Holding Register Offset */ 395 396 #define UART_THR_TXCHR_Pos 0 /**< (UART_THR) Character to be Transmitted Position */ 397 #define UART_THR_TXCHR_Msk (_U_(0xFF) << UART_THR_TXCHR_Pos) /**< (UART_THR) Character to be Transmitted Mask */ 398 #define UART_THR_TXCHR(value) (UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)) 399 #define UART_THR_MASK _U_(0xFF) /**< \deprecated (UART_THR) Register MASK (Use UART_THR_Msk instead) */ 400 #define UART_THR_Msk _U_(0xFF) /**< (UART_THR) Register Mask */ 401 402 403 /* -------- UART_BRGR : (UART Offset: 0x20) (R/W 32) Baud Rate Generator Register -------- */ 404 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 405 #if COMPONENT_TYPEDEF_STYLE == 'N' 406 typedef union { 407 struct { 408 uint32_t CD:16; /**< bit: 0..15 Clock Divisor */ 409 uint32_t :16; /**< bit: 16..31 Reserved */ 410 } bit; /**< Structure used for bit access */ 411 uint32_t reg; /**< Type used for register access */ 412 } UART_BRGR_Type; 413 #endif 414 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 415 416 #define UART_BRGR_OFFSET (0x20) /**< (UART_BRGR) Baud Rate Generator Register Offset */ 417 418 #define UART_BRGR_CD_Pos 0 /**< (UART_BRGR) Clock Divisor Position */ 419 #define UART_BRGR_CD_Msk (_U_(0xFFFF) << UART_BRGR_CD_Pos) /**< (UART_BRGR) Clock Divisor Mask */ 420 #define UART_BRGR_CD(value) (UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)) 421 #define UART_BRGR_MASK _U_(0xFFFF) /**< \deprecated (UART_BRGR) Register MASK (Use UART_BRGR_Msk instead) */ 422 #define UART_BRGR_Msk _U_(0xFFFF) /**< (UART_BRGR) Register Mask */ 423 424 425 /* -------- UART_CMPR : (UART Offset: 0x24) (R/W 32) Comparison Register -------- */ 426 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 427 #if COMPONENT_TYPEDEF_STYLE == 'N' 428 typedef union { 429 struct { 430 uint32_t VAL1:8; /**< bit: 0..7 First Comparison Value for Received Character */ 431 uint32_t :4; /**< bit: 8..11 Reserved */ 432 uint32_t CMPMODE:1; /**< bit: 12 Comparison Mode */ 433 uint32_t :1; /**< bit: 13 Reserved */ 434 uint32_t CMPPAR:1; /**< bit: 14 Compare Parity */ 435 uint32_t :1; /**< bit: 15 Reserved */ 436 uint32_t VAL2:8; /**< bit: 16..23 Second Comparison Value for Received Character */ 437 uint32_t :8; /**< bit: 24..31 Reserved */ 438 } bit; /**< Structure used for bit access */ 439 uint32_t reg; /**< Type used for register access */ 440 } UART_CMPR_Type; 441 #endif 442 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 443 444 #define UART_CMPR_OFFSET (0x24) /**< (UART_CMPR) Comparison Register Offset */ 445 446 #define UART_CMPR_VAL1_Pos 0 /**< (UART_CMPR) First Comparison Value for Received Character Position */ 447 #define UART_CMPR_VAL1_Msk (_U_(0xFF) << UART_CMPR_VAL1_Pos) /**< (UART_CMPR) First Comparison Value for Received Character Mask */ 448 #define UART_CMPR_VAL1(value) (UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos)) 449 #define UART_CMPR_CMPMODE_Pos 12 /**< (UART_CMPR) Comparison Mode Position */ 450 #define UART_CMPR_CMPMODE_Msk (_U_(0x1) << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison Mode Mask */ 451 #define UART_CMPR_CMPMODE UART_CMPR_CMPMODE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CMPR_CMPMODE_Msk instead */ 452 #define UART_CMPR_CMPMODE_FLAG_ONLY_Val _U_(0x0) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. */ 453 #define UART_CMPR_CMPMODE_START_CONDITION_Val _U_(0x1) /**< (UART_CMPR) Comparison condition must be met to start reception. */ 454 #define UART_CMPR_CMPMODE_FLAG_ONLY (UART_CMPR_CMPMODE_FLAG_ONLY_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Any character is received and comparison function drives CMP flag. Position */ 455 #define UART_CMPR_CMPMODE_START_CONDITION (UART_CMPR_CMPMODE_START_CONDITION_Val << UART_CMPR_CMPMODE_Pos) /**< (UART_CMPR) Comparison condition must be met to start reception. Position */ 456 #define UART_CMPR_CMPPAR_Pos 14 /**< (UART_CMPR) Compare Parity Position */ 457 #define UART_CMPR_CMPPAR_Msk (_U_(0x1) << UART_CMPR_CMPPAR_Pos) /**< (UART_CMPR) Compare Parity Mask */ 458 #define UART_CMPR_CMPPAR UART_CMPR_CMPPAR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_CMPR_CMPPAR_Msk instead */ 459 #define UART_CMPR_VAL2_Pos 16 /**< (UART_CMPR) Second Comparison Value for Received Character Position */ 460 #define UART_CMPR_VAL2_Msk (_U_(0xFF) << UART_CMPR_VAL2_Pos) /**< (UART_CMPR) Second Comparison Value for Received Character Mask */ 461 #define UART_CMPR_VAL2(value) (UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos)) 462 #define UART_CMPR_MASK _U_(0xFF50FF) /**< \deprecated (UART_CMPR) Register MASK (Use UART_CMPR_Msk instead) */ 463 #define UART_CMPR_Msk _U_(0xFF50FF) /**< (UART_CMPR) Register Mask */ 464 465 466 /* -------- UART_WPMR : (UART Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 467 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 468 #if COMPONENT_TYPEDEF_STYLE == 'N' 469 typedef union { 470 struct { 471 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 472 uint32_t :7; /**< bit: 1..7 Reserved */ 473 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 474 } bit; /**< Structure used for bit access */ 475 uint32_t reg; /**< Type used for register access */ 476 } UART_WPMR_Type; 477 #endif 478 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 479 480 #define UART_WPMR_OFFSET (0xE4) /**< (UART_WPMR) Write Protection Mode Register Offset */ 481 482 #define UART_WPMR_WPEN_Pos 0 /**< (UART_WPMR) Write Protection Enable Position */ 483 #define UART_WPMR_WPEN_Msk (_U_(0x1) << UART_WPMR_WPEN_Pos) /**< (UART_WPMR) Write Protection Enable Mask */ 484 #define UART_WPMR_WPEN UART_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use UART_WPMR_WPEN_Msk instead */ 485 #define UART_WPMR_WPKEY_Pos 8 /**< (UART_WPMR) Write Protection Key Position */ 486 #define UART_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Write Protection Key Mask */ 487 #define UART_WPMR_WPKEY(value) (UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos)) 488 #define UART_WPMR_WPKEY_PASSWD_Val _U_(0x554152) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ 489 #define UART_WPMR_WPKEY_PASSWD (UART_WPMR_WPKEY_PASSWD_Val << UART_WPMR_WPKEY_Pos) /**< (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */ 490 #define UART_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (UART_WPMR) Register MASK (Use UART_WPMR_Msk instead) */ 491 #define UART_WPMR_Msk _U_(0xFFFFFF01) /**< (UART_WPMR) Register Mask */ 492 493 494 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 495 #if COMPONENT_TYPEDEF_STYLE == 'R' 496 /** \brief UART hardware registers */ 497 typedef struct { 498 __O uint32_t UART_CR; /**< (UART Offset: 0x00) Control Register */ 499 __IO uint32_t UART_MR; /**< (UART Offset: 0x04) Mode Register */ 500 __O uint32_t UART_IER; /**< (UART Offset: 0x08) Interrupt Enable Register */ 501 __O uint32_t UART_IDR; /**< (UART Offset: 0x0C) Interrupt Disable Register */ 502 __I uint32_t UART_IMR; /**< (UART Offset: 0x10) Interrupt Mask Register */ 503 __I uint32_t UART_SR; /**< (UART Offset: 0x14) Status Register */ 504 __I uint32_t UART_RHR; /**< (UART Offset: 0x18) Receive Holding Register */ 505 __O uint32_t UART_THR; /**< (UART Offset: 0x1C) Transmit Holding Register */ 506 __IO uint32_t UART_BRGR; /**< (UART Offset: 0x20) Baud Rate Generator Register */ 507 __IO uint32_t UART_CMPR; /**< (UART Offset: 0x24) Comparison Register */ 508 __I uint8_t Reserved1[188]; 509 __IO uint32_t UART_WPMR; /**< (UART Offset: 0xE4) Write Protection Mode Register */ 510 } Uart; 511 512 #elif COMPONENT_TYPEDEF_STYLE == 'N' 513 /** \brief UART hardware registers */ 514 typedef struct { 515 __O UART_CR_Type UART_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 516 __IO UART_MR_Type UART_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 517 __O UART_IER_Type UART_IER; /**< Offset: 0x08 ( /W 32) Interrupt Enable Register */ 518 __O UART_IDR_Type UART_IDR; /**< Offset: 0x0C ( /W 32) Interrupt Disable Register */ 519 __I UART_IMR_Type UART_IMR; /**< Offset: 0x10 (R/ 32) Interrupt Mask Register */ 520 __I UART_SR_Type UART_SR; /**< Offset: 0x14 (R/ 32) Status Register */ 521 __I UART_RHR_Type UART_RHR; /**< Offset: 0x18 (R/ 32) Receive Holding Register */ 522 __O UART_THR_Type UART_THR; /**< Offset: 0x1C ( /W 32) Transmit Holding Register */ 523 __IO UART_BRGR_Type UART_BRGR; /**< Offset: 0x20 (R/W 32) Baud Rate Generator Register */ 524 __IO UART_CMPR_Type UART_CMPR; /**< Offset: 0x24 (R/W 32) Comparison Register */ 525 __I uint8_t Reserved1[188]; 526 __IO UART_WPMR_Type UART_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 527 } Uart; 528 529 #else /* COMPONENT_TYPEDEF_STYLE */ 530 #error Unknown component typedef style 531 #endif /* COMPONENT_TYPEDEF_STYLE */ 532 533 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 534 /** @} end of Universal Asynchronous Receiver Transmitter */ 535 536 #endif /* _SAME70_UART_COMPONENT_H_ */ 537
