1 /** 2 * \file 3 * 4 * \brief Component description for MATRIX 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:19:59Z */ 31 #ifndef _SAME70_MATRIX_COMPONENT_H_ 32 #define _SAME70_MATRIX_COMPONENT_H_ 33 #define _SAME70_MATRIX_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 AHB Bus Matrix 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR MATRIX */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define MATRIX_11282 /**< (MATRIX) Module ID */ 46 #define REV_MATRIX L /**< (MATRIX) Module revision */ 47 48 /* -------- MATRIX_PRAS : (MATRIX Offset: 0x00) (R/W 32) Priority Register A for Slave 0 -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t M0PR:2; /**< bit: 0..1 Master 0 Priority */ 54 uint32_t :2; /**< bit: 2..3 Reserved */ 55 uint32_t M1PR:2; /**< bit: 4..5 Master 1 Priority */ 56 uint32_t :2; /**< bit: 6..7 Reserved */ 57 uint32_t M2PR:2; /**< bit: 8..9 Master 2 Priority */ 58 uint32_t :2; /**< bit: 10..11 Reserved */ 59 uint32_t M3PR:2; /**< bit: 12..13 Master 3 Priority */ 60 uint32_t :2; /**< bit: 14..15 Reserved */ 61 uint32_t M4PR:2; /**< bit: 16..17 Master 4 Priority */ 62 uint32_t :2; /**< bit: 18..19 Reserved */ 63 uint32_t M5PR:2; /**< bit: 20..21 Master 5 Priority */ 64 uint32_t :2; /**< bit: 22..23 Reserved */ 65 uint32_t M6PR:2; /**< bit: 24..25 Master 6 Priority */ 66 uint32_t :6; /**< bit: 26..31 Reserved */ 67 } bit; /**< Structure used for bit access */ 68 uint32_t reg; /**< Type used for register access */ 69 } MATRIX_PRAS_Type; 70 #endif 71 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 #define MATRIX_PRAS_OFFSET (0x00) /**< (MATRIX_PRAS) Priority Register A for Slave 0 Offset */ 74 75 #define MATRIX_PRAS_M0PR_Pos 0 /**< (MATRIX_PRAS) Master 0 Priority Position */ 76 #define MATRIX_PRAS_M0PR_Msk (_U_(0x3) << MATRIX_PRAS_M0PR_Pos) /**< (MATRIX_PRAS) Master 0 Priority Mask */ 77 #define MATRIX_PRAS_M0PR(value) (MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos)) 78 #define MATRIX_PRAS_M1PR_Pos 4 /**< (MATRIX_PRAS) Master 1 Priority Position */ 79 #define MATRIX_PRAS_M1PR_Msk (_U_(0x3) << MATRIX_PRAS_M1PR_Pos) /**< (MATRIX_PRAS) Master 1 Priority Mask */ 80 #define MATRIX_PRAS_M1PR(value) (MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos)) 81 #define MATRIX_PRAS_M2PR_Pos 8 /**< (MATRIX_PRAS) Master 2 Priority Position */ 82 #define MATRIX_PRAS_M2PR_Msk (_U_(0x3) << MATRIX_PRAS_M2PR_Pos) /**< (MATRIX_PRAS) Master 2 Priority Mask */ 83 #define MATRIX_PRAS_M2PR(value) (MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos)) 84 #define MATRIX_PRAS_M3PR_Pos 12 /**< (MATRIX_PRAS) Master 3 Priority Position */ 85 #define MATRIX_PRAS_M3PR_Msk (_U_(0x3) << MATRIX_PRAS_M3PR_Pos) /**< (MATRIX_PRAS) Master 3 Priority Mask */ 86 #define MATRIX_PRAS_M3PR(value) (MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos)) 87 #define MATRIX_PRAS_M4PR_Pos 16 /**< (MATRIX_PRAS) Master 4 Priority Position */ 88 #define MATRIX_PRAS_M4PR_Msk (_U_(0x3) << MATRIX_PRAS_M4PR_Pos) /**< (MATRIX_PRAS) Master 4 Priority Mask */ 89 #define MATRIX_PRAS_M4PR(value) (MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos)) 90 #define MATRIX_PRAS_M5PR_Pos 20 /**< (MATRIX_PRAS) Master 5 Priority Position */ 91 #define MATRIX_PRAS_M5PR_Msk (_U_(0x3) << MATRIX_PRAS_M5PR_Pos) /**< (MATRIX_PRAS) Master 5 Priority Mask */ 92 #define MATRIX_PRAS_M5PR(value) (MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos)) 93 #define MATRIX_PRAS_M6PR_Pos 24 /**< (MATRIX_PRAS) Master 6 Priority Position */ 94 #define MATRIX_PRAS_M6PR_Msk (_U_(0x3) << MATRIX_PRAS_M6PR_Pos) /**< (MATRIX_PRAS) Master 6 Priority Mask */ 95 #define MATRIX_PRAS_M6PR(value) (MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos)) 96 #define MATRIX_PRAS_MASK _U_(0x3333333) /**< \deprecated (MATRIX_PRAS) Register MASK (Use MATRIX_PRAS_Msk instead) */ 97 #define MATRIX_PRAS_Msk _U_(0x3333333) /**< (MATRIX_PRAS) Register Mask */ 98 99 100 /* -------- MATRIX_PRBS : (MATRIX Offset: 0x04) (R/W 32) Priority Register B for Slave 0 -------- */ 101 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 102 #if COMPONENT_TYPEDEF_STYLE == 'N' 103 typedef union { 104 struct { 105 uint32_t M8PR:2; /**< bit: 0..1 Master 8 Priority */ 106 uint32_t :2; /**< bit: 2..3 Reserved */ 107 uint32_t M9PR:2; /**< bit: 4..5 Master 9 Priority */ 108 uint32_t :2; /**< bit: 6..7 Reserved */ 109 uint32_t M10PR:2; /**< bit: 8..9 Master 10 Priority */ 110 uint32_t :2; /**< bit: 10..11 Reserved */ 111 uint32_t M11PR:2; /**< bit: 12..13 Master 11 Priority */ 112 uint32_t :2; /**< bit: 14..15 Reserved */ 113 uint32_t M12PR:2; /**< bit: 16..17 Master 12 Priority */ 114 uint32_t :14; /**< bit: 18..31 Reserved */ 115 } bit; /**< Structure used for bit access */ 116 uint32_t reg; /**< Type used for register access */ 117 } MATRIX_PRBS_Type; 118 #endif 119 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 120 121 #define MATRIX_PRBS_OFFSET (0x04) /**< (MATRIX_PRBS) Priority Register B for Slave 0 Offset */ 122 123 #define MATRIX_PRBS_M8PR_Pos 0 /**< (MATRIX_PRBS) Master 8 Priority Position */ 124 #define MATRIX_PRBS_M8PR_Msk (_U_(0x3) << MATRIX_PRBS_M8PR_Pos) /**< (MATRIX_PRBS) Master 8 Priority Mask */ 125 #define MATRIX_PRBS_M8PR(value) (MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos)) 126 #define MATRIX_PRBS_M9PR_Pos 4 /**< (MATRIX_PRBS) Master 9 Priority Position */ 127 #define MATRIX_PRBS_M9PR_Msk (_U_(0x3) << MATRIX_PRBS_M9PR_Pos) /**< (MATRIX_PRBS) Master 9 Priority Mask */ 128 #define MATRIX_PRBS_M9PR(value) (MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos)) 129 #define MATRIX_PRBS_M10PR_Pos 8 /**< (MATRIX_PRBS) Master 10 Priority Position */ 130 #define MATRIX_PRBS_M10PR_Msk (_U_(0x3) << MATRIX_PRBS_M10PR_Pos) /**< (MATRIX_PRBS) Master 10 Priority Mask */ 131 #define MATRIX_PRBS_M10PR(value) (MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos)) 132 #define MATRIX_PRBS_M11PR_Pos 12 /**< (MATRIX_PRBS) Master 11 Priority Position */ 133 #define MATRIX_PRBS_M11PR_Msk (_U_(0x3) << MATRIX_PRBS_M11PR_Pos) /**< (MATRIX_PRBS) Master 11 Priority Mask */ 134 #define MATRIX_PRBS_M11PR(value) (MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos)) 135 #define MATRIX_PRBS_M12PR_Pos 16 /**< (MATRIX_PRBS) Master 12 Priority Position */ 136 #define MATRIX_PRBS_M12PR_Msk (_U_(0x3) << MATRIX_PRBS_M12PR_Pos) /**< (MATRIX_PRBS) Master 12 Priority Mask */ 137 #define MATRIX_PRBS_M12PR(value) (MATRIX_PRBS_M12PR_Msk & ((value) << MATRIX_PRBS_M12PR_Pos)) 138 #define MATRIX_PRBS_MASK _U_(0x33333) /**< \deprecated (MATRIX_PRBS) Register MASK (Use MATRIX_PRBS_Msk instead) */ 139 #define MATRIX_PRBS_Msk _U_(0x33333) /**< (MATRIX_PRBS) Register Mask */ 140 141 142 /* -------- MATRIX_MCFG : (MATRIX Offset: 0x00) (R/W 32) Master Configuration Register 0 -------- */ 143 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 144 #if COMPONENT_TYPEDEF_STYLE == 'N' 145 typedef union { 146 struct { 147 uint32_t ULBT:3; /**< bit: 0..2 Undefined Length Burst Type */ 148 uint32_t :29; /**< bit: 3..31 Reserved */ 149 } bit; /**< Structure used for bit access */ 150 uint32_t reg; /**< Type used for register access */ 151 } MATRIX_MCFG_Type; 152 #endif 153 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 154 155 #define MATRIX_MCFG_OFFSET (0x00) /**< (MATRIX_MCFG) Master Configuration Register 0 Offset */ 156 157 #define MATRIX_MCFG_ULBT_Pos 0 /**< (MATRIX_MCFG) Undefined Length Burst Type Position */ 158 #define MATRIX_MCFG_ULBT_Msk (_U_(0x7) << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Undefined Length Burst Type Mask */ 159 #define MATRIX_MCFG_ULBT(value) (MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)) 160 #define MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val _U_(0x0) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ 161 #define MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val _U_(0x1) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ 162 #define MATRIX_MCFG_ULBT_4BEAT_BURST_Val _U_(0x2) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ 163 #define MATRIX_MCFG_ULBT_8BEAT_BURST_Val _U_(0x3) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ 164 #define MATRIX_MCFG_ULBT_16BEAT_BURST_Val _U_(0x4) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ 165 #define MATRIX_MCFG_ULBT_32BEAT_BURST_Val _U_(0x5) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ 166 #define MATRIX_MCFG_ULBT_64BEAT_BURST_Val _U_(0x6) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ 167 #define MATRIX_MCFG_ULBT_128BEAT_BURST_Val _U_(0x7) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ 168 #define MATRIX_MCFG_ULBT_UNLTD_LENGTH (MATRIX_MCFG_ULBT_UNLTD_LENGTH_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. Position */ 169 #define MATRIX_MCFG_ULBT_SINGLE_ACCESS (MATRIX_MCFG_ULBT_SINGLE_ACCESS_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. Position */ 170 #define MATRIX_MCFG_ULBT_4BEAT_BURST (MATRIX_MCFG_ULBT_4BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. Position */ 171 #define MATRIX_MCFG_ULBT_8BEAT_BURST (MATRIX_MCFG_ULBT_8BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. Position */ 172 #define MATRIX_MCFG_ULBT_16BEAT_BURST (MATRIX_MCFG_ULBT_16BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. Position */ 173 #define MATRIX_MCFG_ULBT_32BEAT_BURST (MATRIX_MCFG_ULBT_32BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. Position */ 174 #define MATRIX_MCFG_ULBT_64BEAT_BURST (MATRIX_MCFG_ULBT_64BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. Position */ 175 #define MATRIX_MCFG_ULBT_128BEAT_BURST (MATRIX_MCFG_ULBT_128BEAT_BURST_Val << MATRIX_MCFG_ULBT_Pos) /**< (MATRIX_MCFG) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. Position */ 176 #define MATRIX_MCFG_MASK _U_(0x07) /**< \deprecated (MATRIX_MCFG) Register MASK (Use MATRIX_MCFG_Msk instead) */ 177 #define MATRIX_MCFG_Msk _U_(0x07) /**< (MATRIX_MCFG) Register Mask */ 178 179 180 /* -------- MATRIX_SCFG : (MATRIX Offset: 0x40) (R/W 32) Slave Configuration Register 0 -------- */ 181 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 182 #if COMPONENT_TYPEDEF_STYLE == 'N' 183 typedef union { 184 struct { 185 uint32_t SLOT_CYCLE:9; /**< bit: 0..8 Maximum Bus Grant Duration for Masters */ 186 uint32_t :7; /**< bit: 9..15 Reserved */ 187 uint32_t DEFMSTR_TYPE:2; /**< bit: 16..17 Default Master Type */ 188 uint32_t FIXED_DEFMSTR:4; /**< bit: 18..21 Fixed Default Master */ 189 uint32_t :10; /**< bit: 22..31 Reserved */ 190 } bit; /**< Structure used for bit access */ 191 uint32_t reg; /**< Type used for register access */ 192 } MATRIX_SCFG_Type; 193 #endif 194 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 195 196 #define MATRIX_SCFG_OFFSET (0x40) /**< (MATRIX_SCFG) Slave Configuration Register 0 Offset */ 197 198 #define MATRIX_SCFG_SLOT_CYCLE_Pos 0 /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Position */ 199 #define MATRIX_SCFG_SLOT_CYCLE_Msk (_U_(0x1FF) << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< (MATRIX_SCFG) Maximum Bus Grant Duration for Masters Mask */ 200 #define MATRIX_SCFG_SLOT_CYCLE(value) (MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)) 201 #define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 /**< (MATRIX_SCFG) Default Master Type Position */ 202 #define MATRIX_SCFG_DEFMSTR_TYPE_Msk (_U_(0x3) << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Default Master Type Mask */ 203 #define MATRIX_SCFG_DEFMSTR_TYPE(value) (MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)) 204 #define MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val _U_(0x0) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ 205 #define MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val _U_(0x1) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ 206 #define MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val _U_(0x2) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ 207 #define MATRIX_SCFG_DEFMSTR_TYPE_NONE (MATRIX_SCFG_DEFMSTR_TYPE_NONE_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. Position */ 208 #define MATRIX_SCFG_DEFMSTR_TYPE_LAST (MATRIX_SCFG_DEFMSTR_TYPE_LAST_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. Position */ 209 #define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (MATRIX_SCFG_DEFMSTR_TYPE_FIXED_Val << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< (MATRIX_SCFG) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. Position */ 210 #define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 /**< (MATRIX_SCFG) Fixed Default Master Position */ 211 #define MATRIX_SCFG_FIXED_DEFMSTR_Msk (_U_(0xF) << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< (MATRIX_SCFG) Fixed Default Master Mask */ 212 #define MATRIX_SCFG_FIXED_DEFMSTR(value) (MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)) 213 #define MATRIX_SCFG_MASK _U_(0x3F01FF) /**< \deprecated (MATRIX_SCFG) Register MASK (Use MATRIX_SCFG_Msk instead) */ 214 #define MATRIX_SCFG_Msk _U_(0x3F01FF) /**< (MATRIX_SCFG) Register Mask */ 215 216 217 /* -------- MATRIX_MRCR : (MATRIX Offset: 0x100) (R/W 32) Master Remap Control Register -------- */ 218 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 219 #if COMPONENT_TYPEDEF_STYLE == 'N' 220 typedef union { 221 struct { 222 uint32_t RCB0:1; /**< bit: 0 Remap Command Bit for Master 0 */ 223 uint32_t RCB1:1; /**< bit: 1 Remap Command Bit for Master 1 */ 224 uint32_t RCB2:1; /**< bit: 2 Remap Command Bit for Master 2 */ 225 uint32_t RCB3:1; /**< bit: 3 Remap Command Bit for Master 3 */ 226 uint32_t RCB4:1; /**< bit: 4 Remap Command Bit for Master 4 */ 227 uint32_t RCB5:1; /**< bit: 5 Remap Command Bit for Master 5 */ 228 uint32_t RCB6:1; /**< bit: 6 Remap Command Bit for Master 6 */ 229 uint32_t :1; /**< bit: 7 Reserved */ 230 uint32_t RCB8:1; /**< bit: 8 Remap Command Bit for Master 8 */ 231 uint32_t RCB9:1; /**< bit: 9 Remap Command Bit for Master 9 */ 232 uint32_t RCB10:1; /**< bit: 10 Remap Command Bit for Master 10 */ 233 uint32_t RCB11:1; /**< bit: 11 Remap Command Bit for Master 11 */ 234 uint32_t RCB12:1; /**< bit: 12 Remap Command Bit for Master 12 */ 235 uint32_t :19; /**< bit: 13..31 Reserved */ 236 } bit; /**< Structure used for bit access */ 237 struct { 238 uint32_t RCB:12; /**< bit: 0..11 Remap Command Bit for Master x2 */ 239 uint32_t :20; /**< bit: 12..31 Reserved */ 240 } vec; /**< Structure used for vec access */ 241 uint32_t reg; /**< Type used for register access */ 242 } MATRIX_MRCR_Type; 243 #endif 244 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 245 246 #define MATRIX_MRCR_OFFSET (0x100) /**< (MATRIX_MRCR) Master Remap Control Register Offset */ 247 248 #define MATRIX_MRCR_RCB0_Pos 0 /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Position */ 249 #define MATRIX_MRCR_RCB0_Msk (_U_(0x1) << MATRIX_MRCR_RCB0_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 0 Mask */ 250 #define MATRIX_MRCR_RCB0 MATRIX_MRCR_RCB0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB0_Msk instead */ 251 #define MATRIX_MRCR_RCB1_Pos 1 /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Position */ 252 #define MATRIX_MRCR_RCB1_Msk (_U_(0x1) << MATRIX_MRCR_RCB1_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 1 Mask */ 253 #define MATRIX_MRCR_RCB1 MATRIX_MRCR_RCB1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB1_Msk instead */ 254 #define MATRIX_MRCR_RCB2_Pos 2 /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Position */ 255 #define MATRIX_MRCR_RCB2_Msk (_U_(0x1) << MATRIX_MRCR_RCB2_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 2 Mask */ 256 #define MATRIX_MRCR_RCB2 MATRIX_MRCR_RCB2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB2_Msk instead */ 257 #define MATRIX_MRCR_RCB3_Pos 3 /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Position */ 258 #define MATRIX_MRCR_RCB3_Msk (_U_(0x1) << MATRIX_MRCR_RCB3_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 3 Mask */ 259 #define MATRIX_MRCR_RCB3 MATRIX_MRCR_RCB3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB3_Msk instead */ 260 #define MATRIX_MRCR_RCB4_Pos 4 /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Position */ 261 #define MATRIX_MRCR_RCB4_Msk (_U_(0x1) << MATRIX_MRCR_RCB4_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 4 Mask */ 262 #define MATRIX_MRCR_RCB4 MATRIX_MRCR_RCB4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB4_Msk instead */ 263 #define MATRIX_MRCR_RCB5_Pos 5 /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Position */ 264 #define MATRIX_MRCR_RCB5_Msk (_U_(0x1) << MATRIX_MRCR_RCB5_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 5 Mask */ 265 #define MATRIX_MRCR_RCB5 MATRIX_MRCR_RCB5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB5_Msk instead */ 266 #define MATRIX_MRCR_RCB6_Pos 6 /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Position */ 267 #define MATRIX_MRCR_RCB6_Msk (_U_(0x1) << MATRIX_MRCR_RCB6_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 6 Mask */ 268 #define MATRIX_MRCR_RCB6 MATRIX_MRCR_RCB6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB6_Msk instead */ 269 #define MATRIX_MRCR_RCB8_Pos 8 /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Position */ 270 #define MATRIX_MRCR_RCB8_Msk (_U_(0x1) << MATRIX_MRCR_RCB8_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 8 Mask */ 271 #define MATRIX_MRCR_RCB8 MATRIX_MRCR_RCB8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB8_Msk instead */ 272 #define MATRIX_MRCR_RCB9_Pos 9 /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Position */ 273 #define MATRIX_MRCR_RCB9_Msk (_U_(0x1) << MATRIX_MRCR_RCB9_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 9 Mask */ 274 #define MATRIX_MRCR_RCB9 MATRIX_MRCR_RCB9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB9_Msk instead */ 275 #define MATRIX_MRCR_RCB10_Pos 10 /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Position */ 276 #define MATRIX_MRCR_RCB10_Msk (_U_(0x1) << MATRIX_MRCR_RCB10_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 10 Mask */ 277 #define MATRIX_MRCR_RCB10 MATRIX_MRCR_RCB10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB10_Msk instead */ 278 #define MATRIX_MRCR_RCB11_Pos 11 /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Position */ 279 #define MATRIX_MRCR_RCB11_Msk (_U_(0x1) << MATRIX_MRCR_RCB11_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 11 Mask */ 280 #define MATRIX_MRCR_RCB11 MATRIX_MRCR_RCB11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB11_Msk instead */ 281 #define MATRIX_MRCR_RCB12_Pos 12 /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Position */ 282 #define MATRIX_MRCR_RCB12_Msk (_U_(0x1) << MATRIX_MRCR_RCB12_Pos) /**< (MATRIX_MRCR) Remap Command Bit for Master 12 Mask */ 283 #define MATRIX_MRCR_RCB12 MATRIX_MRCR_RCB12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_MRCR_RCB12_Msk instead */ 284 #define MATRIX_MRCR_MASK _U_(0x1F7F) /**< \deprecated (MATRIX_MRCR) Register MASK (Use MATRIX_MRCR_Msk instead) */ 285 #define MATRIX_MRCR_Msk _U_(0x1F7F) /**< (MATRIX_MRCR) Register Mask */ 286 287 #define MATRIX_MRCR_RCB_Pos 0 /**< (MATRIX_MRCR Position) Remap Command Bit for Master x2 */ 288 #define MATRIX_MRCR_RCB_Msk (_U_(0xFFF) << MATRIX_MRCR_RCB_Pos) /**< (MATRIX_MRCR Mask) RCB */ 289 #define MATRIX_MRCR_RCB(value) (MATRIX_MRCR_RCB_Msk & ((value) << MATRIX_MRCR_RCB_Pos)) 290 291 /* -------- CCFG_CAN0 : (MATRIX Offset: 0x110) (R/W 32) CAN0 Configuration Register -------- */ 292 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 293 #if COMPONENT_TYPEDEF_STYLE == 'N' 294 typedef union { 295 struct { 296 uint32_t :16; /**< bit: 0..15 Reserved */ 297 uint32_t CAN0DMABA:16; /**< bit: 16..31 CAN0 DMA Base Address */ 298 } bit; /**< Structure used for bit access */ 299 uint32_t reg; /**< Type used for register access */ 300 } CCFG_CAN0_Type; 301 #endif 302 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 303 304 #define CCFG_CAN0_OFFSET (0x110) /**< (CCFG_CAN0) CAN0 Configuration Register Offset */ 305 306 #define CCFG_CAN0_CAN0DMABA_Pos 16 /**< (CCFG_CAN0) CAN0 DMA Base Address Position */ 307 #define CCFG_CAN0_CAN0DMABA_Msk (_U_(0xFFFF) << CCFG_CAN0_CAN0DMABA_Pos) /**< (CCFG_CAN0) CAN0 DMA Base Address Mask */ 308 #define CCFG_CAN0_CAN0DMABA(value) (CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos)) 309 #define CCFG_CAN0_MASK _U_(0xFFFF0000) /**< \deprecated (CCFG_CAN0) Register MASK (Use CCFG_CAN0_Msk instead) */ 310 #define CCFG_CAN0_Msk _U_(0xFFFF0000) /**< (CCFG_CAN0) Register Mask */ 311 312 313 /* -------- CCFG_SYSIO : (MATRIX Offset: 0x114) (R/W 32) System I/O and CAN1 Configuration Register -------- */ 314 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 315 #if COMPONENT_TYPEDEF_STYLE == 'N' 316 typedef union { 317 struct { 318 uint32_t :4; /**< bit: 0..3 Reserved */ 319 uint32_t SYSIO4:1; /**< bit: 4 PB4 or TDI Assignment */ 320 uint32_t SYSIO5:1; /**< bit: 5 PB5 or TDO/TRACESWO Assignment */ 321 uint32_t SYSIO6:1; /**< bit: 6 PB6 or TMS/SWDIO Assignment */ 322 uint32_t SYSIO7:1; /**< bit: 7 PB7 or TCK/SWCLK Assignment */ 323 uint32_t :4; /**< bit: 8..11 Reserved */ 324 uint32_t SYSIO12:1; /**< bit: 12 PB12 or ERASE Assignment */ 325 uint32_t :3; /**< bit: 13..15 Reserved */ 326 uint32_t CAN1DMABA:16; /**< bit: 16..31 CAN1 DMA Base Address */ 327 } bit; /**< Structure used for bit access */ 328 struct { 329 uint32_t :4; /**< bit: 0..3 Reserved */ 330 uint32_t SYSIO:5; /**< bit: 4..8 PB4 or TDI Assignment */ 331 uint32_t :23; /**< bit: 9..31 Reserved */ 332 } vec; /**< Structure used for vec access */ 333 uint32_t reg; /**< Type used for register access */ 334 } CCFG_SYSIO_Type; 335 #endif 336 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 337 338 #define CCFG_SYSIO_OFFSET (0x114) /**< (CCFG_SYSIO) System I/O and CAN1 Configuration Register Offset */ 339 340 #define CCFG_SYSIO_SYSIO4_Pos 4 /**< (CCFG_SYSIO) PB4 or TDI Assignment Position */ 341 #define CCFG_SYSIO_SYSIO4_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO4_Pos) /**< (CCFG_SYSIO) PB4 or TDI Assignment Mask */ 342 #define CCFG_SYSIO_SYSIO4 CCFG_SYSIO_SYSIO4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO4_Msk instead */ 343 #define CCFG_SYSIO_SYSIO5_Pos 5 /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Position */ 344 #define CCFG_SYSIO_SYSIO5_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO5_Pos) /**< (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment Mask */ 345 #define CCFG_SYSIO_SYSIO5 CCFG_SYSIO_SYSIO5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO5_Msk instead */ 346 #define CCFG_SYSIO_SYSIO6_Pos 6 /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Position */ 347 #define CCFG_SYSIO_SYSIO6_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO6_Pos) /**< (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment Mask */ 348 #define CCFG_SYSIO_SYSIO6 CCFG_SYSIO_SYSIO6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO6_Msk instead */ 349 #define CCFG_SYSIO_SYSIO7_Pos 7 /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Position */ 350 #define CCFG_SYSIO_SYSIO7_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO7_Pos) /**< (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment Mask */ 351 #define CCFG_SYSIO_SYSIO7 CCFG_SYSIO_SYSIO7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO7_Msk instead */ 352 #define CCFG_SYSIO_SYSIO12_Pos 12 /**< (CCFG_SYSIO) PB12 or ERASE Assignment Position */ 353 #define CCFG_SYSIO_SYSIO12_Msk (_U_(0x1) << CCFG_SYSIO_SYSIO12_Pos) /**< (CCFG_SYSIO) PB12 or ERASE Assignment Mask */ 354 #define CCFG_SYSIO_SYSIO12 CCFG_SYSIO_SYSIO12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SYSIO_SYSIO12_Msk instead */ 355 #define CCFG_SYSIO_CAN1DMABA_Pos 16 /**< (CCFG_SYSIO) CAN1 DMA Base Address Position */ 356 #define CCFG_SYSIO_CAN1DMABA_Msk (_U_(0xFFFF) << CCFG_SYSIO_CAN1DMABA_Pos) /**< (CCFG_SYSIO) CAN1 DMA Base Address Mask */ 357 #define CCFG_SYSIO_CAN1DMABA(value) (CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos)) 358 #define CCFG_SYSIO_MASK _U_(0xFFFF10F0) /**< \deprecated (CCFG_SYSIO) Register MASK (Use CCFG_SYSIO_Msk instead) */ 359 #define CCFG_SYSIO_Msk _U_(0xFFFF10F0) /**< (CCFG_SYSIO) Register Mask */ 360 361 #define CCFG_SYSIO_SYSIO_Pos 4 /**< (CCFG_SYSIO Position) PB4 or TDI Assignment */ 362 #define CCFG_SYSIO_SYSIO_Msk (_U_(0x1F) << CCFG_SYSIO_SYSIO_Pos) /**< (CCFG_SYSIO Mask) SYSIO */ 363 #define CCFG_SYSIO_SYSIO(value) (CCFG_SYSIO_SYSIO_Msk & ((value) << CCFG_SYSIO_SYSIO_Pos)) 364 365 /* -------- CCFG_PCCR : (MATRIX Offset: 0x118) (R/W 32) Peripheral Clock Configuration Register -------- */ 366 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 367 #if COMPONENT_TYPEDEF_STYLE == 'N' 368 typedef union { 369 struct { 370 uint32_t :20; /**< bit: 0..19 Reserved */ 371 uint32_t TC0CC:1; /**< bit: 20 TC0 Clock Configuration */ 372 uint32_t I2SC0CC:1; /**< bit: 21 I2SC0 Clock Configuration */ 373 uint32_t I2SC1CC:1; /**< bit: 22 I2SC1 Clock Configuration */ 374 uint32_t :9; /**< bit: 23..31 Reserved */ 375 } bit; /**< Structure used for bit access */ 376 uint32_t reg; /**< Type used for register access */ 377 } CCFG_PCCR_Type; 378 #endif 379 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 380 381 #define CCFG_PCCR_OFFSET (0x118) /**< (CCFG_PCCR) Peripheral Clock Configuration Register Offset */ 382 383 #define CCFG_PCCR_TC0CC_Pos 20 /**< (CCFG_PCCR) TC0 Clock Configuration Position */ 384 #define CCFG_PCCR_TC0CC_Msk (_U_(0x1) << CCFG_PCCR_TC0CC_Pos) /**< (CCFG_PCCR) TC0 Clock Configuration Mask */ 385 #define CCFG_PCCR_TC0CC CCFG_PCCR_TC0CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_TC0CC_Msk instead */ 386 #define CCFG_PCCR_I2SC0CC_Pos 21 /**< (CCFG_PCCR) I2SC0 Clock Configuration Position */ 387 #define CCFG_PCCR_I2SC0CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC0CC_Pos) /**< (CCFG_PCCR) I2SC0 Clock Configuration Mask */ 388 #define CCFG_PCCR_I2SC0CC CCFG_PCCR_I2SC0CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_I2SC0CC_Msk instead */ 389 #define CCFG_PCCR_I2SC1CC_Pos 22 /**< (CCFG_PCCR) I2SC1 Clock Configuration Position */ 390 #define CCFG_PCCR_I2SC1CC_Msk (_U_(0x1) << CCFG_PCCR_I2SC1CC_Pos) /**< (CCFG_PCCR) I2SC1 Clock Configuration Mask */ 391 #define CCFG_PCCR_I2SC1CC CCFG_PCCR_I2SC1CC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_PCCR_I2SC1CC_Msk instead */ 392 #define CCFG_PCCR_MASK _U_(0x700000) /**< \deprecated (CCFG_PCCR) Register MASK (Use CCFG_PCCR_Msk instead) */ 393 #define CCFG_PCCR_Msk _U_(0x700000) /**< (CCFG_PCCR) Register Mask */ 394 395 396 /* -------- CCFG_DYNCKG : (MATRIX Offset: 0x11c) (R/W 32) Dynamic Clock Gating Register -------- */ 397 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 398 #if COMPONENT_TYPEDEF_STYLE == 'N' 399 typedef union { 400 struct { 401 uint32_t MATCKG:1; /**< bit: 0 MATRIX Dynamic Clock Gating */ 402 uint32_t BRIDCKG:1; /**< bit: 1 Bridge Dynamic Clock Gating Enable */ 403 uint32_t EFCCKG:1; /**< bit: 2 EFC Dynamic Clock Gating Enable */ 404 uint32_t :29; /**< bit: 3..31 Reserved */ 405 } bit; /**< Structure used for bit access */ 406 uint32_t reg; /**< Type used for register access */ 407 } CCFG_DYNCKG_Type; 408 #endif 409 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 410 411 #define CCFG_DYNCKG_OFFSET (0x11C) /**< (CCFG_DYNCKG) Dynamic Clock Gating Register Offset */ 412 413 #define CCFG_DYNCKG_MATCKG_Pos 0 /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Position */ 414 #define CCFG_DYNCKG_MATCKG_Msk (_U_(0x1) << CCFG_DYNCKG_MATCKG_Pos) /**< (CCFG_DYNCKG) MATRIX Dynamic Clock Gating Mask */ 415 #define CCFG_DYNCKG_MATCKG CCFG_DYNCKG_MATCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_MATCKG_Msk instead */ 416 #define CCFG_DYNCKG_BRIDCKG_Pos 1 /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Position */ 417 #define CCFG_DYNCKG_BRIDCKG_Msk (_U_(0x1) << CCFG_DYNCKG_BRIDCKG_Pos) /**< (CCFG_DYNCKG) Bridge Dynamic Clock Gating Enable Mask */ 418 #define CCFG_DYNCKG_BRIDCKG CCFG_DYNCKG_BRIDCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_BRIDCKG_Msk instead */ 419 #define CCFG_DYNCKG_EFCCKG_Pos 2 /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Position */ 420 #define CCFG_DYNCKG_EFCCKG_Msk (_U_(0x1) << CCFG_DYNCKG_EFCCKG_Pos) /**< (CCFG_DYNCKG) EFC Dynamic Clock Gating Enable Mask */ 421 #define CCFG_DYNCKG_EFCCKG CCFG_DYNCKG_EFCCKG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_DYNCKG_EFCCKG_Msk instead */ 422 #define CCFG_DYNCKG_MASK _U_(0x07) /**< \deprecated (CCFG_DYNCKG) Register MASK (Use CCFG_DYNCKG_Msk instead) */ 423 #define CCFG_DYNCKG_Msk _U_(0x07) /**< (CCFG_DYNCKG) Register Mask */ 424 425 426 /* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x124) (R/W 32) SMC NAND Flash Chip Select Configuration Register -------- */ 427 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 428 #if COMPONENT_TYPEDEF_STYLE == 'N' 429 typedef union { 430 struct { 431 uint32_t SMC_NFCS0:1; /**< bit: 0 SMC NAND Flash Chip Select 0 Assignment */ 432 uint32_t SMC_NFCS1:1; /**< bit: 1 SMC NAND Flash Chip Select 1 Assignment */ 433 uint32_t SMC_NFCS2:1; /**< bit: 2 SMC NAND Flash Chip Select 2 Assignment */ 434 uint32_t SMC_NFCS3:1; /**< bit: 3 SMC NAND Flash Chip Select 3 Assignment */ 435 uint32_t SDRAMEN:1; /**< bit: 4 SDRAM Enable */ 436 uint32_t :27; /**< bit: 5..31 Reserved */ 437 } bit; /**< Structure used for bit access */ 438 struct { 439 uint32_t SMC_NFCS:4; /**< bit: 0..3 SMC NAND Flash Chip Select x Assignment */ 440 uint32_t :28; /**< bit: 4..31 Reserved */ 441 } vec; /**< Structure used for vec access */ 442 uint32_t reg; /**< Type used for register access */ 443 } CCFG_SMCNFCS_Type; 444 #endif 445 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 446 447 #define CCFG_SMCNFCS_OFFSET (0x124) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select Configuration Register Offset */ 448 449 #define CCFG_SMCNFCS_SMC_NFCS0_Pos 0 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Position */ 450 #define CCFG_SMCNFCS_SMC_NFCS0_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS0_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment Mask */ 451 #define CCFG_SMCNFCS_SMC_NFCS0 CCFG_SMCNFCS_SMC_NFCS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS0_Msk instead */ 452 #define CCFG_SMCNFCS_SMC_NFCS1_Pos 1 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Position */ 453 #define CCFG_SMCNFCS_SMC_NFCS1_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS1_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment Mask */ 454 #define CCFG_SMCNFCS_SMC_NFCS1 CCFG_SMCNFCS_SMC_NFCS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS1_Msk instead */ 455 #define CCFG_SMCNFCS_SMC_NFCS2_Pos 2 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Position */ 456 #define CCFG_SMCNFCS_SMC_NFCS2_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS2_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment Mask */ 457 #define CCFG_SMCNFCS_SMC_NFCS2 CCFG_SMCNFCS_SMC_NFCS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS2_Msk instead */ 458 #define CCFG_SMCNFCS_SMC_NFCS3_Pos 3 /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Position */ 459 #define CCFG_SMCNFCS_SMC_NFCS3_Msk (_U_(0x1) << CCFG_SMCNFCS_SMC_NFCS3_Pos) /**< (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment Mask */ 460 #define CCFG_SMCNFCS_SMC_NFCS3 CCFG_SMCNFCS_SMC_NFCS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SMC_NFCS3_Msk instead */ 461 #define CCFG_SMCNFCS_SDRAMEN_Pos 4 /**< (CCFG_SMCNFCS) SDRAM Enable Position */ 462 #define CCFG_SMCNFCS_SDRAMEN_Msk (_U_(0x1) << CCFG_SMCNFCS_SDRAMEN_Pos) /**< (CCFG_SMCNFCS) SDRAM Enable Mask */ 463 #define CCFG_SMCNFCS_SDRAMEN CCFG_SMCNFCS_SDRAMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CCFG_SMCNFCS_SDRAMEN_Msk instead */ 464 #define CCFG_SMCNFCS_MASK _U_(0x1F) /**< \deprecated (CCFG_SMCNFCS) Register MASK (Use CCFG_SMCNFCS_Msk instead) */ 465 #define CCFG_SMCNFCS_Msk _U_(0x1F) /**< (CCFG_SMCNFCS) Register Mask */ 466 467 #define CCFG_SMCNFCS_SMC_NFCS_Pos 0 /**< (CCFG_SMCNFCS Position) SMC NAND Flash Chip Select x Assignment */ 468 #define CCFG_SMCNFCS_SMC_NFCS_Msk (_U_(0xF) << CCFG_SMCNFCS_SMC_NFCS_Pos) /**< (CCFG_SMCNFCS Mask) SMC_NFCS */ 469 #define CCFG_SMCNFCS_SMC_NFCS(value) (CCFG_SMCNFCS_SMC_NFCS_Msk & ((value) << CCFG_SMCNFCS_SMC_NFCS_Pos)) 470 471 /* -------- MATRIX_WPMR : (MATRIX Offset: 0x1e4) (R/W 32) Write Protection Mode Register -------- */ 472 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 473 #if COMPONENT_TYPEDEF_STYLE == 'N' 474 typedef union { 475 struct { 476 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 477 uint32_t :7; /**< bit: 1..7 Reserved */ 478 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 479 } bit; /**< Structure used for bit access */ 480 uint32_t reg; /**< Type used for register access */ 481 } MATRIX_WPMR_Type; 482 #endif 483 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 484 485 #define MATRIX_WPMR_OFFSET (0x1E4) /**< (MATRIX_WPMR) Write Protection Mode Register Offset */ 486 487 #define MATRIX_WPMR_WPEN_Pos 0 /**< (MATRIX_WPMR) Write Protection Enable Position */ 488 #define MATRIX_WPMR_WPEN_Msk (_U_(0x1) << MATRIX_WPMR_WPEN_Pos) /**< (MATRIX_WPMR) Write Protection Enable Mask */ 489 #define MATRIX_WPMR_WPEN MATRIX_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_WPMR_WPEN_Msk instead */ 490 #define MATRIX_WPMR_WPKEY_Pos 8 /**< (MATRIX_WPMR) Write Protection Key Position */ 491 #define MATRIX_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Write Protection Key Mask */ 492 #define MATRIX_WPMR_WPKEY(value) (MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)) 493 #define MATRIX_WPMR_WPKEY_PASSWD_Val _U_(0x4D4154) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 494 #define MATRIX_WPMR_WPKEY_PASSWD (MATRIX_WPMR_WPKEY_PASSWD_Val << MATRIX_WPMR_WPKEY_Pos) /**< (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 495 #define MATRIX_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (MATRIX_WPMR) Register MASK (Use MATRIX_WPMR_Msk instead) */ 496 #define MATRIX_WPMR_Msk _U_(0xFFFFFF01) /**< (MATRIX_WPMR) Register Mask */ 497 498 499 /* -------- MATRIX_WPSR : (MATRIX Offset: 0x1e8) (R/ 32) Write Protection Status Register -------- */ 500 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 501 #if COMPONENT_TYPEDEF_STYLE == 'N' 502 typedef union { 503 struct { 504 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 505 uint32_t :7; /**< bit: 1..7 Reserved */ 506 uint32_t WPVSRC:16; /**< bit: 8..23 Write Protection Violation Source */ 507 uint32_t :8; /**< bit: 24..31 Reserved */ 508 } bit; /**< Structure used for bit access */ 509 uint32_t reg; /**< Type used for register access */ 510 } MATRIX_WPSR_Type; 511 #endif 512 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 513 514 #define MATRIX_WPSR_OFFSET (0x1E8) /**< (MATRIX_WPSR) Write Protection Status Register Offset */ 515 516 #define MATRIX_WPSR_WPVS_Pos 0 /**< (MATRIX_WPSR) Write Protection Violation Status Position */ 517 #define MATRIX_WPSR_WPVS_Msk (_U_(0x1) << MATRIX_WPSR_WPVS_Pos) /**< (MATRIX_WPSR) Write Protection Violation Status Mask */ 518 #define MATRIX_WPSR_WPVS MATRIX_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MATRIX_WPSR_WPVS_Msk instead */ 519 #define MATRIX_WPSR_WPVSRC_Pos 8 /**< (MATRIX_WPSR) Write Protection Violation Source Position */ 520 #define MATRIX_WPSR_WPVSRC_Msk (_U_(0xFFFF) << MATRIX_WPSR_WPVSRC_Pos) /**< (MATRIX_WPSR) Write Protection Violation Source Mask */ 521 #define MATRIX_WPSR_WPVSRC(value) (MATRIX_WPSR_WPVSRC_Msk & ((value) << MATRIX_WPSR_WPVSRC_Pos)) 522 #define MATRIX_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (MATRIX_WPSR) Register MASK (Use MATRIX_WPSR_Msk instead) */ 523 #define MATRIX_WPSR_Msk _U_(0xFFFF01) /**< (MATRIX_WPSR) Register Mask */ 524 525 526 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 527 #if COMPONENT_TYPEDEF_STYLE == 'R' 528 /** \brief MATRIX_PR hardware registers */ 529 typedef struct { 530 __IO uint32_t MATRIX_PRAS; /**< (MATRIX_PR Offset: 0x00) Priority Register A for Slave 0 */ 531 __IO uint32_t MATRIX_PRBS; /**< (MATRIX_PR Offset: 0x04) Priority Register B for Slave 0 */ 532 } MatrixPr; 533 534 #define MATRIXPR_NUMBER 9 535 /** \brief MATRIX hardware registers */ 536 typedef struct { 537 __IO uint32_t MATRIX_MCFG[13]; /**< (MATRIX Offset: 0x00) Master Configuration Register 0 */ 538 __I uint8_t Reserved1[12]; 539 __IO uint32_t MATRIX_SCFG[9]; /**< (MATRIX Offset: 0x40) Slave Configuration Register 0 */ 540 __I uint8_t Reserved2[28]; 541 MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< Offset: 0x80 Priority Register A for Slave 0 */ 542 __I uint8_t Reserved3[56]; 543 __IO uint32_t MATRIX_MRCR; /**< (MATRIX Offset: 0x100) Master Remap Control Register */ 544 __I uint8_t Reserved4[12]; 545 __IO uint32_t CCFG_CAN0; /**< (MATRIX Offset: 0x110) CAN0 Configuration Register */ 546 __IO uint32_t CCFG_SYSIO; /**< (MATRIX Offset: 0x114) System I/O and CAN1 Configuration Register */ 547 __IO uint32_t CCFG_PCCR; /**< (MATRIX Offset: 0x118) Peripheral Clock Configuration Register */ 548 __IO uint32_t CCFG_DYNCKG; /**< (MATRIX Offset: 0x11C) Dynamic Clock Gating Register */ 549 __I uint8_t Reserved5[4]; 550 __IO uint32_t CCFG_SMCNFCS; /**< (MATRIX Offset: 0x124) SMC NAND Flash Chip Select Configuration Register */ 551 __I uint8_t Reserved6[188]; 552 __IO uint32_t MATRIX_WPMR; /**< (MATRIX Offset: 0x1E4) Write Protection Mode Register */ 553 __I uint32_t MATRIX_WPSR; /**< (MATRIX Offset: 0x1E8) Write Protection Status Register */ 554 } Matrix; 555 556 #elif COMPONENT_TYPEDEF_STYLE == 'N' 557 /** \brief MATRIX_PR hardware registers */ 558 typedef struct { 559 __IO MATRIX_PRAS_Type MATRIX_PRAS; /**< Offset: 0x00 (R/W 32) Priority Register A for Slave 0 */ 560 __IO MATRIX_PRBS_Type MATRIX_PRBS; /**< Offset: 0x04 (R/W 32) Priority Register B for Slave 0 */ 561 } MatrixPr; 562 563 /** \brief MATRIX hardware registers */ 564 typedef struct { 565 __IO MATRIX_MCFG_Type MATRIX_MCFG[13]; /**< Offset: 0x00 (R/W 32) Master Configuration Register 0 */ 566 __I uint8_t Reserved1[12]; 567 __IO MATRIX_SCFG_Type MATRIX_SCFG[9]; /**< Offset: 0x40 (R/W 32) Slave Configuration Register 0 */ 568 __I uint8_t Reserved2[28]; 569 MatrixPr MATRIX_PR[9]; /**< Offset: 0x80 Priority Register A for Slave 0 */ 570 __I uint8_t Reserved3[56]; 571 __IO MATRIX_MRCR_Type MATRIX_MRCR; /**< Offset: 0x100 (R/W 32) Master Remap Control Register */ 572 __I uint8_t Reserved4[12]; 573 __IO CCFG_CAN0_Type CCFG_CAN0; /**< Offset: 0x110 (R/W 32) CAN0 Configuration Register */ 574 __IO CCFG_SYSIO_Type CCFG_SYSIO; /**< Offset: 0x114 (R/W 32) System I/O and CAN1 Configuration Register */ 575 __IO CCFG_PCCR_Type CCFG_PCCR; /**< Offset: 0x118 (R/W 32) Peripheral Clock Configuration Register */ 576 __IO CCFG_DYNCKG_Type CCFG_DYNCKG; /**< Offset: 0x11C (R/W 32) Dynamic Clock Gating Register */ 577 __I uint8_t Reserved5[4]; 578 __IO CCFG_SMCNFCS_Type CCFG_SMCNFCS; /**< Offset: 0x124 (R/W 32) SMC NAND Flash Chip Select Configuration Register */ 579 __I uint8_t Reserved6[188]; 580 __IO MATRIX_WPMR_Type MATRIX_WPMR; /**< Offset: 0x1E4 (R/W 32) Write Protection Mode Register */ 581 __I MATRIX_WPSR_Type MATRIX_WPSR; /**< Offset: 0x1E8 (R/ 32) Write Protection Status Register */ 582 } Matrix; 583 584 #else /* COMPONENT_TYPEDEF_STYLE */ 585 #error Unknown component typedef style 586 #endif /* COMPONENT_TYPEDEF_STYLE */ 587 588 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 589 /** @} end of AHB Bus Matrix */ 590 591 #endif /* _SAME70_MATRIX_COMPONENT_H_ */ 592
