1 /** 2 * \file 3 * 4 * \brief Instance description for SPI1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-08-25T14:00:00Z */ 31 #ifndef _SAME70_SPI1_INSTANCE_H_ 32 #define _SAME70_SPI1_INSTANCE_H_ 33 34 /* ========== Register definition for SPI1 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_SPI1_CR (0x40058000) /**< (SPI1) Control Register */ 38 #define REG_SPI1_MR (0x40058004) /**< (SPI1) Mode Register */ 39 #define REG_SPI1_RDR (0x40058008) /**< (SPI1) Receive Data Register */ 40 #define REG_SPI1_TDR (0x4005800C) /**< (SPI1) Transmit Data Register */ 41 #define REG_SPI1_SR (0x40058010) /**< (SPI1) Status Register */ 42 #define REG_SPI1_IER (0x40058014) /**< (SPI1) Interrupt Enable Register */ 43 #define REG_SPI1_IDR (0x40058018) /**< (SPI1) Interrupt Disable Register */ 44 #define REG_SPI1_IMR (0x4005801C) /**< (SPI1) Interrupt Mask Register */ 45 #define REG_SPI1_CSR (0x40058030) /**< (SPI1) Chip Select Register 0 */ 46 #define REG_SPI1_CSR0 (0x40058030) /**< (SPI1) Chip Select Register 0 */ 47 #define REG_SPI1_CSR1 (0x40058034) /**< (SPI1) Chip Select Register 1 */ 48 #define REG_SPI1_CSR2 (0x40058038) /**< (SPI1) Chip Select Register 2 */ 49 #define REG_SPI1_CSR3 (0x4005803C) /**< (SPI1) Chip Select Register 3 */ 50 #define REG_SPI1_WPMR (0x400580E4) /**< (SPI1) Write Protection Mode Register */ 51 #define REG_SPI1_WPSR (0x400580E8) /**< (SPI1) Write Protection Status Register */ 52 53 #else 54 55 #define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< (SPI1) Control Register */ 56 #define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< (SPI1) Mode Register */ 57 #define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< (SPI1) Receive Data Register */ 58 #define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< (SPI1) Transmit Data Register */ 59 #define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< (SPI1) Status Register */ 60 #define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< (SPI1) Interrupt Enable Register */ 61 #define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< (SPI1) Interrupt Disable Register */ 62 #define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< (SPI1) Interrupt Mask Register */ 63 #define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register 0 */ 64 #define REG_SPI1_CSR0 (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register 0 */ 65 #define REG_SPI1_CSR1 (*(__IO uint32_t*)0x40058034U) /**< (SPI1) Chip Select Register 1 */ 66 #define REG_SPI1_CSR2 (*(__IO uint32_t*)0x40058038U) /**< (SPI1) Chip Select Register 2 */ 67 #define REG_SPI1_CSR3 (*(__IO uint32_t*)0x4005803CU) /**< (SPI1) Chip Select Register 3 */ 68 #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< (SPI1) Write Protection Mode Register */ 69 #define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< (SPI1) Write Protection Status Register */ 70 71 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 72 73 /* ========== Instance Parameter definitions for SPI1 peripheral ========== */ 74 #define SPI1_DMAC_ID_RX 4 75 #define SPI1_DMAC_ID_TX 3 76 #define SPI1_INSTANCE_ID 42 77 78 #endif /* _SAME70_SPI1_INSTANCE_ */ 79
