1 /** 2 * \file 3 * 4 * \brief Component description for ACC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-08-25T14:00:00Z */ 31 #ifndef _SAME70_ACC_COMPONENT_H_ 32 #define _SAME70_ACC_COMPONENT_H_ 33 #define _SAME70_ACC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 Analog Comparator Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR ACC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define ACC_6490 /**< (ACC) Module ID */ 46 #define REV_ACC H /**< (ACC) Module revision */ 47 48 /* -------- ACC_CR : (ACC Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t SWRST:1; /**< bit: 0 Software Reset */ 54 uint32_t :31; /**< bit: 1..31 Reserved */ 55 } bit; /**< Structure used for bit access */ 56 uint32_t reg; /**< Type used for register access */ 57 } ACC_CR_Type; 58 #endif 59 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 #define ACC_CR_OFFSET (0x00) /**< (ACC_CR) Control Register Offset */ 62 63 #define ACC_CR_SWRST_Pos 0 /**< (ACC_CR) Software Reset Position */ 64 #define ACC_CR_SWRST_Msk (_U_(0x1) << ACC_CR_SWRST_Pos) /**< (ACC_CR) Software Reset Mask */ 65 #define ACC_CR_SWRST ACC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_CR_SWRST_Msk instead */ 66 #define ACC_CR_MASK _U_(0x01) /**< \deprecated (ACC_CR) Register MASK (Use ACC_CR_Msk instead) */ 67 #define ACC_CR_Msk _U_(0x01) /**< (ACC_CR) Register Mask */ 68 69 70 /* -------- ACC_MR : (ACC Offset: 0x04) (R/W 32) Mode Register -------- */ 71 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 72 #if COMPONENT_TYPEDEF_STYLE == 'N' 73 typedef union { 74 struct { 75 uint32_t SELMINUS:3; /**< bit: 0..2 Selection for Minus Comparator Input */ 76 uint32_t :1; /**< bit: 3 Reserved */ 77 uint32_t SELPLUS:3; /**< bit: 4..6 Selection For Plus Comparator Input */ 78 uint32_t :1; /**< bit: 7 Reserved */ 79 uint32_t ACEN:1; /**< bit: 8 Analog Comparator Enable */ 80 uint32_t EDGETYP:2; /**< bit: 9..10 Edge Type */ 81 uint32_t :1; /**< bit: 11 Reserved */ 82 uint32_t INV:1; /**< bit: 12 Invert Comparator Output */ 83 uint32_t SELFS:1; /**< bit: 13 Selection Of Fault Source */ 84 uint32_t FE:1; /**< bit: 14 Fault Enable */ 85 uint32_t :17; /**< bit: 15..31 Reserved */ 86 } bit; /**< Structure used for bit access */ 87 uint32_t reg; /**< Type used for register access */ 88 } ACC_MR_Type; 89 #endif 90 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 #define ACC_MR_OFFSET (0x04) /**< (ACC_MR) Mode Register Offset */ 93 94 #define ACC_MR_SELMINUS_Pos 0 /**< (ACC_MR) Selection for Minus Comparator Input Position */ 95 #define ACC_MR_SELMINUS_Msk (_U_(0x7) << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Selection for Minus Comparator Input Mask */ 96 #define ACC_MR_SELMINUS(value) (ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos)) 97 #define ACC_MR_SELMINUS_TS_Val _U_(0x0) /**< (ACC_MR) Select TS */ 98 #define ACC_MR_SELMINUS_VREFP_Val _U_(0x1) /**< (ACC_MR) Select VREFP */ 99 #define ACC_MR_SELMINUS_DAC0_Val _U_(0x2) /**< (ACC_MR) Select DAC0 */ 100 #define ACC_MR_SELMINUS_DAC1_Val _U_(0x3) /**< (ACC_MR) Select DAC1 */ 101 #define ACC_MR_SELMINUS_AFE0_AD0_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD0 */ 102 #define ACC_MR_SELMINUS_AFE0_AD1_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD1 */ 103 #define ACC_MR_SELMINUS_AFE0_AD2_Val _U_(0x6) /**< (ACC_MR) Select AFE0_AD2 */ 104 #define ACC_MR_SELMINUS_AFE0_AD3_Val _U_(0x7) /**< (ACC_MR) Select AFE0_AD3 */ 105 #define ACC_MR_SELMINUS_TS (ACC_MR_SELMINUS_TS_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select TS Position */ 106 #define ACC_MR_SELMINUS_VREFP (ACC_MR_SELMINUS_VREFP_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select VREFP Position */ 107 #define ACC_MR_SELMINUS_DAC0 (ACC_MR_SELMINUS_DAC0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC0 Position */ 108 #define ACC_MR_SELMINUS_DAC1 (ACC_MR_SELMINUS_DAC1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select DAC1 Position */ 109 #define ACC_MR_SELMINUS_AFE0_AD0 (ACC_MR_SELMINUS_AFE0_AD0_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */ 110 #define ACC_MR_SELMINUS_AFE0_AD1 (ACC_MR_SELMINUS_AFE0_AD1_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */ 111 #define ACC_MR_SELMINUS_AFE0_AD2 (ACC_MR_SELMINUS_AFE0_AD2_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */ 112 #define ACC_MR_SELMINUS_AFE0_AD3 (ACC_MR_SELMINUS_AFE0_AD3_Val << ACC_MR_SELMINUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */ 113 #define ACC_MR_SELPLUS_Pos 4 /**< (ACC_MR) Selection For Plus Comparator Input Position */ 114 #define ACC_MR_SELPLUS_Msk (_U_(0x7) << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Selection For Plus Comparator Input Mask */ 115 #define ACC_MR_SELPLUS(value) (ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos)) 116 #define ACC_MR_SELPLUS_AFE0_AD0_Val _U_(0x0) /**< (ACC_MR) Select AFE0_AD0 */ 117 #define ACC_MR_SELPLUS_AFE0_AD1_Val _U_(0x1) /**< (ACC_MR) Select AFE0_AD1 */ 118 #define ACC_MR_SELPLUS_AFE0_AD2_Val _U_(0x2) /**< (ACC_MR) Select AFE0_AD2 */ 119 #define ACC_MR_SELPLUS_AFE0_AD3_Val _U_(0x3) /**< (ACC_MR) Select AFE0_AD3 */ 120 #define ACC_MR_SELPLUS_AFE0_AD4_Val _U_(0x4) /**< (ACC_MR) Select AFE0_AD4 */ 121 #define ACC_MR_SELPLUS_AFE0_AD5_Val _U_(0x5) /**< (ACC_MR) Select AFE0_AD5 */ 122 #define ACC_MR_SELPLUS_AFE1_AD0_Val _U_(0x6) /**< (ACC_MR) Select AFE1_AD0 */ 123 #define ACC_MR_SELPLUS_AFE1_AD1_Val _U_(0x7) /**< (ACC_MR) Select AFE1_AD1 */ 124 #define ACC_MR_SELPLUS_AFE0_AD0 (ACC_MR_SELPLUS_AFE0_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD0 Position */ 125 #define ACC_MR_SELPLUS_AFE0_AD1 (ACC_MR_SELPLUS_AFE0_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD1 Position */ 126 #define ACC_MR_SELPLUS_AFE0_AD2 (ACC_MR_SELPLUS_AFE0_AD2_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD2 Position */ 127 #define ACC_MR_SELPLUS_AFE0_AD3 (ACC_MR_SELPLUS_AFE0_AD3_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD3 Position */ 128 #define ACC_MR_SELPLUS_AFE0_AD4 (ACC_MR_SELPLUS_AFE0_AD4_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD4 Position */ 129 #define ACC_MR_SELPLUS_AFE0_AD5 (ACC_MR_SELPLUS_AFE0_AD5_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE0_AD5 Position */ 130 #define ACC_MR_SELPLUS_AFE1_AD0 (ACC_MR_SELPLUS_AFE1_AD0_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD0 Position */ 131 #define ACC_MR_SELPLUS_AFE1_AD1 (ACC_MR_SELPLUS_AFE1_AD1_Val << ACC_MR_SELPLUS_Pos) /**< (ACC_MR) Select AFE1_AD1 Position */ 132 #define ACC_MR_ACEN_Pos 8 /**< (ACC_MR) Analog Comparator Enable Position */ 133 #define ACC_MR_ACEN_Msk (_U_(0x1) << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog Comparator Enable Mask */ 134 #define ACC_MR_ACEN ACC_MR_ACEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_ACEN_Msk instead */ 135 #define ACC_MR_ACEN_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator disabled. */ 136 #define ACC_MR_ACEN_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator enabled. */ 137 #define ACC_MR_ACEN_DIS (ACC_MR_ACEN_DIS_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator disabled. Position */ 138 #define ACC_MR_ACEN_EN (ACC_MR_ACEN_EN_Val << ACC_MR_ACEN_Pos) /**< (ACC_MR) Analog comparator enabled. Position */ 139 #define ACC_MR_EDGETYP_Pos 9 /**< (ACC_MR) Edge Type Position */ 140 #define ACC_MR_EDGETYP_Msk (_U_(0x3) << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Edge Type Mask */ 141 #define ACC_MR_EDGETYP(value) (ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos)) 142 #define ACC_MR_EDGETYP_RISING_Val _U_(0x0) /**< (ACC_MR) Only rising edge of comparator output */ 143 #define ACC_MR_EDGETYP_FALLING_Val _U_(0x1) /**< (ACC_MR) Falling edge of comparator output */ 144 #define ACC_MR_EDGETYP_ANY_Val _U_(0x2) /**< (ACC_MR) Any edge of comparator output */ 145 #define ACC_MR_EDGETYP_RISING (ACC_MR_EDGETYP_RISING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Only rising edge of comparator output Position */ 146 #define ACC_MR_EDGETYP_FALLING (ACC_MR_EDGETYP_FALLING_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Falling edge of comparator output Position */ 147 #define ACC_MR_EDGETYP_ANY (ACC_MR_EDGETYP_ANY_Val << ACC_MR_EDGETYP_Pos) /**< (ACC_MR) Any edge of comparator output Position */ 148 #define ACC_MR_INV_Pos 12 /**< (ACC_MR) Invert Comparator Output Position */ 149 #define ACC_MR_INV_Msk (_U_(0x1) << ACC_MR_INV_Pos) /**< (ACC_MR) Invert Comparator Output Mask */ 150 #define ACC_MR_INV ACC_MR_INV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_INV_Msk instead */ 151 #define ACC_MR_INV_DIS_Val _U_(0x0) /**< (ACC_MR) Analog comparator output is directly processed. */ 152 #define ACC_MR_INV_EN_Val _U_(0x1) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. */ 153 #define ACC_MR_INV_DIS (ACC_MR_INV_DIS_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is directly processed. Position */ 154 #define ACC_MR_INV_EN (ACC_MR_INV_EN_Val << ACC_MR_INV_Pos) /**< (ACC_MR) Analog comparator output is inverted prior to being processed. Position */ 155 #define ACC_MR_SELFS_Pos 13 /**< (ACC_MR) Selection Of Fault Source Position */ 156 #define ACC_MR_SELFS_Msk (_U_(0x1) << ACC_MR_SELFS_Pos) /**< (ACC_MR) Selection Of Fault Source Mask */ 157 #define ACC_MR_SELFS ACC_MR_SELFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_SELFS_Msk instead */ 158 #define ACC_MR_SELFS_CE_Val _U_(0x0) /**< (ACC_MR) The CE flag is used to drive the FAULT output. */ 159 #define ACC_MR_SELFS_OUTPUT_Val _U_(0x1) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ 160 #define ACC_MR_SELFS_CE (ACC_MR_SELFS_CE_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The CE flag is used to drive the FAULT output. Position */ 161 #define ACC_MR_SELFS_OUTPUT (ACC_MR_SELFS_OUTPUT_Val << ACC_MR_SELFS_Pos) /**< (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. Position */ 162 #define ACC_MR_FE_Pos 14 /**< (ACC_MR) Fault Enable Position */ 163 #define ACC_MR_FE_Msk (_U_(0x1) << ACC_MR_FE_Pos) /**< (ACC_MR) Fault Enable Mask */ 164 #define ACC_MR_FE ACC_MR_FE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_MR_FE_Msk instead */ 165 #define ACC_MR_FE_DIS_Val _U_(0x0) /**< (ACC_MR) The FAULT output is tied to 0. */ 166 #define ACC_MR_FE_EN_Val _U_(0x1) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ 167 #define ACC_MR_FE_DIS (ACC_MR_FE_DIS_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is tied to 0. Position */ 168 #define ACC_MR_FE_EN (ACC_MR_FE_EN_Val << ACC_MR_FE_Pos) /**< (ACC_MR) The FAULT output is driven by the signal defined by SELFS. Position */ 169 #define ACC_MR_MASK _U_(0x7777) /**< \deprecated (ACC_MR) Register MASK (Use ACC_MR_Msk instead) */ 170 #define ACC_MR_Msk _U_(0x7777) /**< (ACC_MR) Register Mask */ 171 172 173 /* -------- ACC_IER : (ACC Offset: 0x24) (/W 32) Interrupt Enable Register -------- */ 174 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 175 #if COMPONENT_TYPEDEF_STYLE == 'N' 176 typedef union { 177 struct { 178 uint32_t CE:1; /**< bit: 0 Comparison Edge */ 179 uint32_t :31; /**< bit: 1..31 Reserved */ 180 } bit; /**< Structure used for bit access */ 181 uint32_t reg; /**< Type used for register access */ 182 } ACC_IER_Type; 183 #endif 184 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 185 186 #define ACC_IER_OFFSET (0x24) /**< (ACC_IER) Interrupt Enable Register Offset */ 187 188 #define ACC_IER_CE_Pos 0 /**< (ACC_IER) Comparison Edge Position */ 189 #define ACC_IER_CE_Msk (_U_(0x1) << ACC_IER_CE_Pos) /**< (ACC_IER) Comparison Edge Mask */ 190 #define ACC_IER_CE ACC_IER_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_IER_CE_Msk instead */ 191 #define ACC_IER_MASK _U_(0x01) /**< \deprecated (ACC_IER) Register MASK (Use ACC_IER_Msk instead) */ 192 #define ACC_IER_Msk _U_(0x01) /**< (ACC_IER) Register Mask */ 193 194 195 /* -------- ACC_IDR : (ACC Offset: 0x28) (/W 32) Interrupt Disable Register -------- */ 196 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 197 #if COMPONENT_TYPEDEF_STYLE == 'N' 198 typedef union { 199 struct { 200 uint32_t CE:1; /**< bit: 0 Comparison Edge */ 201 uint32_t :31; /**< bit: 1..31 Reserved */ 202 } bit; /**< Structure used for bit access */ 203 uint32_t reg; /**< Type used for register access */ 204 } ACC_IDR_Type; 205 #endif 206 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 207 208 #define ACC_IDR_OFFSET (0x28) /**< (ACC_IDR) Interrupt Disable Register Offset */ 209 210 #define ACC_IDR_CE_Pos 0 /**< (ACC_IDR) Comparison Edge Position */ 211 #define ACC_IDR_CE_Msk (_U_(0x1) << ACC_IDR_CE_Pos) /**< (ACC_IDR) Comparison Edge Mask */ 212 #define ACC_IDR_CE ACC_IDR_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_IDR_CE_Msk instead */ 213 #define ACC_IDR_MASK _U_(0x01) /**< \deprecated (ACC_IDR) Register MASK (Use ACC_IDR_Msk instead) */ 214 #define ACC_IDR_Msk _U_(0x01) /**< (ACC_IDR) Register Mask */ 215 216 217 /* -------- ACC_IMR : (ACC Offset: 0x2c) (R/ 32) Interrupt Mask Register -------- */ 218 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 219 #if COMPONENT_TYPEDEF_STYLE == 'N' 220 typedef union { 221 struct { 222 uint32_t CE:1; /**< bit: 0 Comparison Edge */ 223 uint32_t :31; /**< bit: 1..31 Reserved */ 224 } bit; /**< Structure used for bit access */ 225 uint32_t reg; /**< Type used for register access */ 226 } ACC_IMR_Type; 227 #endif 228 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 229 230 #define ACC_IMR_OFFSET (0x2C) /**< (ACC_IMR) Interrupt Mask Register Offset */ 231 232 #define ACC_IMR_CE_Pos 0 /**< (ACC_IMR) Comparison Edge Position */ 233 #define ACC_IMR_CE_Msk (_U_(0x1) << ACC_IMR_CE_Pos) /**< (ACC_IMR) Comparison Edge Mask */ 234 #define ACC_IMR_CE ACC_IMR_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_IMR_CE_Msk instead */ 235 #define ACC_IMR_MASK _U_(0x01) /**< \deprecated (ACC_IMR) Register MASK (Use ACC_IMR_Msk instead) */ 236 #define ACC_IMR_Msk _U_(0x01) /**< (ACC_IMR) Register Mask */ 237 238 239 /* -------- ACC_ISR : (ACC Offset: 0x30) (R/ 32) Interrupt Status Register -------- */ 240 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 241 #if COMPONENT_TYPEDEF_STYLE == 'N' 242 typedef union { 243 struct { 244 uint32_t CE:1; /**< bit: 0 Comparison Edge (cleared on read) */ 245 uint32_t SCO:1; /**< bit: 1 Synchronized Comparator Output */ 246 uint32_t :29; /**< bit: 2..30 Reserved */ 247 uint32_t MASK:1; /**< bit: 31 Flag Mask */ 248 } bit; /**< Structure used for bit access */ 249 uint32_t reg; /**< Type used for register access */ 250 } ACC_ISR_Type; 251 #endif 252 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 253 254 #define ACC_ISR_OFFSET (0x30) /**< (ACC_ISR) Interrupt Status Register Offset */ 255 256 #define ACC_ISR_CE_Pos 0 /**< (ACC_ISR) Comparison Edge (cleared on read) Position */ 257 #define ACC_ISR_CE_Msk (_U_(0x1) << ACC_ISR_CE_Pos) /**< (ACC_ISR) Comparison Edge (cleared on read) Mask */ 258 #define ACC_ISR_CE ACC_ISR_CE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ISR_CE_Msk instead */ 259 #define ACC_ISR_SCO_Pos 1 /**< (ACC_ISR) Synchronized Comparator Output Position */ 260 #define ACC_ISR_SCO_Msk (_U_(0x1) << ACC_ISR_SCO_Pos) /**< (ACC_ISR) Synchronized Comparator Output Mask */ 261 #define ACC_ISR_SCO ACC_ISR_SCO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ISR_SCO_Msk instead */ 262 #define ACC_ISR_MASK_Pos 31 /**< (ACC_ISR) Flag Mask Position */ 263 #define ACC_ISR_MASK_Msk (_U_(0x1) << ACC_ISR_MASK_Pos) /**< (ACC_ISR) Flag Mask Mask */ 264 #define ACC_ISR_MASK ACC_ISR_MASK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ISR_MASK_Msk instead */ 265 #define ACC_ISR_Msk _U_(0x80000003) /**< (ACC_ISR) Register Mask */ 266 267 268 /* -------- ACC_ACR : (ACC Offset: 0x94) (R/W 32) Analog Control Register -------- */ 269 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 270 #if COMPONENT_TYPEDEF_STYLE == 'N' 271 typedef union { 272 struct { 273 uint32_t ISEL:1; /**< bit: 0 Current Selection */ 274 uint32_t HYST:2; /**< bit: 1..2 Hysteresis Selection */ 275 uint32_t :29; /**< bit: 3..31 Reserved */ 276 } bit; /**< Structure used for bit access */ 277 uint32_t reg; /**< Type used for register access */ 278 } ACC_ACR_Type; 279 #endif 280 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 281 282 #define ACC_ACR_OFFSET (0x94) /**< (ACC_ACR) Analog Control Register Offset */ 283 284 #define ACC_ACR_ISEL_Pos 0 /**< (ACC_ACR) Current Selection Position */ 285 #define ACC_ACR_ISEL_Msk (_U_(0x1) << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Current Selection Mask */ 286 #define ACC_ACR_ISEL ACC_ACR_ISEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_ACR_ISEL_Msk instead */ 287 #define ACC_ACR_ISEL_LOPW_Val _U_(0x0) /**< (ACC_ACR) Low-power option. */ 288 #define ACC_ACR_ISEL_HISP_Val _U_(0x1) /**< (ACC_ACR) High-speed option. */ 289 #define ACC_ACR_ISEL_LOPW (ACC_ACR_ISEL_LOPW_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) Low-power option. Position */ 290 #define ACC_ACR_ISEL_HISP (ACC_ACR_ISEL_HISP_Val << ACC_ACR_ISEL_Pos) /**< (ACC_ACR) High-speed option. Position */ 291 #define ACC_ACR_HYST_Pos 1 /**< (ACC_ACR) Hysteresis Selection Position */ 292 #define ACC_ACR_HYST_Msk (_U_(0x3) << ACC_ACR_HYST_Pos) /**< (ACC_ACR) Hysteresis Selection Mask */ 293 #define ACC_ACR_HYST(value) (ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos)) 294 #define ACC_ACR_MASK _U_(0x07) /**< \deprecated (ACC_ACR) Register MASK (Use ACC_ACR_Msk instead) */ 295 #define ACC_ACR_Msk _U_(0x07) /**< (ACC_ACR) Register Mask */ 296 297 298 /* -------- ACC_WPMR : (ACC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 299 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 300 #if COMPONENT_TYPEDEF_STYLE == 'N' 301 typedef union { 302 struct { 303 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 304 uint32_t :7; /**< bit: 1..7 Reserved */ 305 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 306 } bit; /**< Structure used for bit access */ 307 uint32_t reg; /**< Type used for register access */ 308 } ACC_WPMR_Type; 309 #endif 310 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 311 312 #define ACC_WPMR_OFFSET (0xE4) /**< (ACC_WPMR) Write Protection Mode Register Offset */ 313 314 #define ACC_WPMR_WPEN_Pos 0 /**< (ACC_WPMR) Write Protection Enable Position */ 315 #define ACC_WPMR_WPEN_Msk (_U_(0x1) << ACC_WPMR_WPEN_Pos) /**< (ACC_WPMR) Write Protection Enable Mask */ 316 #define ACC_WPMR_WPEN ACC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_WPMR_WPEN_Msk instead */ 317 #define ACC_WPMR_WPKEY_Pos 8 /**< (ACC_WPMR) Write Protection Key Position */ 318 #define ACC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Write Protection Key Mask */ 319 #define ACC_WPMR_WPKEY(value) (ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos)) 320 #define ACC_WPMR_WPKEY_PASSWD_Val _U_(0x414343) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 321 #define ACC_WPMR_WPKEY_PASSWD (ACC_WPMR_WPKEY_PASSWD_Val << ACC_WPMR_WPKEY_Pos) /**< (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 322 #define ACC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (ACC_WPMR) Register MASK (Use ACC_WPMR_Msk instead) */ 323 #define ACC_WPMR_Msk _U_(0xFFFFFF01) /**< (ACC_WPMR) Register Mask */ 324 325 326 /* -------- ACC_WPSR : (ACC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 327 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 328 #if COMPONENT_TYPEDEF_STYLE == 'N' 329 typedef union { 330 struct { 331 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 332 uint32_t :31; /**< bit: 1..31 Reserved */ 333 } bit; /**< Structure used for bit access */ 334 uint32_t reg; /**< Type used for register access */ 335 } ACC_WPSR_Type; 336 #endif 337 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 338 339 #define ACC_WPSR_OFFSET (0xE8) /**< (ACC_WPSR) Write Protection Status Register Offset */ 340 341 #define ACC_WPSR_WPVS_Pos 0 /**< (ACC_WPSR) Write Protection Violation Status Position */ 342 #define ACC_WPSR_WPVS_Msk (_U_(0x1) << ACC_WPSR_WPVS_Pos) /**< (ACC_WPSR) Write Protection Violation Status Mask */ 343 #define ACC_WPSR_WPVS ACC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ACC_WPSR_WPVS_Msk instead */ 344 #define ACC_WPSR_MASK _U_(0x01) /**< \deprecated (ACC_WPSR) Register MASK (Use ACC_WPSR_Msk instead) */ 345 #define ACC_WPSR_Msk _U_(0x01) /**< (ACC_WPSR) Register Mask */ 346 347 348 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 349 #if COMPONENT_TYPEDEF_STYLE == 'R' 350 /** \brief ACC hardware registers */ 351 typedef struct { 352 __O uint32_t ACC_CR; /**< (ACC Offset: 0x00) Control Register */ 353 __IO uint32_t ACC_MR; /**< (ACC Offset: 0x04) Mode Register */ 354 __I uint8_t Reserved1[28]; 355 __O uint32_t ACC_IER; /**< (ACC Offset: 0x24) Interrupt Enable Register */ 356 __O uint32_t ACC_IDR; /**< (ACC Offset: 0x28) Interrupt Disable Register */ 357 __I uint32_t ACC_IMR; /**< (ACC Offset: 0x2C) Interrupt Mask Register */ 358 __I uint32_t ACC_ISR; /**< (ACC Offset: 0x30) Interrupt Status Register */ 359 __I uint8_t Reserved2[96]; 360 __IO uint32_t ACC_ACR; /**< (ACC Offset: 0x94) Analog Control Register */ 361 __I uint8_t Reserved3[76]; 362 __IO uint32_t ACC_WPMR; /**< (ACC Offset: 0xE4) Write Protection Mode Register */ 363 __I uint32_t ACC_WPSR; /**< (ACC Offset: 0xE8) Write Protection Status Register */ 364 } Acc; 365 366 #elif COMPONENT_TYPEDEF_STYLE == 'N' 367 /** \brief ACC hardware registers */ 368 typedef struct { 369 __O ACC_CR_Type ACC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 370 __IO ACC_MR_Type ACC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 371 __I uint8_t Reserved1[28]; 372 __O ACC_IER_Type ACC_IER; /**< Offset: 0x24 ( /W 32) Interrupt Enable Register */ 373 __O ACC_IDR_Type ACC_IDR; /**< Offset: 0x28 ( /W 32) Interrupt Disable Register */ 374 __I ACC_IMR_Type ACC_IMR; /**< Offset: 0x2C (R/ 32) Interrupt Mask Register */ 375 __I ACC_ISR_Type ACC_ISR; /**< Offset: 0x30 (R/ 32) Interrupt Status Register */ 376 __I uint8_t Reserved2[96]; 377 __IO ACC_ACR_Type ACC_ACR; /**< Offset: 0x94 (R/W 32) Analog Control Register */ 378 __I uint8_t Reserved3[76]; 379 __IO ACC_WPMR_Type ACC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 380 __I ACC_WPSR_Type ACC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 381 } Acc; 382 383 #else /* COMPONENT_TYPEDEF_STYLE */ 384 #error Unknown component typedef style 385 #endif /* COMPONENT_TYPEDEF_STYLE */ 386 387 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 388 /** @} end of Analog Comparator Controller */ 389 390 #endif /* _SAME70_ACC_COMPONENT_H_ */ 391
