1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S2A_ 31 #define _SAM4S2A_ 32 33 /** \addtogroup SAM4S2A_definitions SAM4S2A definitions 34 This file defines all structures and symbols for SAM4S2A: 35 - registers and bitfields 36 - peripheral base address 37 - peripheral ID 38 - PIO definitions 39 */ 40 /*@{*/ 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 47 #include <stdint.h> 48 #endif 49 50 /* ************************************************************************** */ 51 /* CMSIS DEFINITIONS FOR SAM4S2A */ 52 /* ************************************************************************** */ 53 /** \addtogroup SAM4S2A_cmsis CMSIS Definitions */ 54 /*@{*/ 55 56 /**< Interrupt Number Definition */ 57 typedef enum IRQn 58 { 59 /****** Cortex-M4 Processor Exceptions Numbers ******************************/ 60 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ 61 HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ 62 MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ 63 BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ 64 UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ 65 SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ 66 DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ 67 PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ 68 SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ 69 /****** SAM4S2A specific Interrupt Numbers *********************************/ 70 71 SUPC_IRQn = 0, /**< 0 SAM4S2A Supply Controller (SUPC) */ 72 RSTC_IRQn = 1, /**< 1 SAM4S2A Reset Controller (RSTC) */ 73 RTC_IRQn = 2, /**< 2 SAM4S2A Real Time Clock (RTC) */ 74 RTT_IRQn = 3, /**< 3 SAM4S2A Real Time Timer (RTT) */ 75 WDT_IRQn = 4, /**< 4 SAM4S2A Watchdog Timer (WDT) */ 76 PMC_IRQn = 5, /**< 5 SAM4S2A Power Management Controller (PMC) */ 77 EFC0_IRQn = 6, /**< 6 SAM4S2A Enhanced Embedded Flash Controller 0 (EFC0) */ 78 UART0_IRQn = 8, /**< 8 SAM4S2A UART 0 (UART0) */ 79 UART1_IRQn = 9, /**< 9 SAM4S2A UART 1 (UART1) */ 80 PIOA_IRQn = 11, /**< 11 SAM4S2A Parallel I/O Controller A (PIOA) */ 81 PIOB_IRQn = 12, /**< 12 SAM4S2A Parallel I/O Controller B (PIOB) */ 82 USART0_IRQn = 14, /**< 14 SAM4S2A USART 0 (USART0) */ 83 TWI0_IRQn = 19, /**< 19 SAM4S2A Two Wire Interface 0 (TWI0) */ 84 TWI1_IRQn = 20, /**< 20 SAM4S2A Two Wire Interface 1 (TWI1) */ 85 SPI_IRQn = 21, /**< 21 SAM4S2A Serial Peripheral Interface (SPI) */ 86 SSC_IRQn = 22, /**< 22 SAM4S2A Synchronous Serial Controller (SSC) */ 87 TC0_IRQn = 23, /**< 23 SAM4S2A Timer/Counter 0 (TC0) */ 88 TC1_IRQn = 24, /**< 24 SAM4S2A Timer/Counter 1 (TC1) */ 89 TC2_IRQn = 25, /**< 25 SAM4S2A Timer/Counter 2 (TC2) */ 90 ADC_IRQn = 29, /**< 29 SAM4S2A Analog To Digital Converter (ADC) */ 91 PWM_IRQn = 31, /**< 31 SAM4S2A Pulse Width Modulation (PWM) */ 92 CRCCU_IRQn = 32, /**< 32 SAM4S2A CRC Calculation Unit (CRCCU) */ 93 ACC_IRQn = 33, /**< 33 SAM4S2A Analog Comparator (ACC) */ 94 UDP_IRQn = 34, /**< 34 SAM4S2A USB Device Port (UDP) */ 95 96 PERIPH_COUNT_IRQn = 35 /**< Number of peripheral IDs */ 97 } IRQn_Type; 98 99 typedef struct _DeviceVectors 100 { 101 /* Stack pointer */ 102 void* pvStack; 103 104 /* Cortex-M handlers */ 105 void* pfnReset_Handler; 106 void* pfnNMI_Handler; 107 void* pfnHardFault_Handler; 108 void* pfnMemManage_Handler; 109 void* pfnBusFault_Handler; 110 void* pfnUsageFault_Handler; 111 void* pfnReserved1_Handler; 112 void* pfnReserved2_Handler; 113 void* pfnReserved3_Handler; 114 void* pfnReserved4_Handler; 115 void* pfnSVC_Handler; 116 void* pfnDebugMon_Handler; 117 void* pfnReserved5_Handler; 118 void* pfnPendSV_Handler; 119 void* pfnSysTick_Handler; 120 121 /* Peripheral handlers */ 122 void* pfnSUPC_Handler; /* 0 Supply Controller */ 123 void* pfnRSTC_Handler; /* 1 Reset Controller */ 124 void* pfnRTC_Handler; /* 2 Real Time Clock */ 125 void* pfnRTT_Handler; /* 3 Real Time Timer */ 126 void* pfnWDT_Handler; /* 4 Watchdog Timer */ 127 void* pfnPMC_Handler; /* 5 Power Management Controller */ 128 void* pfnEFC0_Handler; /* 6 Enhanced Embedded Flash Controller 0 */ 129 void* pvReserved7; 130 void* pfnUART0_Handler; /* 8 UART 0 */ 131 void* pfnUART1_Handler; /* 9 UART 1 */ 132 void* pvReserved10; 133 void* pfnPIOA_Handler; /* 11 Parallel I/O Controller A */ 134 void* pfnPIOB_Handler; /* 12 Parallel I/O Controller B */ 135 void* pvReserved13; 136 void* pfnUSART0_Handler; /* 14 USART 0 */ 137 void* pvReserved15; 138 void* pvReserved16; 139 void* pvReserved17; 140 void* pvReserved18; 141 void* pfnTWI0_Handler; /* 19 Two Wire Interface 0 */ 142 void* pfnTWI1_Handler; /* 20 Two Wire Interface 1 */ 143 void* pfnSPI_Handler; /* 21 Serial Peripheral Interface */ 144 void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ 145 void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ 146 void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ 147 void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ 148 void* pvReserved26; 149 void* pvReserved27; 150 void* pvReserved28; 151 void* pfnADC_Handler; /* 29 Analog To Digital Converter */ 152 void* pvReserved30; 153 void* pfnPWM_Handler; /* 31 Pulse Width Modulation */ 154 void* pfnCRCCU_Handler; /* 32 CRC Calculation Unit */ 155 void* pfnACC_Handler; /* 33 Analog Comparator */ 156 void* pfnUDP_Handler; /* 34 USB Device Port */ 157 } DeviceVectors; 158 159 /* Cortex-M4 core handlers */ 160 void Reset_Handler ( void ); 161 void NMI_Handler ( void ); 162 void HardFault_Handler ( void ); 163 void MemManage_Handler ( void ); 164 void BusFault_Handler ( void ); 165 void UsageFault_Handler ( void ); 166 void SVC_Handler ( void ); 167 void DebugMon_Handler ( void ); 168 void PendSV_Handler ( void ); 169 void SysTick_Handler ( void ); 170 171 /* Peripherals handlers */ 172 void ACC_Handler ( void ); 173 void ADC_Handler ( void ); 174 void CRCCU_Handler ( void ); 175 void EFC0_Handler ( void ); 176 void PIOA_Handler ( void ); 177 void PIOB_Handler ( void ); 178 void PMC_Handler ( void ); 179 void PWM_Handler ( void ); 180 void RSTC_Handler ( void ); 181 void RTC_Handler ( void ); 182 void RTT_Handler ( void ); 183 void SPI_Handler ( void ); 184 void SSC_Handler ( void ); 185 void SUPC_Handler ( void ); 186 void TC0_Handler ( void ); 187 void TC1_Handler ( void ); 188 void TC2_Handler ( void ); 189 void TWI0_Handler ( void ); 190 void TWI1_Handler ( void ); 191 void UART0_Handler ( void ); 192 void UART1_Handler ( void ); 193 void UDP_Handler ( void ); 194 void USART0_Handler ( void ); 195 void WDT_Handler ( void ); 196 197 /** 198 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals 199 */ 200 201 #define __CM4_REV 0x0001 /**< SAM4S2A core revision number ([15:8] revision number, [7:0] patch number) */ 202 #define __MPU_PRESENT 1 /**< SAM4S2A does provide a MPU */ 203 #define __FPU_PRESENT 0 /**< SAM4S2A does not provide a FPU */ 204 #define __NVIC_PRIO_BITS 4 /**< SAM4S2A uses 4 Bits for the Priority Levels */ 205 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ 206 207 /* 208 * \brief CMSIS includes 209 */ 210 211 #include <core_cm4.h> 212 #if !defined DONT_USE_CMSIS_INIT 213 #include "system_sam4s.h" 214 #endif /* DONT_USE_CMSIS_INIT */ 215 216 /*@}*/ 217 218 /* ************************************************************************** */ 219 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4S2A */ 220 /* ************************************************************************** */ 221 /** \addtogroup SAM4S2A_api Peripheral Software API */ 222 /*@{*/ 223 224 #include "component/acc.h" 225 #include "component/adc.h" 226 #include "component/chipid.h" 227 #include "component/crccu.h" 228 #include "component/efc.h" 229 #include "component/gpbr.h" 230 #include "component/matrix.h" 231 #include "component/pdc.h" 232 #include "component/pio.h" 233 #include "component/pmc.h" 234 #include "component/pwm.h" 235 #include "component/rstc.h" 236 #include "component/rtc.h" 237 #include "component/rtt.h" 238 #include "component/spi.h" 239 #include "component/ssc.h" 240 #include "component/supc.h" 241 #include "component/tc.h" 242 #include "component/twi.h" 243 #include "component/uart.h" 244 #include "component/udp.h" 245 #include "component/usart.h" 246 #include "component/wdt.h" 247 /*@}*/ 248 249 /* ************************************************************************** */ 250 /* REGISTER ACCESS DEFINITIONS FOR SAM4S2A */ 251 /* ************************************************************************** */ 252 /** \addtogroup SAM4S2A_reg Registers Access Definitions */ 253 /*@{*/ 254 255 #include "instance/ssc.h" 256 #include "instance/spi.h" 257 #include "instance/tc0.h" 258 #include "instance/twi0.h" 259 #include "instance/twi1.h" 260 #include "instance/pwm.h" 261 #include "instance/usart0.h" 262 #include "instance/udp.h" 263 #include "instance/adc.h" 264 #include "instance/acc.h" 265 #include "instance/crccu.h" 266 #include "instance/matrix.h" 267 #include "instance/pmc.h" 268 #include "instance/uart0.h" 269 #include "instance/chipid.h" 270 #include "instance/uart1.h" 271 #include "instance/efc0.h" 272 #include "instance/pioa.h" 273 #include "instance/piob.h" 274 #include "instance/rstc.h" 275 #include "instance/supc.h" 276 #include "instance/rtt.h" 277 #include "instance/wdt.h" 278 #include "instance/rtc.h" 279 #include "instance/gpbr.h" 280 /*@}*/ 281 282 /* ************************************************************************** */ 283 /* PERIPHERAL ID DEFINITIONS FOR SAM4S2A */ 284 /* ************************************************************************** */ 285 /** \addtogroup SAM4S2A_id Peripheral Ids Definitions */ 286 /*@{*/ 287 288 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ 289 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ 290 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ 291 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ 292 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ 293 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ 294 #define ID_EFC0 ( 6) /**< \brief Enhanced Embedded Flash Controller 0 (EFC0) */ 295 #define ID_UART0 ( 8) /**< \brief UART 0 (UART0) */ 296 #define ID_UART1 ( 9) /**< \brief UART 1 (UART1) */ 297 #define ID_PIOA (11) /**< \brief Parallel I/O Controller A (PIOA) */ 298 #define ID_PIOB (12) /**< \brief Parallel I/O Controller B (PIOB) */ 299 #define ID_USART0 (14) /**< \brief USART 0 (USART0) */ 300 #define ID_TWI0 (19) /**< \brief Two Wire Interface 0 (TWI0) */ 301 #define ID_TWI1 (20) /**< \brief Two Wire Interface 1 (TWI1) */ 302 #define ID_SPI (21) /**< \brief Serial Peripheral Interface (SPI) */ 303 #define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ 304 #define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ 305 #define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ 306 #define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ 307 #define ID_ADC (29) /**< \brief Analog To Digital Converter (ADC) */ 308 #define ID_PWM (31) /**< \brief Pulse Width Modulation (PWM) */ 309 #define ID_CRCCU (32) /**< \brief CRC Calculation Unit (CRCCU) */ 310 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ 311 #define ID_UDP (34) /**< \brief USB Device Port (UDP) */ 312 313 #define ID_PERIPH_COUNT (35) /**< \brief Number of peripheral IDs */ 314 /*@}*/ 315 316 /* ************************************************************************** */ 317 /* BASE ADDRESS DEFINITIONS FOR SAM4S2A */ 318 /* ************************************************************************** */ 319 /** \addtogroup SAM4S2A_base Peripheral Base Address Definitions */ 320 /*@{*/ 321 322 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 323 #define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ 324 #define PDC_SSC (0x40004100U) /**< \brief (PDC_SSC ) Base Address */ 325 #define SPI (0x40008000U) /**< \brief (SPI ) Base Address */ 326 #define PDC_SPI (0x40008100U) /**< \brief (PDC_SPI ) Base Address */ 327 #define TC0 (0x40010000U) /**< \brief (TC0 ) Base Address */ 328 #define TWI0 (0x40018000U) /**< \brief (TWI0 ) Base Address */ 329 #define PDC_TWI0 (0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ 330 #define TWI1 (0x4001C000U) /**< \brief (TWI1 ) Base Address */ 331 #define PDC_TWI1 (0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ 332 #define PWM (0x40020000U) /**< \brief (PWM ) Base Address */ 333 #define PDC_PWM (0x40020100U) /**< \brief (PDC_PWM ) Base Address */ 334 #define USART0 (0x40024000U) /**< \brief (USART0 ) Base Address */ 335 #define PDC_USART0 (0x40024100U) /**< \brief (PDC_USART0) Base Address */ 336 #define UDP (0x40034000U) /**< \brief (UDP ) Base Address */ 337 #define ADC (0x40038000U) /**< \brief (ADC ) Base Address */ 338 #define PDC_ADC (0x40038100U) /**< \brief (PDC_ADC ) Base Address */ 339 #define ACC (0x40040000U) /**< \brief (ACC ) Base Address */ 340 #define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ 341 #define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ 342 #define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ 343 #define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ 344 #define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 345 #define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ 346 #define UART1 (0x400E0800U) /**< \brief (UART1 ) Base Address */ 347 #define PDC_UART1 (0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ 348 #define EFC0 (0x400E0A00U) /**< \brief (EFC0 ) Base Address */ 349 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ 350 #define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ 351 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ 352 #define RSTC (0x400E1400U) /**< \brief (RSTC ) Base Address */ 353 #define SUPC (0x400E1410U) /**< \brief (SUPC ) Base Address */ 354 #define RTT (0x400E1430U) /**< \brief (RTT ) Base Address */ 355 #define WDT (0x400E1450U) /**< \brief (WDT ) Base Address */ 356 #define RTC (0x400E1460U) /**< \brief (RTC ) Base Address */ 357 #define GPBR (0x400E1490U) /**< \brief (GPBR ) Base Address */ 358 #else 359 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ 360 #define PDC_SSC ((Pdc *)0x40004100U) /**< \brief (PDC_SSC ) Base Address */ 361 #define SPI ((Spi *)0x40008000U) /**< \brief (SPI ) Base Address */ 362 #define PDC_SPI ((Pdc *)0x40008100U) /**< \brief (PDC_SPI ) Base Address */ 363 #define TC0 ((Tc *)0x40010000U) /**< \brief (TC0 ) Base Address */ 364 #define TWI0 ((Twi *)0x40018000U) /**< \brief (TWI0 ) Base Address */ 365 #define PDC_TWI0 ((Pdc *)0x40018100U) /**< \brief (PDC_TWI0 ) Base Address */ 366 #define TWI1 ((Twi *)0x4001C000U) /**< \brief (TWI1 ) Base Address */ 367 #define PDC_TWI1 ((Pdc *)0x4001C100U) /**< \brief (PDC_TWI1 ) Base Address */ 368 #define PWM ((Pwm *)0x40020000U) /**< \brief (PWM ) Base Address */ 369 #define PDC_PWM ((Pdc *)0x40020100U) /**< \brief (PDC_PWM ) Base Address */ 370 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ 371 #define PDC_USART0 ((Pdc *)0x40024100U) /**< \brief (PDC_USART0) Base Address */ 372 #define UDP ((Udp *)0x40034000U) /**< \brief (UDP ) Base Address */ 373 #define ADC ((Adc *)0x40038000U) /**< \brief (ADC ) Base Address */ 374 #define PDC_ADC ((Pdc *)0x40038100U) /**< \brief (PDC_ADC ) Base Address */ 375 #define ACC ((Acc *)0x40040000U) /**< \brief (ACC ) Base Address */ 376 #define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ 377 #define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ 378 #define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ 379 #define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ 380 #define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 381 #define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ 382 #define UART1 ((Uart *)0x400E0800U) /**< \brief (UART1 ) Base Address */ 383 #define PDC_UART1 ((Pdc *)0x400E0900U) /**< \brief (PDC_UART1 ) Base Address */ 384 #define EFC0 ((Efc *)0x400E0A00U) /**< \brief (EFC0 ) Base Address */ 385 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ 386 #define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ 387 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ 388 #define RSTC ((Rstc *)0x400E1400U) /**< \brief (RSTC ) Base Address */ 389 #define SUPC ((Supc *)0x400E1410U) /**< \brief (SUPC ) Base Address */ 390 #define RTT ((Rtt *)0x400E1430U) /**< \brief (RTT ) Base Address */ 391 #define WDT ((Wdt *)0x400E1450U) /**< \brief (WDT ) Base Address */ 392 #define RTC ((Rtc *)0x400E1460U) /**< \brief (RTC ) Base Address */ 393 #define GPBR ((Gpbr *)0x400E1490U) /**< \brief (GPBR ) Base Address */ 394 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 395 /*@}*/ 396 397 /* ************************************************************************** */ 398 /* PIO DEFINITIONS FOR SAM4S2A */ 399 /* ************************************************************************** */ 400 /** \addtogroup SAM4S2A_pio Peripheral Pio Definitions */ 401 /*@{*/ 402 403 #include "pio/sam4s2a.h" 404 /*@}*/ 405 406 /* ************************************************************************** */ 407 /* MEMORY MAPPING DEFINITIONS FOR SAM4S2A */ 408 /* ************************************************************************** */ 409 410 #define IFLASH0_SIZE (0x20000u) 411 #define IFLASH0_PAGE_SIZE (512u) 412 #define IFLASH0_LOCK_REGION_SIZE (8192u) 413 #define IFLASH0_NB_OF_PAGES (256u) 414 #define IFLASH0_NB_OF_LOCK_BITS (16u) 415 #define IRAM_SIZE (0x10000u) 416 #define IFLASH_SIZE (IFLASH0_SIZE) 417 418 #define IFLASH0_ADDR (0x00400000u) /**< Internal Flash 0 base address */ 419 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ 420 #define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ 421 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ 422 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ 423 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ 424 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ 425 426 /* ************************************************************************** */ 427 /* MISCELLANEOUS DEFINITIONS FOR SAM4S2A */ 428 /* ************************************************************************** */ 429 430 #define CHIP_JTAGID (0x05B3203FUL) 431 #define CHIP_CIDR (0x288B07E0UL) 432 #define CHIP_EXID (0x0UL) 433 #define NB_CH_ADC (7UL) 434 #define NB_CH_DAC (-UL) 435 #define USB_DEVICE_MAX_EP (8UL) 436 437 /* ************************************************************************** */ 438 /* ELECTRICAL DEFINITIONS FOR SAM4S2A */ 439 /* ************************************************************************** */ 440 441 /* Device characteristics */ 442 #define CHIP_FREQ_SLCK_RC_MIN (20000UL) 443 #define CHIP_FREQ_SLCK_RC (32000UL) 444 #define CHIP_FREQ_SLCK_RC_MAX (44000UL) 445 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) 446 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) 447 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) 448 #define CHIP_FREQ_CPU_MAX (120000000UL) 449 #define CHIP_FREQ_XTAL_32K (32768UL) 450 451 /* Embedded Flash Write Wait State */ 452 #define CHIP_FLASH_WRITE_WAIT_STATE (6U) 453 454 #if defined __SAM4S2A__ || defined __SAM4S2B__ || defined __SAM4S2C__ || \ 455 defined __SAM4S4A__ || defined __SAM4S4B__ || defined __SAM4S4C__ 456 457 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V and VDDIO 3.3V) */ 458 #define CHIP_FREQ_FWS_0 (29000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 459 #define CHIP_FREQ_FWS_1 (58000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 460 #define CHIP_FREQ_FWS_2 (88000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 461 #define CHIP_FREQ_FWS_3 (10800000UL) /**< \brief Maximum operating frequency when FWS is 3 */ 462 #define CHIP_FREQ_FWS_4 (120000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ 463 464 #else /* SAM4S8/S16/SA16/SD16/SD32 */ 465 466 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V and VDDIO 3.3V) */ 467 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 468 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 469 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 470 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ 471 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ 472 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ 473 474 #endif 475 476 /* HYSTeresis levels: please refer to Electrical Characteristics */ 477 #define ACC_ACR_HYST_50MV_MAX (0x01UL) 478 #define ACC_ACR_HYST_90MV_MAX (0x11UL) 479 480 481 482 #ifdef __cplusplus 483 } 484 #endif 485 486 /*@}*/ 487 488 #endif /* _SAM4S2A_ */ 489
