1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4S_UART_COMPONENT_ 31 #define _SAM4S_UART_COMPONENT_ 32 33 /* ============================================================================= */ 34 /** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ 35 /* ============================================================================= */ 36 /** \addtogroup SAM4S_UART Universal Asynchronous Receiver Transmitter */ 37 /*@{*/ 38 39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 40 /** \brief Uart hardware registers */ 41 typedef struct { 42 __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ 43 __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ 44 __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ 45 __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ 46 __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ 47 __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ 48 __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ 49 __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ 50 __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ 51 __I uint32_t Reserved1[55]; 52 __IO uint32_t UART_RPR; /**< \brief (Uart Offset: 0x100) Receive Pointer Register */ 53 __IO uint32_t UART_RCR; /**< \brief (Uart Offset: 0x104) Receive Counter Register */ 54 __IO uint32_t UART_TPR; /**< \brief (Uart Offset: 0x108) Transmit Pointer Register */ 55 __IO uint32_t UART_TCR; /**< \brief (Uart Offset: 0x10C) Transmit Counter Register */ 56 __IO uint32_t UART_RNPR; /**< \brief (Uart Offset: 0x110) Receive Next Pointer Register */ 57 __IO uint32_t UART_RNCR; /**< \brief (Uart Offset: 0x114) Receive Next Counter Register */ 58 __IO uint32_t UART_TNPR; /**< \brief (Uart Offset: 0x118) Transmit Next Pointer Register */ 59 __IO uint32_t UART_TNCR; /**< \brief (Uart Offset: 0x11C) Transmit Next Counter Register */ 60 __O uint32_t UART_PTCR; /**< \brief (Uart Offset: 0x120) Transfer Control Register */ 61 __I uint32_t UART_PTSR; /**< \brief (Uart Offset: 0x124) Transfer Status Register */ 62 } Uart; 63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 /* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ 65 #define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ 66 #define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ 67 #define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ 68 #define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ 69 #define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ 70 #define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ 71 #define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ 72 /* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ 73 #define UART_MR_PAR_Pos 9 74 #define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ 75 #define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) 76 #define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ 77 #define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ 78 #define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ 79 #define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ 80 #define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ 81 #define UART_MR_CHMODE_Pos 14 82 #define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ 83 #define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) 84 #define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ 85 #define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ 86 #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ 87 #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ 88 /* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ 89 #define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ 90 #define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ 91 #define UART_IER_ENDRX (0x1u << 3) /**< \brief (UART_IER) Enable End of Receive Transfer Interrupt */ 92 #define UART_IER_ENDTX (0x1u << 4) /**< \brief (UART_IER) Enable End of Transmit Interrupt */ 93 #define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ 94 #define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ 95 #define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ 96 #define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ 97 #define UART_IER_TXBUFE (0x1u << 11) /**< \brief (UART_IER) Enable Buffer Empty Interrupt */ 98 #define UART_IER_RXBUFF (0x1u << 12) /**< \brief (UART_IER) Enable Buffer Full Interrupt */ 99 /* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ 100 #define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ 101 #define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ 102 #define UART_IDR_ENDRX (0x1u << 3) /**< \brief (UART_IDR) Disable End of Receive Transfer Interrupt */ 103 #define UART_IDR_ENDTX (0x1u << 4) /**< \brief (UART_IDR) Disable End of Transmit Interrupt */ 104 #define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ 105 #define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ 106 #define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ 107 #define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ 108 #define UART_IDR_TXBUFE (0x1u << 11) /**< \brief (UART_IDR) Disable Buffer Empty Interrupt */ 109 #define UART_IDR_RXBUFF (0x1u << 12) /**< \brief (UART_IDR) Disable Buffer Full Interrupt */ 110 /* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ 111 #define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ 112 #define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ 113 #define UART_IMR_ENDRX (0x1u << 3) /**< \brief (UART_IMR) Mask End of Receive Transfer Interrupt */ 114 #define UART_IMR_ENDTX (0x1u << 4) /**< \brief (UART_IMR) Mask End of Transmit Interrupt */ 115 #define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ 116 #define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ 117 #define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ 118 #define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ 119 #define UART_IMR_TXBUFE (0x1u << 11) /**< \brief (UART_IMR) Mask TXBUFE Interrupt */ 120 #define UART_IMR_RXBUFF (0x1u << 12) /**< \brief (UART_IMR) Mask RXBUFF Interrupt */ 121 /* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ 122 #define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ 123 #define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ 124 #define UART_SR_ENDRX (0x1u << 3) /**< \brief (UART_SR) End of Receiver Transfer */ 125 #define UART_SR_ENDTX (0x1u << 4) /**< \brief (UART_SR) End of Transmitter Transfer */ 126 #define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ 127 #define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ 128 #define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ 129 #define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ 130 #define UART_SR_TXBUFE (0x1u << 11) /**< \brief (UART_SR) Transmission Buffer Empty */ 131 #define UART_SR_RXBUFF (0x1u << 12) /**< \brief (UART_SR) Receive Buffer Full */ 132 /* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ 133 #define UART_RHR_RXCHR_Pos 0 134 #define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ 135 /* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ 136 #define UART_THR_TXCHR_Pos 0 137 #define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ 138 #define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) 139 /* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ 140 #define UART_BRGR_CD_Pos 0 141 #define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ 142 #define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) 143 /* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */ 144 #define UART_RPR_RXPTR_Pos 0 145 #define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) /**< \brief (UART_RPR) Receive Pointer Register */ 146 #define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos))) 147 /* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */ 148 #define UART_RCR_RXCTR_Pos 0 149 #define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) /**< \brief (UART_RCR) Receive Counter Register */ 150 #define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos))) 151 /* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */ 152 #define UART_TPR_TXPTR_Pos 0 153 #define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) /**< \brief (UART_TPR) Transmit Counter Register */ 154 #define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos))) 155 /* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */ 156 #define UART_TCR_TXCTR_Pos 0 157 #define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) /**< \brief (UART_TCR) Transmit Counter Register */ 158 #define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos))) 159 /* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */ 160 #define UART_RNPR_RXNPTR_Pos 0 161 #define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) /**< \brief (UART_RNPR) Receive Next Pointer */ 162 #define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos))) 163 /* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */ 164 #define UART_RNCR_RXNCTR_Pos 0 165 #define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) /**< \brief (UART_RNCR) Receive Next Counter */ 166 #define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos))) 167 /* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */ 168 #define UART_TNPR_TXNPTR_Pos 0 169 #define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) /**< \brief (UART_TNPR) Transmit Next Pointer */ 170 #define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos))) 171 /* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */ 172 #define UART_TNCR_TXNCTR_Pos 0 173 #define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) /**< \brief (UART_TNCR) Transmit Counter Next */ 174 #define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos))) 175 /* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */ 176 #define UART_PTCR_RXTEN (0x1u << 0) /**< \brief (UART_PTCR) Receiver Transfer Enable */ 177 #define UART_PTCR_RXTDIS (0x1u << 1) /**< \brief (UART_PTCR) Receiver Transfer Disable */ 178 #define UART_PTCR_TXTEN (0x1u << 8) /**< \brief (UART_PTCR) Transmitter Transfer Enable */ 179 #define UART_PTCR_TXTDIS (0x1u << 9) /**< \brief (UART_PTCR) Transmitter Transfer Disable */ 180 /* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */ 181 #define UART_PTSR_RXTEN (0x1u << 0) /**< \brief (UART_PTSR) Receiver Transfer Enable */ 182 #define UART_PTSR_TXTEN (0x1u << 8) /**< \brief (UART_PTSR) Transmitter Transfer Enable */ 183 184 /*@}*/ 185 186 187 #endif /* _SAM4S_UART_COMPONENT_ */ 188
