1 /** 2 * \file 3 * 4 * \brief Instance description for TWIS1 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAM4L_TWIS1_INSTANCE_ 30 #define _SAM4L_TWIS1_INSTANCE_ 31 32 /* ========== Register definition for TWIS1 peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_TWIS1_CR (0x4001C400) /**< \brief (TWIS1) Control Register */ 35 #define REG_TWIS1_NBYTES (0x4001C404) /**< \brief (TWIS1) NBYTES Register */ 36 #define REG_TWIS1_TR (0x4001C408) /**< \brief (TWIS1) Timing Register */ 37 #define REG_TWIS1_RHR (0x4001C40C) /**< \brief (TWIS1) Receive Holding Register */ 38 #define REG_TWIS1_THR (0x4001C410) /**< \brief (TWIS1) Transmit Holding Register */ 39 #define REG_TWIS1_PECR (0x4001C414) /**< \brief (TWIS1) Packet Error Check Register */ 40 #define REG_TWIS1_SR (0x4001C418) /**< \brief (TWIS1) Status Register */ 41 #define REG_TWIS1_IER (0x4001C41C) /**< \brief (TWIS1) Interrupt Enable Register */ 42 #define REG_TWIS1_IDR (0x4001C420) /**< \brief (TWIS1) Interrupt Disable Register */ 43 #define REG_TWIS1_IMR (0x4001C424) /**< \brief (TWIS1) Interrupt Mask Register */ 44 #define REG_TWIS1_SCR (0x4001C428) /**< \brief (TWIS1) Status Clear Register */ 45 #define REG_TWIS1_PR (0x4001C42C) /**< \brief (TWIS1) Parameter Register */ 46 #define REG_TWIS1_VR (0x4001C430) /**< \brief (TWIS1) Version Register */ 47 #define REG_TWIS1_HSTR (0x4001C434) /**< \brief (TWIS1) HS-mode Timing Register */ 48 #define REG_TWIS1_SRR (0x4001C438) /**< \brief (TWIS1) Slew Rate Register */ 49 #define REG_TWIS1_HSSRR (0x4001C43C) /**< \brief (TWIS1) HS-mode Slew Rate Register */ 50 #else 51 #define REG_TWIS1_CR (*(RwReg *)0x4001C400UL) /**< \brief (TWIS1) Control Register */ 52 #define REG_TWIS1_NBYTES (*(RwReg *)0x4001C404UL) /**< \brief (TWIS1) NBYTES Register */ 53 #define REG_TWIS1_TR (*(RwReg *)0x4001C408UL) /**< \brief (TWIS1) Timing Register */ 54 #define REG_TWIS1_RHR (*(RoReg *)0x4001C40CUL) /**< \brief (TWIS1) Receive Holding Register */ 55 #define REG_TWIS1_THR (*(WoReg *)0x4001C410UL) /**< \brief (TWIS1) Transmit Holding Register */ 56 #define REG_TWIS1_PECR (*(RoReg *)0x4001C414UL) /**< \brief (TWIS1) Packet Error Check Register */ 57 #define REG_TWIS1_SR (*(RoReg *)0x4001C418UL) /**< \brief (TWIS1) Status Register */ 58 #define REG_TWIS1_IER (*(WoReg *)0x4001C41CUL) /**< \brief (TWIS1) Interrupt Enable Register */ 59 #define REG_TWIS1_IDR (*(WoReg *)0x4001C420UL) /**< \brief (TWIS1) Interrupt Disable Register */ 60 #define REG_TWIS1_IMR (*(RoReg *)0x4001C424UL) /**< \brief (TWIS1) Interrupt Mask Register */ 61 #define REG_TWIS1_SCR (*(WoReg *)0x4001C428UL) /**< \brief (TWIS1) Status Clear Register */ 62 #define REG_TWIS1_PR (*(RoReg *)0x4001C42CUL) /**< \brief (TWIS1) Parameter Register */ 63 #define REG_TWIS1_VR (*(RoReg *)0x4001C430UL) /**< \brief (TWIS1) Version Register */ 64 #define REG_TWIS1_HSTR (*(RwReg *)0x4001C434UL) /**< \brief (TWIS1) HS-mode Timing Register */ 65 #define REG_TWIS1_SRR (*(RwReg *)0x4001C438UL) /**< \brief (TWIS1) Slew Rate Register */ 66 #define REG_TWIS1_HSSRR (*(RwReg *)0x4001C43CUL) /**< \brief (TWIS1) HS-mode Slew Rate Register */ 67 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 68 69 /* ========== Instance parameters for TWIS1 peripheral ========== */ 70 #define TWIS1_PDCA_ID_RX 10 71 #define TWIS1_PDCA_ID_TX 28 72 73 #endif /* _SAM4L_TWIS1_INSTANCE_ */ 74
