1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM4E8E_ 31 #define _SAM4E8E_ 32 33 /** \addtogroup SAM4E8E_definitions SAM4E8E definitions 34 This file defines all structures and symbols for SAM4E8E: 35 - registers and bitfields 36 - peripheral base address 37 - peripheral ID 38 - PIO definitions 39 */ 40 /*@{*/ 41 42 #ifdef __cplusplus 43 extern "C" { 44 #endif 45 46 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 47 #include <stdint.h> 48 #ifndef __cplusplus 49 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 50 #else 51 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 52 #endif 53 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 54 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 55 #endif 56 57 /* ************************************************************************** */ 58 /* CMSIS DEFINITIONS FOR SAM4E8E */ 59 /* ************************************************************************** */ 60 /** \addtogroup SAM4E8E_cmsis CMSIS Definitions */ 61 /*@{*/ 62 63 /**< Interrupt Number Definition */ 64 typedef enum IRQn 65 { 66 /****** Cortex-M4 Processor Exceptions Numbers ******************************/ 67 NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ 68 MemoryManagement_IRQn = -12, /**< 4 Cortex-M4 Memory Management Interrupt */ 69 BusFault_IRQn = -11, /**< 5 Cortex-M4 Bus Fault Interrupt */ 70 UsageFault_IRQn = -10, /**< 6 Cortex-M4 Usage Fault Interrupt */ 71 SVCall_IRQn = -5, /**< 11 Cortex-M4 SV Call Interrupt */ 72 DebugMonitor_IRQn = -4, /**< 12 Cortex-M4 Debug Monitor Interrupt */ 73 PendSV_IRQn = -2, /**< 14 Cortex-M4 Pend SV Interrupt */ 74 SysTick_IRQn = -1, /**< 15 Cortex-M4 System Tick Interrupt */ 75 /****** SAM4E8E specific Interrupt Numbers *********************************/ 76 77 SUPC_IRQn = 0, /**< 0 SAM4E8E Supply Controller (SUPC) */ 78 RSTC_IRQn = 1, /**< 1 SAM4E8E Reset Controller (RSTC) */ 79 RTC_IRQn = 2, /**< 2 SAM4E8E Real Time Clock (RTC) */ 80 RTT_IRQn = 3, /**< 3 SAM4E8E Real Time Timer (RTT) */ 81 WDT_IRQn = 4, /**< 4 SAM4E8E Watchdog/Dual Watchdog Timer (WDT) */ 82 PMC_IRQn = 5, /**< 5 SAM4E8E Power Management Controller (PMC) */ 83 EFC_IRQn = 6, /**< 6 SAM4E8E Enhanced Embedded Flash Controller (EFC) */ 84 UART0_IRQn = 7, /**< 7 SAM4E8E UART 0 (UART0) */ 85 PIOA_IRQn = 9, /**< 9 SAM4E8E Parallel I/O Controller A (PIOA) */ 86 PIOB_IRQn = 10, /**< 10 SAM4E8E Parallel I/O Controller B (PIOB) */ 87 PIOC_IRQn = 11, /**< 11 SAM4E8E Parallel I/O Controller C (PIOC) */ 88 PIOD_IRQn = 12, /**< 12 SAM4E8E Parallel I/O Controller D (PIOD) */ 89 PIOE_IRQn = 13, /**< 13 SAM4E8E Parallel I/O Controller E (PIOE) */ 90 USART0_IRQn = 14, /**< 14 SAM4E8E USART 0 (USART0) */ 91 USART1_IRQn = 15, /**< 15 SAM4E8E USART 1 (USART1) */ 92 HSMCI_IRQn = 16, /**< 16 SAM4E8E Multimedia Card Interface (HSMCI) */ 93 TWI0_IRQn = 17, /**< 17 SAM4E8E Two Wire Interface 0 (TWI0) */ 94 TWI1_IRQn = 18, /**< 18 SAM4E8E Two Wire Interface 1 (TWI1) */ 95 SPI_IRQn = 19, /**< 19 SAM4E8E Serial Peripheral Interface (SPI) */ 96 DMAC_IRQn = 20, /**< 20 SAM4E8E DMAC (DMAC) */ 97 TC0_IRQn = 21, /**< 21 SAM4E8E Timer/Counter 0 (TC0) */ 98 TC1_IRQn = 22, /**< 22 SAM4E8E Timer/Counter 1 (TC1) */ 99 TC2_IRQn = 23, /**< 23 SAM4E8E Timer/Counter 2 (TC2) */ 100 TC3_IRQn = 24, /**< 24 SAM4E8E Timer/Counter 3 (TC3) */ 101 TC4_IRQn = 25, /**< 25 SAM4E8E Timer/Counter 4 (TC4) */ 102 TC5_IRQn = 26, /**< 26 SAM4E8E Timer/Counter 5 (TC5) */ 103 TC6_IRQn = 27, /**< 27 SAM4E8E Timer/Counter 6 (TC6) */ 104 TC7_IRQn = 28, /**< 28 SAM4E8E Timer/Counter 7 (TC7) */ 105 TC8_IRQn = 29, /**< 29 SAM4E8E Timer/Counter 8 (TC8) */ 106 AFEC0_IRQn = 30, /**< 30 SAM4E8E Analog Front End 0 (AFEC0) */ 107 AFEC1_IRQn = 31, /**< 31 SAM4E8E Analog Front End 1 (AFEC1) */ 108 DACC_IRQn = 32, /**< 32 SAM4E8E Digital To Analog Converter (DACC) */ 109 ACC_IRQn = 33, /**< 33 SAM4E8E Analog Comparator (ACC) */ 110 ARM_IRQn = 34, /**< 34 SAM4E8E FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ 111 UDP_IRQn = 35, /**< 35 SAM4E8E USB DEVICE (UDP) */ 112 PWM_IRQn = 36, /**< 36 SAM4E8E PWM (PWM) */ 113 CAN0_IRQn = 37, /**< 37 SAM4E8E CAN0 (CAN0) */ 114 CAN1_IRQn = 38, /**< 38 SAM4E8E CAN1 (CAN1) */ 115 AES_IRQn = 39, /**< 39 SAM4E8E AES (AES) */ 116 GMAC_IRQn = 44, /**< 44 SAM4E8E EMAC (GMAC) */ 117 UART1_IRQn = 45, /**< 45 SAM4E8E UART (UART1) */ 118 119 PERIPH_COUNT_IRQn = 46 /**< Number of peripheral IDs */ 120 } IRQn_Type; 121 122 typedef struct _DeviceVectors 123 { 124 /* Stack pointer */ 125 void* pvStack; 126 127 /* Cortex-M handlers */ 128 void* pfnReset_Handler; 129 void* pfnNMI_Handler; 130 void* pfnHardFault_Handler; 131 void* pfnMemManage_Handler; 132 void* pfnBusFault_Handler; 133 void* pfnUsageFault_Handler; 134 void* pfnReserved1_Handler; 135 void* pfnReserved2_Handler; 136 void* pfnReserved3_Handler; 137 void* pfnReserved4_Handler; 138 void* pfnSVC_Handler; 139 void* pfnDebugMon_Handler; 140 void* pfnReserved5_Handler; 141 void* pfnPendSV_Handler; 142 void* pfnSysTick_Handler; 143 144 /* Peripheral handlers */ 145 void* pfnSUPC_Handler; /* 0 Supply Controller */ 146 void* pfnRSTC_Handler; /* 1 Reset Controller */ 147 void* pfnRTC_Handler; /* 2 Real Time Clock */ 148 void* pfnRTT_Handler; /* 3 Real Time Timer */ 149 void* pfnWDT_Handler; /* 4 Watchdog/Dual Watchdog Timer */ 150 void* pfnPMC_Handler; /* 5 Power Management Controller */ 151 void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ 152 void* pfnUART0_Handler; /* 7 UART 0 */ 153 void* pvReserved8; 154 void* pfnPIOA_Handler; /* 9 Parallel I/O Controller A */ 155 void* pfnPIOB_Handler; /* 10 Parallel I/O Controller B */ 156 void* pfnPIOC_Handler; /* 11 Parallel I/O Controller C */ 157 void* pfnPIOD_Handler; /* 12 Parallel I/O Controller D */ 158 void* pfnPIOE_Handler; /* 13 Parallel I/O Controller E */ 159 void* pfnUSART0_Handler; /* 14 USART 0 */ 160 void* pfnUSART1_Handler; /* 15 USART 1 */ 161 void* pfnHSMCI_Handler; /* 16 Multimedia Card Interface */ 162 void* pfnTWI0_Handler; /* 17 Two Wire Interface 0 */ 163 void* pfnTWI1_Handler; /* 18 Two Wire Interface 1 */ 164 void* pfnSPI_Handler; /* 19 Serial Peripheral Interface */ 165 void* pfnDMAC_Handler; /* 20 DMAC */ 166 void* pfnTC0_Handler; /* 21 Timer/Counter 0 */ 167 void* pfnTC1_Handler; /* 22 Timer/Counter 1 */ 168 void* pfnTC2_Handler; /* 23 Timer/Counter 2 */ 169 void* pfnTC3_Handler; /* 24 Timer/Counter 3 */ 170 void* pfnTC4_Handler; /* 25 Timer/Counter 4 */ 171 void* pfnTC5_Handler; /* 26 Timer/Counter 5 */ 172 void* pfnTC6_Handler; /* 27 Timer/Counter 6 */ 173 void* pfnTC7_Handler; /* 28 Timer/Counter 7 */ 174 void* pfnTC8_Handler; /* 29 Timer/Counter 8 */ 175 void* pfnAFEC0_Handler; /* 30 Analog Front End 0 */ 176 void* pfnAFEC1_Handler; /* 31 Analog Front End 1 */ 177 void* pfnDACC_Handler; /* 32 Digital To Analog Converter */ 178 void* pfnACC_Handler; /* 33 Analog Comparator */ 179 void* pfnARM_Handler; /* 34 FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC */ 180 void* pfnUDP_Handler; /* 35 USB DEVICE */ 181 void* pfnPWM_Handler; /* 36 PWM */ 182 void* pfnCAN0_Handler; /* 37 CAN0 */ 183 void* pfnCAN1_Handler; /* 38 CAN1 */ 184 void* pfnAES_Handler; /* 39 AES */ 185 void* pvReserved40; 186 void* pvReserved41; 187 void* pvReserved42; 188 void* pvReserved43; 189 void* pfnGMAC_Handler; /* 44 EMAC */ 190 void* pfnUART1_Handler; /* 45 UART */ 191 } DeviceVectors; 192 193 /* Cortex-M4 core handlers */ 194 void Reset_Handler ( void ); 195 void NMI_Handler ( void ); 196 void HardFault_Handler ( void ); 197 void MemManage_Handler ( void ); 198 void BusFault_Handler ( void ); 199 void UsageFault_Handler ( void ); 200 void SVC_Handler ( void ); 201 void DebugMon_Handler ( void ); 202 void PendSV_Handler ( void ); 203 void SysTick_Handler ( void ); 204 205 /* Peripherals handlers */ 206 void ACC_Handler ( void ); 207 void AES_Handler ( void ); 208 void AFEC0_Handler ( void ); 209 void AFEC1_Handler ( void ); 210 void ARM_Handler ( void ); 211 void CAN0_Handler ( void ); 212 void CAN1_Handler ( void ); 213 void DACC_Handler ( void ); 214 void DMAC_Handler ( void ); 215 void EFC_Handler ( void ); 216 void GMAC_Handler ( void ); 217 void HSMCI_Handler ( void ); 218 void PIOA_Handler ( void ); 219 void PIOB_Handler ( void ); 220 void PIOC_Handler ( void ); 221 void PIOD_Handler ( void ); 222 void PIOE_Handler ( void ); 223 void PMC_Handler ( void ); 224 void PWM_Handler ( void ); 225 void RSTC_Handler ( void ); 226 void RTC_Handler ( void ); 227 void RTT_Handler ( void ); 228 void SPI_Handler ( void ); 229 void SUPC_Handler ( void ); 230 void TC0_Handler ( void ); 231 void TC1_Handler ( void ); 232 void TC2_Handler ( void ); 233 void TC3_Handler ( void ); 234 void TC4_Handler ( void ); 235 void TC5_Handler ( void ); 236 void TC6_Handler ( void ); 237 void TC7_Handler ( void ); 238 void TC8_Handler ( void ); 239 void TWI0_Handler ( void ); 240 void TWI1_Handler ( void ); 241 void UART0_Handler ( void ); 242 void UART1_Handler ( void ); 243 void UDP_Handler ( void ); 244 void USART0_Handler ( void ); 245 void USART1_Handler ( void ); 246 void WDT_Handler ( void ); 247 248 /** 249 * \brief Configuration of the Cortex-M4 Processor and Core Peripherals 250 */ 251 252 #define __CM4_REV 0x0000 /**< SAM4E8E core revision number ([15:8] revision number, [7:0] patch number) */ 253 #define __MPU_PRESENT 1 /**< SAM4E8E does provide a MPU */ 254 #define __FPU_PRESENT 1 /**< SAM4E8E does provide a FPU */ 255 #define __NVIC_PRIO_BITS 4 /**< SAM4E8E uses 4 Bits for the Priority Levels */ 256 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ 257 258 /* 259 * \brief CMSIS includes 260 */ 261 262 #include <core_cm4.h> 263 #if !defined DONT_USE_CMSIS_INIT 264 #include "system_sam4e.h" 265 #endif /* DONT_USE_CMSIS_INIT */ 266 267 /*@}*/ 268 269 /* ************************************************************************** */ 270 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAM4E8E */ 271 /* ************************************************************************** */ 272 /** \addtogroup SAM4E8E_api Peripheral Software API */ 273 /*@{*/ 274 275 #include "component/acc.h" 276 #include "component/aes.h" 277 #include "component/afec.h" 278 #include "component/can.h" 279 #include "component/chipid.h" 280 #include "component/cmcc.h" 281 #include "component/crccu.h" 282 #include "component/dacc.h" 283 #include "component/dmac.h" 284 #include "component/efc.h" 285 #include "component/gmac.h" 286 #include "component/gpbr.h" 287 #include "component/hsmci.h" 288 #include "component/matrix.h" 289 #include "component/pdc.h" 290 #include "component/pio.h" 291 #include "component/pmc.h" 292 #include "component/pwm.h" 293 #include "component/rstc.h" 294 #include "component/rtc.h" 295 #include "component/rtt.h" 296 #include "component/smc.h" 297 #include "component/spi.h" 298 #include "component/supc.h" 299 #include "component/tc.h" 300 #include "component/twi.h" 301 #include "component/uart.h" 302 #include "component/udp.h" 303 #include "component/usart.h" 304 #include "component/wdt.h" 305 /*@}*/ 306 307 /* ************************************************************************** */ 308 /* REGISTER ACCESS DEFINITIONS FOR SAM4E8E */ 309 /* ************************************************************************** */ 310 /** \addtogroup SAM4E8E_reg Registers Access Definitions */ 311 /*@{*/ 312 313 #include "instance/pwm.h" 314 #include "instance/aes.h" 315 #include "instance/can0.h" 316 #include "instance/can1.h" 317 #include "instance/gmac.h" 318 #include "instance/crccu.h" 319 #include "instance/smc.h" 320 #include "instance/uart1.h" 321 #include "instance/hsmci.h" 322 #include "instance/udp.h" 323 #include "instance/spi.h" 324 #include "instance/tc0.h" 325 #include "instance/tc1.h" 326 #include "instance/tc2.h" 327 #include "instance/usart0.h" 328 #include "instance/usart1.h" 329 #include "instance/twi0.h" 330 #include "instance/twi1.h" 331 #include "instance/afec0.h" 332 #include "instance/afec1.h" 333 #include "instance/dacc.h" 334 #include "instance/acc.h" 335 #include "instance/dmac.h" 336 #include "instance/cmcc.h" 337 #include "instance/matrix.h" 338 #include "instance/pmc.h" 339 #include "instance/uart0.h" 340 #include "instance/chipid.h" 341 #include "instance/efc.h" 342 #include "instance/pioa.h" 343 #include "instance/piob.h" 344 #include "instance/pioc.h" 345 #include "instance/piod.h" 346 #include "instance/pioe.h" 347 #include "instance/rstc.h" 348 #include "instance/supc.h" 349 #include "instance/rtt.h" 350 #include "instance/wdt.h" 351 #include "instance/rtc.h" 352 #include "instance/gpbr.h" 353 /*@}*/ 354 355 /* ************************************************************************** */ 356 /* PERIPHERAL ID DEFINITIONS FOR SAM4E8E */ 357 /* ************************************************************************** */ 358 /** \addtogroup SAM4E8E_id Peripheral Ids Definitions */ 359 /*@{*/ 360 361 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ 362 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ 363 #define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ 364 #define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ 365 #define ID_WDT ( 4) /**< \brief Watchdog/Dual Watchdog Timer (WDT) */ 366 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ 367 #define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ 368 #define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ 369 #define ID_SMC ( 8) /**< \brief Static Memory Controller (SMC) */ 370 #define ID_PIOA ( 9) /**< \brief Parallel I/O Controller A (PIOA) */ 371 #define ID_PIOB (10) /**< \brief Parallel I/O Controller B (PIOB) */ 372 #define ID_PIOC (11) /**< \brief Parallel I/O Controller C (PIOC) */ 373 #define ID_PIOD (12) /**< \brief Parallel I/O Controller D (PIOD) */ 374 #define ID_PIOE (13) /**< \brief Parallel I/O Controller E (PIOE) */ 375 #define ID_USART0 (14) /**< \brief USART 0 (USART0) */ 376 #define ID_USART1 (15) /**< \brief USART 1 (USART1) */ 377 #define ID_HSMCI (16) /**< \brief Multimedia Card Interface (HSMCI) */ 378 #define ID_TWI0 (17) /**< \brief Two Wire Interface 0 (TWI0) */ 379 #define ID_TWI1 (18) /**< \brief Two Wire Interface 1 (TWI1) */ 380 #define ID_SPI (19) /**< \brief Serial Peripheral Interface (SPI) */ 381 #define ID_DMAC (20) /**< \brief DMAC (DMAC) */ 382 #define ID_TC0 (21) /**< \brief Timer/Counter 0 (TC0) */ 383 #define ID_TC1 (22) /**< \brief Timer/Counter 1 (TC1) */ 384 #define ID_TC2 (23) /**< \brief Timer/Counter 2 (TC2) */ 385 #define ID_TC3 (24) /**< \brief Timer/Counter 3 (TC3) */ 386 #define ID_TC4 (25) /**< \brief Timer/Counter 4 (TC4) */ 387 #define ID_TC5 (26) /**< \brief Timer/Counter 5 (TC5) */ 388 #define ID_TC6 (27) /**< \brief Timer/Counter 6 (TC6) */ 389 #define ID_TC7 (28) /**< \brief Timer/Counter 7 (TC7) */ 390 #define ID_TC8 (29) /**< \brief Timer/Counter 8 (TC8) */ 391 #define ID_AFEC0 (30) /**< \brief Analog Front End 0 (AFEC0) */ 392 #define ID_AFEC1 (31) /**< \brief Analog Front End 1 (AFEC1) */ 393 #define ID_DACC (32) /**< \brief Digital To Analog Converter (DACC) */ 394 #define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ 395 #define ID_ARM (34) /**< \brief FPU signals : FPIXC, FPOFC, FPUFC, FPIOC, FPDZC, FPIDC, FPIXC (ARM) */ 396 #define ID_UDP (35) /**< \brief USB DEVICE (UDP) */ 397 #define ID_PWM (36) /**< \brief PWM (PWM) */ 398 #define ID_CAN0 (37) /**< \brief CAN0 (CAN0) */ 399 #define ID_CAN1 (38) /**< \brief CAN1 (CAN1) */ 400 #define ID_AES (39) /**< \brief AES (AES) */ 401 #define ID_GMAC (44) /**< \brief EMAC (GMAC) */ 402 #define ID_UART1 (45) /**< \brief UART (UART1) */ 403 404 #define ID_PERIPH_COUNT (46) /**< \brief Number of peripheral IDs */ 405 /*@}*/ 406 407 /* ************************************************************************** */ 408 /* BASE ADDRESS DEFINITIONS FOR SAM4E8E */ 409 /* ************************************************************************** */ 410 /** \addtogroup SAM4E8E_base Peripheral Base Address Definitions */ 411 /*@{*/ 412 413 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 414 #define PWM (0x40000000U) /**< \brief (PWM ) Base Address */ 415 #define PDC_PWM (0x40000100U) /**< \brief (PDC_PWM ) Base Address */ 416 #define AES (0x40004000U) /**< \brief (AES ) Base Address */ 417 #define CAN0 (0x40010000U) /**< \brief (CAN0 ) Base Address */ 418 #define CAN1 (0x40014000U) /**< \brief (CAN1 ) Base Address */ 419 #define GMAC (0x40034000U) /**< \brief (GMAC ) Base Address */ 420 #define CRCCU (0x40044000U) /**< \brief (CRCCU ) Base Address */ 421 #define SMC (0x40060000U) /**< \brief (SMC ) Base Address */ 422 #define UART1 (0x40060600U) /**< \brief (UART1 ) Base Address */ 423 #define PDC_UART1 (0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ 424 #define HSMCI (0x40080000U) /**< \brief (HSMCI ) Base Address */ 425 #define PDC_HSMCI (0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ 426 #define UDP (0x40084000U) /**< \brief (UDP ) Base Address */ 427 #define SPI (0x40088000U) /**< \brief (SPI ) Base Address */ 428 #define PDC_SPI (0x40088100U) /**< \brief (PDC_SPI ) Base Address */ 429 #define TC0 (0x40090000U) /**< \brief (TC0 ) Base Address */ 430 #define PDC_TC0 (0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ 431 #define TC1 (0x40094000U) /**< \brief (TC1 ) Base Address */ 432 #define PDC_TC1 (0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ 433 #define TC2 (0x40098000U) /**< \brief (TC2 ) Base Address */ 434 #define USART0 (0x400A0000U) /**< \brief (USART0 ) Base Address */ 435 #define PDC_USART0 (0x400A0100U) /**< \brief (PDC_USART0) Base Address */ 436 #define USART1 (0x400A4000U) /**< \brief (USART1 ) Base Address */ 437 #define PDC_USART1 (0x400A4100U) /**< \brief (PDC_USART1) Base Address */ 438 #define TWI0 (0x400A8000U) /**< \brief (TWI0 ) Base Address */ 439 #define PDC_TWI0 (0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ 440 #define TWI1 (0x400AC000U) /**< \brief (TWI1 ) Base Address */ 441 #define PDC_TWI1 (0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ 442 #define AFEC0 (0x400B0000U) /**< \brief (AFEC0 ) Base Address */ 443 #define PDC_AFEC0 (0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ 444 #define AFEC1 (0x400B4000U) /**< \brief (AFEC1 ) Base Address */ 445 #define PDC_AFEC1 (0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ 446 #define DACC (0x400B8000U) /**< \brief (DACC ) Base Address */ 447 #define PDC_DACC (0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ 448 #define ACC (0x400BC000U) /**< \brief (ACC ) Base Address */ 449 #define DMAC (0x400C0000U) /**< \brief (DMAC ) Base Address */ 450 #define CMCC (0x400C4000U) /**< \brief (CMCC ) Base Address */ 451 #define MATRIX (0x400E0200U) /**< \brief (MATRIX ) Base Address */ 452 #define PMC (0x400E0400U) /**< \brief (PMC ) Base Address */ 453 #define UART0 (0x400E0600U) /**< \brief (UART0 ) Base Address */ 454 #define PDC_UART0 (0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 455 #define CHIPID (0x400E0740U) /**< \brief (CHIPID ) Base Address */ 456 #define EFC (0x400E0A00U) /**< \brief (EFC ) Base Address */ 457 #define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ 458 #define PDC_PIOA (0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ 459 #define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ 460 #define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ 461 #define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ 462 #define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ 463 #define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ 464 #define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ 465 #define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ 466 #define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ 467 #define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ 468 #define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ 469 #else 470 #define PWM ((Pwm *)0x40000000U) /**< \brief (PWM ) Base Address */ 471 #define PDC_PWM ((Pdc *)0x40000100U) /**< \brief (PDC_PWM ) Base Address */ 472 #define AES ((Aes *)0x40004000U) /**< \brief (AES ) Base Address */ 473 #define CAN0 ((Can *)0x40010000U) /**< \brief (CAN0 ) Base Address */ 474 #define CAN1 ((Can *)0x40014000U) /**< \brief (CAN1 ) Base Address */ 475 #define GMAC ((Gmac *)0x40034000U) /**< \brief (GMAC ) Base Address */ 476 #define CRCCU ((Crccu *)0x40044000U) /**< \brief (CRCCU ) Base Address */ 477 #define SMC ((Smc *)0x40060000U) /**< \brief (SMC ) Base Address */ 478 #define UART1 ((Uart *)0x40060600U) /**< \brief (UART1 ) Base Address */ 479 #define PDC_UART1 ((Pdc *)0x40060700U) /**< \brief (PDC_UART1 ) Base Address */ 480 #define HSMCI ((Hsmci *)0x40080000U) /**< \brief (HSMCI ) Base Address */ 481 #define PDC_HSMCI ((Pdc *)0x40080100U) /**< \brief (PDC_HSMCI ) Base Address */ 482 #define UDP ((Udp *)0x40084000U) /**< \brief (UDP ) Base Address */ 483 #define SPI ((Spi *)0x40088000U) /**< \brief (SPI ) Base Address */ 484 #define PDC_SPI ((Pdc *)0x40088100U) /**< \brief (PDC_SPI ) Base Address */ 485 #define TC0 ((Tc *)0x40090000U) /**< \brief (TC0 ) Base Address */ 486 #define PDC_TC0 ((Pdc *)0x40090100U) /**< \brief (PDC_TC0 ) Base Address */ 487 #define TC1 ((Tc *)0x40094000U) /**< \brief (TC1 ) Base Address */ 488 #define PDC_TC1 ((Pdc *)0x40094100U) /**< \brief (PDC_TC1 ) Base Address */ 489 #define TC2 ((Tc *)0x40098000U) /**< \brief (TC2 ) Base Address */ 490 #define USART0 ((Usart *)0x400A0000U) /**< \brief (USART0 ) Base Address */ 491 #define PDC_USART0 ((Pdc *)0x400A0100U) /**< \brief (PDC_USART0) Base Address */ 492 #define USART1 ((Usart *)0x400A4000U) /**< \brief (USART1 ) Base Address */ 493 #define PDC_USART1 ((Pdc *)0x400A4100U) /**< \brief (PDC_USART1) Base Address */ 494 #define TWI0 ((Twi *)0x400A8000U) /**< \brief (TWI0 ) Base Address */ 495 #define PDC_TWI0 ((Pdc *)0x400A8100U) /**< \brief (PDC_TWI0 ) Base Address */ 496 #define TWI1 ((Twi *)0x400AC000U) /**< \brief (TWI1 ) Base Address */ 497 #define PDC_TWI1 ((Pdc *)0x400AC100U) /**< \brief (PDC_TWI1 ) Base Address */ 498 #define AFEC0 ((Afec *)0x400B0000U) /**< \brief (AFEC0 ) Base Address */ 499 #define PDC_AFEC0 ((Pdc *)0x400B0100U) /**< \brief (PDC_AFEC0 ) Base Address */ 500 #define AFEC1 ((Afec *)0x400B4000U) /**< \brief (AFEC1 ) Base Address */ 501 #define PDC_AFEC1 ((Pdc *)0x400B4100U) /**< \brief (PDC_AFEC1 ) Base Address */ 502 #define DACC ((Dacc *)0x400B8000U) /**< \brief (DACC ) Base Address */ 503 #define PDC_DACC ((Pdc *)0x400B8100U) /**< \brief (PDC_DACC ) Base Address */ 504 #define ACC ((Acc *)0x400BC000U) /**< \brief (ACC ) Base Address */ 505 #define DMAC ((Dmac *)0x400C0000U) /**< \brief (DMAC ) Base Address */ 506 #define CMCC ((Cmcc *)0x400C4000U) /**< \brief (CMCC ) Base Address */ 507 #define MATRIX ((Matrix *)0x400E0200U) /**< \brief (MATRIX ) Base Address */ 508 #define PMC ((Pmc *)0x400E0400U) /**< \brief (PMC ) Base Address */ 509 #define UART0 ((Uart *)0x400E0600U) /**< \brief (UART0 ) Base Address */ 510 #define PDC_UART0 ((Pdc *)0x400E0700U) /**< \brief (PDC_UART0 ) Base Address */ 511 #define CHIPID ((Chipid *)0x400E0740U) /**< \brief (CHIPID ) Base Address */ 512 #define EFC ((Efc *)0x400E0A00U) /**< \brief (EFC ) Base Address */ 513 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ 514 #define PDC_PIOA ((Pdc *)0x400E0F68U) /**< \brief (PDC_PIOA ) Base Address */ 515 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ 516 #define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ 517 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ 518 #define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ 519 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ 520 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ 521 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ 522 #define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ 523 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ 524 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ 525 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 526 /*@}*/ 527 528 /* ************************************************************************** */ 529 /* PIO DEFINITIONS FOR SAM4E8E */ 530 /* ************************************************************************** */ 531 /** \addtogroup SAM4E8E_pio Peripheral Pio Definitions */ 532 /*@{*/ 533 534 #include "pio/sam4e8e.h" 535 /*@}*/ 536 537 /* ************************************************************************** */ 538 /* MEMORY MAPPING DEFINITIONS FOR SAM4E8E */ 539 /* ************************************************************************** */ 540 541 #define IFLASH_SIZE (0x80000u) 542 #define IFLASH_PAGE_SIZE (512u) 543 #define IFLASH_LOCK_REGION_SIZE (8192u) 544 #define IFLASH_NB_OF_PAGES (1024u) 545 #define IFLASH_NB_OF_LOCK_BITS (128u) 546 #define IRAM_SIZE (0x20000u) 547 548 #define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ 549 #define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ 550 #define IRAM_ADDR (0x20000000u) /**< Internal RAM base address */ 551 #define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ 552 #define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ 553 #define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ 554 #define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ 555 556 /* ************************************************************************** */ 557 /* MISCELLANEOUS DEFINITIONS FOR SAM4E8E */ 558 /* ************************************************************************** */ 559 560 #define CHIP_JTAGID (0x05B3703FUL) 561 #define CHIP_CIDR (0xA3CC0CE0UL) 562 #define CHIP_EXID (0x00120208UL) 563 564 /* ************************************************************************** */ 565 /* ELECTRICAL DEFINITIONS FOR SAM4E8E */ 566 /* ************************************************************************** */ 567 568 /* Device characteristics */ 569 #define CHIP_FREQ_SLCK_RC_MIN (20000UL) 570 #define CHIP_FREQ_SLCK_RC (32000UL) 571 #define CHIP_FREQ_SLCK_RC_MAX (44000UL) 572 #define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) 573 #define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) 574 #define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) 575 #define CHIP_FREQ_CPU_MAX (120000000UL) 576 #define CHIP_FREQ_XTAL_32K (32768UL) 577 #define CHIP_FREQ_XTAL_12M (12000000UL) 578 579 /* Embedded Flash Write Wait State */ 580 #define CHIP_FLASH_WRITE_WAIT_STATE (6U) 581 582 /* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ 583 #define CHIP_FREQ_FWS_0 (20000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ 584 #define CHIP_FREQ_FWS_1 (40000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ 585 #define CHIP_FREQ_FWS_2 (60000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ 586 #define CHIP_FREQ_FWS_3 (80000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ 587 #define CHIP_FREQ_FWS_4 (100000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ 588 #define CHIP_FREQ_FWS_5 (123000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ 589 590 #ifdef __cplusplus 591 } 592 #endif 593 594 /*@}*/ 595 596 #endif /* _SAM4E8E_ */ 597
