1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_PMC_INSTANCE_ 31 #define _SAM3XA_PMC_INSTANCE_ 32 33 /* ========== Register definition for PMC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ 36 #define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ 37 #define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */ 38 #define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ 39 #define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ 40 #define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ 41 #define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ 42 #define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ 43 #define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ 44 #define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */ 45 #define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */ 46 #define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */ 47 #define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ 48 #define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ 49 #define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ 50 #define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */ 51 #define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ 52 #define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Start-up Mode Register */ 53 #define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Start-up Polarity Register */ 54 #define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ 55 #define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */ 56 #define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */ 57 #define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ 58 #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ 59 #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ 60 #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ 61 #else 62 #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ 63 #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ 64 #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */ 65 #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ 66 #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ 67 #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ 68 #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ 69 #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ 70 #define REG_CKGR_MCFR (*(__I uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ 71 #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */ 72 #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */ 73 #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */ 74 #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ 75 #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ 76 #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ 77 #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */ 78 #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ 79 #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Start-up Mode Register */ 80 #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Start-up Polarity Register */ 81 #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ 82 #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */ 83 #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */ 84 #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ 85 #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ 86 #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ 87 #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ 88 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 89 90 #endif /* _SAM3XA_PMC_INSTANCE_ */ 91
