1 /* ---------------------------------------------------------------------------- */ 2 /* Atmel Microcontroller Software Support */ 3 /* SAM Software Package License */ 4 /* ---------------------------------------------------------------------------- */ 5 /* Copyright (c) %copyright_year%, Atmel Corporation */ 6 /* */ 7 /* All rights reserved. */ 8 /* */ 9 /* Redistribution and use in source and binary forms, with or without */ 10 /* modification, are permitted provided that the following condition is met: */ 11 /* */ 12 /* - Redistributions of source code must retain the above copyright notice, */ 13 /* this list of conditions and the disclaimer below. */ 14 /* */ 15 /* Atmel's name may not be used to endorse or promote products derived from */ 16 /* this software without specific prior written permission. */ 17 /* */ 18 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 19 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 20 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 21 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 22 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 23 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 24 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 25 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 26 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 27 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 28 /* ---------------------------------------------------------------------------- */ 29 30 #ifndef _SAM3XA_EMAC_INSTANCE_ 31 #define _SAM3XA_EMAC_INSTANCE_ 32 33 /* ========== Register definition for EMAC peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_EMAC_NCR (0x400B0000U) /**< \brief (EMAC) Network Control Register */ 36 #define REG_EMAC_NCFGR (0x400B0004U) /**< \brief (EMAC) Network Configuration Register */ 37 #define REG_EMAC_NSR (0x400B0008U) /**< \brief (EMAC) Network Status Register */ 38 #define REG_EMAC_TSR (0x400B0014U) /**< \brief (EMAC) Transmit Status Register */ 39 #define REG_EMAC_RBQP (0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ 40 #define REG_EMAC_TBQP (0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ 41 #define REG_EMAC_RSR (0x400B0020U) /**< \brief (EMAC) Receive Status Register */ 42 #define REG_EMAC_ISR (0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */ 43 #define REG_EMAC_IER (0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */ 44 #define REG_EMAC_IDR (0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */ 45 #define REG_EMAC_IMR (0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */ 46 #define REG_EMAC_MAN (0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */ 47 #define REG_EMAC_PTR (0x400B0038U) /**< \brief (EMAC) Pause Time Register */ 48 #define REG_EMAC_PFR (0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */ 49 #define REG_EMAC_FTO (0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ 50 #define REG_EMAC_SCF (0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */ 51 #define REG_EMAC_MCF (0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */ 52 #define REG_EMAC_FRO (0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */ 53 #define REG_EMAC_FCSE (0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ 54 #define REG_EMAC_ALE (0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */ 55 #define REG_EMAC_DTF (0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ 56 #define REG_EMAC_LCOL (0x400B005CU) /**< \brief (EMAC) Late Collisions Register */ 57 #define REG_EMAC_ECOL (0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */ 58 #define REG_EMAC_TUND (0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ 59 #define REG_EMAC_CSE (0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */ 60 #define REG_EMAC_RRE (0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */ 61 #define REG_EMAC_ROV (0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */ 62 #define REG_EMAC_RSE (0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */ 63 #define REG_EMAC_ELE (0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */ 64 #define REG_EMAC_RJA (0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */ 65 #define REG_EMAC_USF (0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */ 66 #define REG_EMAC_STE (0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */ 67 #define REG_EMAC_RLE (0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ 68 #define REG_EMAC_HRB (0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ 69 #define REG_EMAC_HRT (0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ 70 #define REG_EMAC_SA1B (0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ 71 #define REG_EMAC_SA1T (0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */ 72 #define REG_EMAC_SA2B (0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ 73 #define REG_EMAC_SA2T (0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ 74 #define REG_EMAC_SA3B (0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ 75 #define REG_EMAC_SA3T (0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ 76 #define REG_EMAC_SA4B (0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ 77 #define REG_EMAC_SA4T (0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ 78 #define REG_EMAC_TID (0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */ 79 #define REG_EMAC_USRIO (0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */ 80 #else 81 #define REG_EMAC_NCR (*(__IO uint32_t*)0x400B0000U) /**< \brief (EMAC) Network Control Register */ 82 #define REG_EMAC_NCFGR (*(__IO uint32_t*)0x400B0004U) /**< \brief (EMAC) Network Configuration Register */ 83 #define REG_EMAC_NSR (*(__I uint32_t*)0x400B0008U) /**< \brief (EMAC) Network Status Register */ 84 #define REG_EMAC_TSR (*(__IO uint32_t*)0x400B0014U) /**< \brief (EMAC) Transmit Status Register */ 85 #define REG_EMAC_RBQP (*(__IO uint32_t*)0x400B0018U) /**< \brief (EMAC) Receive Buffer Queue Pointer Register */ 86 #define REG_EMAC_TBQP (*(__IO uint32_t*)0x400B001CU) /**< \brief (EMAC) Transmit Buffer Queue Pointer Register */ 87 #define REG_EMAC_RSR (*(__IO uint32_t*)0x400B0020U) /**< \brief (EMAC) Receive Status Register */ 88 #define REG_EMAC_ISR (*(__IO uint32_t*)0x400B0024U) /**< \brief (EMAC) Interrupt Status Register */ 89 #define REG_EMAC_IER (*(__O uint32_t*)0x400B0028U) /**< \brief (EMAC) Interrupt Enable Register */ 90 #define REG_EMAC_IDR (*(__O uint32_t*)0x400B002CU) /**< \brief (EMAC) Interrupt Disable Register */ 91 #define REG_EMAC_IMR (*(__I uint32_t*)0x400B0030U) /**< \brief (EMAC) Interrupt Mask Register */ 92 #define REG_EMAC_MAN (*(__IO uint32_t*)0x400B0034U) /**< \brief (EMAC) Phy Maintenance Register */ 93 #define REG_EMAC_PTR (*(__IO uint32_t*)0x400B0038U) /**< \brief (EMAC) Pause Time Register */ 94 #define REG_EMAC_PFR (*(__IO uint32_t*)0x400B003CU) /**< \brief (EMAC) Pause Frames Received Register */ 95 #define REG_EMAC_FTO (*(__IO uint32_t*)0x400B0040U) /**< \brief (EMAC) Frames Transmitted Ok Register */ 96 #define REG_EMAC_SCF (*(__IO uint32_t*)0x400B0044U) /**< \brief (EMAC) Single Collision Frames Register */ 97 #define REG_EMAC_MCF (*(__IO uint32_t*)0x400B0048U) /**< \brief (EMAC) Multiple Collision Frames Register */ 98 #define REG_EMAC_FRO (*(__IO uint32_t*)0x400B004CU) /**< \brief (EMAC) Frames Received Ok Register */ 99 #define REG_EMAC_FCSE (*(__IO uint32_t*)0x400B0050U) /**< \brief (EMAC) Frame Check Sequence Errors Register */ 100 #define REG_EMAC_ALE (*(__IO uint32_t*)0x400B0054U) /**< \brief (EMAC) Alignment Errors Register */ 101 #define REG_EMAC_DTF (*(__IO uint32_t*)0x400B0058U) /**< \brief (EMAC) Deferred Transmission Frames Register */ 102 #define REG_EMAC_LCOL (*(__IO uint32_t*)0x400B005CU) /**< \brief (EMAC) Late Collisions Register */ 103 #define REG_EMAC_ECOL (*(__IO uint32_t*)0x400B0060U) /**< \brief (EMAC) Excessive Collisions Register */ 104 #define REG_EMAC_TUND (*(__IO uint32_t*)0x400B0064U) /**< \brief (EMAC) Transmit Underrun Errors Register */ 105 #define REG_EMAC_CSE (*(__IO uint32_t*)0x400B0068U) /**< \brief (EMAC) Carrier Sense Errors Register */ 106 #define REG_EMAC_RRE (*(__IO uint32_t*)0x400B006CU) /**< \brief (EMAC) Receive Resource Errors Register */ 107 #define REG_EMAC_ROV (*(__IO uint32_t*)0x400B0070U) /**< \brief (EMAC) Receive Overrun Errors Register */ 108 #define REG_EMAC_RSE (*(__IO uint32_t*)0x400B0074U) /**< \brief (EMAC) Receive Symbol Errors Register */ 109 #define REG_EMAC_ELE (*(__IO uint32_t*)0x400B0078U) /**< \brief (EMAC) Excessive Length Errors Register */ 110 #define REG_EMAC_RJA (*(__IO uint32_t*)0x400B007CU) /**< \brief (EMAC) Receive Jabbers Register */ 111 #define REG_EMAC_USF (*(__IO uint32_t*)0x400B0080U) /**< \brief (EMAC) Undersize Frames Register */ 112 #define REG_EMAC_STE (*(__IO uint32_t*)0x400B0084U) /**< \brief (EMAC) SQE Test Errors Register */ 113 #define REG_EMAC_RLE (*(__IO uint32_t*)0x400B0088U) /**< \brief (EMAC) Received Length Field Mismatch Register */ 114 #define REG_EMAC_HRB (*(__IO uint32_t*)0x400B0090U) /**< \brief (EMAC) Hash Register Bottom [31:0] Register */ 115 #define REG_EMAC_HRT (*(__IO uint32_t*)0x400B0094U) /**< \brief (EMAC) Hash Register Top [63:32] Register */ 116 #define REG_EMAC_SA1B (*(__IO uint32_t*)0x400B0098U) /**< \brief (EMAC) Specific Address 1 Bottom Register */ 117 #define REG_EMAC_SA1T (*(__IO uint32_t*)0x400B009CU) /**< \brief (EMAC) Specific Address 1 Top Register */ 118 #define REG_EMAC_SA2B (*(__IO uint32_t*)0x400B00A0U) /**< \brief (EMAC) Specific Address 2 Bottom Register */ 119 #define REG_EMAC_SA2T (*(__IO uint32_t*)0x400B00A4U) /**< \brief (EMAC) Specific Address 2 Top Register */ 120 #define REG_EMAC_SA3B (*(__IO uint32_t*)0x400B00A8U) /**< \brief (EMAC) Specific Address 3 Bottom Register */ 121 #define REG_EMAC_SA3T (*(__IO uint32_t*)0x400B00ACU) /**< \brief (EMAC) Specific Address 3 Top Register */ 122 #define REG_EMAC_SA4B (*(__IO uint32_t*)0x400B00B0U) /**< \brief (EMAC) Specific Address 4 Bottom Register */ 123 #define REG_EMAC_SA4T (*(__IO uint32_t*)0x400B00B4U) /**< \brief (EMAC) Specific Address 4 Top Register */ 124 #define REG_EMAC_TID (*(__IO uint32_t*)0x400B00B8U) /**< \brief (EMAC) Type ID Checking Register */ 125 #define REG_EMAC_USRIO (*(__IO uint32_t*)0x400B00C0U) /**< \brief (EMAC) User Input/Output Register */ 126 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 127 128 #endif /* _SAM3XA_EMAC_INSTANCE_ */ 129
