1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* pa0_gpio */ 10 #define PA0_GPIO \ 11 SAM_PINMUX(a, 0, gpio, gpio) 12 13 /* pa0a_pwmc0_pwmh0 */ 14 #define PA0A_PWMC0_PWMH0 \ 15 SAM_PINMUX(a, 0, a, periph) 16 17 /* pa0b_tc0_tioa0 */ 18 #define PA0B_TC0_TIOA0 \ 19 SAM_PINMUX(a, 0, b, periph) 20 21 /* pa0c_ebi_a17_ba1 */ 22 #define PA0C_EBI_A17_BA1 \ 23 SAM_PINMUX(a, 0, c, periph) 24 25 /* pa0d_i2sc0_mck */ 26 #define PA0D_I2SC0_MCK \ 27 SAM_PINMUX(a, 0, d, periph) 28 29 /* pa0x_supc_wkup0 */ 30 #define PA0X_SUPC_WKUP0 \ 31 SAM_PINMUX(a, 0, x, extra) 32 33 /* pa1_gpio */ 34 #define PA1_GPIO \ 35 SAM_PINMUX(a, 1, gpio, gpio) 36 37 /* pa1a_pwmc0_pwml0 */ 38 #define PA1A_PWMC0_PWML0 \ 39 SAM_PINMUX(a, 1, a, periph) 40 41 /* pa1b_tc0_tiob0 */ 42 #define PA1B_TC0_TIOB0 \ 43 SAM_PINMUX(a, 1, b, periph) 44 45 /* pa1c_ebi_a18 */ 46 #define PA1C_EBI_A18 \ 47 SAM_PINMUX(a, 1, c, periph) 48 49 /* pa1d_i2sc0_ck */ 50 #define PA1D_I2SC0_CK \ 51 SAM_PINMUX(a, 1, d, periph) 52 53 /* pa1x_supc_wkup1 */ 54 #define PA1X_SUPC_WKUP1 \ 55 SAM_PINMUX(a, 1, x, extra) 56 57 /* pa2_gpio */ 58 #define PA2_GPIO \ 59 SAM_PINMUX(a, 2, gpio, gpio) 60 61 /* pa2a_pwmc0_pwmh1 */ 62 #define PA2A_PWMC0_PWMH1 \ 63 SAM_PINMUX(a, 2, a, periph) 64 65 /* pa2c_dacc_datrg */ 66 #define PA2C_DACC_DATRG \ 67 SAM_PINMUX(a, 2, c, periph) 68 69 /* pa2x_supc_wkup2 */ 70 #define PA2X_SUPC_WKUP2 \ 71 SAM_PINMUX(a, 2, x, extra) 72 73 /* pa3_gpio */ 74 #define PA3_GPIO \ 75 SAM_PINMUX(a, 3, gpio, gpio) 76 77 /* pa3a_twi0_twd */ 78 #define PA3A_TWI0_TWD \ 79 SAM_PINMUX(a, 3, a, periph) 80 81 /* pa3b_lon_col1 */ 82 #define PA3B_LON_COL1 \ 83 SAM_PINMUX(a, 3, b, periph) 84 85 /* pa3c_pmc_pck2 */ 86 #define PA3C_PMC_PCK2 \ 87 SAM_PINMUX(a, 3, c, periph) 88 89 /* pa3x_pio_piodc0 */ 90 #define PA3X_PIO_PIODC0 \ 91 SAM_PINMUX(a, 3, x, extra) 92 93 /* pa4_gpio */ 94 #define PA4_GPIO \ 95 SAM_PINMUX(a, 4, gpio, gpio) 96 97 /* pa4a_twi0_twck */ 98 #define PA4A_TWI0_TWCK \ 99 SAM_PINMUX(a, 4, a, periph) 100 101 /* pa4b_tc0_tclk0 */ 102 #define PA4B_TC0_TCLK0 \ 103 SAM_PINMUX(a, 4, b, periph) 104 105 /* pa4c_uart1_txd */ 106 #define PA4C_UART1_TXD \ 107 SAM_PINMUX(a, 4, c, periph) 108 109 /* pa4x_pio_piodc1 */ 110 #define PA4X_PIO_PIODC1 \ 111 SAM_PINMUX(a, 4, x, extra) 112 113 /* pa4x_supc_wkup3 */ 114 #define PA4X_SUPC_WKUP3 \ 115 SAM_PINMUX(a, 4, x, extra) 116 117 /* pa5_gpio */ 118 #define PA5_GPIO \ 119 SAM_PINMUX(a, 5, gpio, gpio) 120 121 /* pa5a_pwmc1_pwml3 */ 122 #define PA5A_PWMC1_PWML3 \ 123 SAM_PINMUX(a, 5, a, periph) 124 125 /* pa5b_isi_d4 */ 126 #define PA5B_ISI_D4 \ 127 SAM_PINMUX(a, 5, b, periph) 128 129 /* pa5c_uart1_rxd */ 130 #define PA5C_UART1_RXD \ 131 SAM_PINMUX(a, 5, c, periph) 132 133 /* pa5x_pio_piodc2 */ 134 #define PA5X_PIO_PIODC2 \ 135 SAM_PINMUX(a, 5, x, extra) 136 137 /* pa5x_supc_wkup4 */ 138 #define PA5X_SUPC_WKUP4 \ 139 SAM_PINMUX(a, 5, x, extra) 140 141 /* pa6_gpio */ 142 #define PA6_GPIO \ 143 SAM_PINMUX(a, 6, gpio, gpio) 144 145 /* pa6b_pmc_pck0 */ 146 #define PA6B_PMC_PCK0 \ 147 SAM_PINMUX(a, 6, b, periph) 148 149 /* pa6c_uart1_txd */ 150 #define PA6C_UART1_TXD \ 151 SAM_PINMUX(a, 6, c, periph) 152 153 /* pa7_gpio */ 154 #define PA7_GPIO \ 155 SAM_PINMUX(a, 7, gpio, gpio) 156 157 /* pa7b_pwmc0_pwmh3 */ 158 #define PA7B_PWMC0_PWMH3 \ 159 SAM_PINMUX(a, 7, b, periph) 160 161 /* pa7s_supc_xin32 */ 162 #define PA7S_SUPC_XIN32 \ 163 SAM_PINMUX(a, 7, s, system) 164 165 /* pa8_gpio */ 166 #define PA8_GPIO \ 167 SAM_PINMUX(a, 8, gpio, gpio) 168 169 /* pa8a_pwmc1_pwmh3 */ 170 #define PA8A_PWMC1_PWMH3 \ 171 SAM_PINMUX(a, 8, a, periph) 172 173 /* pa8b_afe0_adtrg */ 174 #define PA8B_AFE0_ADTRG \ 175 SAM_PINMUX(a, 8, b, periph) 176 177 /* pa8s_supc_xout32 */ 178 #define PA8S_SUPC_XOUT32 \ 179 SAM_PINMUX(a, 8, s, system) 180 181 /* pa9_gpio */ 182 #define PA9_GPIO \ 183 SAM_PINMUX(a, 9, gpio, gpio) 184 185 /* pa9a_uart0_rxd */ 186 #define PA9A_UART0_RXD \ 187 SAM_PINMUX(a, 9, a, periph) 188 189 /* pa9b_isi_d3 */ 190 #define PA9B_ISI_D3 \ 191 SAM_PINMUX(a, 9, b, periph) 192 193 /* pa9c_pwmc0_pwmfi0 */ 194 #define PA9C_PWMC0_PWMFI0 \ 195 SAM_PINMUX(a, 9, c, periph) 196 197 /* pa9x_pio_piodc3 */ 198 #define PA9X_PIO_PIODC3 \ 199 SAM_PINMUX(a, 9, x, extra) 200 201 /* pa9x_supc_wkup6 */ 202 #define PA9X_SUPC_WKUP6 \ 203 SAM_PINMUX(a, 9, x, extra) 204 205 /* pa10_gpio */ 206 #define PA10_GPIO \ 207 SAM_PINMUX(a, 10, gpio, gpio) 208 209 /* pa10a_uart0_txd */ 210 #define PA10A_UART0_TXD \ 211 SAM_PINMUX(a, 10, a, periph) 212 213 /* pa10b_pwmc0_pwmextrg0 */ 214 #define PA10B_PWMC0_PWMEXTRG0 \ 215 SAM_PINMUX(a, 10, b, periph) 216 217 /* pa10c_ssc_rd */ 218 #define PA10C_SSC_RD \ 219 SAM_PINMUX(a, 10, c, periph) 220 221 /* pa10x_pio_piodc4 */ 222 #define PA10X_PIO_PIODC4 \ 223 SAM_PINMUX(a, 10, x, extra) 224 225 /* pa11_gpio */ 226 #define PA11_GPIO \ 227 SAM_PINMUX(a, 11, gpio, gpio) 228 229 /* pa11a_qspi_qcs */ 230 #define PA11A_QSPI_QCS \ 231 SAM_PINMUX(a, 11, a, periph) 232 233 /* pa11b_pwmc0_pwmh0 */ 234 #define PA11B_PWMC0_PWMH0 \ 235 SAM_PINMUX(a, 11, b, periph) 236 237 /* pa11c_pwmc1_pwml0 */ 238 #define PA11C_PWMC1_PWML0 \ 239 SAM_PINMUX(a, 11, c, periph) 240 241 /* pa11x_pio_piodc5 */ 242 #define PA11X_PIO_PIODC5 \ 243 SAM_PINMUX(a, 11, x, extra) 244 245 /* pa11x_supc_wkup7 */ 246 #define PA11X_SUPC_WKUP7 \ 247 SAM_PINMUX(a, 11, x, extra) 248 249 /* pa12_gpio */ 250 #define PA12_GPIO \ 251 SAM_PINMUX(a, 12, gpio, gpio) 252 253 /* pa12a_qspi_qio1 */ 254 #define PA12A_QSPI_QIO1 \ 255 SAM_PINMUX(a, 12, a, periph) 256 257 /* pa12b_pwmc0_pwmh1 */ 258 #define PA12B_PWMC0_PWMH1 \ 259 SAM_PINMUX(a, 12, b, periph) 260 261 /* pa12c_pwmc1_pwmh0 */ 262 #define PA12C_PWMC1_PWMH0 \ 263 SAM_PINMUX(a, 12, c, periph) 264 265 /* pa12x_pio_piodc6 */ 266 #define PA12X_PIO_PIODC6 \ 267 SAM_PINMUX(a, 12, x, extra) 268 269 /* pa13_gpio */ 270 #define PA13_GPIO \ 271 SAM_PINMUX(a, 13, gpio, gpio) 272 273 /* pa13a_qspi_qio0 */ 274 #define PA13A_QSPI_QIO0 \ 275 SAM_PINMUX(a, 13, a, periph) 276 277 /* pa13b_pwmc0_pwmh2 */ 278 #define PA13B_PWMC0_PWMH2 \ 279 SAM_PINMUX(a, 13, b, periph) 280 281 /* pa13c_pwmc1_pwml1 */ 282 #define PA13C_PWMC1_PWML1 \ 283 SAM_PINMUX(a, 13, c, periph) 284 285 /* pa13x_pio_piodc7 */ 286 #define PA13X_PIO_PIODC7 \ 287 SAM_PINMUX(a, 13, x, extra) 288 289 /* pa14_gpio */ 290 #define PA14_GPIO \ 291 SAM_PINMUX(a, 14, gpio, gpio) 292 293 /* pa14a_qspi_qsck */ 294 #define PA14A_QSPI_QSCK \ 295 SAM_PINMUX(a, 14, a, periph) 296 297 /* pa14b_pwmc0_pwmh3 */ 298 #define PA14B_PWMC0_PWMH3 \ 299 SAM_PINMUX(a, 14, b, periph) 300 301 /* pa14c_pwmc1_pwmh1 */ 302 #define PA14C_PWMC1_PWMH1 \ 303 SAM_PINMUX(a, 14, c, periph) 304 305 /* pa14x_pio_pioden1 */ 306 #define PA14X_PIO_PIODEN1 \ 307 SAM_PINMUX(a, 14, x, extra) 308 309 /* pa14x_supc_wkup8 */ 310 #define PA14X_SUPC_WKUP8 \ 311 SAM_PINMUX(a, 14, x, extra) 312 313 /* pa15_gpio */ 314 #define PA15_GPIO \ 315 SAM_PINMUX(a, 15, gpio, gpio) 316 317 /* pa15a_ebi_d14 */ 318 #define PA15A_EBI_D14 \ 319 SAM_PINMUX(a, 15, a, periph) 320 321 /* pa15b_tc0_tioa1 */ 322 #define PA15B_TC0_TIOA1 \ 323 SAM_PINMUX(a, 15, b, periph) 324 325 /* pa15c_pwmc0_pwml3 */ 326 #define PA15C_PWMC0_PWML3 \ 327 SAM_PINMUX(a, 15, c, periph) 328 329 /* pa15d_i2sc0_ws */ 330 #define PA15D_I2SC0_WS \ 331 SAM_PINMUX(a, 15, d, periph) 332 333 /* pa16_gpio */ 334 #define PA16_GPIO \ 335 SAM_PINMUX(a, 16, gpio, gpio) 336 337 /* pa16a_ebi_d15 */ 338 #define PA16A_EBI_D15 \ 339 SAM_PINMUX(a, 16, a, periph) 340 341 /* pa16b_tc0_tiob1 */ 342 #define PA16B_TC0_TIOB1 \ 343 SAM_PINMUX(a, 16, b, periph) 344 345 /* pa16c_pwmc0_pwml2 */ 346 #define PA16C_PWMC0_PWML2 \ 347 SAM_PINMUX(a, 16, c, periph) 348 349 /* pa16d_i2sc0_di */ 350 #define PA16D_I2SC0_DI \ 351 SAM_PINMUX(a, 16, d, periph) 352 353 /* pa17_gpio */ 354 #define PA17_GPIO \ 355 SAM_PINMUX(a, 17, gpio, gpio) 356 357 /* pa17a_qspi_qio2 */ 358 #define PA17A_QSPI_QIO2 \ 359 SAM_PINMUX(a, 17, a, periph) 360 361 /* pa17b_pmc_pck1 */ 362 #define PA17B_PMC_PCK1 \ 363 SAM_PINMUX(a, 17, b, periph) 364 365 /* pa17c_pwmc0_pwmh3 */ 366 #define PA17C_PWMC0_PWMH3 \ 367 SAM_PINMUX(a, 17, c, periph) 368 369 /* pa17x_afe0_ad6 */ 370 #define PA17X_AFE0_AD6 \ 371 SAM_PINMUX(a, 17, x, extra) 372 373 /* pa18_gpio */ 374 #define PA18_GPIO \ 375 SAM_PINMUX(a, 18, gpio, gpio) 376 377 /* pa18a_pwmc1_pwmextrg1 */ 378 #define PA18A_PWMC1_PWMEXTRG1 \ 379 SAM_PINMUX(a, 18, a, periph) 380 381 /* pa18b_pmc_pck2 */ 382 #define PA18B_PMC_PCK2 \ 383 SAM_PINMUX(a, 18, b, periph) 384 385 /* pa18c_ebi_a14 */ 386 #define PA18C_EBI_A14 \ 387 SAM_PINMUX(a, 18, c, periph) 388 389 /* pa18x_afe0_ad7 */ 390 #define PA18X_AFE0_AD7 \ 391 SAM_PINMUX(a, 18, x, extra) 392 393 /* pa19_gpio */ 394 #define PA19_GPIO \ 395 SAM_PINMUX(a, 19, gpio, gpio) 396 397 /* pa19b_pwmc0_pwml0 */ 398 #define PA19B_PWMC0_PWML0 \ 399 SAM_PINMUX(a, 19, b, periph) 400 401 /* pa19c_ebi_a15 */ 402 #define PA19C_EBI_A15 \ 403 SAM_PINMUX(a, 19, c, periph) 404 405 /* pa19d_i2sc1_mck */ 406 #define PA19D_I2SC1_MCK \ 407 SAM_PINMUX(a, 19, d, periph) 408 409 /* pa19x_afe0_ad8 */ 410 #define PA19X_AFE0_AD8 \ 411 SAM_PINMUX(a, 19, x, extra) 412 413 /* pa19x_supc_wkup9 */ 414 #define PA19X_SUPC_WKUP9 \ 415 SAM_PINMUX(a, 19, x, extra) 416 417 /* pa20_gpio */ 418 #define PA20_GPIO \ 419 SAM_PINMUX(a, 20, gpio, gpio) 420 421 /* pa20b_pwmc0_pwml1 */ 422 #define PA20B_PWMC0_PWML1 \ 423 SAM_PINMUX(a, 20, b, periph) 424 425 /* pa20c_ebi_a16_ba0 */ 426 #define PA20C_EBI_A16_BA0 \ 427 SAM_PINMUX(a, 20, c, periph) 428 429 /* pa20d_i2sc1_ck */ 430 #define PA20D_I2SC1_CK \ 431 SAM_PINMUX(a, 20, d, periph) 432 433 /* pa20x_afe0_ad9 */ 434 #define PA20X_AFE0_AD9 \ 435 SAM_PINMUX(a, 20, x, extra) 436 437 /* pa20x_supc_wkup10 */ 438 #define PA20X_SUPC_WKUP10 \ 439 SAM_PINMUX(a, 20, x, extra) 440 441 /* pa21_gpio */ 442 #define PA21_GPIO \ 443 SAM_PINMUX(a, 21, gpio, gpio) 444 445 /* pa21a_usart1_rxd */ 446 #define PA21A_USART1_RXD \ 447 SAM_PINMUX(a, 21, a, periph) 448 449 /* pa21b_pmc_pck1 */ 450 #define PA21B_PMC_PCK1 \ 451 SAM_PINMUX(a, 21, b, periph) 452 453 /* pa21c_pwmc1_pwmfi0 */ 454 #define PA21C_PWMC1_PWMFI0 \ 455 SAM_PINMUX(a, 21, c, periph) 456 457 /* pa21x_afe1_ad1 */ 458 #define PA21X_AFE1_AD1 \ 459 SAM_PINMUX(a, 21, x, extra) 460 461 /* pa21x_pio_piodcen2 */ 462 #define PA21X_PIO_PIODCEN2 \ 463 SAM_PINMUX(a, 21, x, extra) 464 465 /* pa22_gpio */ 466 #define PA22_GPIO \ 467 SAM_PINMUX(a, 22, gpio, gpio) 468 469 /* pa22a_ssc_rk */ 470 #define PA22A_SSC_RK \ 471 SAM_PINMUX(a, 22, a, periph) 472 473 /* pa22b_pwmc0_pwmextrg1 */ 474 #define PA22B_PWMC0_PWMEXTRG1 \ 475 SAM_PINMUX(a, 22, b, periph) 476 477 /* pa22c_ebi_ncs2 */ 478 #define PA22C_EBI_NCS2 \ 479 SAM_PINMUX(a, 22, c, periph) 480 481 /* pa22x_pio_piodcclk */ 482 #define PA22X_PIO_PIODCCLK \ 483 SAM_PINMUX(a, 22, x, extra) 484 485 /* pa23_gpio */ 486 #define PA23_GPIO \ 487 SAM_PINMUX(a, 23, gpio, gpio) 488 489 /* pa23a_usart1_sck */ 490 #define PA23A_USART1_SCK \ 491 SAM_PINMUX(a, 23, a, periph) 492 493 /* pa23b_pwmc0_pwmh0 */ 494 #define PA23B_PWMC0_PWMH0 \ 495 SAM_PINMUX(a, 23, b, periph) 496 497 /* pa23c_ebi_a19 */ 498 #define PA23C_EBI_A19 \ 499 SAM_PINMUX(a, 23, c, periph) 500 501 /* pa23d_pwmc1_pwml2 */ 502 #define PA23D_PWMC1_PWML2 \ 503 SAM_PINMUX(a, 23, d, periph) 504 505 /* pa24_gpio */ 506 #define PA24_GPIO \ 507 SAM_PINMUX(a, 24, gpio, gpio) 508 509 /* pa24a_usart1_rts */ 510 #define PA24A_USART1_RTS \ 511 SAM_PINMUX(a, 24, a, periph) 512 513 /* pa24b_pwmc0_pwmh1 */ 514 #define PA24B_PWMC0_PWMH1 \ 515 SAM_PINMUX(a, 24, b, periph) 516 517 /* pa24c_ebi_a20 */ 518 #define PA24C_EBI_A20 \ 519 SAM_PINMUX(a, 24, c, periph) 520 521 /* pa24d_isi_pck */ 522 #define PA24D_ISI_PCK \ 523 SAM_PINMUX(a, 24, d, periph) 524 525 /* pa25_gpio */ 526 #define PA25_GPIO \ 527 SAM_PINMUX(a, 25, gpio, gpio) 528 529 /* pa25a_usart1_cts */ 530 #define PA25A_USART1_CTS \ 531 SAM_PINMUX(a, 25, a, periph) 532 533 /* pa25b_pwmc0_pwmh2 */ 534 #define PA25B_PWMC0_PWMH2 \ 535 SAM_PINMUX(a, 25, b, periph) 536 537 /* pa25c_ebi_a23 */ 538 #define PA25C_EBI_A23 \ 539 SAM_PINMUX(a, 25, c, periph) 540 541 /* pa25d_hsmci_mcck */ 542 #define PA25D_HSMCI_MCCK \ 543 SAM_PINMUX(a, 25, d, periph) 544 545 /* pa26_gpio */ 546 #define PA26_GPIO \ 547 SAM_PINMUX(a, 26, gpio, gpio) 548 549 /* pa26a_usart1_dcd */ 550 #define PA26A_USART1_DCD \ 551 SAM_PINMUX(a, 26, a, periph) 552 553 /* pa26b_tc0_tioa2 */ 554 #define PA26B_TC0_TIOA2 \ 555 SAM_PINMUX(a, 26, b, periph) 556 557 /* pa26c_hsmci_mcda2 */ 558 #define PA26C_HSMCI_MCDA2 \ 559 SAM_PINMUX(a, 26, c, periph) 560 561 /* pa26d_pwmc1_pwmfi1 */ 562 #define PA26D_PWMC1_PWMFI1 \ 563 SAM_PINMUX(a, 26, d, periph) 564 565 /* pa27_gpio */ 566 #define PA27_GPIO \ 567 SAM_PINMUX(a, 27, gpio, gpio) 568 569 /* pa27a_usart1_dtr */ 570 #define PA27A_USART1_DTR \ 571 SAM_PINMUX(a, 27, a, periph) 572 573 /* pa27b_tc0_tiob2 */ 574 #define PA27B_TC0_TIOB2 \ 575 SAM_PINMUX(a, 27, b, periph) 576 577 /* pa27c_hsmci_mcda3 */ 578 #define PA27C_HSMCI_MCDA3 \ 579 SAM_PINMUX(a, 27, c, periph) 580 581 /* pa27d_isi_d7 */ 582 #define PA27D_ISI_D7 \ 583 SAM_PINMUX(a, 27, d, periph) 584 585 /* pa28_gpio */ 586 #define PA28_GPIO \ 587 SAM_PINMUX(a, 28, gpio, gpio) 588 589 /* pa28a_usart1_dsr */ 590 #define PA28A_USART1_DSR \ 591 SAM_PINMUX(a, 28, a, periph) 592 593 /* pa28b_tc0_tclk1 */ 594 #define PA28B_TC0_TCLK1 \ 595 SAM_PINMUX(a, 28, b, periph) 596 597 /* pa28c_hsmci_mccda */ 598 #define PA28C_HSMCI_MCCDA \ 599 SAM_PINMUX(a, 28, c, periph) 600 601 /* pa28d_pwmc1_pwmfi2 */ 602 #define PA28D_PWMC1_PWMFI2 \ 603 SAM_PINMUX(a, 28, d, periph) 604 605 /* pa29_gpio */ 606 #define PA29_GPIO \ 607 SAM_PINMUX(a, 29, gpio, gpio) 608 609 /* pa29a_usart1_ri */ 610 #define PA29A_USART1_RI \ 611 SAM_PINMUX(a, 29, a, periph) 612 613 /* pa29b_tc0_tclk2 */ 614 #define PA29B_TC0_TCLK2 \ 615 SAM_PINMUX(a, 29, b, periph) 616 617 /* pa30_gpio */ 618 #define PA30_GPIO \ 619 SAM_PINMUX(a, 30, gpio, gpio) 620 621 /* pa30a_pwmc0_pwml2 */ 622 #define PA30A_PWMC0_PWML2 \ 623 SAM_PINMUX(a, 30, a, periph) 624 625 /* pa30b_pwmc1_pwmextrg0 */ 626 #define PA30B_PWMC1_PWMEXTRG0 \ 627 SAM_PINMUX(a, 30, b, periph) 628 629 /* pa30c_hsmci_mcda0 */ 630 #define PA30C_HSMCI_MCDA0 \ 631 SAM_PINMUX(a, 30, c, periph) 632 633 /* pa30d_i2sc0_do */ 634 #define PA30D_I2SC0_DO \ 635 SAM_PINMUX(a, 30, d, periph) 636 637 /* pa30x_supc_wkup11 */ 638 #define PA30X_SUPC_WKUP11 \ 639 SAM_PINMUX(a, 30, x, extra) 640 641 /* pa31_gpio */ 642 #define PA31_GPIO \ 643 SAM_PINMUX(a, 31, gpio, gpio) 644 645 /* pa31a_spi0_npcs1 */ 646 #define PA31A_SPI0_NPCS1 \ 647 SAM_PINMUX(a, 31, a, periph) 648 649 /* pa31b_pmc_pck2 */ 650 #define PA31B_PMC_PCK2 \ 651 SAM_PINMUX(a, 31, b, periph) 652 653 /* pa31c_hsmci_mcda1 */ 654 #define PA31C_HSMCI_MCDA1 \ 655 SAM_PINMUX(a, 31, c, periph) 656 657 /* pa31d_pwmc1_pwmh2 */ 658 #define PA31D_PWMC1_PWMH2 \ 659 SAM_PINMUX(a, 31, d, periph) 660 661 /* pb0_gpio */ 662 #define PB0_GPIO \ 663 SAM_PINMUX(b, 0, gpio, gpio) 664 665 /* pb0a_pwmc0_pwmh0 */ 666 #define PB0A_PWMC0_PWMH0 \ 667 SAM_PINMUX(b, 0, a, periph) 668 669 /* pb0c_usart0_rxd */ 670 #define PB0C_USART0_RXD \ 671 SAM_PINMUX(b, 0, c, periph) 672 673 /* pb0d_ssc_tf */ 674 #define PB0D_SSC_TF \ 675 SAM_PINMUX(b, 0, d, periph) 676 677 /* pb0x_afe0_ad10 */ 678 #define PB0X_AFE0_AD10 \ 679 SAM_PINMUX(b, 0, x, extra) 680 681 /* pb0x_rtc_out0 */ 682 #define PB0X_RTC_OUT0 \ 683 SAM_PINMUX(b, 0, x, extra) 684 685 /* pb1_gpio */ 686 #define PB1_GPIO \ 687 SAM_PINMUX(b, 1, gpio, gpio) 688 689 /* pb1a_pwmc0_pwmh1 */ 690 #define PB1A_PWMC0_PWMH1 \ 691 SAM_PINMUX(b, 1, a, periph) 692 693 /* pb1b_gmac_gtsucomp */ 694 #define PB1B_GMAC_GTSUCOMP \ 695 SAM_PINMUX(b, 1, b, periph) 696 697 /* pb1c_usart0_txd */ 698 #define PB1C_USART0_TXD \ 699 SAM_PINMUX(b, 1, c, periph) 700 701 /* pb1d_ssc_tk */ 702 #define PB1D_SSC_TK \ 703 SAM_PINMUX(b, 1, d, periph) 704 705 /* pb1x_afe1_ad0 */ 706 #define PB1X_AFE1_AD0 \ 707 SAM_PINMUX(b, 1, x, extra) 708 709 /* pb1x_rtc_out1 */ 710 #define PB1X_RTC_OUT1 \ 711 SAM_PINMUX(b, 1, x, extra) 712 713 /* pb2_gpio */ 714 #define PB2_GPIO \ 715 SAM_PINMUX(b, 2, gpio, gpio) 716 717 /* pb2a_can0_tx */ 718 #define PB2A_CAN0_TX \ 719 SAM_PINMUX(b, 2, a, periph) 720 721 /* pb2c_usart0_cts */ 722 #define PB2C_USART0_CTS \ 723 SAM_PINMUX(b, 2, c, periph) 724 725 /* pb2d_spi0_npcs0 */ 726 #define PB2D_SPI0_NPCS0 \ 727 SAM_PINMUX(b, 2, d, periph) 728 729 /* pb2x_afe0_ad5 */ 730 #define PB2X_AFE0_AD5 \ 731 SAM_PINMUX(b, 2, x, extra) 732 733 /* pb3_gpio */ 734 #define PB3_GPIO \ 735 SAM_PINMUX(b, 3, gpio, gpio) 736 737 /* pb3a_can0_rx */ 738 #define PB3A_CAN0_RX \ 739 SAM_PINMUX(b, 3, a, periph) 740 741 /* pb3b_pmc_pck2 */ 742 #define PB3B_PMC_PCK2 \ 743 SAM_PINMUX(b, 3, b, periph) 744 745 /* pb3c_usart0_rts */ 746 #define PB3C_USART0_RTS \ 747 SAM_PINMUX(b, 3, c, periph) 748 749 /* pb3d_isi_d2 */ 750 #define PB3D_ISI_D2 \ 751 SAM_PINMUX(b, 3, d, periph) 752 753 /* pb3x_afe0_ad2 */ 754 #define PB3X_AFE0_AD2 \ 755 SAM_PINMUX(b, 3, x, extra) 756 757 /* pb3x_supc_wkup12 */ 758 #define PB3X_SUPC_WKUP12 \ 759 SAM_PINMUX(b, 3, x, extra) 760 761 /* pb4_gpio */ 762 #define PB4_GPIO \ 763 SAM_PINMUX(b, 4, gpio, gpio) 764 765 /* pb4a_twi1_twd */ 766 #define PB4A_TWI1_TWD \ 767 SAM_PINMUX(b, 4, a, periph) 768 769 /* pb4b_pwmc0_pwmh2 */ 770 #define PB4B_PWMC0_PWMH2 \ 771 SAM_PINMUX(b, 4, b, periph) 772 773 /* pb4c_mlb_clk */ 774 #define PB4C_MLB_CLK \ 775 SAM_PINMUX(b, 4, c, periph) 776 777 /* pb4d_usart1_txd */ 778 #define PB4D_USART1_TXD \ 779 SAM_PINMUX(b, 4, d, periph) 780 781 /* pb4s_jtag_tdi */ 782 #define PB4S_JTAG_TDI \ 783 SAM_PINMUX(b, 4, s, system) 784 785 /* pb5_gpio */ 786 #define PB5_GPIO \ 787 SAM_PINMUX(b, 5, gpio, gpio) 788 789 /* pb5a_twi1_twck */ 790 #define PB5A_TWI1_TWCK \ 791 SAM_PINMUX(b, 5, a, periph) 792 793 /* pb5b_pwmc0_pwml0 */ 794 #define PB5B_PWMC0_PWML0 \ 795 SAM_PINMUX(b, 5, b, periph) 796 797 /* pb5c_mlb_dat */ 798 #define PB5C_MLB_DAT \ 799 SAM_PINMUX(b, 5, c, periph) 800 801 /* pb5d_ssc_td */ 802 #define PB5D_SSC_TD \ 803 SAM_PINMUX(b, 5, d, periph) 804 805 /* pb5x_supc_wkup13 */ 806 #define PB5X_SUPC_WKUP13 \ 807 SAM_PINMUX(b, 5, x, extra) 808 809 /* pb5s_jtag_tdo */ 810 #define PB5S_JTAG_TDO \ 811 SAM_PINMUX(b, 5, s, system) 812 813 /* pb5s_swd_traceswo */ 814 #define PB5S_SWD_TRACESWO \ 815 SAM_PINMUX(b, 5, s, system) 816 817 /* pb6_gpio */ 818 #define PB6_GPIO \ 819 SAM_PINMUX(b, 6, gpio, gpio) 820 821 /* pb6s_jtag_tms */ 822 #define PB6S_JTAG_TMS \ 823 SAM_PINMUX(b, 6, s, system) 824 825 /* pb6s_swd_swdio */ 826 #define PB6S_SWD_SWDIO \ 827 SAM_PINMUX(b, 6, s, system) 828 829 /* pb7_gpio */ 830 #define PB7_GPIO \ 831 SAM_PINMUX(b, 7, gpio, gpio) 832 833 /* pb7s_jtag_tck */ 834 #define PB7S_JTAG_TCK \ 835 SAM_PINMUX(b, 7, s, system) 836 837 /* pb7s_swd_swclk */ 838 #define PB7S_SWD_SWCLK \ 839 SAM_PINMUX(b, 7, s, system) 840 841 /* pb8_gpio */ 842 #define PB8_GPIO \ 843 SAM_PINMUX(b, 8, gpio, gpio) 844 845 /* pb8s_supc_xout */ 846 #define PB8S_SUPC_XOUT \ 847 SAM_PINMUX(b, 8, s, system) 848 849 /* pb9_gpio */ 850 #define PB9_GPIO \ 851 SAM_PINMUX(b, 9, gpio, gpio) 852 853 /* pb9s_supc_xin */ 854 #define PB9S_SUPC_XIN \ 855 SAM_PINMUX(b, 9, s, system) 856 857 /* pb12_gpio */ 858 #define PB12_GPIO \ 859 SAM_PINMUX(b, 12, gpio, gpio) 860 861 /* pb12a_pwmc0_pwml1 */ 862 #define PB12A_PWMC0_PWML1 \ 863 SAM_PINMUX(b, 12, a, periph) 864 865 /* pb12b_gmac_gtsucomp */ 866 #define PB12B_GMAC_GTSUCOMP \ 867 SAM_PINMUX(b, 12, b, periph) 868 869 /* pb12d_pcm_pck0 */ 870 #define PB12D_PCM_PCK0 \ 871 SAM_PINMUX(b, 12, d, periph) 872 873 /* pb12s_flash_erase */ 874 #define PB12S_FLASH_ERASE \ 875 SAM_PINMUX(b, 12, s, system) 876 877 /* pb13_gpio */ 878 #define PB13_GPIO \ 879 SAM_PINMUX(b, 13, gpio, gpio) 880 881 /* pb13a_pwmc0_pwml2 */ 882 #define PB13A_PWMC0_PWML2 \ 883 SAM_PINMUX(b, 13, a, periph) 884 885 /* pb13b_pcm_pck0 */ 886 #define PB13B_PCM_PCK0 \ 887 SAM_PINMUX(b, 13, b, periph) 888 889 /* pb13c_usart0_sck */ 890 #define PB13C_USART0_SCK \ 891 SAM_PINMUX(b, 13, c, periph) 892 893 /* pb13x_dacc_dac0 */ 894 #define PB13X_DACC_DAC0 \ 895 SAM_PINMUX(b, 13, x, extra) 896 897 /* pc0_gpio */ 898 #define PC0_GPIO \ 899 SAM_PINMUX(c, 0, gpio, gpio) 900 901 /* pc0a_ebi_d0 */ 902 #define PC0A_EBI_D0 \ 903 SAM_PINMUX(c, 0, a, periph) 904 905 /* pc0b_pwmc0_pwml0 */ 906 #define PC0B_PWMC0_PWML0 \ 907 SAM_PINMUX(c, 0, b, periph) 908 909 /* pc0x_afe1_ad9 */ 910 #define PC0X_AFE1_AD9 \ 911 SAM_PINMUX(c, 0, x, extra) 912 913 /* pc1_gpio */ 914 #define PC1_GPIO \ 915 SAM_PINMUX(c, 1, gpio, gpio) 916 917 /* pc1a_ebi_d1 */ 918 #define PC1A_EBI_D1 \ 919 SAM_PINMUX(c, 1, a, periph) 920 921 /* pc1b_pwmc0_pwml1 */ 922 #define PC1B_PWMC0_PWML1 \ 923 SAM_PINMUX(c, 1, b, periph) 924 925 /* pc2_gpio */ 926 #define PC2_GPIO \ 927 SAM_PINMUX(c, 2, gpio, gpio) 928 929 /* pc2a_ebi_d2 */ 930 #define PC2A_EBI_D2 \ 931 SAM_PINMUX(c, 2, a, periph) 932 933 /* pc2b_pwmc0_pwml2 */ 934 #define PC2B_PWMC0_PWML2 \ 935 SAM_PINMUX(c, 2, b, periph) 936 937 /* pc3_gpio */ 938 #define PC3_GPIO \ 939 SAM_PINMUX(c, 3, gpio, gpio) 940 941 /* pc3a_ebi_d3 */ 942 #define PC3A_EBI_D3 \ 943 SAM_PINMUX(c, 3, a, periph) 944 945 /* pc3b_pwmc0_pwml3 */ 946 #define PC3B_PWMC0_PWML3 \ 947 SAM_PINMUX(c, 3, b, periph) 948 949 /* pc4_gpio */ 950 #define PC4_GPIO \ 951 SAM_PINMUX(c, 4, gpio, gpio) 952 953 /* pc4a_ebi_d4 */ 954 #define PC4A_EBI_D4 \ 955 SAM_PINMUX(c, 4, a, periph) 956 957 /* pc5_gpio */ 958 #define PC5_GPIO \ 959 SAM_PINMUX(c, 5, gpio, gpio) 960 961 /* pc5a_ebi_d5 */ 962 #define PC5A_EBI_D5 \ 963 SAM_PINMUX(c, 5, a, periph) 964 965 /* pc5b_tc2_tioa6 */ 966 #define PC5B_TC2_TIOA6 \ 967 SAM_PINMUX(c, 5, b, periph) 968 969 /* pc6_gpio */ 970 #define PC6_GPIO \ 971 SAM_PINMUX(c, 6, gpio, gpio) 972 973 /* pc6a_ebi_d6 */ 974 #define PC6A_EBI_D6 \ 975 SAM_PINMUX(c, 6, a, periph) 976 977 /* pc6b_tc2_tiob6 */ 978 #define PC6B_TC2_TIOB6 \ 979 SAM_PINMUX(c, 6, b, periph) 980 981 /* pc7_gpio */ 982 #define PC7_GPIO \ 983 SAM_PINMUX(c, 7, gpio, gpio) 984 985 /* pc7a_ebi_d7 */ 986 #define PC7A_EBI_D7 \ 987 SAM_PINMUX(c, 7, a, periph) 988 989 /* pc7b_tc2_tclk6 */ 990 #define PC7B_TC2_TCLK6 \ 991 SAM_PINMUX(c, 7, b, periph) 992 993 /* pc8_gpio */ 994 #define PC8_GPIO \ 995 SAM_PINMUX(c, 8, gpio, gpio) 996 997 /* pc8a_ebi_nwe_nwr0 */ 998 #define PC8A_EBI_NWE_NWR0 \ 999 SAM_PINMUX(c, 8, a, periph) 1000 1001 /* pc8b_tc2_tioa7 */ 1002 #define PC8B_TC2_TIOA7 \ 1003 SAM_PINMUX(c, 8, b, periph) 1004 1005 /* pc9_gpio */ 1006 #define PC9_GPIO \ 1007 SAM_PINMUX(c, 9, gpio, gpio) 1008 1009 /* pc9a_ebi_nandoe */ 1010 #define PC9A_EBI_NANDOE \ 1011 SAM_PINMUX(c, 9, a, periph) 1012 1013 /* pc9b_tc2_tiob7 */ 1014 #define PC9B_TC2_TIOB7 \ 1015 SAM_PINMUX(c, 9, b, periph) 1016 1017 /* pc10_gpio */ 1018 #define PC10_GPIO \ 1019 SAM_PINMUX(c, 10, gpio, gpio) 1020 1021 /* pc10a_ebi_nandwe */ 1022 #define PC10A_EBI_NANDWE \ 1023 SAM_PINMUX(c, 10, a, periph) 1024 1025 /* pc10b_tc2_tclk7 */ 1026 #define PC10B_TC2_TCLK7 \ 1027 SAM_PINMUX(c, 10, b, periph) 1028 1029 /* pc11_gpio */ 1030 #define PC11_GPIO \ 1031 SAM_PINMUX(c, 11, gpio, gpio) 1032 1033 /* pc11a_ebi_nrd */ 1034 #define PC11A_EBI_NRD \ 1035 SAM_PINMUX(c, 11, a, periph) 1036 1037 /* pc11b_tc2_tioa8 */ 1038 #define PC11B_TC2_TIOA8 \ 1039 SAM_PINMUX(c, 11, b, periph) 1040 1041 /* pc12_gpio */ 1042 #define PC12_GPIO \ 1043 SAM_PINMUX(c, 12, gpio, gpio) 1044 1045 /* pc12a_ebi_ncs3 */ 1046 #define PC12A_EBI_NCS3 \ 1047 SAM_PINMUX(c, 12, a, periph) 1048 1049 /* pc12b_tc2_tiob8 */ 1050 #define PC12B_TC2_TIOB8 \ 1051 SAM_PINMUX(c, 12, b, periph) 1052 1053 /* pc12c_can1_rx */ 1054 #define PC12C_CAN1_RX \ 1055 SAM_PINMUX(c, 12, c, periph) 1056 1057 /* pc12x_afe1_ad3 */ 1058 #define PC12X_AFE1_AD3 \ 1059 SAM_PINMUX(c, 12, x, extra) 1060 1061 /* pc13_gpio */ 1062 #define PC13_GPIO \ 1063 SAM_PINMUX(c, 13, gpio, gpio) 1064 1065 /* pc13a_ebi_nwait */ 1066 #define PC13A_EBI_NWAIT \ 1067 SAM_PINMUX(c, 13, a, periph) 1068 1069 /* pc13b_pwmc0_pwmh3 */ 1070 #define PC13B_PWMC0_PWMH3 \ 1071 SAM_PINMUX(c, 13, b, periph) 1072 1073 /* pc13c_ebi_sda10 */ 1074 #define PC13C_EBI_SDA10 \ 1075 SAM_PINMUX(c, 13, c, periph) 1076 1077 /* pc13x_afe1_ad1 */ 1078 #define PC13X_AFE1_AD1 \ 1079 SAM_PINMUX(c, 13, x, extra) 1080 1081 /* pc14_gpio */ 1082 #define PC14_GPIO \ 1083 SAM_PINMUX(c, 14, gpio, gpio) 1084 1085 /* pc14a_ebi_ncs0 */ 1086 #define PC14A_EBI_NCS0 \ 1087 SAM_PINMUX(c, 14, a, periph) 1088 1089 /* pc14b_tc2_tclk8 */ 1090 #define PC14B_TC2_TCLK8 \ 1091 SAM_PINMUX(c, 14, b, periph) 1092 1093 /* pc14c_can1_tx */ 1094 #define PC14C_CAN1_TX \ 1095 SAM_PINMUX(c, 14, c, periph) 1096 1097 /* pc15_gpio */ 1098 #define PC15_GPIO \ 1099 SAM_PINMUX(c, 15, gpio, gpio) 1100 1101 /* pc15a_ebi_ncs1_sdcs */ 1102 #define PC15A_EBI_NCS1_SDCS \ 1103 SAM_PINMUX(c, 15, a, periph) 1104 1105 /* pc15b_pwmc0_pwml3 */ 1106 #define PC15B_PWMC0_PWML3 \ 1107 SAM_PINMUX(c, 15, b, periph) 1108 1109 /* pc15x_afe1_ad2 */ 1110 #define PC15X_AFE1_AD2 \ 1111 SAM_PINMUX(c, 15, x, extra) 1112 1113 /* pc16_gpio */ 1114 #define PC16_GPIO \ 1115 SAM_PINMUX(c, 16, gpio, gpio) 1116 1117 /* pc16a_ebi_a21_nandale */ 1118 #define PC16A_EBI_A21_NANDALE \ 1119 SAM_PINMUX(c, 16, a, periph) 1120 1121 /* pc17_gpio */ 1122 #define PC17_GPIO \ 1123 SAM_PINMUX(c, 17, gpio, gpio) 1124 1125 /* pc17a_ebi_a22_nandcle */ 1126 #define PC17A_EBI_A22_NANDCLE \ 1127 SAM_PINMUX(c, 17, a, periph) 1128 1129 /* pc18_gpio */ 1130 #define PC18_GPIO \ 1131 SAM_PINMUX(c, 18, gpio, gpio) 1132 1133 /* pc18a_ebi_a0_nbs0 */ 1134 #define PC18A_EBI_A0_NBS0 \ 1135 SAM_PINMUX(c, 18, a, periph) 1136 1137 /* pc18b_pwmc0_pwml1 */ 1138 #define PC18B_PWMC0_PWML1 \ 1139 SAM_PINMUX(c, 18, b, periph) 1140 1141 /* pc19_gpio */ 1142 #define PC19_GPIO \ 1143 SAM_PINMUX(c, 19, gpio, gpio) 1144 1145 /* pc19a_ebi_a1 */ 1146 #define PC19A_EBI_A1 \ 1147 SAM_PINMUX(c, 19, a, periph) 1148 1149 /* pc19b_pwmc0_pwmh2 */ 1150 #define PC19B_PWMC0_PWMH2 \ 1151 SAM_PINMUX(c, 19, b, periph) 1152 1153 /* pc20_gpio */ 1154 #define PC20_GPIO \ 1155 SAM_PINMUX(c, 20, gpio, gpio) 1156 1157 /* pc20a_ebi_a2 */ 1158 #define PC20A_EBI_A2 \ 1159 SAM_PINMUX(c, 20, a, periph) 1160 1161 /* pc20b_pwmc0_pwml2 */ 1162 #define PC20B_PWMC0_PWML2 \ 1163 SAM_PINMUX(c, 20, b, periph) 1164 1165 /* pc21_gpio */ 1166 #define PC21_GPIO \ 1167 SAM_PINMUX(c, 21, gpio, gpio) 1168 1169 /* pc21a_ebi_a3 */ 1170 #define PC21A_EBI_A3 \ 1171 SAM_PINMUX(c, 21, a, periph) 1172 1173 /* pc21b_pwmc0_pwmh3 */ 1174 #define PC21B_PWMC0_PWMH3 \ 1175 SAM_PINMUX(c, 21, b, periph) 1176 1177 /* pc22_gpio */ 1178 #define PC22_GPIO \ 1179 SAM_PINMUX(c, 22, gpio, gpio) 1180 1181 /* pc22a_ebi_a4 */ 1182 #define PC22A_EBI_A4 \ 1183 SAM_PINMUX(c, 22, a, periph) 1184 1185 /* pc22b_pwmc0_pwml3 */ 1186 #define PC22B_PWMC0_PWML3 \ 1187 SAM_PINMUX(c, 22, b, periph) 1188 1189 /* pc23_gpio */ 1190 #define PC23_GPIO \ 1191 SAM_PINMUX(c, 23, gpio, gpio) 1192 1193 /* pc23a_ebi_a5 */ 1194 #define PC23A_EBI_A5 \ 1195 SAM_PINMUX(c, 23, a, periph) 1196 1197 /* pc23b_tc1_tioa3 */ 1198 #define PC23B_TC1_TIOA3 \ 1199 SAM_PINMUX(c, 23, b, periph) 1200 1201 /* pc24_gpio */ 1202 #define PC24_GPIO \ 1203 SAM_PINMUX(c, 24, gpio, gpio) 1204 1205 /* pc24a_ebi_a6 */ 1206 #define PC24A_EBI_A6 \ 1207 SAM_PINMUX(c, 24, a, periph) 1208 1209 /* pc24b_tc1_tiob3 */ 1210 #define PC24B_TC1_TIOB3 \ 1211 SAM_PINMUX(c, 24, b, periph) 1212 1213 /* pc24c_spi1_spck */ 1214 #define PC24C_SPI1_SPCK \ 1215 SAM_PINMUX(c, 24, c, periph) 1216 1217 /* pc25_gpio */ 1218 #define PC25_GPIO \ 1219 SAM_PINMUX(c, 25, gpio, gpio) 1220 1221 /* pc25a_ebi_a7 */ 1222 #define PC25A_EBI_A7 \ 1223 SAM_PINMUX(c, 25, a, periph) 1224 1225 /* pc25b_tc1_tclk3 */ 1226 #define PC25B_TC1_TCLK3 \ 1227 SAM_PINMUX(c, 25, b, periph) 1228 1229 /* pc25c_spi1_npcs0 */ 1230 #define PC25C_SPI1_NPCS0 \ 1231 SAM_PINMUX(c, 25, c, periph) 1232 1233 /* pc26_gpio */ 1234 #define PC26_GPIO \ 1235 SAM_PINMUX(c, 26, gpio, gpio) 1236 1237 /* pc26a_ebi_a8 */ 1238 #define PC26A_EBI_A8 \ 1239 SAM_PINMUX(c, 26, a, periph) 1240 1241 /* pc26b_tc1_tioa4 */ 1242 #define PC26B_TC1_TIOA4 \ 1243 SAM_PINMUX(c, 26, b, periph) 1244 1245 /* pc26c_spi1_miso */ 1246 #define PC26C_SPI1_MISO \ 1247 SAM_PINMUX(c, 26, c, periph) 1248 1249 /* pc26x_afe1_ad7 */ 1250 #define PC26X_AFE1_AD7 \ 1251 SAM_PINMUX(c, 26, x, extra) 1252 1253 /* pc27_gpio */ 1254 #define PC27_GPIO \ 1255 SAM_PINMUX(c, 27, gpio, gpio) 1256 1257 /* pc27a_ebi_a9 */ 1258 #define PC27A_EBI_A9 \ 1259 SAM_PINMUX(c, 27, a, periph) 1260 1261 /* pc27b_tc1_tiob4 */ 1262 #define PC27B_TC1_TIOB4 \ 1263 SAM_PINMUX(c, 27, b, periph) 1264 1265 /* pc27c_spi1_mosi */ 1266 #define PC27C_SPI1_MOSI \ 1267 SAM_PINMUX(c, 27, c, periph) 1268 1269 /* pc27x_afe1_ad8 */ 1270 #define PC27X_AFE1_AD8 \ 1271 SAM_PINMUX(c, 27, x, extra) 1272 1273 /* pc28_gpio */ 1274 #define PC28_GPIO \ 1275 SAM_PINMUX(c, 28, gpio, gpio) 1276 1277 /* pc28a_ebi_a10 */ 1278 #define PC28A_EBI_A10 \ 1279 SAM_PINMUX(c, 28, a, periph) 1280 1281 /* pc28b_tc1_tclk4 */ 1282 #define PC28B_TC1_TCLK4 \ 1283 SAM_PINMUX(c, 28, b, periph) 1284 1285 /* pc28c_spi1_npcs1 */ 1286 #define PC28C_SPI1_NPCS1 \ 1287 SAM_PINMUX(c, 28, c, periph) 1288 1289 /* pc29_gpio */ 1290 #define PC29_GPIO \ 1291 SAM_PINMUX(c, 29, gpio, gpio) 1292 1293 /* pc29a_ebi_a11 */ 1294 #define PC29A_EBI_A11 \ 1295 SAM_PINMUX(c, 29, a, periph) 1296 1297 /* pc29b_tc1_tioa5 */ 1298 #define PC29B_TC1_TIOA5 \ 1299 SAM_PINMUX(c, 29, b, periph) 1300 1301 /* pc29c_spi1_npcs2 */ 1302 #define PC29C_SPI1_NPCS2 \ 1303 SAM_PINMUX(c, 29, c, periph) 1304 1305 /* pc29x_afe1_ad4 */ 1306 #define PC29X_AFE1_AD4 \ 1307 SAM_PINMUX(c, 29, x, extra) 1308 1309 /* pc30_gpio */ 1310 #define PC30_GPIO \ 1311 SAM_PINMUX(c, 30, gpio, gpio) 1312 1313 /* pc30a_ebi_a12 */ 1314 #define PC30A_EBI_A12 \ 1315 SAM_PINMUX(c, 30, a, periph) 1316 1317 /* pc30b_tc1_tiob5 */ 1318 #define PC30B_TC1_TIOB5 \ 1319 SAM_PINMUX(c, 30, b, periph) 1320 1321 /* pc30c_spi1_npcs3 */ 1322 #define PC30C_SPI1_NPCS3 \ 1323 SAM_PINMUX(c, 30, c, periph) 1324 1325 /* pc30x_afe1_ad5 */ 1326 #define PC30X_AFE1_AD5 \ 1327 SAM_PINMUX(c, 30, x, extra) 1328 1329 /* pc31_gpio */ 1330 #define PC31_GPIO \ 1331 SAM_PINMUX(c, 31, gpio, gpio) 1332 1333 /* pc31a_ebi_a13 */ 1334 #define PC31A_EBI_A13 \ 1335 SAM_PINMUX(c, 31, a, periph) 1336 1337 /* pc31b_tc1_tclk5 */ 1338 #define PC31B_TC1_TCLK5 \ 1339 SAM_PINMUX(c, 31, b, periph) 1340 1341 /* pc31x_afe1_ad6 */ 1342 #define PC31X_AFE1_AD6 \ 1343 SAM_PINMUX(c, 31, x, extra) 1344 1345 /* pd0_gpio */ 1346 #define PD0_GPIO \ 1347 SAM_PINMUX(d, 0, gpio, gpio) 1348 1349 /* pd0a_gmac_gtxck */ 1350 #define PD0A_GMAC_GTXCK \ 1351 SAM_PINMUX(d, 0, a, periph) 1352 1353 /* pd0b_pwmc1_pwml0 */ 1354 #define PD0B_PWMC1_PWML0 \ 1355 SAM_PINMUX(d, 0, b, periph) 1356 1357 /* pd0c_spi1_npcs1 */ 1358 #define PD0C_SPI1_NPCS1 \ 1359 SAM_PINMUX(d, 0, c, periph) 1360 1361 /* pd0d_usart0_dcd */ 1362 #define PD0D_USART0_DCD \ 1363 SAM_PINMUX(d, 0, d, periph) 1364 1365 /* pd0x_dacc_dac1 */ 1366 #define PD0X_DACC_DAC1 \ 1367 SAM_PINMUX(d, 0, x, extra) 1368 1369 /* pd1_gpio */ 1370 #define PD1_GPIO \ 1371 SAM_PINMUX(d, 1, gpio, gpio) 1372 1373 /* pd1a_gmac_gtxen */ 1374 #define PD1A_GMAC_GTXEN \ 1375 SAM_PINMUX(d, 1, a, periph) 1376 1377 /* pd1b_pwmc1_pwmh0 */ 1378 #define PD1B_PWMC1_PWMH0 \ 1379 SAM_PINMUX(d, 1, b, periph) 1380 1381 /* pd1c_spi1_npcs2 */ 1382 #define PD1C_SPI1_NPCS2 \ 1383 SAM_PINMUX(d, 1, c, periph) 1384 1385 /* pd1d_usart0_dtr */ 1386 #define PD1D_USART0_DTR \ 1387 SAM_PINMUX(d, 1, d, periph) 1388 1389 /* pd2_gpio */ 1390 #define PD2_GPIO \ 1391 SAM_PINMUX(d, 2, gpio, gpio) 1392 1393 /* pd2a_gmac_gtx0 */ 1394 #define PD2A_GMAC_GTX0 \ 1395 SAM_PINMUX(d, 2, a, periph) 1396 1397 /* pd2b_pwmc1_pwml1 */ 1398 #define PD2B_PWMC1_PWML1 \ 1399 SAM_PINMUX(d, 2, b, periph) 1400 1401 /* pd2c_spi1_npcs3 */ 1402 #define PD2C_SPI1_NPCS3 \ 1403 SAM_PINMUX(d, 2, c, periph) 1404 1405 /* pd2d_usart0_dsr */ 1406 #define PD2D_USART0_DSR \ 1407 SAM_PINMUX(d, 2, d, periph) 1408 1409 /* pd3_gpio */ 1410 #define PD3_GPIO \ 1411 SAM_PINMUX(d, 3, gpio, gpio) 1412 1413 /* pd3a_gmac_gtx1 */ 1414 #define PD3A_GMAC_GTX1 \ 1415 SAM_PINMUX(d, 3, a, periph) 1416 1417 /* pd3b_pwmc1_pwmh1 */ 1418 #define PD3B_PWMC1_PWMH1 \ 1419 SAM_PINMUX(d, 3, b, periph) 1420 1421 /* pd3c_uart4_txd */ 1422 #define PD3C_UART4_TXD \ 1423 SAM_PINMUX(d, 3, c, periph) 1424 1425 /* pd3d_usart0_ri */ 1426 #define PD3D_USART0_RI \ 1427 SAM_PINMUX(d, 3, d, periph) 1428 1429 /* pd4_gpio */ 1430 #define PD4_GPIO \ 1431 SAM_PINMUX(d, 4, gpio, gpio) 1432 1433 /* pd4a_gmac_grxdv */ 1434 #define PD4A_GMAC_GRXDV \ 1435 SAM_PINMUX(d, 4, a, periph) 1436 1437 /* pd4b_pwmc1_pwml2 */ 1438 #define PD4B_PWMC1_PWML2 \ 1439 SAM_PINMUX(d, 4, b, periph) 1440 1441 /* pd4c_trace_d0 */ 1442 #define PD4C_TRACE_D0 \ 1443 SAM_PINMUX(d, 4, c, periph) 1444 1445 /* pd4d_usart2_dcd */ 1446 #define PD4D_USART2_DCD \ 1447 SAM_PINMUX(d, 4, d, periph) 1448 1449 /* pd5_gpio */ 1450 #define PD5_GPIO \ 1451 SAM_PINMUX(d, 5, gpio, gpio) 1452 1453 /* pd5a_gmac_grx0 */ 1454 #define PD5A_GMAC_GRX0 \ 1455 SAM_PINMUX(d, 5, a, periph) 1456 1457 /* pd5b_pwmc1_pwmh2 */ 1458 #define PD5B_PWMC1_PWMH2 \ 1459 SAM_PINMUX(d, 5, b, periph) 1460 1461 /* pd5c_trace_d1 */ 1462 #define PD5C_TRACE_D1 \ 1463 SAM_PINMUX(d, 5, c, periph) 1464 1465 /* pd5d_usart2_dtr */ 1466 #define PD5D_USART2_DTR \ 1467 SAM_PINMUX(d, 5, d, periph) 1468 1469 /* pd6_gpio */ 1470 #define PD6_GPIO \ 1471 SAM_PINMUX(d, 6, gpio, gpio) 1472 1473 /* pd6a_gmac_grx1 */ 1474 #define PD6A_GMAC_GRX1 \ 1475 SAM_PINMUX(d, 6, a, periph) 1476 1477 /* pd6b_pwmc1_pwml3 */ 1478 #define PD6B_PWMC1_PWML3 \ 1479 SAM_PINMUX(d, 6, b, periph) 1480 1481 /* pd6c_trace_d2 */ 1482 #define PD6C_TRACE_D2 \ 1483 SAM_PINMUX(d, 6, c, periph) 1484 1485 /* pd6d_usart2_dsr */ 1486 #define PD6D_USART2_DSR \ 1487 SAM_PINMUX(d, 6, d, periph) 1488 1489 /* pd7_gpio */ 1490 #define PD7_GPIO \ 1491 SAM_PINMUX(d, 7, gpio, gpio) 1492 1493 /* pd7a_gmac_grxer */ 1494 #define PD7A_GMAC_GRXER \ 1495 SAM_PINMUX(d, 7, a, periph) 1496 1497 /* pd7b_pwmc1_pwmh3 */ 1498 #define PD7B_PWMC1_PWMH3 \ 1499 SAM_PINMUX(d, 7, b, periph) 1500 1501 /* pd7c_trace_d3 */ 1502 #define PD7C_TRACE_D3 \ 1503 SAM_PINMUX(d, 7, c, periph) 1504 1505 /* pd7d_usart2_ri */ 1506 #define PD7D_USART2_RI \ 1507 SAM_PINMUX(d, 7, d, periph) 1508 1509 /* pd8_gpio */ 1510 #define PD8_GPIO \ 1511 SAM_PINMUX(d, 8, gpio, gpio) 1512 1513 /* pd8a_gmac_gmdc */ 1514 #define PD8A_GMAC_GMDC \ 1515 SAM_PINMUX(d, 8, a, periph) 1516 1517 /* pd8b_pwmc0_pwmfi1 */ 1518 #define PD8B_PWMC0_PWMFI1 \ 1519 SAM_PINMUX(d, 8, b, periph) 1520 1521 /* pd8d_trace_clk */ 1522 #define PD8D_TRACE_CLK \ 1523 SAM_PINMUX(d, 8, d, periph) 1524 1525 /* pd9_gpio */ 1526 #define PD9_GPIO \ 1527 SAM_PINMUX(d, 9, gpio, gpio) 1528 1529 /* pd9a_gmac_gmdio */ 1530 #define PD9A_GMAC_GMDIO \ 1531 SAM_PINMUX(d, 9, a, periph) 1532 1533 /* pd9b_pwmc0_pwmfi2 */ 1534 #define PD9B_PWMC0_PWMFI2 \ 1535 SAM_PINMUX(d, 9, b, periph) 1536 1537 /* pd9c_afe1_adtrg */ 1538 #define PD9C_AFE1_ADTRG \ 1539 SAM_PINMUX(d, 9, c, periph) 1540 1541 /* pd10_gpio */ 1542 #define PD10_GPIO \ 1543 SAM_PINMUX(d, 10, gpio, gpio) 1544 1545 /* pd10a_gmac_gcrs */ 1546 #define PD10A_GMAC_GCRS \ 1547 SAM_PINMUX(d, 10, a, periph) 1548 1549 /* pd10b_pwmc0_pwml0 */ 1550 #define PD10B_PWMC0_PWML0 \ 1551 SAM_PINMUX(d, 10, b, periph) 1552 1553 /* pd10c_ssc_td */ 1554 #define PD10C_SSC_TD \ 1555 SAM_PINMUX(d, 10, c, periph) 1556 1557 /* pd10d_mlb_sig */ 1558 #define PD10D_MLB_SIG \ 1559 SAM_PINMUX(d, 10, d, periph) 1560 1561 /* pd11_gpio */ 1562 #define PD11_GPIO \ 1563 SAM_PINMUX(d, 11, gpio, gpio) 1564 1565 /* pd11a_gmac_grx2 */ 1566 #define PD11A_GMAC_GRX2 \ 1567 SAM_PINMUX(d, 11, a, periph) 1568 1569 /* pd11b_pwmc0_pwmh0 */ 1570 #define PD11B_PWMC0_PWMH0 \ 1571 SAM_PINMUX(d, 11, b, periph) 1572 1573 /* pd11c_gmac_gtsucomp */ 1574 #define PD11C_GMAC_GTSUCOMP \ 1575 SAM_PINMUX(d, 11, c, periph) 1576 1577 /* pd11d_isi_d5 */ 1578 #define PD11D_ISI_D5 \ 1579 SAM_PINMUX(d, 11, d, periph) 1580 1581 /* pd12_gpio */ 1582 #define PD12_GPIO \ 1583 SAM_PINMUX(d, 12, gpio, gpio) 1584 1585 /* pd12a_gmac_grx3 */ 1586 #define PD12A_GMAC_GRX3 \ 1587 SAM_PINMUX(d, 12, a, periph) 1588 1589 /* pd12b_can1_tx */ 1590 #define PD12B_CAN1_TX \ 1591 SAM_PINMUX(d, 12, b, periph) 1592 1593 /* pd12c_spi0_npcs2 */ 1594 #define PD12C_SPI0_NPCS2 \ 1595 SAM_PINMUX(d, 12, c, periph) 1596 1597 /* pd12d_isi_d6 */ 1598 #define PD12D_ISI_D6 \ 1599 SAM_PINMUX(d, 12, d, periph) 1600 1601 /* pd13_gpio */ 1602 #define PD13_GPIO \ 1603 SAM_PINMUX(d, 13, gpio, gpio) 1604 1605 /* pd13a_gmac_gcol */ 1606 #define PD13A_GMAC_GCOL \ 1607 SAM_PINMUX(d, 13, a, periph) 1608 1609 /* pd13c_ebi_sda10 */ 1610 #define PD13C_EBI_SDA10 \ 1611 SAM_PINMUX(d, 13, c, periph) 1612 1613 /* pd14_gpio */ 1614 #define PD14_GPIO \ 1615 SAM_PINMUX(d, 14, gpio, gpio) 1616 1617 /* pd14a_gmac_grxck */ 1618 #define PD14A_GMAC_GRXCK \ 1619 SAM_PINMUX(d, 14, a, periph) 1620 1621 /* pd14c_ebi_sdcke */ 1622 #define PD14C_EBI_SDCKE \ 1623 SAM_PINMUX(d, 14, c, periph) 1624 1625 /* pd15_gpio */ 1626 #define PD15_GPIO \ 1627 SAM_PINMUX(d, 15, gpio, gpio) 1628 1629 /* pd15a_gmac_gtx2 */ 1630 #define PD15A_GMAC_GTX2 \ 1631 SAM_PINMUX(d, 15, a, periph) 1632 1633 /* pd15b_usart2_rxd */ 1634 #define PD15B_USART2_RXD \ 1635 SAM_PINMUX(d, 15, b, periph) 1636 1637 /* pd15c_ebi_nwr1_nbs1 */ 1638 #define PD15C_EBI_NWR1_NBS1 \ 1639 SAM_PINMUX(d, 15, c, periph) 1640 1641 /* pd16_gpio */ 1642 #define PD16_GPIO \ 1643 SAM_PINMUX(d, 16, gpio, gpio) 1644 1645 /* pd16a_gmac_gtx3 */ 1646 #define PD16A_GMAC_GTX3 \ 1647 SAM_PINMUX(d, 16, a, periph) 1648 1649 /* pd16b_usart2_txd */ 1650 #define PD16B_USART2_TXD \ 1651 SAM_PINMUX(d, 16, b, periph) 1652 1653 /* pd16c_ebi_ras */ 1654 #define PD16C_EBI_RAS \ 1655 SAM_PINMUX(d, 16, c, periph) 1656 1657 /* pd17_gpio */ 1658 #define PD17_GPIO \ 1659 SAM_PINMUX(d, 17, gpio, gpio) 1660 1661 /* pd17a_gmac_gtxer */ 1662 #define PD17A_GMAC_GTXER \ 1663 SAM_PINMUX(d, 17, a, periph) 1664 1665 /* pd17b_usart2_sck */ 1666 #define PD17B_USART2_SCK \ 1667 SAM_PINMUX(d, 17, b, periph) 1668 1669 /* pd17c_ebi_cas */ 1670 #define PD17C_EBI_CAS \ 1671 SAM_PINMUX(d, 17, c, periph) 1672 1673 /* pd18_gpio */ 1674 #define PD18_GPIO \ 1675 SAM_PINMUX(d, 18, gpio, gpio) 1676 1677 /* pd18a_ebi_ncs1_sdcs */ 1678 #define PD18A_EBI_NCS1_SDCS \ 1679 SAM_PINMUX(d, 18, a, periph) 1680 1681 /* pd18b_usart2_rts */ 1682 #define PD18B_USART2_RTS \ 1683 SAM_PINMUX(d, 18, b, periph) 1684 1685 /* pd18c_uart4_rxd */ 1686 #define PD18C_UART4_RXD \ 1687 SAM_PINMUX(d, 18, c, periph) 1688 1689 /* pd19_gpio */ 1690 #define PD19_GPIO \ 1691 SAM_PINMUX(d, 19, gpio, gpio) 1692 1693 /* pd19a_ebi_ncs3 */ 1694 #define PD19A_EBI_NCS3 \ 1695 SAM_PINMUX(d, 19, a, periph) 1696 1697 /* pd19b_usart2_cts */ 1698 #define PD19B_USART2_CTS \ 1699 SAM_PINMUX(d, 19, b, periph) 1700 1701 /* pd19c_uart4_txd */ 1702 #define PD19C_UART4_TXD \ 1703 SAM_PINMUX(d, 19, c, periph) 1704 1705 /* pd20_gpio */ 1706 #define PD20_GPIO \ 1707 SAM_PINMUX(d, 20, gpio, gpio) 1708 1709 /* pd20a_pwmc0_pwmh0 */ 1710 #define PD20A_PWMC0_PWMH0 \ 1711 SAM_PINMUX(d, 20, a, periph) 1712 1713 /* pd20b_spi0_miso */ 1714 #define PD20B_SPI0_MISO \ 1715 SAM_PINMUX(d, 20, b, periph) 1716 1717 /* pd20c_gmac_gtsucomp */ 1718 #define PD20C_GMAC_GTSUCOMP \ 1719 SAM_PINMUX(d, 20, c, periph) 1720 1721 /* pd21_gpio */ 1722 #define PD21_GPIO \ 1723 SAM_PINMUX(d, 21, gpio, gpio) 1724 1725 /* pd21a_pwmc0_pwmh1 */ 1726 #define PD21A_PWMC0_PWMH1 \ 1727 SAM_PINMUX(d, 21, a, periph) 1728 1729 /* pd21b_spi0_mosi */ 1730 #define PD21B_SPI0_MOSI \ 1731 SAM_PINMUX(d, 21, b, periph) 1732 1733 /* pd21c_tc3_tioa11 */ 1734 #define PD21C_TC3_TIOA11 \ 1735 SAM_PINMUX(d, 21, c, periph) 1736 1737 /* pd21d_isi_d1 */ 1738 #define PD21D_ISI_D1 \ 1739 SAM_PINMUX(d, 21, d, periph) 1740 1741 /* pd22_gpio */ 1742 #define PD22_GPIO \ 1743 SAM_PINMUX(d, 22, gpio, gpio) 1744 1745 /* pd22a_pwmc0_pwmh2 */ 1746 #define PD22A_PWMC0_PWMH2 \ 1747 SAM_PINMUX(d, 22, a, periph) 1748 1749 /* pd22b_spi0_spck */ 1750 #define PD22B_SPI0_SPCK \ 1751 SAM_PINMUX(d, 22, b, periph) 1752 1753 /* pd22c_tc3_tiob11 */ 1754 #define PD22C_TC3_TIOB11 \ 1755 SAM_PINMUX(d, 22, c, periph) 1756 1757 /* pd22d_isi_d0 */ 1758 #define PD22D_ISI_D0 \ 1759 SAM_PINMUX(d, 22, d, periph) 1760 1761 /* pd23_gpio */ 1762 #define PD23_GPIO \ 1763 SAM_PINMUX(d, 23, gpio, gpio) 1764 1765 /* pd23a_pwmc0_pwmh3 */ 1766 #define PD23A_PWMC0_PWMH3 \ 1767 SAM_PINMUX(d, 23, a, periph) 1768 1769 /* pd23c_ebi_sdck */ 1770 #define PD23C_EBI_SDCK \ 1771 SAM_PINMUX(d, 23, c, periph) 1772 1773 /* pd24_gpio */ 1774 #define PD24_GPIO \ 1775 SAM_PINMUX(d, 24, gpio, gpio) 1776 1777 /* pd24a_pwmc0_pwml0 */ 1778 #define PD24A_PWMC0_PWML0 \ 1779 SAM_PINMUX(d, 24, a, periph) 1780 1781 /* pd24b_ssc_rf */ 1782 #define PD24B_SSC_RF \ 1783 SAM_PINMUX(d, 24, b, periph) 1784 1785 /* pd24c_tc3_tclk11 */ 1786 #define PD24C_TC3_TCLK11 \ 1787 SAM_PINMUX(d, 24, c, periph) 1788 1789 /* pd24d_isi_hsync */ 1790 #define PD24D_ISI_HSYNC \ 1791 SAM_PINMUX(d, 24, d, periph) 1792 1793 /* pd25_gpio */ 1794 #define PD25_GPIO \ 1795 SAM_PINMUX(d, 25, gpio, gpio) 1796 1797 /* pd25a_pwmc0_pwml1 */ 1798 #define PD25A_PWMC0_PWML1 \ 1799 SAM_PINMUX(d, 25, a, periph) 1800 1801 /* pd25b_spi0_npcs1 */ 1802 #define PD25B_SPI0_NPCS1 \ 1803 SAM_PINMUX(d, 25, b, periph) 1804 1805 /* pd25c_uart2_rxd */ 1806 #define PD25C_UART2_RXD \ 1807 SAM_PINMUX(d, 25, c, periph) 1808 1809 /* pd25d_isi_vsync */ 1810 #define PD25D_ISI_VSYNC \ 1811 SAM_PINMUX(d, 25, d, periph) 1812 1813 /* pd26_gpio */ 1814 #define PD26_GPIO \ 1815 SAM_PINMUX(d, 26, gpio, gpio) 1816 1817 /* pd26a_pwmc0_pwml2 */ 1818 #define PD26A_PWMC0_PWML2 \ 1819 SAM_PINMUX(d, 26, a, periph) 1820 1821 /* pd26b_ssc_td */ 1822 #define PD26B_SSC_TD \ 1823 SAM_PINMUX(d, 26, b, periph) 1824 1825 /* pd26c_uart2_txd */ 1826 #define PD26C_UART2_TXD \ 1827 SAM_PINMUX(d, 26, c, periph) 1828 1829 /* pd26d_uart1_txd */ 1830 #define PD26D_UART1_TXD \ 1831 SAM_PINMUX(d, 26, d, periph) 1832 1833 /* pd27_gpio */ 1834 #define PD27_GPIO \ 1835 SAM_PINMUX(d, 27, gpio, gpio) 1836 1837 /* pd27a_pwmc0_pwml3 */ 1838 #define PD27A_PWMC0_PWML3 \ 1839 SAM_PINMUX(d, 27, a, periph) 1840 1841 /* pd27b_spi0_npcs3 */ 1842 #define PD27B_SPI0_NPCS3 \ 1843 SAM_PINMUX(d, 27, b, periph) 1844 1845 /* pd27c_twi2_twd */ 1846 #define PD27C_TWI2_TWD \ 1847 SAM_PINMUX(d, 27, c, periph) 1848 1849 /* pd27d_isi_d8 */ 1850 #define PD27D_ISI_D8 \ 1851 SAM_PINMUX(d, 27, d, periph) 1852 1853 /* pd28_gpio */ 1854 #define PD28_GPIO \ 1855 SAM_PINMUX(d, 28, gpio, gpio) 1856 1857 /* pd28a_uart3_rxd */ 1858 #define PD28A_UART3_RXD \ 1859 SAM_PINMUX(d, 28, a, periph) 1860 1861 /* pd28b_can1_rx */ 1862 #define PD28B_CAN1_RX \ 1863 SAM_PINMUX(d, 28, b, periph) 1864 1865 /* pd28c_twi2_twck */ 1866 #define PD28C_TWI2_TWCK \ 1867 SAM_PINMUX(d, 28, c, periph) 1868 1869 /* pd28d_isi_d9 */ 1870 #define PD28D_ISI_D9 \ 1871 SAM_PINMUX(d, 28, d, periph) 1872 1873 /* pd28x_supc_wkup5 */ 1874 #define PD28X_SUPC_WKUP5 \ 1875 SAM_PINMUX(d, 28, x, extra) 1876 1877 /* pd29_gpio */ 1878 #define PD29_GPIO \ 1879 SAM_PINMUX(d, 29, gpio, gpio) 1880 1881 /* pd29c_ebi_sdwe */ 1882 #define PD29C_EBI_SDWE \ 1883 SAM_PINMUX(d, 29, c, periph) 1884 1885 /* pd30_gpio */ 1886 #define PD30_GPIO \ 1887 SAM_PINMUX(d, 30, gpio, gpio) 1888 1889 /* pd30a_uart3_txd */ 1890 #define PD30A_UART3_TXD \ 1891 SAM_PINMUX(d, 30, a, periph) 1892 1893 /* pd30d_isi_d10 */ 1894 #define PD30D_ISI_D10 \ 1895 SAM_PINMUX(d, 30, d, periph) 1896 1897 /* pd30x_afe0_ad0 */ 1898 #define PD30X_AFE0_AD0 \ 1899 SAM_PINMUX(d, 30, x, extra) 1900 1901 /* pd31_gpio */ 1902 #define PD31_GPIO \ 1903 SAM_PINMUX(d, 31, gpio, gpio) 1904 1905 /* pd31a_qspi_qio3 */ 1906 #define PD31A_QSPI_QIO3 \ 1907 SAM_PINMUX(d, 31, a, periph) 1908 1909 /* pd31b_uart3_txd */ 1910 #define PD31B_UART3_TXD \ 1911 SAM_PINMUX(d, 31, b, periph) 1912 1913 /* pd31c_pmc_pck2 */ 1914 #define PD31C_PMC_PCK2 \ 1915 SAM_PINMUX(d, 31, c, periph) 1916 1917 /* pd31d_isi_d11 */ 1918 #define PD31D_ISI_D11 \ 1919 SAM_PINMUX(d, 31, d, periph) 1920 1921 /* pe0_gpio */ 1922 #define PE0_GPIO \ 1923 SAM_PINMUX(e, 0, gpio, gpio) 1924 1925 /* pe0a_ebi_d8 */ 1926 #define PE0A_EBI_D8 \ 1927 SAM_PINMUX(e, 0, a, periph) 1928 1929 /* pe0b_tc3_tioa9 */ 1930 #define PE0B_TC3_TIOA9 \ 1931 SAM_PINMUX(e, 0, b, periph) 1932 1933 /* pe0c_i2sc1_ws */ 1934 #define PE0C_I2SC1_WS \ 1935 SAM_PINMUX(e, 0, c, periph) 1936 1937 /* pe0x_afe1_ad11 */ 1938 #define PE0X_AFE1_AD11 \ 1939 SAM_PINMUX(e, 0, x, extra) 1940 1941 /* pe1_gpio */ 1942 #define PE1_GPIO \ 1943 SAM_PINMUX(e, 1, gpio, gpio) 1944 1945 /* pe1a_ebi_d9 */ 1946 #define PE1A_EBI_D9 \ 1947 SAM_PINMUX(e, 1, a, periph) 1948 1949 /* pe1b_tc3_tiob9 */ 1950 #define PE1B_TC3_TIOB9 \ 1951 SAM_PINMUX(e, 1, b, periph) 1952 1953 /* pe1c_i2sc1_do */ 1954 #define PE1C_I2SC1_DO \ 1955 SAM_PINMUX(e, 1, c, periph) 1956 1957 /* pe2_gpio */ 1958 #define PE2_GPIO \ 1959 SAM_PINMUX(e, 2, gpio, gpio) 1960 1961 /* pe2a_ebi_d10 */ 1962 #define PE2A_EBI_D10 \ 1963 SAM_PINMUX(e, 2, a, periph) 1964 1965 /* pe2b_tc3_tclk9 */ 1966 #define PE2B_TC3_TCLK9 \ 1967 SAM_PINMUX(e, 2, b, periph) 1968 1969 /* pe2c_i2sc1_di */ 1970 #define PE2C_I2SC1_DI \ 1971 SAM_PINMUX(e, 2, c, periph) 1972 1973 /* pe3_gpio */ 1974 #define PE3_GPIO \ 1975 SAM_PINMUX(e, 3, gpio, gpio) 1976 1977 /* pe3a_ebi_d11 */ 1978 #define PE3A_EBI_D11 \ 1979 SAM_PINMUX(e, 3, a, periph) 1980 1981 /* pe3b_tc3_tioa10 */ 1982 #define PE3B_TC3_TIOA10 \ 1983 SAM_PINMUX(e, 3, b, periph) 1984 1985 /* pe3x_afe1_ad10 */ 1986 #define PE3X_AFE1_AD10 \ 1987 SAM_PINMUX(e, 3, x, extra) 1988 1989 /* pe4_gpio */ 1990 #define PE4_GPIO \ 1991 SAM_PINMUX(e, 4, gpio, gpio) 1992 1993 /* pe4a_ebi_d12 */ 1994 #define PE4A_EBI_D12 \ 1995 SAM_PINMUX(e, 4, a, periph) 1996 1997 /* pe4b_tc3_tiob10 */ 1998 #define PE4B_TC3_TIOB10 \ 1999 SAM_PINMUX(e, 4, b, periph) 2000 2001 /* pe4x_afe1_ad4 */ 2002 #define PE4X_AFE1_AD4 \ 2003 SAM_PINMUX(e, 4, x, extra) 2004 2005 /* pe5_gpio */ 2006 #define PE5_GPIO \ 2007 SAM_PINMUX(e, 5, gpio, gpio) 2008 2009 /* pe5a_ebi_d13 */ 2010 #define PE5A_EBI_D13 \ 2011 SAM_PINMUX(e, 5, a, periph) 2012 2013 /* pe5b_tc3_tclk10 */ 2014 #define PE5B_TC3_TCLK10 \ 2015 SAM_PINMUX(e, 5, b, periph) 2016 2017 /* pe5x_afe1_ad3 */ 2018 #define PE5X_AFE1_AD3 \ 2019 SAM_PINMUX(e, 5, x, extra) 2020
