1 /* 2 * Autogenerated file 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #include <dt-bindings/pinctrl/atmel_sam_pinctrl.h> 8 9 /* 10 * WARNING: this variant has package exception. 11 * 12 * Read datasheet topics related to I/O Multiplexing and Considerations or 13 * Peripheral Signal Multiplexing on I/O Lines for more information. 14 */ 15 16 /* pa0_gpio */ 17 #define PA0_GPIO \ 18 SAM_PINMUX(a, 0, gpio, gpio) 19 20 /* pa0a_eic_extint0 */ 21 #define PA0A_EIC_EXTINT0 \ 22 SAM_PINMUX(a, 0, a, periph) 23 24 /* pa0d_sercom1_pad0 */ 25 #define PA0D_SERCOM1_PAD0 \ 26 SAM_PINMUX(a, 0, d, periph) 27 28 /* pa0f_tc2_wo0 */ 29 #define PA0F_TC2_WO0 \ 30 SAM_PINMUX(a, 0, f, periph) 31 32 /* pa1_gpio */ 33 #define PA1_GPIO \ 34 SAM_PINMUX(a, 1, gpio, gpio) 35 36 /* pa1a_eic_extint1 */ 37 #define PA1A_EIC_EXTINT1 \ 38 SAM_PINMUX(a, 1, a, periph) 39 40 /* pa1d_sercom1_pad1 */ 41 #define PA1D_SERCOM1_PAD1 \ 42 SAM_PINMUX(a, 1, d, periph) 43 44 /* pa1f_tc2_wo1 */ 45 #define PA1F_TC2_WO1 \ 46 SAM_PINMUX(a, 1, f, periph) 47 48 /* pa2_gpio */ 49 #define PA2_GPIO \ 50 SAM_PINMUX(a, 2, gpio, gpio) 51 52 /* pa2a_eic_extint2 */ 53 #define PA2A_EIC_EXTINT2 \ 54 SAM_PINMUX(a, 2, a, periph) 55 56 /* pa2b_adc_ain0 */ 57 #define PA2B_ADC_AIN0 \ 58 SAM_PINMUX(a, 2, b, periph) 59 60 /* pa2b_ptc_y0 */ 61 #define PA2B_PTC_Y0 \ 62 SAM_PINMUX(a, 2, b, periph) 63 64 /* pa2b_dac_vout */ 65 #define PA2B_DAC_VOUT \ 66 SAM_PINMUX(a, 2, b, periph) 67 68 /* pa3_gpio */ 69 #define PA3_GPIO \ 70 SAM_PINMUX(a, 3, gpio, gpio) 71 72 /* pa3a_eic_extint3 */ 73 #define PA3A_EIC_EXTINT3 \ 74 SAM_PINMUX(a, 3, a, periph) 75 76 /* pa3b_adc_dac_vrfea */ 77 #define PA3B_ADC_DAC_VRFEA \ 78 SAM_PINMUX(a, 3, b, periph) 79 80 /* pa3b_adc_ain1 */ 81 #define PA3B_ADC_AIN1 \ 82 SAM_PINMUX(a, 3, b, periph) 83 84 /* pa3b_ptc_y1 */ 85 #define PA3B_PTC_Y1 \ 86 SAM_PINMUX(a, 3, b, periph) 87 88 /* pa4_gpio */ 89 #define PA4_GPIO \ 90 SAM_PINMUX(a, 4, gpio, gpio) 91 92 /* pa4a_eic_extint4 */ 93 #define PA4A_EIC_EXTINT4 \ 94 SAM_PINMUX(a, 4, a, periph) 95 96 /* pa4b_adc_vrefb */ 97 #define PA4B_ADC_VREFB \ 98 SAM_PINMUX(a, 4, b, periph) 99 100 /* pa4b_adc_ain4 */ 101 #define PA4B_ADC_AIN4 \ 102 SAM_PINMUX(a, 4, b, periph) 103 104 /* pa4b_ac_ain0 */ 105 #define PA4B_AC_AIN0 \ 106 SAM_PINMUX(a, 4, b, periph) 107 108 /* pa4b_ptc_y2 */ 109 #define PA4B_PTC_Y2 \ 110 SAM_PINMUX(a, 4, b, periph) 111 112 /* pa4d_sercom0_pad0 */ 113 #define PA4D_SERCOM0_PAD0 \ 114 SAM_PINMUX(a, 4, d, periph) 115 116 /* pa4f_tc0_wo0 */ 117 #define PA4F_TC0_WO0 \ 118 SAM_PINMUX(a, 4, f, periph) 119 120 /* pa5_gpio */ 121 #define PA5_GPIO \ 122 SAM_PINMUX(a, 5, gpio, gpio) 123 124 /* pa5a_eic_extint5 */ 125 #define PA5A_EIC_EXTINT5 \ 126 SAM_PINMUX(a, 5, a, periph) 127 128 /* pa5b_adc_ain5 */ 129 #define PA5B_ADC_AIN5 \ 130 SAM_PINMUX(a, 5, b, periph) 131 132 /* pa5b_ac_ain1 */ 133 #define PA5B_AC_AIN1 \ 134 SAM_PINMUX(a, 5, b, periph) 135 136 /* pa5b_ptc_y3 */ 137 #define PA5B_PTC_Y3 \ 138 SAM_PINMUX(a, 5, b, periph) 139 140 /* pa5d_sercom0_pad1 */ 141 #define PA5D_SERCOM0_PAD1 \ 142 SAM_PINMUX(a, 5, d, periph) 143 144 /* pa5f_tc0_wo1 */ 145 #define PA5F_TC0_WO1 \ 146 SAM_PINMUX(a, 5, f, periph) 147 148 /* pa6_gpio */ 149 #define PA6_GPIO \ 150 SAM_PINMUX(a, 6, gpio, gpio) 151 152 /* pa6a_eic_extint6 */ 153 #define PA6A_EIC_EXTINT6 \ 154 SAM_PINMUX(a, 6, a, periph) 155 156 /* pa6b_adc_ain6 */ 157 #define PA6B_ADC_AIN6 \ 158 SAM_PINMUX(a, 6, b, periph) 159 160 /* pa6b_ac_ain2 */ 161 #define PA6B_AC_AIN2 \ 162 SAM_PINMUX(a, 6, b, periph) 163 164 /* pa6b_ptc_y4 */ 165 #define PA6B_PTC_Y4 \ 166 SAM_PINMUX(a, 6, b, periph) 167 168 /* pa6d_sercom0_pad2 */ 169 #define PA6D_SERCOM0_PAD2 \ 170 SAM_PINMUX(a, 6, d, periph) 171 172 /* pa6f_tc1_wo0 */ 173 #define PA6F_TC1_WO0 \ 174 SAM_PINMUX(a, 6, f, periph) 175 176 /* pa7_gpio */ 177 #define PA7_GPIO \ 178 SAM_PINMUX(a, 7, gpio, gpio) 179 180 /* pa7a_eic_extint7 */ 181 #define PA7A_EIC_EXTINT7 \ 182 SAM_PINMUX(a, 7, a, periph) 183 184 /* pa7b_adc_ain7 */ 185 #define PA7B_ADC_AIN7 \ 186 SAM_PINMUX(a, 7, b, periph) 187 188 /* pa7b_ac_ain3 */ 189 #define PA7B_AC_AIN3 \ 190 SAM_PINMUX(a, 7, b, periph) 191 192 /* pa7b_ptc_y5 */ 193 #define PA7B_PTC_Y5 \ 194 SAM_PINMUX(a, 7, b, periph) 195 196 /* pa7d_sercom0_pad3 */ 197 #define PA7D_SERCOM0_PAD3 \ 198 SAM_PINMUX(a, 7, d, periph) 199 200 /* pa7f_tc1_wo1 */ 201 #define PA7F_TC1_WO1 \ 202 SAM_PINMUX(a, 7, f, periph) 203 204 /* pa8_gpio */ 205 #define PA8_GPIO \ 206 SAM_PINMUX(a, 8, gpio, gpio) 207 208 /* pa8a_eic_nmi */ 209 #define PA8A_EIC_NMI \ 210 SAM_PINMUX(a, 8, a, periph) 211 212 /* pa8b_adc_ain16 */ 213 #define PA8B_ADC_AIN16 \ 214 SAM_PINMUX(a, 8, b, periph) 215 216 /* pa8b_ptc_x0 */ 217 #define PA8B_PTC_X0 \ 218 SAM_PINMUX(a, 8, b, periph) 219 220 /* pa8c_sercom0_pad0 */ 221 #define PA8C_SERCOM0_PAD0 \ 222 SAM_PINMUX(a, 8, c, periph) 223 224 /* pa8d_sercom2_pad0 */ 225 #define PA8D_SERCOM2_PAD0 \ 226 SAM_PINMUX(a, 8, d, periph) 227 228 /* pa8e_tc0_wo0 */ 229 #define PA8E_TC0_WO0 \ 230 SAM_PINMUX(a, 8, e, periph) 231 232 /* pa9_gpio */ 233 #define PA9_GPIO \ 234 SAM_PINMUX(a, 9, gpio, gpio) 235 236 /* pa9a_eic_extint9 */ 237 #define PA9A_EIC_EXTINT9 \ 238 SAM_PINMUX(a, 9, a, periph) 239 240 /* pa9b_adc_ain17 */ 241 #define PA9B_ADC_AIN17 \ 242 SAM_PINMUX(a, 9, b, periph) 243 244 /* pa9b_ptc_x1 */ 245 #define PA9B_PTC_X1 \ 246 SAM_PINMUX(a, 9, b, periph) 247 248 /* pa9c_sercom0_pad1 */ 249 #define PA9C_SERCOM0_PAD1 \ 250 SAM_PINMUX(a, 9, c, periph) 251 252 /* pa9d_sercom2_pad1 */ 253 #define PA9D_SERCOM2_PAD1 \ 254 SAM_PINMUX(a, 9, d, periph) 255 256 /* pa9e_tc0_wo1 */ 257 #define PA9E_TC0_WO1 \ 258 SAM_PINMUX(a, 9, e, periph) 259 260 /* pa10_gpio */ 261 #define PA10_GPIO \ 262 SAM_PINMUX(a, 10, gpio, gpio) 263 264 /* pa10a_eic_extint10 */ 265 #define PA10A_EIC_EXTINT10 \ 266 SAM_PINMUX(a, 10, a, periph) 267 268 /* pa10b_adc_ain18 */ 269 #define PA10B_ADC_AIN18 \ 270 SAM_PINMUX(a, 10, b, periph) 271 272 /* pa10b_ptc_x2 */ 273 #define PA10B_PTC_X2 \ 274 SAM_PINMUX(a, 10, b, periph) 275 276 /* pa10c_sercom0_pad2 */ 277 #define PA10C_SERCOM0_PAD2 \ 278 SAM_PINMUX(a, 10, c, periph) 279 280 /* pa10d_sercom2_pad2 */ 281 #define PA10D_SERCOM2_PAD2 \ 282 SAM_PINMUX(a, 10, d, periph) 283 284 /* pa10e_tc1_wo0 */ 285 #define PA10E_TC1_WO0 \ 286 SAM_PINMUX(a, 10, e, periph) 287 288 /* pa10h_gclk_io4 */ 289 #define PA10H_GCLK_IO4 \ 290 SAM_PINMUX(a, 10, h, periph) 291 292 /* pa11_gpio */ 293 #define PA11_GPIO \ 294 SAM_PINMUX(a, 11, gpio, gpio) 295 296 /* pa11a_eic_extint11 */ 297 #define PA11A_EIC_EXTINT11 \ 298 SAM_PINMUX(a, 11, a, periph) 299 300 /* pa11b_adc_ain19 */ 301 #define PA11B_ADC_AIN19 \ 302 SAM_PINMUX(a, 11, b, periph) 303 304 /* pa11b_ptc_x3 */ 305 #define PA11B_PTC_X3 \ 306 SAM_PINMUX(a, 11, b, periph) 307 308 /* pa11c_sercom0_pad3 */ 309 #define PA11C_SERCOM0_PAD3 \ 310 SAM_PINMUX(a, 11, c, periph) 311 312 /* pa11d_sercom2_pad3 */ 313 #define PA11D_SERCOM2_PAD3 \ 314 SAM_PINMUX(a, 11, d, periph) 315 316 /* pa11e_tc1_wo1 */ 317 #define PA11E_TC1_WO1 \ 318 SAM_PINMUX(a, 11, e, periph) 319 320 /* pa11h_gclk_io5 */ 321 #define PA11H_GCLK_IO5 \ 322 SAM_PINMUX(a, 11, h, periph) 323 324 /* pa12_gpio */ 325 #define PA12_GPIO \ 326 SAM_PINMUX(a, 12, gpio, gpio) 327 328 /* pa12a_eic_extint12 */ 329 #define PA12A_EIC_EXTINT12 \ 330 SAM_PINMUX(a, 12, a, periph) 331 332 /* pa12c_sercom2_pad0 */ 333 #define PA12C_SERCOM2_PAD0 \ 334 SAM_PINMUX(a, 12, c, periph) 335 336 /* pa12d_sercom4_pad0 */ 337 #define PA12D_SERCOM4_PAD0 \ 338 SAM_PINMUX(a, 12, d, periph) 339 340 /* pa12e_tc2_wo0 */ 341 #define PA12E_TC2_WO0 \ 342 SAM_PINMUX(a, 12, e, periph) 343 344 /* pa12h_ac_cmp0 */ 345 #define PA12H_AC_CMP0 \ 346 SAM_PINMUX(a, 12, h, periph) 347 348 /* pa13_gpio */ 349 #define PA13_GPIO \ 350 SAM_PINMUX(a, 13, gpio, gpio) 351 352 /* pa13a_eic_extint13 */ 353 #define PA13A_EIC_EXTINT13 \ 354 SAM_PINMUX(a, 13, a, periph) 355 356 /* pa13c_sercom2_pad1 */ 357 #define PA13C_SERCOM2_PAD1 \ 358 SAM_PINMUX(a, 13, c, periph) 359 360 /* pa13d_sercom4_pad1 */ 361 #define PA13D_SERCOM4_PAD1 \ 362 SAM_PINMUX(a, 13, d, periph) 363 364 /* pa13e_tc2_wo1 */ 365 #define PA13E_TC2_WO1 \ 366 SAM_PINMUX(a, 13, e, periph) 367 368 /* pa13h_ac_cmp1 */ 369 #define PA13H_AC_CMP1 \ 370 SAM_PINMUX(a, 13, h, periph) 371 372 /* pa14_gpio */ 373 #define PA14_GPIO \ 374 SAM_PINMUX(a, 14, gpio, gpio) 375 376 /* pa14a_eic_extint14 */ 377 #define PA14A_EIC_EXTINT14 \ 378 SAM_PINMUX(a, 14, a, periph) 379 380 /* pa14c_sercom2_pad2 */ 381 #define PA14C_SERCOM2_PAD2 \ 382 SAM_PINMUX(a, 14, c, periph) 383 384 /* pa14d_sercom4_pad2 */ 385 #define PA14D_SERCOM4_PAD2 \ 386 SAM_PINMUX(a, 14, d, periph) 387 388 /* pa14e_tc3_wo0 */ 389 #define PA14E_TC3_WO0 \ 390 SAM_PINMUX(a, 14, e, periph) 391 392 /* pa14h_gclk_io0 */ 393 #define PA14H_GCLK_IO0 \ 394 SAM_PINMUX(a, 14, h, periph) 395 396 /* pa15_gpio */ 397 #define PA15_GPIO \ 398 SAM_PINMUX(a, 15, gpio, gpio) 399 400 /* pa15a_eic_extint15 */ 401 #define PA15A_EIC_EXTINT15 \ 402 SAM_PINMUX(a, 15, a, periph) 403 404 /* pa15c_sercom2_pad3 */ 405 #define PA15C_SERCOM2_PAD3 \ 406 SAM_PINMUX(a, 15, c, periph) 407 408 /* pa15d_sercom4_pad3 */ 409 #define PA15D_SERCOM4_PAD3 \ 410 SAM_PINMUX(a, 15, d, periph) 411 412 /* pa15e_tc3_wo1 */ 413 #define PA15E_TC3_WO1 \ 414 SAM_PINMUX(a, 15, e, periph) 415 416 /* pa15h_gclk_io1 */ 417 #define PA15H_GCLK_IO1 \ 418 SAM_PINMUX(a, 15, h, periph) 419 420 /* pa16_gpio */ 421 #define PA16_GPIO \ 422 SAM_PINMUX(a, 16, gpio, gpio) 423 424 /* pa16a_eic_extint0 */ 425 #define PA16A_EIC_EXTINT0 \ 426 SAM_PINMUX(a, 16, a, periph) 427 428 /* pa16b_ptc_x4 */ 429 #define PA16B_PTC_X4 \ 430 SAM_PINMUX(a, 16, b, periph) 431 432 /* pa16c_sercom1_pad0 */ 433 #define PA16C_SERCOM1_PAD0 \ 434 SAM_PINMUX(a, 16, c, periph) 435 436 /* pa16d_sercom3_pad0 */ 437 #define PA16D_SERCOM3_PAD0 \ 438 SAM_PINMUX(a, 16, d, periph) 439 440 /* pa16f_tc2_wo0 */ 441 #define PA16F_TC2_WO0 \ 442 SAM_PINMUX(a, 16, f, periph) 443 444 /* pa16h_gclk_io2 */ 445 #define PA16H_GCLK_IO2 \ 446 SAM_PINMUX(a, 16, h, periph) 447 448 /* pa17_gpio */ 449 #define PA17_GPIO \ 450 SAM_PINMUX(a, 17, gpio, gpio) 451 452 /* pa17a_eic_extint1 */ 453 #define PA17A_EIC_EXTINT1 \ 454 SAM_PINMUX(a, 17, a, periph) 455 456 /* pa17b_ptc_x5 */ 457 #define PA17B_PTC_X5 \ 458 SAM_PINMUX(a, 17, b, periph) 459 460 /* pa17c_sercom1_pad1 */ 461 #define PA17C_SERCOM1_PAD1 \ 462 SAM_PINMUX(a, 17, c, periph) 463 464 /* pa17d_sercom3_pad1 */ 465 #define PA17D_SERCOM3_PAD1 \ 466 SAM_PINMUX(a, 17, d, periph) 467 468 /* pa17f_tc2_wo1 */ 469 #define PA17F_TC2_WO1 \ 470 SAM_PINMUX(a, 17, f, periph) 471 472 /* pa17h_gclk_io3 */ 473 #define PA17H_GCLK_IO3 \ 474 SAM_PINMUX(a, 17, h, periph) 475 476 /* pa18_gpio */ 477 #define PA18_GPIO \ 478 SAM_PINMUX(a, 18, gpio, gpio) 479 480 /* pa18a_eic_extint2 */ 481 #define PA18A_EIC_EXTINT2 \ 482 SAM_PINMUX(a, 18, a, periph) 483 484 /* pa18b_ptc_x6 */ 485 #define PA18B_PTC_X6 \ 486 SAM_PINMUX(a, 18, b, periph) 487 488 /* pa18c_sercom1_pad2 */ 489 #define PA18C_SERCOM1_PAD2 \ 490 SAM_PINMUX(a, 18, c, periph) 491 492 /* pa18d_sercom3_pad2 */ 493 #define PA18D_SERCOM3_PAD2 \ 494 SAM_PINMUX(a, 18, d, periph) 495 496 /* pa18f_tc3_wo0 */ 497 #define PA18F_TC3_WO0 \ 498 SAM_PINMUX(a, 18, f, periph) 499 500 /* pa18h_ac_cmp0 */ 501 #define PA18H_AC_CMP0 \ 502 SAM_PINMUX(a, 18, h, periph) 503 504 /* pa19_gpio */ 505 #define PA19_GPIO \ 506 SAM_PINMUX(a, 19, gpio, gpio) 507 508 /* pa19a_eic_extint3 */ 509 #define PA19A_EIC_EXTINT3 \ 510 SAM_PINMUX(a, 19, a, periph) 511 512 /* pa19b_ptc_x7 */ 513 #define PA19B_PTC_X7 \ 514 SAM_PINMUX(a, 19, b, periph) 515 516 /* pa19c_sercom1_pad3 */ 517 #define PA19C_SERCOM1_PAD3 \ 518 SAM_PINMUX(a, 19, c, periph) 519 520 /* pa19d_sercom3_pad3 */ 521 #define PA19D_SERCOM3_PAD3 \ 522 SAM_PINMUX(a, 19, d, periph) 523 524 /* pa19f_tc3_wo1 */ 525 #define PA19F_TC3_WO1 \ 526 SAM_PINMUX(a, 19, f, periph) 527 528 /* pa19g_iis0_sd */ 529 #define PA19G_IIS0_SD \ 530 SAM_PINMUX(a, 19, g, periph) 531 532 /* pa19h_ac_cmp1 */ 533 #define PA19H_AC_CMP1 \ 534 SAM_PINMUX(a, 19, h, periph) 535 536 /* pa20_gpio */ 537 #define PA20_GPIO \ 538 SAM_PINMUX(a, 20, gpio, gpio) 539 540 /* pa20a_eic_extint4 */ 541 #define PA20A_EIC_EXTINT4 \ 542 SAM_PINMUX(a, 20, a, periph) 543 544 /* pa20b_ptc_x8 */ 545 #define PA20B_PTC_X8 \ 546 SAM_PINMUX(a, 20, b, periph) 547 548 /* pa20c_sercom5_pad2 */ 549 #define PA20C_SERCOM5_PAD2 \ 550 SAM_PINMUX(a, 20, c, periph) 551 552 /* pa20d_sercom3_pad2 */ 553 #define PA20D_SERCOM3_PAD2 \ 554 SAM_PINMUX(a, 20, d, periph) 555 556 /* pa20e_tc7_wo0 */ 557 #define PA20E_TC7_WO0 \ 558 SAM_PINMUX(a, 20, e, periph) 559 560 /* pa20h_gclk_io4 */ 561 #define PA20H_GCLK_IO4 \ 562 SAM_PINMUX(a, 20, h, periph) 563 564 /* pa21_gpio */ 565 #define PA21_GPIO \ 566 SAM_PINMUX(a, 21, gpio, gpio) 567 568 /* pa21a_eic_extint5 */ 569 #define PA21A_EIC_EXTINT5 \ 570 SAM_PINMUX(a, 21, a, periph) 571 572 /* pa21b_ptc_x9 */ 573 #define PA21B_PTC_X9 \ 574 SAM_PINMUX(a, 21, b, periph) 575 576 /* pa21c_sercom5_pad3 */ 577 #define PA21C_SERCOM5_PAD3 \ 578 SAM_PINMUX(a, 21, c, periph) 579 580 /* pa21d_sercom3_pad3 */ 581 #define PA21D_SERCOM3_PAD3 \ 582 SAM_PINMUX(a, 21, d, periph) 583 584 /* pa21e_tc7_wo1 */ 585 #define PA21E_TC7_WO1 \ 586 SAM_PINMUX(a, 21, e, periph) 587 588 /* pa21h_gclk_io5 */ 589 #define PA21H_GCLK_IO5 \ 590 SAM_PINMUX(a, 21, h, periph) 591 592 /* pa22_gpio */ 593 #define PA22_GPIO \ 594 SAM_PINMUX(a, 22, gpio, gpio) 595 596 /* pa22a_eic_extint6 */ 597 #define PA22A_EIC_EXTINT6 \ 598 SAM_PINMUX(a, 22, a, periph) 599 600 /* pa22b_ptc_x10 */ 601 #define PA22B_PTC_X10 \ 602 SAM_PINMUX(a, 22, b, periph) 603 604 /* pa22c_sercom3_pad0 */ 605 #define PA22C_SERCOM3_PAD0 \ 606 SAM_PINMUX(a, 22, c, periph) 607 608 /* pa22d_sercom5_pad0 */ 609 #define PA22D_SERCOM5_PAD0 \ 610 SAM_PINMUX(a, 22, d, periph) 611 612 /* pa22f_tc4_wo0 */ 613 #define PA22F_TC4_WO0 \ 614 SAM_PINMUX(a, 22, f, periph) 615 616 /* pa22h_gclk_io6 */ 617 #define PA22H_GCLK_IO6 \ 618 SAM_PINMUX(a, 22, h, periph) 619 620 /* pa23_gpio */ 621 #define PA23_GPIO \ 622 SAM_PINMUX(a, 23, gpio, gpio) 623 624 /* pa23a_eic_extint7 */ 625 #define PA23A_EIC_EXTINT7 \ 626 SAM_PINMUX(a, 23, a, periph) 627 628 /* pa23b_ptc_x11 */ 629 #define PA23B_PTC_X11 \ 630 SAM_PINMUX(a, 23, b, periph) 631 632 /* pa23c_sercom3_pad1 */ 633 #define PA23C_SERCOM3_PAD1 \ 634 SAM_PINMUX(a, 23, c, periph) 635 636 /* pa23d_sercom5_pad1 */ 637 #define PA23D_SERCOM5_PAD1 \ 638 SAM_PINMUX(a, 23, d, periph) 639 640 /* pa23f_tc4_wo1 */ 641 #define PA23F_TC4_WO1 \ 642 SAM_PINMUX(a, 23, f, periph) 643 644 /* pa23h_gclk_io7 */ 645 #define PA23H_GCLK_IO7 \ 646 SAM_PINMUX(a, 23, h, periph) 647 648 /* pa24_gpio */ 649 #define PA24_GPIO \ 650 SAM_PINMUX(a, 24, gpio, gpio) 651 652 /* pa24a_eic_extint12 */ 653 #define PA24A_EIC_EXTINT12 \ 654 SAM_PINMUX(a, 24, a, periph) 655 656 /* pa24c_sercom3_pad2 */ 657 #define PA24C_SERCOM3_PAD2 \ 658 SAM_PINMUX(a, 24, c, periph) 659 660 /* pa24d_sercom5_pad2 */ 661 #define PA24D_SERCOM5_PAD2 \ 662 SAM_PINMUX(a, 24, d, periph) 663 664 /* pa24f_tc5_wo0 */ 665 #define PA24F_TC5_WO0 \ 666 SAM_PINMUX(a, 24, f, periph) 667 668 /* pa25_gpio */ 669 #define PA25_GPIO \ 670 SAM_PINMUX(a, 25, gpio, gpio) 671 672 /* pa25a_eic_extint13 */ 673 #define PA25A_EIC_EXTINT13 \ 674 SAM_PINMUX(a, 25, a, periph) 675 676 /* pa25c_sercom3_pad3 */ 677 #define PA25C_SERCOM3_PAD3 \ 678 SAM_PINMUX(a, 25, c, periph) 679 680 /* pa25d_sercom5_pad3 */ 681 #define PA25D_SERCOM5_PAD3 \ 682 SAM_PINMUX(a, 25, d, periph) 683 684 /* pa25f_tc5_wo1 */ 685 #define PA25F_TC5_WO1 \ 686 SAM_PINMUX(a, 25, f, periph) 687 688 /* pa27_gpio */ 689 #define PA27_GPIO \ 690 SAM_PINMUX(a, 27, gpio, gpio) 691 692 /* pa27a_eic_extint15 */ 693 #define PA27A_EIC_EXTINT15 \ 694 SAM_PINMUX(a, 27, a, periph) 695 696 /* pa27h_gclk_io0 */ 697 #define PA27H_GCLK_IO0 \ 698 SAM_PINMUX(a, 27, h, periph) 699 700 /* pa28_gpio */ 701 #define PA28_GPIO \ 702 SAM_PINMUX(a, 28, gpio, gpio) 703 704 /* pa28a_eic_extint8 */ 705 #define PA28A_EIC_EXTINT8 \ 706 SAM_PINMUX(a, 28, a, periph) 707 708 /* pa28h_gclk_io0 */ 709 #define PA28H_GCLK_IO0 \ 710 SAM_PINMUX(a, 28, h, periph) 711 712 /* pa30_gpio */ 713 #define PA30_GPIO \ 714 SAM_PINMUX(a, 30, gpio, gpio) 715 716 /* pa30a_eic_extint10 */ 717 #define PA30A_EIC_EXTINT10 \ 718 SAM_PINMUX(a, 30, a, periph) 719 720 /* pa30d_sercom1_pad2 */ 721 #define PA30D_SERCOM1_PAD2 \ 722 SAM_PINMUX(a, 30, d, periph) 723 724 /* pa30f_tc1_wo0 */ 725 #define PA30F_TC1_WO0 \ 726 SAM_PINMUX(a, 30, f, periph) 727 728 /* pa30g_swd_clk */ 729 #define PA30G_SWD_CLK \ 730 SAM_PINMUX(a, 30, g, periph) 731 732 /* pa30h_gclk_io0 */ 733 #define PA30H_GCLK_IO0 \ 734 SAM_PINMUX(a, 30, h, periph) 735 736 /* pa31_gpio */ 737 #define PA31_GPIO \ 738 SAM_PINMUX(a, 31, gpio, gpio) 739 740 /* pa31a_eic_extint11 */ 741 #define PA31A_EIC_EXTINT11 \ 742 SAM_PINMUX(a, 31, a, periph) 743 744 /* pa31d_sercom1_pad3 */ 745 #define PA31D_SERCOM1_PAD3 \ 746 SAM_PINMUX(a, 31, d, periph) 747 748 /* pa31f_tc1_wo1 */ 749 #define PA31F_TC1_WO1 \ 750 SAM_PINMUX(a, 31, f, periph) 751 752 /* pa31g_swd_io */ 753 #define PA31G_SWD_IO \ 754 SAM_PINMUX(a, 31, g, periph) 755 756 /* pb2_gpio */ 757 #define PB2_GPIO \ 758 SAM_PINMUX(b, 2, gpio, gpio) 759 760 /* pb2a_eic_extint2 */ 761 #define PB2A_EIC_EXTINT2 \ 762 SAM_PINMUX(b, 2, a, periph) 763 764 /* pb2b_adc_ain10 */ 765 #define PB2B_ADC_AIN10 \ 766 SAM_PINMUX(b, 2, b, periph) 767 768 /* pb2b_ptc_y8 */ 769 #define PB2B_PTC_Y8 \ 770 SAM_PINMUX(b, 2, b, periph) 771 772 /* pb2d_sercom5_pad0 */ 773 #define PB2D_SERCOM5_PAD0 \ 774 SAM_PINMUX(b, 2, d, periph) 775 776 /* pb2f_tc6_wo0 */ 777 #define PB2F_TC6_WO0 \ 778 SAM_PINMUX(b, 2, f, periph) 779 780 /* pb3_gpio */ 781 #define PB3_GPIO \ 782 SAM_PINMUX(b, 3, gpio, gpio) 783 784 /* pb3a_eic_extint3 */ 785 #define PB3A_EIC_EXTINT3 \ 786 SAM_PINMUX(b, 3, a, periph) 787 788 /* pb3b_adc_ain11 */ 789 #define PB3B_ADC_AIN11 \ 790 SAM_PINMUX(b, 3, b, periph) 791 792 /* pb3b_ptc_y9 */ 793 #define PB3B_PTC_Y9 \ 794 SAM_PINMUX(b, 3, b, periph) 795 796 /* pb3d_sercom5_pad1 */ 797 #define PB3D_SERCOM5_PAD1 \ 798 SAM_PINMUX(b, 3, d, periph) 799 800 /* pb3f_tc6_wo1 */ 801 #define PB3F_TC6_WO1 \ 802 SAM_PINMUX(b, 3, f, periph) 803 804 /* pb8_gpio */ 805 #define PB8_GPIO \ 806 SAM_PINMUX(b, 8, gpio, gpio) 807 808 /* pb8a_eic_extint8 */ 809 #define PB8A_EIC_EXTINT8 \ 810 SAM_PINMUX(b, 8, a, periph) 811 812 /* pb8b_adc_ain2 */ 813 #define PB8B_ADC_AIN2 \ 814 SAM_PINMUX(b, 8, b, periph) 815 816 /* pb8b_ptc_y14 */ 817 #define PB8B_PTC_Y14 \ 818 SAM_PINMUX(b, 8, b, periph) 819 820 /* pb8d_sercom4_pad0 */ 821 #define PB8D_SERCOM4_PAD0 \ 822 SAM_PINMUX(b, 8, d, periph) 823 824 /* pb8f_tc4_wo0 */ 825 #define PB8F_TC4_WO0 \ 826 SAM_PINMUX(b, 8, f, periph) 827 828 /* pb9_gpio */ 829 #define PB9_GPIO \ 830 SAM_PINMUX(b, 9, gpio, gpio) 831 832 /* pb9a_eic_extint9 */ 833 #define PB9A_EIC_EXTINT9 \ 834 SAM_PINMUX(b, 9, a, periph) 835 836 /* pb9b_adc_ain3 */ 837 #define PB9B_ADC_AIN3 \ 838 SAM_PINMUX(b, 9, b, periph) 839 840 /* pb9b_ptc_y15 */ 841 #define PB9B_PTC_Y15 \ 842 SAM_PINMUX(b, 9, b, periph) 843 844 /* pb9d_sercom4_pad1 */ 845 #define PB9D_SERCOM4_PAD1 \ 846 SAM_PINMUX(b, 9, d, periph) 847 848 /* pb9f_tc4_wo1 */ 849 #define PB9F_TC4_WO1 \ 850 SAM_PINMUX(b, 9, f, periph) 851 852 /* pb10_gpio */ 853 #define PB10_GPIO \ 854 SAM_PINMUX(b, 10, gpio, gpio) 855 856 /* pb10a_eic_extint10 */ 857 #define PB10A_EIC_EXTINT10 \ 858 SAM_PINMUX(b, 10, a, periph) 859 860 /* pb10d_sercom4_pad2 */ 861 #define PB10D_SERCOM4_PAD2 \ 862 SAM_PINMUX(b, 10, d, periph) 863 864 /* pb10f_tc5_wo0 */ 865 #define PB10F_TC5_WO0 \ 866 SAM_PINMUX(b, 10, f, periph) 867 868 /* pb10h_gclk_io4 */ 869 #define PB10H_GCLK_IO4 \ 870 SAM_PINMUX(b, 10, h, periph) 871 872 /* pb11_gpio */ 873 #define PB11_GPIO \ 874 SAM_PINMUX(b, 11, gpio, gpio) 875 876 /* pb11a_eic_extint11 */ 877 #define PB11A_EIC_EXTINT11 \ 878 SAM_PINMUX(b, 11, a, periph) 879 880 /* pb11d_sercom4_pad3 */ 881 #define PB11D_SERCOM4_PAD3 \ 882 SAM_PINMUX(b, 11, d, periph) 883 884 /* pb11f_tc5_wo1 */ 885 #define PB11F_TC5_WO1 \ 886 SAM_PINMUX(b, 11, f, periph) 887 888 /* pb11h_gclk_io5 */ 889 #define PB11H_GCLK_IO5 \ 890 SAM_PINMUX(b, 11, h, periph) 891 892 /* pb22_gpio */ 893 #define PB22_GPIO \ 894 SAM_PINMUX(b, 22, gpio, gpio) 895 896 /* pb22a_eic_extint6 */ 897 #define PB22A_EIC_EXTINT6 \ 898 SAM_PINMUX(b, 22, a, periph) 899 900 /* pb22d_sercom5_pad2 */ 901 #define PB22D_SERCOM5_PAD2 \ 902 SAM_PINMUX(b, 22, d, periph) 903 904 /* pb22f_tc7_wo0 */ 905 #define PB22F_TC7_WO0 \ 906 SAM_PINMUX(b, 22, f, periph) 907 908 /* pb22h_gclk_io0 */ 909 #define PB22H_GCLK_IO0 \ 910 SAM_PINMUX(b, 22, h, periph) 911 912 /* pb23_gpio */ 913 #define PB23_GPIO \ 914 SAM_PINMUX(b, 23, gpio, gpio) 915 916 /* pb23a_eic_extint7 */ 917 #define PB23A_EIC_EXTINT7 \ 918 SAM_PINMUX(b, 23, a, periph) 919 920 /* pb23d_sercom5_pad3 */ 921 #define PB23D_SERCOM5_PAD3 \ 922 SAM_PINMUX(b, 23, d, periph) 923 924 /* pb23f_tc7_wo1 */ 925 #define PB23F_TC7_WO1 \ 926 SAM_PINMUX(b, 23, f, periph) 927 928 /* pb23h_gclk_io1 */ 929 #define PB23H_GCLK_IO1 \ 930 SAM_PINMUX(b, 23, h, periph) 931
