1 /** 2 * \file 3 * 4 * \brief Header file for SAMR35J18B 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMR35J18B_ 31 #define _SAMR35J18B_ 32 33 /** 34 * \ingroup SAMR35_definitions 35 * \addtogroup SAMR35J18B_definitions SAMR35J18B definitions 36 * This file defines all structures and symbols for SAMR35J18B: 37 * - registers and bitfields 38 * - peripheral base address 39 * - peripheral ID 40 * - PIO definitions 41 */ 42 /*@{*/ 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 #include <stdint.h> 50 #ifndef __cplusplus 51 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 52 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 53 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 54 #else 55 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 56 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 57 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 58 #endif 59 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 60 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 61 typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 62 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 63 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 64 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 65 #endif 66 67 #if !defined(SKIP_INTEGER_LITERALS) 68 #if defined(_U_) || defined(_L_) || defined(_UL_) 69 #error "Integer Literals macros already defined elsewhere" 70 #endif 71 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */ 74 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 75 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 76 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 77 #else /* Assembler */ 78 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 79 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 80 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 #endif /* SKIP_INTEGER_LITERALS */ 83 84 /* ************************************************************************** */ 85 /** CMSIS DEFINITIONS FOR SAMR35J18B */ 86 /* ************************************************************************** */ 87 /** \defgroup SAMR35J18B_cmsis CMSIS Definitions */ 88 /*@{*/ 89 90 /** Interrupt Number Definition */ 91 typedef enum IRQn 92 { 93 /****** Cortex-M0+ Processor Exceptions Numbers *******************/ 94 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 95 HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ 96 SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ 97 PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ 98 SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ 99 /****** SAMR35J18B-specific Interrupt Numbers *********************/ 100 SYSTEM_IRQn = 0, /**< 0 SAMR35J18B System Interrupts */ 101 WDT_IRQn = 1, /**< 1 SAMR35J18B Watchdog Timer (WDT) */ 102 RTC_IRQn = 2, /**< 2 SAMR35J18B Real-Time Counter (RTC) */ 103 EIC_IRQn = 3, /**< 3 SAMR35J18B External Interrupt Controller (EIC) */ 104 NVMCTRL_IRQn = 4, /**< 4 SAMR35J18B Non-Volatile Memory Controller (NVMCTRL) */ 105 DMAC_IRQn = 5, /**< 5 SAMR35J18B Direct Memory Access Controller (DMAC) */ 106 EVSYS_IRQn = 7, /**< 7 SAMR35J18B Event System Interface (EVSYS) */ 107 SERCOM0_IRQn = 8, /**< 8 SAMR35J18B Serial Communication Interface 0 (SERCOM0) */ 108 SERCOM1_IRQn = 9, /**< 9 SAMR35J18B Serial Communication Interface 1 (SERCOM1) */ 109 SERCOM2_IRQn = 10, /**< 10 SAMR35J18B Serial Communication Interface 2 (SERCOM2) */ 110 SERCOM3_IRQn = 11, /**< 11 SAMR35J18B Serial Communication Interface 3 (SERCOM3) */ 111 SERCOM4_IRQn = 12, /**< 12 SAMR35J18B Serial Communication Interface 4 (SERCOM4) */ 112 SERCOM5_IRQn = 13, /**< 13 SAMR35J18B Serial Communication Interface 5 (SERCOM5) */ 113 TCC0_IRQn = 14, /**< 14 SAMR35J18B Timer Counter Control 0 (TCC0) */ 114 TCC1_IRQn = 15, /**< 15 SAMR35J18B Timer Counter Control 1 (TCC1) */ 115 TCC2_IRQn = 16, /**< 16 SAMR35J18B Timer Counter Control 2 (TCC2) */ 116 TC0_IRQn = 17, /**< 17 SAMR35J18B Basic Timer Counter 0 (TC0) */ 117 TC1_IRQn = 18, /**< 18 SAMR35J18B Basic Timer Counter 1 (TC1) */ 118 TC2_IRQn = 19, /**< 19 SAMR35J18B Basic Timer Counter 2 (TC2) */ 119 TC3_IRQn = 20, /**< 20 SAMR35J18B Basic Timer Counter 3 (TC3) */ 120 TC4_IRQn = 21, /**< 21 SAMR35J18B Basic Timer Counter 4 (TC4) */ 121 ADC_IRQn = 22, /**< 22 SAMR35J18B Analog Digital Converter (ADC) */ 122 AC_IRQn = 23, /**< 23 SAMR35J18B Analog Comparators (AC) */ 123 DAC_IRQn = 24, /**< 24 SAMR35J18B Digital-to-Analog Converter (DAC) */ 124 PTC_IRQn = 25, /**< 25 SAMR35J18B Peripheral Touch Controller (PTC) */ 125 AES_IRQn = 26, /**< 26 SAMR35J18B Advanced Encryption Standard (AES) */ 126 TRNG_IRQn = 27, /**< 27 SAMR35J18B True Random Generator (TRNG) */ 127 128 PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ 129 } IRQn_Type; 130 131 typedef struct _DeviceVectors 132 { 133 /* Stack pointer */ 134 void* pvStack; 135 136 /* Cortex-M handlers */ 137 void* pfnReset_Handler; 138 void* pfnNonMaskableInt_Handler; 139 void* pfnHardFault_Handler; 140 void* pvReservedM12; 141 void* pvReservedM11; 142 void* pvReservedM10; 143 void* pvReservedM9; 144 void* pvReservedM8; 145 void* pvReservedM7; 146 void* pvReservedM6; 147 void* pfnSVCall_Handler; 148 void* pvReservedM4; 149 void* pvReservedM3; 150 void* pfnPendSV_Handler; 151 void* pfnSysTick_Handler; 152 153 /* Peripheral handlers */ 154 void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ 155 void* pfnWDT_Handler; /* 1 Watchdog Timer */ 156 void* pfnRTC_Handler; /* 2 Real-Time Counter */ 157 void* pfnEIC_Handler; /* 3 External Interrupt Controller */ 158 void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ 159 void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ 160 void* pvReserved6; 161 void* pfnEVSYS_Handler; /* 7 Event System Interface */ 162 void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ 163 void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ 164 void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ 165 void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ 166 void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ 167 void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ 168 void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ 169 void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ 170 void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ 171 void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ 172 void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ 173 void* pfnTC2_Handler; /* 19 Basic Timer Counter 2 */ 174 void* pfnTC3_Handler; /* 20 Basic Timer Counter 3 */ 175 void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ 176 void* pfnADC_Handler; /* 22 Analog Digital Converter */ 177 void* pfnAC_Handler; /* 23 Analog Comparators */ 178 void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ 179 void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ 180 void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ 181 void* pfnTRNG_Handler; /* 27 True Random Generator */ 182 void* pvReserved28; 183 } DeviceVectors; 184 185 /* Cortex-M0+ processor handlers */ 186 void Reset_Handler ( void ); 187 void NonMaskableInt_Handler ( void ); 188 void HardFault_Handler ( void ); 189 void SVCall_Handler ( void ); 190 void PendSV_Handler ( void ); 191 void SysTick_Handler ( void ); 192 193 /* Peripherals handlers */ 194 void SYSTEM_Handler ( void ); 195 void WDT_Handler ( void ); 196 void RTC_Handler ( void ); 197 void EIC_Handler ( void ); 198 void NVMCTRL_Handler ( void ); 199 void DMAC_Handler ( void ); 200 void EVSYS_Handler ( void ); 201 void SERCOM0_Handler ( void ); 202 void SERCOM1_Handler ( void ); 203 void SERCOM2_Handler ( void ); 204 void SERCOM3_Handler ( void ); 205 void SERCOM4_Handler ( void ); 206 void SERCOM5_Handler ( void ); 207 void TCC0_Handler ( void ); 208 void TCC1_Handler ( void ); 209 void TCC2_Handler ( void ); 210 void TC0_Handler ( void ); 211 void TC1_Handler ( void ); 212 void TC2_Handler ( void ); 213 void TC3_Handler ( void ); 214 void TC4_Handler ( void ); 215 void ADC_Handler ( void ); 216 void AC_Handler ( void ); 217 void DAC_Handler ( void ); 218 void PTC_Handler ( void ); 219 void AES_Handler ( void ); 220 void TRNG_Handler ( void ); 221 222 /* 223 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 224 */ 225 226 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 227 #define __MPU_PRESENT 0 /*!< MPU present or not */ 228 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 229 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 230 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 231 232 /** 233 * \brief CMSIS includes 234 */ 235 236 #include <core_cm0plus.h> 237 #if !defined DONT_USE_CMSIS_INIT 238 #include "system_samr35.h" 239 #endif /* DONT_USE_CMSIS_INIT */ 240 241 /*@}*/ 242 243 /* ************************************************************************** */ 244 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMR35J18B */ 245 /* ************************************************************************** */ 246 /** \defgroup SAMR35J18B_api Peripheral Software API */ 247 /*@{*/ 248 249 #include "component/ac.h" 250 #include "component/adc.h" 251 #include "component/aes.h" 252 #include "component/ccl.h" 253 #include "component/dac.h" 254 #include "component/dmac.h" 255 #include "component/dsu.h" 256 #include "component/eic.h" 257 #include "component/evsys.h" 258 #include "component/gclk.h" 259 #include "component/mclk.h" 260 #include "component/mtb.h" 261 #include "component/nvmctrl.h" 262 #include "component/oscctrl.h" 263 #include "component/osc32kctrl.h" 264 #include "component/pac.h" 265 #include "component/pm.h" 266 #include "component/port.h" 267 #include "component/rstc.h" 268 #include "component/rtc.h" 269 #include "component/sercom.h" 270 #include "component/supc.h" 271 #include "component/tc.h" 272 #include "component/tcc.h" 273 #include "component/trng.h" 274 #include "component/wdt.h" 275 /*@}*/ 276 277 /* ************************************************************************** */ 278 /** REGISTERS ACCESS DEFINITIONS FOR SAMR35J18B */ 279 /* ************************************************************************** */ 280 /** \defgroup SAMR35J18B_reg Registers Access Definitions */ 281 /*@{*/ 282 283 #include "instance/ac.h" 284 #include "instance/adc.h" 285 #include "instance/aes.h" 286 #include "instance/ccl.h" 287 #include "instance/dac.h" 288 #include "instance/dmac.h" 289 #include "instance/dsu.h" 290 #include "instance/eic.h" 291 #include "instance/evsys.h" 292 #include "instance/gclk.h" 293 #include "instance/mclk.h" 294 #include "instance/mtb.h" 295 #include "instance/nvmctrl.h" 296 #include "instance/oscctrl.h" 297 #include "instance/osc32kctrl.h" 298 #include "instance/pac.h" 299 #include "instance/pm.h" 300 #include "instance/port.h" 301 #include "instance/ptc.h" 302 #include "instance/rstc.h" 303 #include "instance/rtc.h" 304 #include "instance/sercom0.h" 305 #include "instance/sercom1.h" 306 #include "instance/sercom2.h" 307 #include "instance/sercom3.h" 308 #include "instance/sercom4.h" 309 #include "instance/sercom5.h" 310 #include "instance/supc.h" 311 #include "instance/tc0.h" 312 #include "instance/tc1.h" 313 #include "instance/tc2.h" 314 #include "instance/tc3.h" 315 #include "instance/tc4.h" 316 #include "instance/tcc0.h" 317 #include "instance/tcc1.h" 318 #include "instance/tcc2.h" 319 #include "instance/trng.h" 320 #include "instance/wdt.h" 321 /*@}*/ 322 323 /* ************************************************************************** */ 324 /** PERIPHERAL ID DEFINITIONS FOR SAMR35J18B */ 325 /* ************************************************************************** */ 326 /** \defgroup SAMR35J18B_id Peripheral Ids Definitions */ 327 /*@{*/ 328 329 // Peripheral instances on HPB0 bridge 330 #define ID_PM 0 /**< \brief Power Manager (PM) */ 331 #define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ 332 #define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ 333 #define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ 334 #define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ 335 #define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ 336 #define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ 337 #define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ 338 #define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ 339 #define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ 340 #define ID_PORT 10 /**< \brief Port Module (PORT) */ 341 342 // Peripheral instances on HPB1 bridge 343 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 344 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 345 #define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ 346 347 // Peripheral instances on HPB2 bridge 348 #define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 349 #define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 350 #define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 351 #define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 352 #define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ 353 #define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ 354 #define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ 355 #define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ 356 #define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ 357 #define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ 358 #define ID_TC2 74 /**< \brief Basic Timer Counter 2 (TC2) */ 359 #define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ 360 #define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ 361 #define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ 362 #define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ 363 364 // Peripheral instances on HPB3 bridge 365 #define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ 366 #define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ 367 #define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ 368 #define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ 369 #define ID_AC 100 /**< \brief Analog Comparators (AC) */ 370 #define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ 371 #define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ 372 373 // Peripheral instances on HPB4 bridge 374 #define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ 375 #define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ 376 377 #define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ 378 /*@}*/ 379 380 /* ************************************************************************** */ 381 /** BASE ADDRESS DEFINITIONS FOR SAMR35J18B */ 382 /* ************************************************************************** */ 383 /** \defgroup SAMR35J18B_base Peripheral Base Address Definitions */ 384 /*@{*/ 385 386 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 387 #define AC (0x43001000) /**< \brief (AC) APB Base Address */ 388 #define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ 389 #define AES (0x42003400) /**< \brief (AES) APB Base Address */ 390 #define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ 391 #define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ 392 #define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ 393 #define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ 394 #define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ 395 #define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ 396 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ 397 #define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ 398 #define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ 399 #define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ 400 #define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ 401 #define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 402 #define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ 403 #define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ 404 #define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ 405 #define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ 406 #define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ 407 #define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 408 #define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ 409 #define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ 410 #define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ 411 #define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ 412 #define PM (0x40000000) /**< \brief (PM) APB Base Address */ 413 #define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ 414 #define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ 415 #define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ 416 #define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ 417 #define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ 418 #define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ 419 #define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ 420 #define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ 421 #define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ 422 #define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ 423 #define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ 424 #define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ 425 #define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ 426 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ 427 #define TC2 (0x42002800) /**< \brief (TC2) APB Base Address */ 428 #define TC3 (0x42002C00) /**< \brief (TC3) APB Base Address */ 429 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ 430 #define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ 431 #define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ 432 #define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ 433 #define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ 434 #define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ 435 #else 436 #define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ 437 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 438 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 439 440 #define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ 441 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ 442 #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ 443 444 #define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ 445 #define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ 446 #define AES_INSTS { AES } /**< \brief (AES) Instances List */ 447 448 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ 449 #define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ 450 #define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ 451 452 #define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ 453 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 454 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 455 456 #define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ 457 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ 458 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ 459 460 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 461 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 462 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 463 464 #define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ 465 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 466 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 467 468 #define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ 469 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 470 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 471 472 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ 473 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 474 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 475 476 #define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ 477 #define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ 478 #define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ 479 480 #define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ 481 #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ 482 #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ 483 484 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 485 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 486 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 487 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 488 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 489 #define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ 490 #define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 491 #define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ 492 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 493 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 494 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 495 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 496 497 #define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ 498 #define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ 499 #define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ 500 501 #define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ 502 #define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ 503 #define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ 504 505 #define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ 506 #define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ 507 #define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ 508 509 #define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ 510 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 511 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 512 513 #define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ 514 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 515 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 516 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 517 #define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ 518 #define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ 519 520 #define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ 521 #define PTC_GCLK_ID 33 522 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 523 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 524 525 #define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ 526 #define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ 527 #define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ 528 529 #define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ 530 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 531 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 532 533 #define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ 534 #define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ 535 #define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ 536 #define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ 537 #define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ 538 #define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ 539 #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ 540 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ 541 542 #define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ 543 #define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ 544 #define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ 545 546 #define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ 547 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ 548 #define TC2 ((Tc *)0x42002800UL) /**< \brief (TC2) APB Base Address */ 549 #define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ 550 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ 551 #define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ 552 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */ 553 554 #define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ 555 #define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ 556 #define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ 557 #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ 558 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ 559 560 #define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ 561 #define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ 562 #define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ 563 564 #define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ 565 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 566 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 567 568 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 569 /*@}*/ 570 571 /* ************************************************************************** */ 572 /** PORT DEFINITIONS FOR SAMR35J18B */ 573 /* ************************************************************************** */ 574 /** \defgroup SAMR35J18B_port PORT Definitions */ 575 /*@{*/ 576 577 #include "pio/samr35j18b.h" 578 /*@}*/ 579 580 /* ************************************************************************** */ 581 /** MEMORY MAPPING DEFINITIONS FOR SAMR35J18B */ 582 /* ************************************************************************** */ 583 584 #define FLASH_SIZE _UL_(0x00040000) /* 256 kB */ 585 #define FLASH_PAGE_SIZE 64 586 #define FLASH_NB_OF_PAGES 4096 587 #define FLASH_USER_PAGE_SIZE 64 588 #define HSRAM_SIZE _UL_(0x00008000) /* 32 kB */ 589 #define LPRAM_SIZE _UL_(0x00002000) /* 8 kB */ 590 591 #define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ 592 #define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ 593 #define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ 594 #define LPRAM_ADDR _UL_(0x30000000) /**< LPRAM base address */ 595 #define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ 596 #define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ 597 #define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ 598 #define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ 599 #define HPB4_ADDR _UL_(0x44000000) /**< HPB4 base address */ 600 #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ 601 602 #define DSU_DID_RESETVALUE _UL_(0x1081022B) 603 #define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00002000) /* 8 kB */ 604 #define PORT_GROUPS 3 605 #define SIP_CONFIG SX1276 606 607 /* ************************************************************************** */ 608 /** ELECTRICAL DEFINITIONS FOR SAMR35J18B */ 609 /* ************************************************************************** */ 610 611 612 #ifdef __cplusplus 613 } 614 #endif 615 616 /*@}*/ 617 618 #endif /* SAMR35J18B_H */ 619
