1 /** 2 * \file 3 * 4 * \brief Instance description for WDT 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21_WDT_INSTANCE_ 30 #define _SAMR21_WDT_INSTANCE_ 31 32 /* ========== Register definition for WDT peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_WDT_CTRL (0x40001000) /**< \brief (WDT) Control */ 35 #define REG_WDT_CONFIG (0x40001001) /**< \brief (WDT) Configuration */ 36 #define REG_WDT_EWCTRL (0x40001002) /**< \brief (WDT) Early Warning Interrupt Control */ 37 #define REG_WDT_INTENCLR (0x40001004) /**< \brief (WDT) Interrupt Enable Clear */ 38 #define REG_WDT_INTENSET (0x40001005) /**< \brief (WDT) Interrupt Enable Set */ 39 #define REG_WDT_INTFLAG (0x40001006) /**< \brief (WDT) Interrupt Flag Status and Clear */ 40 #define REG_WDT_STATUS (0x40001007) /**< \brief (WDT) Status */ 41 #define REG_WDT_CLEAR (0x40001008) /**< \brief (WDT) Clear */ 42 #else 43 #define REG_WDT_CTRL (*(RwReg8 *)0x40001000UL) /**< \brief (WDT) Control */ 44 #define REG_WDT_CONFIG (*(RwReg8 *)0x40001001UL) /**< \brief (WDT) Configuration */ 45 #define REG_WDT_EWCTRL (*(RwReg8 *)0x40001002UL) /**< \brief (WDT) Early Warning Interrupt Control */ 46 #define REG_WDT_INTENCLR (*(RwReg8 *)0x40001004UL) /**< \brief (WDT) Interrupt Enable Clear */ 47 #define REG_WDT_INTENSET (*(RwReg8 *)0x40001005UL) /**< \brief (WDT) Interrupt Enable Set */ 48 #define REG_WDT_INTFLAG (*(RwReg8 *)0x40001006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ 49 #define REG_WDT_STATUS (*(RoReg8 *)0x40001007UL) /**< \brief (WDT) Status */ 50 #define REG_WDT_CLEAR (*(WoReg8 *)0x40001008UL) /**< \brief (WDT) Clear */ 51 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 /* ========== Instance parameters for WDT peripheral ========== */ 54 #define WDT_GCLK_ID 3 // Index of Generic Clock 55 56 #endif /* _SAMR21_WDT_INSTANCE_ */ 57
