1 /** 2 * \file 3 * 4 * \brief Component description for DSU 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMR21_DSU_COMPONENT_ 30 #define _SAMR21_DSU_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR DSU */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMR21_DSU Device Service Unit */ 36 /*@{*/ 37 38 #define DSU_U2209 39 #define REV_DSU 0x200 40 41 /* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t :1; /*!< bit: 1 Reserved */ 47 uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */ 48 uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */ 49 uint8_t CE:1; /*!< bit: 4 Chip Erase */ 50 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 51 } bit; /*!< Structure used for bit access */ 52 uint8_t reg; /*!< Type used for register access */ 53 } DSU_CTRL_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define DSU_CTRL_OFFSET 0x0000 /**< \brief (DSU_CTRL offset) Control */ 57 #define DSU_CTRL_RESETVALUE _U_(0x00) /**< \brief (DSU_CTRL reset_value) Control */ 58 59 #define DSU_CTRL_SWRST_Pos 0 /**< \brief (DSU_CTRL) Software Reset */ 60 #define DSU_CTRL_SWRST (_U_(0x1) << DSU_CTRL_SWRST_Pos) 61 #define DSU_CTRL_CRC_Pos 2 /**< \brief (DSU_CTRL) 32-bit Cyclic Redundancy Check */ 62 #define DSU_CTRL_CRC (_U_(0x1) << DSU_CTRL_CRC_Pos) 63 #define DSU_CTRL_MBIST_Pos 3 /**< \brief (DSU_CTRL) Memory Built-In Self-Test */ 64 #define DSU_CTRL_MBIST (_U_(0x1) << DSU_CTRL_MBIST_Pos) 65 #define DSU_CTRL_CE_Pos 4 /**< \brief (DSU_CTRL) Chip Erase */ 66 #define DSU_CTRL_CE (_U_(0x1) << DSU_CTRL_CE_Pos) 67 #define DSU_CTRL_MASK _U_(0x1D) /**< \brief (DSU_CTRL) MASK Register */ 68 69 /* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */ 70 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 71 typedef union { 72 struct { 73 uint8_t DONE:1; /*!< bit: 0 Done */ 74 uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ 75 uint8_t BERR:1; /*!< bit: 2 Bus Error */ 76 uint8_t FAIL:1; /*!< bit: 3 Failure */ 77 uint8_t PERR:1; /*!< bit: 4 Protection Error */ 78 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 79 } bit; /*!< Structure used for bit access */ 80 uint8_t reg; /*!< Type used for register access */ 81 } DSU_STATUSA_Type; 82 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 83 84 #define DSU_STATUSA_OFFSET 0x0001 /**< \brief (DSU_STATUSA offset) Status A */ 85 #define DSU_STATUSA_RESETVALUE _U_(0x00) /**< \brief (DSU_STATUSA reset_value) Status A */ 86 87 #define DSU_STATUSA_DONE_Pos 0 /**< \brief (DSU_STATUSA) Done */ 88 #define DSU_STATUSA_DONE (_U_(0x1) << DSU_STATUSA_DONE_Pos) 89 #define DSU_STATUSA_CRSTEXT_Pos 1 /**< \brief (DSU_STATUSA) CPU Reset Phase Extension */ 90 #define DSU_STATUSA_CRSTEXT (_U_(0x1) << DSU_STATUSA_CRSTEXT_Pos) 91 #define DSU_STATUSA_BERR_Pos 2 /**< \brief (DSU_STATUSA) Bus Error */ 92 #define DSU_STATUSA_BERR (_U_(0x1) << DSU_STATUSA_BERR_Pos) 93 #define DSU_STATUSA_FAIL_Pos 3 /**< \brief (DSU_STATUSA) Failure */ 94 #define DSU_STATUSA_FAIL (_U_(0x1) << DSU_STATUSA_FAIL_Pos) 95 #define DSU_STATUSA_PERR_Pos 4 /**< \brief (DSU_STATUSA) Protection Error */ 96 #define DSU_STATUSA_PERR (_U_(0x1) << DSU_STATUSA_PERR_Pos) 97 #define DSU_STATUSA_MASK _U_(0x1F) /**< \brief (DSU_STATUSA) MASK Register */ 98 99 /* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */ 100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 101 typedef union { 102 struct { 103 uint8_t PROT:1; /*!< bit: 0 Protected */ 104 uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ 105 uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ 106 uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ 107 uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ 108 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 109 } bit; /*!< Structure used for bit access */ 110 struct { 111 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 112 uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ 113 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 114 } vec; /*!< Structure used for vec access */ 115 uint8_t reg; /*!< Type used for register access */ 116 } DSU_STATUSB_Type; 117 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 118 119 #define DSU_STATUSB_OFFSET 0x0002 /**< \brief (DSU_STATUSB offset) Status B */ 120 #define DSU_STATUSB_RESETVALUE _U_(0x10) /**< \brief (DSU_STATUSB reset_value) Status B */ 121 122 #define DSU_STATUSB_PROT_Pos 0 /**< \brief (DSU_STATUSB) Protected */ 123 #define DSU_STATUSB_PROT (_U_(0x1) << DSU_STATUSB_PROT_Pos) 124 #define DSU_STATUSB_DBGPRES_Pos 1 /**< \brief (DSU_STATUSB) Debugger Present */ 125 #define DSU_STATUSB_DBGPRES (_U_(0x1) << DSU_STATUSB_DBGPRES_Pos) 126 #define DSU_STATUSB_DCCD0_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel 0 Dirty */ 127 #define DSU_STATUSB_DCCD0 (1 << DSU_STATUSB_DCCD0_Pos) 128 #define DSU_STATUSB_DCCD1_Pos 3 /**< \brief (DSU_STATUSB) Debug Communication Channel 1 Dirty */ 129 #define DSU_STATUSB_DCCD1 (1 << DSU_STATUSB_DCCD1_Pos) 130 #define DSU_STATUSB_DCCD_Pos 2 /**< \brief (DSU_STATUSB) Debug Communication Channel x Dirty */ 131 #define DSU_STATUSB_DCCD_Msk (_U_(0x3) << DSU_STATUSB_DCCD_Pos) 132 #define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & ((value) << DSU_STATUSB_DCCD_Pos)) 133 #define DSU_STATUSB_HPE_Pos 4 /**< \brief (DSU_STATUSB) Hot-Plugging Enable */ 134 #define DSU_STATUSB_HPE (_U_(0x1) << DSU_STATUSB_HPE_Pos) 135 #define DSU_STATUSB_MASK _U_(0x1F) /**< \brief (DSU_STATUSB) MASK Register */ 136 137 /* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */ 138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 139 typedef union { 140 struct { 141 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 142 uint32_t ADDR:30; /*!< bit: 2..31 Address */ 143 } bit; /*!< Structure used for bit access */ 144 uint32_t reg; /*!< Type used for register access */ 145 } DSU_ADDR_Type; 146 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 147 148 #define DSU_ADDR_OFFSET 0x0004 /**< \brief (DSU_ADDR offset) Address */ 149 #define DSU_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (DSU_ADDR reset_value) Address */ 150 151 #define DSU_ADDR_ADDR_Pos 2 /**< \brief (DSU_ADDR) Address */ 152 #define DSU_ADDR_ADDR_Msk (_U_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos) 153 #define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & ((value) << DSU_ADDR_ADDR_Pos)) 154 #define DSU_ADDR_MASK _U_(0xFFFFFFFC) /**< \brief (DSU_ADDR) MASK Register */ 155 156 /* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */ 157 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 158 typedef union { 159 struct { 160 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 161 uint32_t LENGTH:30; /*!< bit: 2..31 Length */ 162 } bit; /*!< Structure used for bit access */ 163 uint32_t reg; /*!< Type used for register access */ 164 } DSU_LENGTH_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 #define DSU_LENGTH_OFFSET 0x0008 /**< \brief (DSU_LENGTH offset) Length */ 168 #define DSU_LENGTH_RESETVALUE _U_(0x00000000) /**< \brief (DSU_LENGTH reset_value) Length */ 169 170 #define DSU_LENGTH_LENGTH_Pos 2 /**< \brief (DSU_LENGTH) Length */ 171 #define DSU_LENGTH_LENGTH_Msk (_U_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos) 172 #define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & ((value) << DSU_LENGTH_LENGTH_Pos)) 173 #define DSU_LENGTH_MASK _U_(0xFFFFFFFC) /**< \brief (DSU_LENGTH) MASK Register */ 174 175 /* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */ 176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 177 typedef union { 178 struct { 179 uint32_t DATA:32; /*!< bit: 0..31 Data */ 180 } bit; /*!< Structure used for bit access */ 181 uint32_t reg; /*!< Type used for register access */ 182 } DSU_DATA_Type; 183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 184 185 #define DSU_DATA_OFFSET 0x000C /**< \brief (DSU_DATA offset) Data */ 186 #define DSU_DATA_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DATA reset_value) Data */ 187 188 #define DSU_DATA_DATA_Pos 0 /**< \brief (DSU_DATA) Data */ 189 #define DSU_DATA_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DATA_DATA_Pos) 190 #define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & ((value) << DSU_DATA_DATA_Pos)) 191 #define DSU_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DATA) MASK Register */ 192 193 /* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */ 194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 195 typedef union { 196 struct { 197 uint32_t DATA:32; /*!< bit: 0..31 Data */ 198 } bit; /*!< Structure used for bit access */ 199 uint32_t reg; /*!< Type used for register access */ 200 } DSU_DCC_Type; 201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 202 203 #define DSU_DCC_OFFSET 0x0010 /**< \brief (DSU_DCC offset) Debug Communication Channel n */ 204 #define DSU_DCC_RESETVALUE _U_(0x00000000) /**< \brief (DSU_DCC reset_value) Debug Communication Channel n */ 205 206 #define DSU_DCC_DATA_Pos 0 /**< \brief (DSU_DCC) Data */ 207 #define DSU_DCC_DATA_Msk (_U_(0xFFFFFFFF) << DSU_DCC_DATA_Pos) 208 #define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & ((value) << DSU_DCC_DATA_Pos)) 209 #define DSU_DCC_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_DCC) MASK Register */ 210 211 /* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */ 212 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 213 typedef union { 214 struct { 215 uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ 216 uint32_t REVISION:4; /*!< bit: 8..11 Revision */ 217 uint32_t DIE:4; /*!< bit: 12..15 Die Identification */ 218 uint32_t SERIES:6; /*!< bit: 16..21 Product Series */ 219 uint32_t :1; /*!< bit: 22 Reserved */ 220 uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */ 221 uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ 222 } bit; /*!< Structure used for bit access */ 223 uint32_t reg; /*!< Type used for register access */ 224 } DSU_DID_Type; 225 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 226 227 #define DSU_DID_OFFSET 0x0018 /**< \brief (DSU_DID offset) Device Identification */ 228 229 #define DSU_DID_DEVSEL_Pos 0 /**< \brief (DSU_DID) Device Select */ 230 #define DSU_DID_DEVSEL_Msk (_U_(0xFF) << DSU_DID_DEVSEL_Pos) 231 #define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & ((value) << DSU_DID_DEVSEL_Pos)) 232 #define DSU_DID_REVISION_Pos 8 /**< \brief (DSU_DID) Revision */ 233 #define DSU_DID_REVISION_Msk (_U_(0xF) << DSU_DID_REVISION_Pos) 234 #define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & ((value) << DSU_DID_REVISION_Pos)) 235 #define DSU_DID_DIE_Pos 12 /**< \brief (DSU_DID) Die Identification */ 236 #define DSU_DID_DIE_Msk (_U_(0xF) << DSU_DID_DIE_Pos) 237 #define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & ((value) << DSU_DID_DIE_Pos)) 238 #define DSU_DID_SERIES_Pos 16 /**< \brief (DSU_DID) Product Series */ 239 #define DSU_DID_SERIES_Msk (_U_(0x3F) << DSU_DID_SERIES_Pos) 240 #define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & ((value) << DSU_DID_SERIES_Pos)) 241 #define DSU_DID_FAMILY_Pos 23 /**< \brief (DSU_DID) Product Family */ 242 #define DSU_DID_FAMILY_Msk (_U_(0x1F) << DSU_DID_FAMILY_Pos) 243 #define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & ((value) << DSU_DID_FAMILY_Pos)) 244 #define DSU_DID_PROCESSOR_Pos 28 /**< \brief (DSU_DID) Processor */ 245 #define DSU_DID_PROCESSOR_Msk (_U_(0xF) << DSU_DID_PROCESSOR_Pos) 246 #define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & ((value) << DSU_DID_PROCESSOR_Pos)) 247 #define DSU_DID_MASK _U_(0xFFBFFFFF) /**< \brief (DSU_DID) MASK Register */ 248 249 /* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */ 250 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 251 typedef union { 252 struct { 253 uint32_t EPRES:1; /*!< bit: 0 Entry Present */ 254 uint32_t FMT:1; /*!< bit: 1 Format */ 255 uint32_t :10; /*!< bit: 2..11 Reserved */ 256 uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ 257 } bit; /*!< Structure used for bit access */ 258 uint32_t reg; /*!< Type used for register access */ 259 } DSU_ENTRY_Type; 260 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 261 262 #define DSU_ENTRY_OFFSET 0x1000 /**< \brief (DSU_ENTRY offset) Coresight ROM Table Entry n */ 263 #define DSU_ENTRY_RESETVALUE _U_(0x00000002) /**< \brief (DSU_ENTRY reset_value) Coresight ROM Table Entry n */ 264 265 #define DSU_ENTRY_EPRES_Pos 0 /**< \brief (DSU_ENTRY) Entry Present */ 266 #define DSU_ENTRY_EPRES (_U_(0x1) << DSU_ENTRY_EPRES_Pos) 267 #define DSU_ENTRY_FMT_Pos 1 /**< \brief (DSU_ENTRY) Format */ 268 #define DSU_ENTRY_FMT (_U_(0x1) << DSU_ENTRY_FMT_Pos) 269 #define DSU_ENTRY_ADDOFF_Pos 12 /**< \brief (DSU_ENTRY) Address Offset */ 270 #define DSU_ENTRY_ADDOFF_Msk (_U_(0xFFFFF) << DSU_ENTRY_ADDOFF_Pos) 271 #define DSU_ENTRY_ADDOFF(value) (DSU_ENTRY_ADDOFF_Msk & ((value) << DSU_ENTRY_ADDOFF_Pos)) 272 #define DSU_ENTRY_MASK _U_(0xFFFFF003) /**< \brief (DSU_ENTRY) MASK Register */ 273 274 /* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */ 275 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 276 typedef union { 277 struct { 278 uint32_t END:32; /*!< bit: 0..31 End Marker */ 279 } bit; /*!< Structure used for bit access */ 280 uint32_t reg; /*!< Type used for register access */ 281 } DSU_END_Type; 282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 283 284 #define DSU_END_OFFSET 0x1008 /**< \brief (DSU_END offset) Coresight ROM Table End */ 285 #define DSU_END_RESETVALUE _U_(0x00000000) /**< \brief (DSU_END reset_value) Coresight ROM Table End */ 286 287 #define DSU_END_END_Pos 0 /**< \brief (DSU_END) End Marker */ 288 #define DSU_END_END_Msk (_U_(0xFFFFFFFF) << DSU_END_END_Pos) 289 #define DSU_END_END(value) (DSU_END_END_Msk & ((value) << DSU_END_END_Pos)) 290 #define DSU_END_MASK _U_(0xFFFFFFFF) /**< \brief (DSU_END) MASK Register */ 291 292 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */ 293 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 294 typedef union { 295 struct { 296 uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ 297 uint32_t :31; /*!< bit: 1..31 Reserved */ 298 } bit; /*!< Structure used for bit access */ 299 uint32_t reg; /*!< Type used for register access */ 300 } DSU_MEMTYPE_Type; 301 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 302 303 #define DSU_MEMTYPE_OFFSET 0x1FCC /**< \brief (DSU_MEMTYPE offset) Coresight ROM Table Memory Type */ 304 #define DSU_MEMTYPE_RESETVALUE _U_(0x00000000) /**< \brief (DSU_MEMTYPE reset_value) Coresight ROM Table Memory Type */ 305 306 #define DSU_MEMTYPE_SMEMP_Pos 0 /**< \brief (DSU_MEMTYPE) System Memory Present */ 307 #define DSU_MEMTYPE_SMEMP (_U_(0x1) << DSU_MEMTYPE_SMEMP_Pos) 308 #define DSU_MEMTYPE_MASK _U_(0x00000001) /**< \brief (DSU_MEMTYPE) MASK Register */ 309 310 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */ 311 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 312 typedef union { 313 struct { 314 uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ 315 uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */ 316 uint32_t :24; /*!< bit: 8..31 Reserved */ 317 } bit; /*!< Structure used for bit access */ 318 uint32_t reg; /*!< Type used for register access */ 319 } DSU_PID4_Type; 320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 321 322 #define DSU_PID4_OFFSET 0x1FD0 /**< \brief (DSU_PID4 offset) Peripheral Identification 4 */ 323 #define DSU_PID4_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID4 reset_value) Peripheral Identification 4 */ 324 325 #define DSU_PID4_JEPCC_Pos 0 /**< \brief (DSU_PID4) JEP-106 Continuation Code */ 326 #define DSU_PID4_JEPCC_Msk (_U_(0xF) << DSU_PID4_JEPCC_Pos) 327 #define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & ((value) << DSU_PID4_JEPCC_Pos)) 328 #define DSU_PID4_FKBC_Pos 4 /**< \brief (DSU_PID4) 4KB Count */ 329 #define DSU_PID4_FKBC_Msk (_U_(0xF) << DSU_PID4_FKBC_Pos) 330 #define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & ((value) << DSU_PID4_FKBC_Pos)) 331 #define DSU_PID4_MASK _U_(0x000000FF) /**< \brief (DSU_PID4) MASK Register */ 332 333 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */ 334 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 335 typedef union { 336 struct { 337 uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ 338 uint32_t :24; /*!< bit: 8..31 Reserved */ 339 } bit; /*!< Structure used for bit access */ 340 uint32_t reg; /*!< Type used for register access */ 341 } DSU_PID0_Type; 342 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 343 344 #define DSU_PID0_OFFSET 0x1FE0 /**< \brief (DSU_PID0 offset) Peripheral Identification 0 */ 345 #define DSU_PID0_RESETVALUE _U_(0x000000D0) /**< \brief (DSU_PID0 reset_value) Peripheral Identification 0 */ 346 347 #define DSU_PID0_PARTNBL_Pos 0 /**< \brief (DSU_PID0) Part Number Low */ 348 #define DSU_PID0_PARTNBL_Msk (_U_(0xFF) << DSU_PID0_PARTNBL_Pos) 349 #define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & ((value) << DSU_PID0_PARTNBL_Pos)) 350 #define DSU_PID0_MASK _U_(0x000000FF) /**< \brief (DSU_PID0) MASK Register */ 351 352 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */ 353 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 354 typedef union { 355 struct { 356 uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ 357 uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ 358 uint32_t :24; /*!< bit: 8..31 Reserved */ 359 } bit; /*!< Structure used for bit access */ 360 uint32_t reg; /*!< Type used for register access */ 361 } DSU_PID1_Type; 362 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 363 364 #define DSU_PID1_OFFSET 0x1FE4 /**< \brief (DSU_PID1 offset) Peripheral Identification 1 */ 365 #define DSU_PID1_RESETVALUE _U_(0x000000FC) /**< \brief (DSU_PID1 reset_value) Peripheral Identification 1 */ 366 367 #define DSU_PID1_PARTNBH_Pos 0 /**< \brief (DSU_PID1) Part Number High */ 368 #define DSU_PID1_PARTNBH_Msk (_U_(0xF) << DSU_PID1_PARTNBH_Pos) 369 #define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & ((value) << DSU_PID1_PARTNBH_Pos)) 370 #define DSU_PID1_JEPIDCL_Pos 4 /**< \brief (DSU_PID1) Low part of the JEP-106 Identity Code */ 371 #define DSU_PID1_JEPIDCL_Msk (_U_(0xF) << DSU_PID1_JEPIDCL_Pos) 372 #define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & ((value) << DSU_PID1_JEPIDCL_Pos)) 373 #define DSU_PID1_MASK _U_(0x000000FF) /**< \brief (DSU_PID1) MASK Register */ 374 375 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */ 376 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 377 typedef union { 378 struct { 379 uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ 380 uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ 381 uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ 382 uint32_t :24; /*!< bit: 8..31 Reserved */ 383 } bit; /*!< Structure used for bit access */ 384 uint32_t reg; /*!< Type used for register access */ 385 } DSU_PID2_Type; 386 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 387 388 #define DSU_PID2_OFFSET 0x1FE8 /**< \brief (DSU_PID2 offset) Peripheral Identification 2 */ 389 #define DSU_PID2_RESETVALUE _U_(0x00000009) /**< \brief (DSU_PID2 reset_value) Peripheral Identification 2 */ 390 391 #define DSU_PID2_JEPIDCH_Pos 0 /**< \brief (DSU_PID2) JEP-106 Identity Code High */ 392 #define DSU_PID2_JEPIDCH_Msk (_U_(0x7) << DSU_PID2_JEPIDCH_Pos) 393 #define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & ((value) << DSU_PID2_JEPIDCH_Pos)) 394 #define DSU_PID2_JEPU_Pos 3 /**< \brief (DSU_PID2) JEP-106 Identity Code is used */ 395 #define DSU_PID2_JEPU (_U_(0x1) << DSU_PID2_JEPU_Pos) 396 #define DSU_PID2_REVISION_Pos 4 /**< \brief (DSU_PID2) Revision Number */ 397 #define DSU_PID2_REVISION_Msk (_U_(0xF) << DSU_PID2_REVISION_Pos) 398 #define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & ((value) << DSU_PID2_REVISION_Pos)) 399 #define DSU_PID2_MASK _U_(0x000000FF) /**< \brief (DSU_PID2) MASK Register */ 400 401 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */ 402 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 403 typedef union { 404 struct { 405 uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ 406 uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ 407 uint32_t :24; /*!< bit: 8..31 Reserved */ 408 } bit; /*!< Structure used for bit access */ 409 uint32_t reg; /*!< Type used for register access */ 410 } DSU_PID3_Type; 411 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 412 413 #define DSU_PID3_OFFSET 0x1FEC /**< \brief (DSU_PID3 offset) Peripheral Identification 3 */ 414 #define DSU_PID3_RESETVALUE _U_(0x00000000) /**< \brief (DSU_PID3 reset_value) Peripheral Identification 3 */ 415 416 #define DSU_PID3_CUSMOD_Pos 0 /**< \brief (DSU_PID3) ARM CUSMOD */ 417 #define DSU_PID3_CUSMOD_Msk (_U_(0xF) << DSU_PID3_CUSMOD_Pos) 418 #define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & ((value) << DSU_PID3_CUSMOD_Pos)) 419 #define DSU_PID3_REVAND_Pos 4 /**< \brief (DSU_PID3) Revision Number */ 420 #define DSU_PID3_REVAND_Msk (_U_(0xF) << DSU_PID3_REVAND_Pos) 421 #define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & ((value) << DSU_PID3_REVAND_Pos)) 422 #define DSU_PID3_MASK _U_(0x000000FF) /**< \brief (DSU_PID3) MASK Register */ 423 424 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */ 425 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 426 typedef union { 427 struct { 428 uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ 429 uint32_t :24; /*!< bit: 8..31 Reserved */ 430 } bit; /*!< Structure used for bit access */ 431 uint32_t reg; /*!< Type used for register access */ 432 } DSU_CID0_Type; 433 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 434 435 #define DSU_CID0_OFFSET 0x1FF0 /**< \brief (DSU_CID0 offset) Component Identification 0 */ 436 #define DSU_CID0_RESETVALUE _U_(0x0000000D) /**< \brief (DSU_CID0 reset_value) Component Identification 0 */ 437 438 #define DSU_CID0_PREAMBLEB0_Pos 0 /**< \brief (DSU_CID0) Preamble Byte 0 */ 439 #define DSU_CID0_PREAMBLEB0_Msk (_U_(0xFF) << DSU_CID0_PREAMBLEB0_Pos) 440 #define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & ((value) << DSU_CID0_PREAMBLEB0_Pos)) 441 #define DSU_CID0_MASK _U_(0x000000FF) /**< \brief (DSU_CID0) MASK Register */ 442 443 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */ 444 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 445 typedef union { 446 struct { 447 uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ 448 uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ 449 uint32_t :24; /*!< bit: 8..31 Reserved */ 450 } bit; /*!< Structure used for bit access */ 451 uint32_t reg; /*!< Type used for register access */ 452 } DSU_CID1_Type; 453 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 454 455 #define DSU_CID1_OFFSET 0x1FF4 /**< \brief (DSU_CID1 offset) Component Identification 1 */ 456 #define DSU_CID1_RESETVALUE _U_(0x00000010) /**< \brief (DSU_CID1 reset_value) Component Identification 1 */ 457 458 #define DSU_CID1_PREAMBLE_Pos 0 /**< \brief (DSU_CID1) Preamble */ 459 #define DSU_CID1_PREAMBLE_Msk (_U_(0xF) << DSU_CID1_PREAMBLE_Pos) 460 #define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & ((value) << DSU_CID1_PREAMBLE_Pos)) 461 #define DSU_CID1_CCLASS_Pos 4 /**< \brief (DSU_CID1) Component Class */ 462 #define DSU_CID1_CCLASS_Msk (_U_(0xF) << DSU_CID1_CCLASS_Pos) 463 #define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & ((value) << DSU_CID1_CCLASS_Pos)) 464 #define DSU_CID1_MASK _U_(0x000000FF) /**< \brief (DSU_CID1) MASK Register */ 465 466 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */ 467 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 468 typedef union { 469 struct { 470 uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ 471 uint32_t :24; /*!< bit: 8..31 Reserved */ 472 } bit; /*!< Structure used for bit access */ 473 uint32_t reg; /*!< Type used for register access */ 474 } DSU_CID2_Type; 475 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 476 477 #define DSU_CID2_OFFSET 0x1FF8 /**< \brief (DSU_CID2 offset) Component Identification 2 */ 478 #define DSU_CID2_RESETVALUE _U_(0x00000005) /**< \brief (DSU_CID2 reset_value) Component Identification 2 */ 479 480 #define DSU_CID2_PREAMBLEB2_Pos 0 /**< \brief (DSU_CID2) Preamble Byte 2 */ 481 #define DSU_CID2_PREAMBLEB2_Msk (_U_(0xFF) << DSU_CID2_PREAMBLEB2_Pos) 482 #define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & ((value) << DSU_CID2_PREAMBLEB2_Pos)) 483 #define DSU_CID2_MASK _U_(0x000000FF) /**< \brief (DSU_CID2) MASK Register */ 484 485 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */ 486 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 487 typedef union { 488 struct { 489 uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ 490 uint32_t :24; /*!< bit: 8..31 Reserved */ 491 } bit; /*!< Structure used for bit access */ 492 uint32_t reg; /*!< Type used for register access */ 493 } DSU_CID3_Type; 494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 495 496 #define DSU_CID3_OFFSET 0x1FFC /**< \brief (DSU_CID3 offset) Component Identification 3 */ 497 #define DSU_CID3_RESETVALUE _U_(0x000000B1) /**< \brief (DSU_CID3 reset_value) Component Identification 3 */ 498 499 #define DSU_CID3_PREAMBLEB3_Pos 0 /**< \brief (DSU_CID3) Preamble Byte 3 */ 500 #define DSU_CID3_PREAMBLEB3_Msk (_U_(0xFF) << DSU_CID3_PREAMBLEB3_Pos) 501 #define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & ((value) << DSU_CID3_PREAMBLEB3_Pos)) 502 #define DSU_CID3_MASK _U_(0x000000FF) /**< \brief (DSU_CID3) MASK Register */ 503 504 /** \brief DSU hardware registers */ 505 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 506 typedef struct { 507 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ 508 __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ 509 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ 510 RoReg8 Reserved1[0x1]; 511 __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ 512 __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ 513 __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ 514 __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ 515 __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ 516 RoReg8 Reserved2[0xFE4]; 517 __I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */ 518 __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */ 519 RoReg8 Reserved3[0xFC0]; 520 __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */ 521 __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ 522 RoReg8 Reserved4[0xC]; 523 __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ 524 __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ 525 __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ 526 __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ 527 __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ 528 __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ 529 __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ 530 __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ 531 } Dsu; 532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 533 534 /*@}*/ 535 536 #endif /* _SAMR21_DSU_COMPONENT_ */ 537
