1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAML21G16B 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAML21G16B_PIO_ 31 #define _SAML21G16B_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 38 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 39 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 40 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 41 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 42 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 43 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 44 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 45 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 46 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 47 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 48 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 49 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 50 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 51 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 52 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 53 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 54 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 55 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 56 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 57 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 58 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 59 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 60 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 61 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 62 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 63 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 64 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 65 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 66 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 67 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 68 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 69 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 70 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 71 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 72 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 73 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 74 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 75 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 76 #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ 77 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 78 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 79 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 80 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 81 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 82 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 83 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 84 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 85 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 86 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 87 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 88 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 89 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 90 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 91 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 92 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 93 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 94 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 95 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 96 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 97 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 98 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 99 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 100 #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ 101 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 102 #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ 103 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 104 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 105 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 106 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 107 /* ========== PORT definition for RSTC peripheral ========== */ 108 #define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ 109 #define MUX_PA00A_RSTC_EXTWAKE0 _L_(0) 110 #define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) 111 #define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0) 112 #define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ 113 #define MUX_PA01A_RSTC_EXTWAKE1 _L_(0) 114 #define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) 115 #define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1) 116 #define PIN_PA02A_RSTC_EXTWAKE2 _L_(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ 117 #define MUX_PA02A_RSTC_EXTWAKE2 _L_(0) 118 #define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) 119 #define PORT_PA02A_RSTC_EXTWAKE2 (_UL_(1) << 2) 120 #define PIN_PA03A_RSTC_EXTWAKE3 _L_(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ 121 #define MUX_PA03A_RSTC_EXTWAKE3 _L_(0) 122 #define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) 123 #define PORT_PA03A_RSTC_EXTWAKE3 (_UL_(1) << 3) 124 #define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ 125 #define MUX_PA04A_RSTC_EXTWAKE4 _L_(0) 126 #define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) 127 #define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4) 128 #define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ 129 #define MUX_PA05A_RSTC_EXTWAKE5 _L_(0) 130 #define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) 131 #define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5) 132 #define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ 133 #define MUX_PA06A_RSTC_EXTWAKE6 _L_(0) 134 #define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) 135 #define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6) 136 #define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ 137 #define MUX_PA07A_RSTC_EXTWAKE7 _L_(0) 138 #define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) 139 #define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7) 140 /* ========== PORT definition for SUPC peripheral ========== */ 141 #define PIN_PB02H_SUPC_OUT1 _L_(34) /**< \brief SUPC signal: OUT1 on PB02 mux H */ 142 #define MUX_PB02H_SUPC_OUT1 _L_(7) 143 #define PINMUX_PB02H_SUPC_OUT1 ((PIN_PB02H_SUPC_OUT1 << 16) | MUX_PB02H_SUPC_OUT1) 144 #define PORT_PB02H_SUPC_OUT1 (_UL_(1) << 2) 145 #define PIN_PB03H_SUPC_VBAT _L_(35) /**< \brief SUPC signal: VBAT on PB03 mux H */ 146 #define MUX_PB03H_SUPC_VBAT _L_(7) 147 #define PINMUX_PB03H_SUPC_VBAT ((PIN_PB03H_SUPC_VBAT << 16) | MUX_PB03H_SUPC_VBAT) 148 #define PORT_PB03H_SUPC_VBAT (_UL_(1) << 3) 149 /* ========== PORT definition for GCLK peripheral ========== */ 150 #define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ 151 #define MUX_PB22H_GCLK_IO0 _L_(7) 152 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) 153 #define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) 154 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 155 #define MUX_PA14H_GCLK_IO0 _L_(7) 156 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 157 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 158 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 159 #define MUX_PA27H_GCLK_IO0 _L_(7) 160 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 161 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 162 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 163 #define MUX_PA30H_GCLK_IO0 _L_(7) 164 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 165 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 166 #define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ 167 #define MUX_PB23H_GCLK_IO1 _L_(7) 168 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) 169 #define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) 170 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 171 #define MUX_PA15H_GCLK_IO1 _L_(7) 172 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 173 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 174 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 175 #define MUX_PA16H_GCLK_IO2 _L_(7) 176 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 177 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 178 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 179 #define MUX_PA17H_GCLK_IO3 _L_(7) 180 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 181 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 182 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 183 #define MUX_PA10H_GCLK_IO4 _L_(7) 184 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 185 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 186 #define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ 187 #define MUX_PA20H_GCLK_IO4 _L_(7) 188 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) 189 #define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) 190 #define PIN_PB10H_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux H */ 191 #define MUX_PB10H_GCLK_IO4 _L_(7) 192 #define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) 193 #define PORT_PB10H_GCLK_IO4 (_UL_(1) << 10) 194 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 195 #define MUX_PA11H_GCLK_IO5 _L_(7) 196 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 197 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 198 #define PIN_PA21H_GCLK_IO5 _L_(21) /**< \brief GCLK signal: IO5 on PA21 mux H */ 199 #define MUX_PA21H_GCLK_IO5 _L_(7) 200 #define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) 201 #define PORT_PA21H_GCLK_IO5 (_UL_(1) << 21) 202 #define PIN_PB11H_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux H */ 203 #define MUX_PB11H_GCLK_IO5 _L_(7) 204 #define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) 205 #define PORT_PB11H_GCLK_IO5 (_UL_(1) << 11) 206 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 207 #define MUX_PA22H_GCLK_IO6 _L_(7) 208 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 209 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 210 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 211 #define MUX_PA23H_GCLK_IO7 _L_(7) 212 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 213 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 214 /* ========== PORT definition for EIC peripheral ========== */ 215 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 216 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 217 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 218 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 219 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 220 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 221 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 222 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 223 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 224 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 225 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 226 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 227 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 228 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 229 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 230 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 231 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 232 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 233 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 234 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 235 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 236 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 237 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 238 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 239 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 240 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 241 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 242 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 243 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 244 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 245 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 246 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 247 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 248 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 249 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 250 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 251 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 252 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 253 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 254 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 255 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 256 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 257 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 258 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 259 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 260 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 261 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 262 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 263 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 264 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 265 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 266 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 267 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 268 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 269 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 270 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 271 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 272 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 273 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 274 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 275 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 276 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 277 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 278 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 279 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 280 #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ 281 #define MUX_PA21A_EIC_EXTINT5 _L_(0) 282 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 283 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) 284 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 285 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 286 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 287 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 288 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 289 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 290 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 291 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 292 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 293 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 294 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 295 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 296 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 297 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 298 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 299 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 300 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 301 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 302 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 303 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 304 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 305 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 306 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 307 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 308 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 309 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 310 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 311 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 312 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 313 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 314 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 315 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 316 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 317 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 318 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 319 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 320 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 321 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 322 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 323 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 324 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 325 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 326 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 327 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 328 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 329 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 330 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 331 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 332 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 333 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 334 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 335 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 336 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 337 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 338 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 339 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 340 #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ 341 #define MUX_PB10A_EIC_EXTINT10 _L_(0) 342 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 343 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) 344 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ 345 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 346 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 347 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 348 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 349 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 350 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 351 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 352 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 353 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 354 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 355 #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ 356 #define MUX_PB11A_EIC_EXTINT11 _L_(0) 357 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 358 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) 359 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ 360 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 361 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 362 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 363 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 364 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 365 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 366 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 367 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 368 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 369 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 370 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 371 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 372 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 373 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 374 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 375 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 376 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 377 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 378 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 379 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 380 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 381 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 382 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 383 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 384 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 385 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 386 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 387 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 388 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 389 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 390 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 391 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 392 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 393 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 394 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 395 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 396 #define MUX_PA08A_EIC_NMI _L_(0) 397 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 398 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 399 /* ========== PORT definition for USB peripheral ========== */ 400 #define PIN_PA24G_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux G */ 401 #define MUX_PA24G_USB_DM _L_(6) 402 #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) 403 #define PORT_PA24G_USB_DM (_UL_(1) << 24) 404 #define PIN_PA25G_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux G */ 405 #define MUX_PA25G_USB_DP _L_(6) 406 #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) 407 #define PORT_PA25G_USB_DP (_UL_(1) << 25) 408 #define PIN_PA23G_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ 409 #define MUX_PA23G_USB_SOF_1KHZ _L_(6) 410 #define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) 411 #define PORT_PA23G_USB_SOF_1KHZ (_UL_(1) << 23) 412 /* ========== PORT definition for SERCOM0 peripheral ========== */ 413 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 414 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 415 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 416 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 417 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 418 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 419 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 420 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 421 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 422 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 423 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 424 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 425 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 426 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 427 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 428 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 429 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 430 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 431 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 432 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 433 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 434 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 435 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 436 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 437 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 438 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 439 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 440 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 441 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 442 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 443 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 444 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 445 /* ========== PORT definition for SERCOM1 peripheral ========== */ 446 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 447 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 448 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 449 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 450 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 451 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 452 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 453 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 454 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 455 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 456 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 457 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 458 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 459 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 460 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 461 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 462 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 463 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 464 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 465 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 466 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 467 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 468 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 469 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 470 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 471 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 472 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 473 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 474 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 475 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 476 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 477 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 478 /* ========== PORT definition for SERCOM2 peripheral ========== */ 479 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 480 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 481 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 482 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 483 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 484 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 485 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 486 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 487 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 488 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 489 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 490 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 491 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 492 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 493 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 494 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 495 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 496 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 497 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 498 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 499 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 500 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 501 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 502 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 503 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 504 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 505 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 506 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 507 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 508 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 509 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 510 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 511 /* ========== PORT definition for SERCOM3 peripheral ========== */ 512 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 513 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 514 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 515 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 516 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 517 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 518 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 519 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 520 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 521 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 522 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 523 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 524 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 525 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 526 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 527 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 528 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 529 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 530 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 531 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 532 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 533 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 534 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 535 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 536 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 537 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 538 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 539 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 540 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 541 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 542 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 543 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 544 #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ 545 #define MUX_PA21D_SERCOM3_PAD3 _L_(3) 546 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 547 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) 548 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 549 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 550 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 551 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 552 /* ========== PORT definition for SERCOM4 peripheral ========== */ 553 #define PIN_PA12D_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ 554 #define MUX_PA12D_SERCOM4_PAD0 _L_(3) 555 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) 556 #define PORT_PA12D_SERCOM4_PAD0 (_UL_(1) << 12) 557 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 558 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 559 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 560 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 561 #define PIN_PA13D_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ 562 #define MUX_PA13D_SERCOM4_PAD1 _L_(3) 563 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) 564 #define PORT_PA13D_SERCOM4_PAD1 (_UL_(1) << 13) 565 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 566 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 567 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 568 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 569 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 570 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 571 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 572 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 573 #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ 574 #define MUX_PB10D_SERCOM4_PAD2 _L_(3) 575 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 576 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) 577 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 578 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 579 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 580 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 581 #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ 582 #define MUX_PB11D_SERCOM4_PAD3 _L_(3) 583 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 584 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) 585 /* ========== PORT definition for TCC0 peripheral ========== */ 586 #define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 587 #define MUX_PA04E_TCC0_WO0 _L_(4) 588 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 589 #define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) 590 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 591 #define MUX_PA08E_TCC0_WO0 _L_(4) 592 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 593 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 594 #define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 595 #define MUX_PA05E_TCC0_WO1 _L_(4) 596 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 597 #define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) 598 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 599 #define MUX_PA09E_TCC0_WO1 _L_(4) 600 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 601 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 602 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 603 #define MUX_PA10F_TCC0_WO2 _L_(5) 604 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 605 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 606 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 607 #define MUX_PA18F_TCC0_WO2 _L_(5) 608 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 609 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 610 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 611 #define MUX_PA11F_TCC0_WO3 _L_(5) 612 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 613 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 614 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 615 #define MUX_PA19F_TCC0_WO3 _L_(5) 616 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 617 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 618 #define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 619 #define MUX_PA22F_TCC0_WO4 _L_(5) 620 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 621 #define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) 622 #define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ 623 #define MUX_PB10F_TCC0_WO4 _L_(5) 624 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) 625 #define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) 626 #define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ 627 #define MUX_PA14F_TCC0_WO4 _L_(5) 628 #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) 629 #define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) 630 #define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ 631 #define MUX_PA15F_TCC0_WO5 _L_(5) 632 #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) 633 #define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) 634 #define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 635 #define MUX_PA23F_TCC0_WO5 _L_(5) 636 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 637 #define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) 638 #define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ 639 #define MUX_PB11F_TCC0_WO5 _L_(5) 640 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) 641 #define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) 642 #define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ 643 #define MUX_PA12F_TCC0_WO6 _L_(5) 644 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 645 #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) 646 #define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ 647 #define MUX_PA16F_TCC0_WO6 _L_(5) 648 #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) 649 #define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) 650 #define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ 651 #define MUX_PA20F_TCC0_WO6 _L_(5) 652 #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) 653 #define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) 654 #define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ 655 #define MUX_PA13F_TCC0_WO7 _L_(5) 656 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 657 #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) 658 #define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ 659 #define MUX_PA17F_TCC0_WO7 _L_(5) 660 #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) 661 #define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) 662 #define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ 663 #define MUX_PA21F_TCC0_WO7 _L_(5) 664 #define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) 665 #define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) 666 /* ========== PORT definition for TCC1 peripheral ========== */ 667 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 668 #define MUX_PA06E_TCC1_WO0 _L_(4) 669 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 670 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 671 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 672 #define MUX_PA10E_TCC1_WO0 _L_(4) 673 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 674 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 675 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 676 #define MUX_PA30E_TCC1_WO0 _L_(4) 677 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 678 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 679 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 680 #define MUX_PA07E_TCC1_WO1 _L_(4) 681 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 682 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 683 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 684 #define MUX_PA11E_TCC1_WO1 _L_(4) 685 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 686 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 687 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 688 #define MUX_PA31E_TCC1_WO1 _L_(4) 689 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 690 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 691 #define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */ 692 #define MUX_PA08F_TCC1_WO2 _L_(5) 693 #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) 694 #define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8) 695 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 696 #define MUX_PA24F_TCC1_WO2 _L_(5) 697 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 698 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 699 #define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */ 700 #define MUX_PA09F_TCC1_WO3 _L_(5) 701 #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) 702 #define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9) 703 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 704 #define MUX_PA25F_TCC1_WO3 _L_(5) 705 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 706 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 707 /* ========== PORT definition for TCC2 peripheral ========== */ 708 #define PIN_PA12E_TCC2_WO0 _L_(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */ 709 #define MUX_PA12E_TCC2_WO0 _L_(4) 710 #define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) 711 #define PORT_PA12E_TCC2_WO0 (_UL_(1) << 12) 712 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 713 #define MUX_PA16E_TCC2_WO0 _L_(4) 714 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 715 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 716 #define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 717 #define MUX_PA00E_TCC2_WO0 _L_(4) 718 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 719 #define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0) 720 #define PIN_PA13E_TCC2_WO1 _L_(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */ 721 #define MUX_PA13E_TCC2_WO1 _L_(4) 722 #define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) 723 #define PORT_PA13E_TCC2_WO1 (_UL_(1) << 13) 724 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 725 #define MUX_PA17E_TCC2_WO1 _L_(4) 726 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 727 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 728 #define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 729 #define MUX_PA01E_TCC2_WO1 _L_(4) 730 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 731 #define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1) 732 /* ========== PORT definition for TC0 peripheral ========== */ 733 #define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ 734 #define MUX_PA22E_TC0_WO0 _L_(4) 735 #define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) 736 #define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) 737 #define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ 738 #define MUX_PB08E_TC0_WO0 _L_(4) 739 #define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) 740 #define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) 741 #define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ 742 #define MUX_PA23E_TC0_WO1 _L_(4) 743 #define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) 744 #define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) 745 #define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ 746 #define MUX_PB09E_TC0_WO1 _L_(4) 747 #define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) 748 #define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) 749 /* ========== PORT definition for TC1 peripheral ========== */ 750 #define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ 751 #define MUX_PA24E_TC1_WO0 _L_(4) 752 #define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) 753 #define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) 754 #define PIN_PB10E_TC1_WO0 _L_(42) /**< \brief TC1 signal: WO0 on PB10 mux E */ 755 #define MUX_PB10E_TC1_WO0 _L_(4) 756 #define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) 757 #define PORT_PB10E_TC1_WO0 (_UL_(1) << 10) 758 #define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ 759 #define MUX_PA25E_TC1_WO1 _L_(4) 760 #define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) 761 #define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) 762 #define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ 763 #define MUX_PB11E_TC1_WO1 _L_(4) 764 #define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) 765 #define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) 766 /* ========== PORT definition for DAC peripheral ========== */ 767 #define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ 768 #define MUX_PA02B_DAC_VOUT0 _L_(1) 769 #define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) 770 #define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) 771 #define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ 772 #define MUX_PA05B_DAC_VOUT1 _L_(1) 773 #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) 774 #define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) 775 #define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 776 #define MUX_PA03B_DAC_VREFP _L_(1) 777 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 778 #define PORT_PA03B_DAC_VREFP (_UL_(1) << 3) 779 /* ========== PORT definition for SERCOM5 peripheral ========== */ 780 #define PIN_PA22D_SERCOM5_PAD0 _L_(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 781 #define MUX_PA22D_SERCOM5_PAD0 _L_(3) 782 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 783 #define PORT_PA22D_SERCOM5_PAD0 (_UL_(1) << 22) 784 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 785 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 786 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 787 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 788 #define PIN_PA23D_SERCOM5_PAD1 _L_(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 789 #define MUX_PA23D_SERCOM5_PAD1 _L_(3) 790 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 791 #define PORT_PA23D_SERCOM5_PAD1 (_UL_(1) << 23) 792 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 793 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 794 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 795 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 796 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 797 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 798 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 799 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 800 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 801 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 802 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 803 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 804 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 805 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 806 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 807 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 808 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 809 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 810 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 811 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 812 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 813 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 814 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 815 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 816 #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ 817 #define MUX_PA21C_SERCOM5_PAD3 _L_(2) 818 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 819 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) 820 /* ========== PORT definition for TC4 peripheral ========== */ 821 #define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */ 822 #define MUX_PA18E_TC4_WO0 _L_(4) 823 #define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) 824 #define PORT_PA18E_TC4_WO0 (_UL_(1) << 18) 825 #define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */ 826 #define MUX_PA14E_TC4_WO0 _L_(4) 827 #define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) 828 #define PORT_PA14E_TC4_WO0 (_UL_(1) << 14) 829 #define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */ 830 #define MUX_PA19E_TC4_WO1 _L_(4) 831 #define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) 832 #define PORT_PA19E_TC4_WO1 (_UL_(1) << 19) 833 #define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */ 834 #define MUX_PA15E_TC4_WO1 _L_(4) 835 #define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) 836 #define PORT_PA15E_TC4_WO1 (_UL_(1) << 15) 837 /* ========== PORT definition for ADC peripheral ========== */ 838 #define PIN_PA02B_ADC_AIN0 _L_(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ 839 #define MUX_PA02B_ADC_AIN0 _L_(1) 840 #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) 841 #define PORT_PA02B_ADC_AIN0 (_UL_(1) << 2) 842 #define PIN_PA03B_ADC_AIN1 _L_(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ 843 #define MUX_PA03B_ADC_AIN1 _L_(1) 844 #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) 845 #define PORT_PA03B_ADC_AIN1 (_UL_(1) << 3) 846 #define PIN_PB08B_ADC_AIN2 _L_(40) /**< \brief ADC signal: AIN2 on PB08 mux B */ 847 #define MUX_PB08B_ADC_AIN2 _L_(1) 848 #define PINMUX_PB08B_ADC_AIN2 ((PIN_PB08B_ADC_AIN2 << 16) | MUX_PB08B_ADC_AIN2) 849 #define PORT_PB08B_ADC_AIN2 (_UL_(1) << 8) 850 #define PIN_PB09B_ADC_AIN3 _L_(41) /**< \brief ADC signal: AIN3 on PB09 mux B */ 851 #define MUX_PB09B_ADC_AIN3 _L_(1) 852 #define PINMUX_PB09B_ADC_AIN3 ((PIN_PB09B_ADC_AIN3 << 16) | MUX_PB09B_ADC_AIN3) 853 #define PORT_PB09B_ADC_AIN3 (_UL_(1) << 9) 854 #define PIN_PA04B_ADC_AIN4 _L_(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ 855 #define MUX_PA04B_ADC_AIN4 _L_(1) 856 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) 857 #define PORT_PA04B_ADC_AIN4 (_UL_(1) << 4) 858 #define PIN_PA05B_ADC_AIN5 _L_(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ 859 #define MUX_PA05B_ADC_AIN5 _L_(1) 860 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) 861 #define PORT_PA05B_ADC_AIN5 (_UL_(1) << 5) 862 #define PIN_PA06B_ADC_AIN6 _L_(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 863 #define MUX_PA06B_ADC_AIN6 _L_(1) 864 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 865 #define PORT_PA06B_ADC_AIN6 (_UL_(1) << 6) 866 #define PIN_PA07B_ADC_AIN7 _L_(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 867 #define MUX_PA07B_ADC_AIN7 _L_(1) 868 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 869 #define PORT_PA07B_ADC_AIN7 (_UL_(1) << 7) 870 #define PIN_PB02B_ADC_AIN10 _L_(34) /**< \brief ADC signal: AIN10 on PB02 mux B */ 871 #define MUX_PB02B_ADC_AIN10 _L_(1) 872 #define PINMUX_PB02B_ADC_AIN10 ((PIN_PB02B_ADC_AIN10 << 16) | MUX_PB02B_ADC_AIN10) 873 #define PORT_PB02B_ADC_AIN10 (_UL_(1) << 2) 874 #define PIN_PB03B_ADC_AIN11 _L_(35) /**< \brief ADC signal: AIN11 on PB03 mux B */ 875 #define MUX_PB03B_ADC_AIN11 _L_(1) 876 #define PINMUX_PB03B_ADC_AIN11 ((PIN_PB03B_ADC_AIN11 << 16) | MUX_PB03B_ADC_AIN11) 877 #define PORT_PB03B_ADC_AIN11 (_UL_(1) << 3) 878 #define PIN_PA08B_ADC_AIN16 _L_(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 879 #define MUX_PA08B_ADC_AIN16 _L_(1) 880 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 881 #define PORT_PA08B_ADC_AIN16 (_UL_(1) << 8) 882 #define PIN_PA09B_ADC_AIN17 _L_(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 883 #define MUX_PA09B_ADC_AIN17 _L_(1) 884 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 885 #define PORT_PA09B_ADC_AIN17 (_UL_(1) << 9) 886 #define PIN_PA10B_ADC_AIN18 _L_(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 887 #define MUX_PA10B_ADC_AIN18 _L_(1) 888 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 889 #define PORT_PA10B_ADC_AIN18 (_UL_(1) << 10) 890 #define PIN_PA11B_ADC_AIN19 _L_(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 891 #define MUX_PA11B_ADC_AIN19 _L_(1) 892 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 893 #define PORT_PA11B_ADC_AIN19 (_UL_(1) << 11) 894 #define PIN_PA04B_ADC_VREFP _L_(4) /**< \brief ADC signal: VREFP on PA04 mux B */ 895 #define MUX_PA04B_ADC_VREFP _L_(1) 896 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) 897 #define PORT_PA04B_ADC_VREFP (_UL_(1) << 4) 898 /* ========== PORT definition for AC peripheral ========== */ 899 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 900 #define MUX_PA04B_AC_AIN0 _L_(1) 901 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 902 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 903 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 904 #define MUX_PA05B_AC_AIN1 _L_(1) 905 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 906 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 907 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 908 #define MUX_PA06B_AC_AIN2 _L_(1) 909 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 910 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 911 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 912 #define MUX_PA07B_AC_AIN3 _L_(1) 913 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 914 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 915 #define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ 916 #define MUX_PA12H_AC_CMP0 _L_(7) 917 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) 918 #define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) 919 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 920 #define MUX_PA18H_AC_CMP0 _L_(7) 921 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 922 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 923 #define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ 924 #define MUX_PA13H_AC_CMP1 _L_(7) 925 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) 926 #define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) 927 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 928 #define MUX_PA19H_AC_CMP1 _L_(7) 929 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 930 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 931 /* ========== PORT definition for OPAMP peripheral ========== */ 932 #define PIN_PA02B_OPAMP_OANEG0 _L_(2) /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ 933 #define MUX_PA02B_OPAMP_OANEG0 _L_(1) 934 #define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) 935 #define PORT_PA02B_OPAMP_OANEG0 (_UL_(1) << 2) 936 #define PIN_PA07B_OPAMP_OAOUT0 _L_(7) /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ 937 #define MUX_PA07B_OPAMP_OAOUT0 _L_(1) 938 #define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) 939 #define PORT_PA07B_OPAMP_OAOUT0 (_UL_(1) << 7) 940 #define PIN_PB08B_OPAMP_OAOUT1 _L_(40) /**< \brief OPAMP signal: OAOUT1 on PB08 mux B */ 941 #define MUX_PB08B_OPAMP_OAOUT1 _L_(1) 942 #define PINMUX_PB08B_OPAMP_OAOUT1 ((PIN_PB08B_OPAMP_OAOUT1 << 16) | MUX_PB08B_OPAMP_OAOUT1) 943 #define PORT_PB08B_OPAMP_OAOUT1 (_UL_(1) << 8) 944 #define PIN_PA04B_OPAMP_OAOUT2 _L_(4) /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ 945 #define MUX_PA04B_OPAMP_OAOUT2 _L_(1) 946 #define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) 947 #define PORT_PA04B_OPAMP_OAOUT2 (_UL_(1) << 4) 948 #define PIN_PA06B_OPAMP_OAPOS0 _L_(6) /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ 949 #define MUX_PA06B_OPAMP_OAPOS0 _L_(1) 950 #define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) 951 #define PORT_PA06B_OPAMP_OAPOS0 (_UL_(1) << 6) 952 #define PIN_PB09B_OPAMP_OAPOS1 _L_(41) /**< \brief OPAMP signal: OAPOS1 on PB09 mux B */ 953 #define MUX_PB09B_OPAMP_OAPOS1 _L_(1) 954 #define PINMUX_PB09B_OPAMP_OAPOS1 ((PIN_PB09B_OPAMP_OAPOS1 << 16) | MUX_PB09B_OPAMP_OAPOS1) 955 #define PORT_PB09B_OPAMP_OAPOS1 (_UL_(1) << 9) 956 #define PIN_PA05B_OPAMP_OAPOS2 _L_(5) /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ 957 #define MUX_PA05B_OPAMP_OAPOS2 _L_(1) 958 #define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) 959 #define PORT_PA05B_OPAMP_OAPOS2 (_UL_(1) << 5) 960 /* ========== PORT definition for CCL peripheral ========== */ 961 #define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ 962 #define MUX_PA04I_CCL_IN0 _L_(8) 963 #define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) 964 #define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) 965 #define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ 966 #define MUX_PA16I_CCL_IN0 _L_(8) 967 #define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) 968 #define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) 969 #define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ 970 #define MUX_PB22I_CCL_IN0 _L_(8) 971 #define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) 972 #define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) 973 #define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ 974 #define MUX_PA05I_CCL_IN1 _L_(8) 975 #define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) 976 #define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) 977 #define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ 978 #define MUX_PA17I_CCL_IN1 _L_(8) 979 #define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) 980 #define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) 981 #define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ 982 #define MUX_PA06I_CCL_IN2 _L_(8) 983 #define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) 984 #define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) 985 #define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ 986 #define MUX_PA18I_CCL_IN2 _L_(8) 987 #define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) 988 #define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) 989 #define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ 990 #define MUX_PA08I_CCL_IN3 _L_(8) 991 #define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) 992 #define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) 993 #define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ 994 #define MUX_PA30I_CCL_IN3 _L_(8) 995 #define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) 996 #define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) 997 #define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ 998 #define MUX_PA09I_CCL_IN4 _L_(8) 999 #define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) 1000 #define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) 1001 #define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ 1002 #define MUX_PA10I_CCL_IN5 _L_(8) 1003 #define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) 1004 #define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) 1005 #define PIN_PB10I_CCL_IN5 _L_(42) /**< \brief CCL signal: IN5 on PB10 mux I */ 1006 #define MUX_PB10I_CCL_IN5 _L_(8) 1007 #define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) 1008 #define PORT_PB10I_CCL_IN5 (_UL_(1) << 10) 1009 #define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ 1010 #define MUX_PA22I_CCL_IN6 _L_(8) 1011 #define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) 1012 #define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) 1013 #define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ 1014 #define MUX_PA23I_CCL_IN7 _L_(8) 1015 #define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) 1016 #define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) 1017 #define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ 1018 #define MUX_PA24I_CCL_IN8 _L_(8) 1019 #define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) 1020 #define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) 1021 #define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ 1022 #define MUX_PB08I_CCL_IN8 _L_(8) 1023 #define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) 1024 #define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) 1025 #define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ 1026 #define MUX_PA07I_CCL_OUT0 _L_(8) 1027 #define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) 1028 #define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) 1029 #define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ 1030 #define MUX_PA19I_CCL_OUT0 _L_(8) 1031 #define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) 1032 #define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) 1033 #define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ 1034 #define MUX_PB02I_CCL_OUT0 _L_(8) 1035 #define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) 1036 #define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) 1037 #define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ 1038 #define MUX_PB23I_CCL_OUT0 _L_(8) 1039 #define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) 1040 #define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) 1041 #define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ 1042 #define MUX_PA11I_CCL_OUT1 _L_(8) 1043 #define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) 1044 #define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) 1045 #define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ 1046 #define MUX_PA31I_CCL_OUT1 _L_(8) 1047 #define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) 1048 #define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) 1049 #define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ 1050 #define MUX_PB11I_CCL_OUT1 _L_(8) 1051 #define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) 1052 #define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) 1053 #define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ 1054 #define MUX_PA25I_CCL_OUT2 _L_(8) 1055 #define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) 1056 #define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) 1057 #define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ 1058 #define MUX_PB09I_CCL_OUT2 _L_(8) 1059 #define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) 1060 #define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) 1061 1062 #endif /* _SAML21G16B_PIO_ */ 1063
