1 /** 2 * \file 3 * 4 * \brief Instance description for GCLK 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAML21_GCLK_INSTANCE_ 31 #define _SAML21_GCLK_INSTANCE_ 32 33 /* ========== Register definition for GCLK peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_GCLK_CTRLA (0x40001800) /**< \brief (GCLK) Control */ 36 #define REG_GCLK_SYNCBUSY (0x40001804) /**< \brief (GCLK) Synchronization Busy */ 37 #define REG_GCLK_GENCTRL0 (0x40001820) /**< \brief (GCLK) Generic Clock Generator Control 0 */ 38 #define REG_GCLK_GENCTRL1 (0x40001824) /**< \brief (GCLK) Generic Clock Generator Control 1 */ 39 #define REG_GCLK_GENCTRL2 (0x40001828) /**< \brief (GCLK) Generic Clock Generator Control 2 */ 40 #define REG_GCLK_GENCTRL3 (0x4000182C) /**< \brief (GCLK) Generic Clock Generator Control 3 */ 41 #define REG_GCLK_GENCTRL4 (0x40001830) /**< \brief (GCLK) Generic Clock Generator Control 4 */ 42 #define REG_GCLK_GENCTRL5 (0x40001834) /**< \brief (GCLK) Generic Clock Generator Control 5 */ 43 #define REG_GCLK_GENCTRL6 (0x40001838) /**< \brief (GCLK) Generic Clock Generator Control 6 */ 44 #define REG_GCLK_GENCTRL7 (0x4000183C) /**< \brief (GCLK) Generic Clock Generator Control 7 */ 45 #define REG_GCLK_GENCTRL8 (0x40001840) /**< \brief (GCLK) Generic Clock Generator Control 8 */ 46 #define REG_GCLK_PCHCTRL0 (0x40001880) /**< \brief (GCLK) Peripheral Clock Control 0 */ 47 #define REG_GCLK_PCHCTRL1 (0x40001884) /**< \brief (GCLK) Peripheral Clock Control 1 */ 48 #define REG_GCLK_PCHCTRL2 (0x40001888) /**< \brief (GCLK) Peripheral Clock Control 2 */ 49 #define REG_GCLK_PCHCTRL3 (0x4000188C) /**< \brief (GCLK) Peripheral Clock Control 3 */ 50 #define REG_GCLK_PCHCTRL4 (0x40001890) /**< \brief (GCLK) Peripheral Clock Control 4 */ 51 #define REG_GCLK_PCHCTRL5 (0x40001894) /**< \brief (GCLK) Peripheral Clock Control 5 */ 52 #define REG_GCLK_PCHCTRL6 (0x40001898) /**< \brief (GCLK) Peripheral Clock Control 6 */ 53 #define REG_GCLK_PCHCTRL7 (0x4000189C) /**< \brief (GCLK) Peripheral Clock Control 7 */ 54 #define REG_GCLK_PCHCTRL8 (0x400018A0) /**< \brief (GCLK) Peripheral Clock Control 8 */ 55 #define REG_GCLK_PCHCTRL9 (0x400018A4) /**< \brief (GCLK) Peripheral Clock Control 9 */ 56 #define REG_GCLK_PCHCTRL10 (0x400018A8) /**< \brief (GCLK) Peripheral Clock Control 10 */ 57 #define REG_GCLK_PCHCTRL11 (0x400018AC) /**< \brief (GCLK) Peripheral Clock Control 11 */ 58 #define REG_GCLK_PCHCTRL12 (0x400018B0) /**< \brief (GCLK) Peripheral Clock Control 12 */ 59 #define REG_GCLK_PCHCTRL13 (0x400018B4) /**< \brief (GCLK) Peripheral Clock Control 13 */ 60 #define REG_GCLK_PCHCTRL14 (0x400018B8) /**< \brief (GCLK) Peripheral Clock Control 14 */ 61 #define REG_GCLK_PCHCTRL15 (0x400018BC) /**< \brief (GCLK) Peripheral Clock Control 15 */ 62 #define REG_GCLK_PCHCTRL16 (0x400018C0) /**< \brief (GCLK) Peripheral Clock Control 16 */ 63 #define REG_GCLK_PCHCTRL17 (0x400018C4) /**< \brief (GCLK) Peripheral Clock Control 17 */ 64 #define REG_GCLK_PCHCTRL18 (0x400018C8) /**< \brief (GCLK) Peripheral Clock Control 18 */ 65 #define REG_GCLK_PCHCTRL19 (0x400018CC) /**< \brief (GCLK) Peripheral Clock Control 19 */ 66 #define REG_GCLK_PCHCTRL20 (0x400018D0) /**< \brief (GCLK) Peripheral Clock Control 20 */ 67 #define REG_GCLK_PCHCTRL21 (0x400018D4) /**< \brief (GCLK) Peripheral Clock Control 21 */ 68 #define REG_GCLK_PCHCTRL22 (0x400018D8) /**< \brief (GCLK) Peripheral Clock Control 22 */ 69 #define REG_GCLK_PCHCTRL23 (0x400018DC) /**< \brief (GCLK) Peripheral Clock Control 23 */ 70 #define REG_GCLK_PCHCTRL24 (0x400018E0) /**< \brief (GCLK) Peripheral Clock Control 24 */ 71 #define REG_GCLK_PCHCTRL25 (0x400018E4) /**< \brief (GCLK) Peripheral Clock Control 25 */ 72 #define REG_GCLK_PCHCTRL26 (0x400018E8) /**< \brief (GCLK) Peripheral Clock Control 26 */ 73 #define REG_GCLK_PCHCTRL27 (0x400018EC) /**< \brief (GCLK) Peripheral Clock Control 27 */ 74 #define REG_GCLK_PCHCTRL28 (0x400018F0) /**< \brief (GCLK) Peripheral Clock Control 28 */ 75 #define REG_GCLK_PCHCTRL29 (0x400018F4) /**< \brief (GCLK) Peripheral Clock Control 29 */ 76 #define REG_GCLK_PCHCTRL30 (0x400018F8) /**< \brief (GCLK) Peripheral Clock Control 30 */ 77 #define REG_GCLK_PCHCTRL31 (0x400018FC) /**< \brief (GCLK) Peripheral Clock Control 31 */ 78 #define REG_GCLK_PCHCTRL32 (0x40001900) /**< \brief (GCLK) Peripheral Clock Control 32 */ 79 #define REG_GCLK_PCHCTRL33 (0x40001904) /**< \brief (GCLK) Peripheral Clock Control 33 */ 80 #define REG_GCLK_PCHCTRL34 (0x40001908) /**< \brief (GCLK) Peripheral Clock Control 34 */ 81 #define REG_GCLK_PCHCTRL35 (0x4000190C) /**< \brief (GCLK) Peripheral Clock Control 35 */ 82 #else 83 #define REG_GCLK_CTRLA (*(RwReg8 *)0x40001800UL) /**< \brief (GCLK) Control */ 84 #define REG_GCLK_SYNCBUSY (*(RoReg *)0x40001804UL) /**< \brief (GCLK) Synchronization Busy */ 85 #define REG_GCLK_GENCTRL0 (*(RwReg *)0x40001820UL) /**< \brief (GCLK) Generic Clock Generator Control 0 */ 86 #define REG_GCLK_GENCTRL1 (*(RwReg *)0x40001824UL) /**< \brief (GCLK) Generic Clock Generator Control 1 */ 87 #define REG_GCLK_GENCTRL2 (*(RwReg *)0x40001828UL) /**< \brief (GCLK) Generic Clock Generator Control 2 */ 88 #define REG_GCLK_GENCTRL3 (*(RwReg *)0x4000182CUL) /**< \brief (GCLK) Generic Clock Generator Control 3 */ 89 #define REG_GCLK_GENCTRL4 (*(RwReg *)0x40001830UL) /**< \brief (GCLK) Generic Clock Generator Control 4 */ 90 #define REG_GCLK_GENCTRL5 (*(RwReg *)0x40001834UL) /**< \brief (GCLK) Generic Clock Generator Control 5 */ 91 #define REG_GCLK_GENCTRL6 (*(RwReg *)0x40001838UL) /**< \brief (GCLK) Generic Clock Generator Control 6 */ 92 #define REG_GCLK_GENCTRL7 (*(RwReg *)0x4000183CUL) /**< \brief (GCLK) Generic Clock Generator Control 7 */ 93 #define REG_GCLK_GENCTRL8 (*(RwReg *)0x40001840UL) /**< \brief (GCLK) Generic Clock Generator Control 8 */ 94 #define REG_GCLK_PCHCTRL0 (*(RwReg *)0x40001880UL) /**< \brief (GCLK) Peripheral Clock Control 0 */ 95 #define REG_GCLK_PCHCTRL1 (*(RwReg *)0x40001884UL) /**< \brief (GCLK) Peripheral Clock Control 1 */ 96 #define REG_GCLK_PCHCTRL2 (*(RwReg *)0x40001888UL) /**< \brief (GCLK) Peripheral Clock Control 2 */ 97 #define REG_GCLK_PCHCTRL3 (*(RwReg *)0x4000188CUL) /**< \brief (GCLK) Peripheral Clock Control 3 */ 98 #define REG_GCLK_PCHCTRL4 (*(RwReg *)0x40001890UL) /**< \brief (GCLK) Peripheral Clock Control 4 */ 99 #define REG_GCLK_PCHCTRL5 (*(RwReg *)0x40001894UL) /**< \brief (GCLK) Peripheral Clock Control 5 */ 100 #define REG_GCLK_PCHCTRL6 (*(RwReg *)0x40001898UL) /**< \brief (GCLK) Peripheral Clock Control 6 */ 101 #define REG_GCLK_PCHCTRL7 (*(RwReg *)0x4000189CUL) /**< \brief (GCLK) Peripheral Clock Control 7 */ 102 #define REG_GCLK_PCHCTRL8 (*(RwReg *)0x400018A0UL) /**< \brief (GCLK) Peripheral Clock Control 8 */ 103 #define REG_GCLK_PCHCTRL9 (*(RwReg *)0x400018A4UL) /**< \brief (GCLK) Peripheral Clock Control 9 */ 104 #define REG_GCLK_PCHCTRL10 (*(RwReg *)0x400018A8UL) /**< \brief (GCLK) Peripheral Clock Control 10 */ 105 #define REG_GCLK_PCHCTRL11 (*(RwReg *)0x400018ACUL) /**< \brief (GCLK) Peripheral Clock Control 11 */ 106 #define REG_GCLK_PCHCTRL12 (*(RwReg *)0x400018B0UL) /**< \brief (GCLK) Peripheral Clock Control 12 */ 107 #define REG_GCLK_PCHCTRL13 (*(RwReg *)0x400018B4UL) /**< \brief (GCLK) Peripheral Clock Control 13 */ 108 #define REG_GCLK_PCHCTRL14 (*(RwReg *)0x400018B8UL) /**< \brief (GCLK) Peripheral Clock Control 14 */ 109 #define REG_GCLK_PCHCTRL15 (*(RwReg *)0x400018BCUL) /**< \brief (GCLK) Peripheral Clock Control 15 */ 110 #define REG_GCLK_PCHCTRL16 (*(RwReg *)0x400018C0UL) /**< \brief (GCLK) Peripheral Clock Control 16 */ 111 #define REG_GCLK_PCHCTRL17 (*(RwReg *)0x400018C4UL) /**< \brief (GCLK) Peripheral Clock Control 17 */ 112 #define REG_GCLK_PCHCTRL18 (*(RwReg *)0x400018C8UL) /**< \brief (GCLK) Peripheral Clock Control 18 */ 113 #define REG_GCLK_PCHCTRL19 (*(RwReg *)0x400018CCUL) /**< \brief (GCLK) Peripheral Clock Control 19 */ 114 #define REG_GCLK_PCHCTRL20 (*(RwReg *)0x400018D0UL) /**< \brief (GCLK) Peripheral Clock Control 20 */ 115 #define REG_GCLK_PCHCTRL21 (*(RwReg *)0x400018D4UL) /**< \brief (GCLK) Peripheral Clock Control 21 */ 116 #define REG_GCLK_PCHCTRL22 (*(RwReg *)0x400018D8UL) /**< \brief (GCLK) Peripheral Clock Control 22 */ 117 #define REG_GCLK_PCHCTRL23 (*(RwReg *)0x400018DCUL) /**< \brief (GCLK) Peripheral Clock Control 23 */ 118 #define REG_GCLK_PCHCTRL24 (*(RwReg *)0x400018E0UL) /**< \brief (GCLK) Peripheral Clock Control 24 */ 119 #define REG_GCLK_PCHCTRL25 (*(RwReg *)0x400018E4UL) /**< \brief (GCLK) Peripheral Clock Control 25 */ 120 #define REG_GCLK_PCHCTRL26 (*(RwReg *)0x400018E8UL) /**< \brief (GCLK) Peripheral Clock Control 26 */ 121 #define REG_GCLK_PCHCTRL27 (*(RwReg *)0x400018ECUL) /**< \brief (GCLK) Peripheral Clock Control 27 */ 122 #define REG_GCLK_PCHCTRL28 (*(RwReg *)0x400018F0UL) /**< \brief (GCLK) Peripheral Clock Control 28 */ 123 #define REG_GCLK_PCHCTRL29 (*(RwReg *)0x400018F4UL) /**< \brief (GCLK) Peripheral Clock Control 29 */ 124 #define REG_GCLK_PCHCTRL30 (*(RwReg *)0x400018F8UL) /**< \brief (GCLK) Peripheral Clock Control 30 */ 125 #define REG_GCLK_PCHCTRL31 (*(RwReg *)0x400018FCUL) /**< \brief (GCLK) Peripheral Clock Control 31 */ 126 #define REG_GCLK_PCHCTRL32 (*(RwReg *)0x40001900UL) /**< \brief (GCLK) Peripheral Clock Control 32 */ 127 #define REG_GCLK_PCHCTRL33 (*(RwReg *)0x40001904UL) /**< \brief (GCLK) Peripheral Clock Control 33 */ 128 #define REG_GCLK_PCHCTRL34 (*(RwReg *)0x40001908UL) /**< \brief (GCLK) Peripheral Clock Control 34 */ 129 #define REG_GCLK_PCHCTRL35 (*(RwReg *)0x4000190CUL) /**< \brief (GCLK) Peripheral Clock Control 35 */ 130 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 131 132 /* ========== Instance parameters for GCLK peripheral ========== */ 133 #define GCLK_GENDIV_BITS 16 134 #define GCLK_GEN_BITS 4 135 #define GCLK_GEN_NUM 9 // Number of Generic Clock Generators 136 #define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1 137 #define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1 138 #define GCLK_NUM 36 // Number of Generic Clock Users 139 #define GCLK_SOURCE_BITS 4 140 #define GCLK_SOURCE_DFLL48M 7 141 #define GCLK_SOURCE_DPLL96M 8 142 #define GCLK_SOURCE_GCLKGEN1 2 143 #define GCLK_SOURCE_GCLKIN 1 144 #define GCLK_SOURCE_NUM 9 // Number of Generic Clock Sources 145 #define GCLK_SOURCE_OSCULP32K 3 146 #define GCLK_SOURCE_OSC16M 6 147 #define GCLK_SOURCE_OSC32K 4 148 #define GCLK_SOURCE_XOSC 0 149 #define GCLK_SOURCE_XOSC32K 5 150 151 #endif /* _SAML21_GCLK_INSTANCE_ */ 152
