1 /** 2 * \file 3 * 4 * \brief Instance description for DSU 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAML21_DSU_INSTANCE_ 31 #define _SAML21_DSU_INSTANCE_ 32 33 /* ========== Register definition for DSU peripheral ========== */ 34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 #define REG_DSU_CTRL (0x41002000) /**< \brief (DSU) Control */ 36 #define REG_DSU_STATUSA (0x41002001) /**< \brief (DSU) Status A */ 37 #define REG_DSU_STATUSB (0x41002002) /**< \brief (DSU) Status B */ 38 #define REG_DSU_ADDR (0x41002004) /**< \brief (DSU) Address */ 39 #define REG_DSU_LENGTH (0x41002008) /**< \brief (DSU) Length */ 40 #define REG_DSU_DATA (0x4100200C) /**< \brief (DSU) Data */ 41 #define REG_DSU_DCC0 (0x41002010) /**< \brief (DSU) Debug Communication Channel 0 */ 42 #define REG_DSU_DCC1 (0x41002014) /**< \brief (DSU) Debug Communication Channel 1 */ 43 #define REG_DSU_DID (0x41002018) /**< \brief (DSU) Device Identification */ 44 #define REG_DSU_DCFG0 (0x410020F0) /**< \brief (DSU) Device Configuration 0 */ 45 #define REG_DSU_DCFG1 (0x410020F4) /**< \brief (DSU) Device Configuration 1 */ 46 #define REG_DSU_ENTRY0 (0x41003000) /**< \brief (DSU) Coresight ROM Table Entry 0 */ 47 #define REG_DSU_ENTRY1 (0x41003004) /**< \brief (DSU) Coresight ROM Table Entry 1 */ 48 #define REG_DSU_END (0x41003008) /**< \brief (DSU) Coresight ROM Table End */ 49 #define REG_DSU_MEMTYPE (0x41003FCC) /**< \brief (DSU) Coresight ROM Table Memory Type */ 50 #define REG_DSU_PID4 (0x41003FD0) /**< \brief (DSU) Peripheral Identification 4 */ 51 #define REG_DSU_PID5 (0x41003FD4) /**< \brief (DSU) Peripheral Identification 5 */ 52 #define REG_DSU_PID6 (0x41003FD8) /**< \brief (DSU) Peripheral Identification 6 */ 53 #define REG_DSU_PID7 (0x41003FDC) /**< \brief (DSU) Peripheral Identification 7 */ 54 #define REG_DSU_PID0 (0x41003FE0) /**< \brief (DSU) Peripheral Identification 0 */ 55 #define REG_DSU_PID1 (0x41003FE4) /**< \brief (DSU) Peripheral Identification 1 */ 56 #define REG_DSU_PID2 (0x41003FE8) /**< \brief (DSU) Peripheral Identification 2 */ 57 #define REG_DSU_PID3 (0x41003FEC) /**< \brief (DSU) Peripheral Identification 3 */ 58 #define REG_DSU_CID0 (0x41003FF0) /**< \brief (DSU) Component Identification 0 */ 59 #define REG_DSU_CID1 (0x41003FF4) /**< \brief (DSU) Component Identification 1 */ 60 #define REG_DSU_CID2 (0x41003FF8) /**< \brief (DSU) Component Identification 2 */ 61 #define REG_DSU_CID3 (0x41003FFC) /**< \brief (DSU) Component Identification 3 */ 62 #else 63 #define REG_DSU_CTRL (*(WoReg8 *)0x41002000UL) /**< \brief (DSU) Control */ 64 #define REG_DSU_STATUSA (*(RwReg8 *)0x41002001UL) /**< \brief (DSU) Status A */ 65 #define REG_DSU_STATUSB (*(RoReg8 *)0x41002002UL) /**< \brief (DSU) Status B */ 66 #define REG_DSU_ADDR (*(RwReg *)0x41002004UL) /**< \brief (DSU) Address */ 67 #define REG_DSU_LENGTH (*(RwReg *)0x41002008UL) /**< \brief (DSU) Length */ 68 #define REG_DSU_DATA (*(RwReg *)0x4100200CUL) /**< \brief (DSU) Data */ 69 #define REG_DSU_DCC0 (*(RwReg *)0x41002010UL) /**< \brief (DSU) Debug Communication Channel 0 */ 70 #define REG_DSU_DCC1 (*(RwReg *)0x41002014UL) /**< \brief (DSU) Debug Communication Channel 1 */ 71 #define REG_DSU_DID (*(RoReg *)0x41002018UL) /**< \brief (DSU) Device Identification */ 72 #define REG_DSU_DCFG0 (*(RwReg *)0x410020F0UL) /**< \brief (DSU) Device Configuration 0 */ 73 #define REG_DSU_DCFG1 (*(RwReg *)0x410020F4UL) /**< \brief (DSU) Device Configuration 1 */ 74 #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000UL) /**< \brief (DSU) Coresight ROM Table Entry 0 */ 75 #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004UL) /**< \brief (DSU) Coresight ROM Table Entry 1 */ 76 #define REG_DSU_END (*(RoReg *)0x41003008UL) /**< \brief (DSU) Coresight ROM Table End */ 77 #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCUL) /**< \brief (DSU) Coresight ROM Table Memory Type */ 78 #define REG_DSU_PID4 (*(RoReg *)0x41003FD0UL) /**< \brief (DSU) Peripheral Identification 4 */ 79 #define REG_DSU_PID5 (*(RoReg *)0x41003FD4UL) /**< \brief (DSU) Peripheral Identification 5 */ 80 #define REG_DSU_PID6 (*(RoReg *)0x41003FD8UL) /**< \brief (DSU) Peripheral Identification 6 */ 81 #define REG_DSU_PID7 (*(RoReg *)0x41003FDCUL) /**< \brief (DSU) Peripheral Identification 7 */ 82 #define REG_DSU_PID0 (*(RoReg *)0x41003FE0UL) /**< \brief (DSU) Peripheral Identification 0 */ 83 #define REG_DSU_PID1 (*(RoReg *)0x41003FE4UL) /**< \brief (DSU) Peripheral Identification 1 */ 84 #define REG_DSU_PID2 (*(RoReg *)0x41003FE8UL) /**< \brief (DSU) Peripheral Identification 2 */ 85 #define REG_DSU_PID3 (*(RoReg *)0x41003FECUL) /**< \brief (DSU) Peripheral Identification 3 */ 86 #define REG_DSU_CID0 (*(RoReg *)0x41003FF0UL) /**< \brief (DSU) Component Identification 0 */ 87 #define REG_DSU_CID1 (*(RoReg *)0x41003FF4UL) /**< \brief (DSU) Component Identification 1 */ 88 #define REG_DSU_CID2 (*(RoReg *)0x41003FF8UL) /**< \brief (DSU) Component Identification 2 */ 89 #define REG_DSU_CID3 (*(RoReg *)0x41003FFCUL) /**< \brief (DSU) Component Identification 3 */ 90 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 /* ========== Instance parameters for DSU peripheral ========== */ 93 #define DSU_CLK_AHB_ID 5 94 95 #endif /* _SAML21_DSU_INSTANCE_ */ 96
