1 /** 2 * \file 3 * 4 * \brief Component description for OSCCTRL 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAML21_OSCCTRL_COMPONENT_ 31 #define _SAML21_OSCCTRL_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR OSCCTRL */ 35 /* ========================================================================== */ 36 /** \addtogroup SAML21_OSCCTRL Oscillators Control */ 37 /*@{*/ 38 39 #define OSCCTRL_U2119 40 #define REV_OSCCTRL 0x110 41 42 /* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ 47 uint32_t :3; /*!< bit: 1.. 3 Reserved */ 48 uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready Interrupt Enable */ 49 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 50 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ 51 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ 52 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ 53 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ 54 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ 55 uint32_t :3; /*!< bit: 13..15 Reserved */ 56 uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise Interrupt Enable */ 57 uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall Interrupt Enable */ 58 uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Time Out Interrupt Enable */ 59 uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready Interrupt Enable */ 60 uint32_t :12; /*!< bit: 20..31 Reserved */ 61 } bit; /*!< Structure used for bit access */ 62 uint32_t reg; /*!< Type used for register access */ 63 } OSCCTRL_INTENCLR_Type; 64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 65 66 #define OSCCTRL_INTENCLR_OFFSET 0x00 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */ 67 #define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 68 69 #define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC Ready Interrupt Enable */ 70 #define OSCCTRL_INTENCLR_XOSCRDY (_U_(0x1) << OSCCTRL_INTENCLR_XOSCRDY_Pos) 71 #define OSCCTRL_INTENCLR_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTENCLR) OSC16M Ready Interrupt Enable */ 72 #define OSCCTRL_INTENCLR_OSC16MRDY (_U_(0x1) << OSCCTRL_INTENCLR_OSC16MRDY_Pos) 73 #define OSCCTRL_INTENCLR_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */ 74 #define OSCCTRL_INTENCLR_DFLLRDY (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos) 75 #define OSCCTRL_INTENCLR_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */ 76 #define OSCCTRL_INTENCLR_DFLLOOB (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos) 77 #define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */ 78 #define OSCCTRL_INTENCLR_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos) 79 #define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */ 80 #define OSCCTRL_INTENCLR_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos) 81 #define OSCCTRL_INTENCLR_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */ 82 #define OSCCTRL_INTENCLR_DFLLRCS (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos) 83 #define OSCCTRL_INTENCLR_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Rise Interrupt Enable */ 84 #define OSCCTRL_INTENCLR_DPLLLCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLCKR_Pos) 85 #define OSCCTRL_INTENCLR_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTENCLR) DPLL Lock Fall Interrupt Enable */ 86 #define OSCCTRL_INTENCLR_DPLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLCKF_Pos) 87 #define OSCCTRL_INTENCLR_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTENCLR) DPLL Time Out Interrupt Enable */ 88 #define OSCCTRL_INTENCLR_DPLLLTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLTO_Pos) 89 #define OSCCTRL_INTENCLR_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTENCLR) DPLL Ratio Ready Interrupt Enable */ 90 #define OSCCTRL_INTENCLR_DPLLLDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLLLDRTO_Pos) 91 #define OSCCTRL_INTENCLR_MASK _U_(0x000F1F11) /**< \brief (OSCCTRL_INTENCLR) MASK Register */ 92 93 /* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 95 typedef union { 96 struct { 97 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */ 98 uint32_t :3; /*!< bit: 1.. 3 Reserved */ 99 uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready Interrupt Enable */ 100 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 101 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ 102 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ 103 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ 104 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ 105 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ 106 uint32_t :3; /*!< bit: 13..15 Reserved */ 107 uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise Interrupt Enable */ 108 uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall Interrupt Enable */ 109 uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Time Out Interrupt Enable */ 110 uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready Interrupt Enable */ 111 uint32_t :12; /*!< bit: 20..31 Reserved */ 112 } bit; /*!< Structure used for bit access */ 113 uint32_t reg; /*!< Type used for register access */ 114 } OSCCTRL_INTENSET_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 #define OSCCTRL_INTENSET_OFFSET 0x04 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */ 118 #define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */ 119 120 #define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC Ready Interrupt Enable */ 121 #define OSCCTRL_INTENSET_XOSCRDY (_U_(0x1) << OSCCTRL_INTENSET_XOSCRDY_Pos) 122 #define OSCCTRL_INTENSET_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTENSET) OSC16M Ready Interrupt Enable */ 123 #define OSCCTRL_INTENSET_OSC16MRDY (_U_(0x1) << OSCCTRL_INTENSET_OSC16MRDY_Pos) 124 #define OSCCTRL_INTENSET_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */ 125 #define OSCCTRL_INTENSET_DFLLRDY (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos) 126 #define OSCCTRL_INTENSET_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */ 127 #define OSCCTRL_INTENSET_DFLLOOB (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos) 128 #define OSCCTRL_INTENSET_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */ 129 #define OSCCTRL_INTENSET_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos) 130 #define OSCCTRL_INTENSET_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */ 131 #define OSCCTRL_INTENSET_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos) 132 #define OSCCTRL_INTENSET_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */ 133 #define OSCCTRL_INTENSET_DFLLRCS (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos) 134 #define OSCCTRL_INTENSET_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Rise Interrupt Enable */ 135 #define OSCCTRL_INTENSET_DPLLLCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLLLCKR_Pos) 136 #define OSCCTRL_INTENSET_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTENSET) DPLL Lock Fall Interrupt Enable */ 137 #define OSCCTRL_INTENSET_DPLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLLLCKF_Pos) 138 #define OSCCTRL_INTENSET_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTENSET) DPLL Time Out Interrupt Enable */ 139 #define OSCCTRL_INTENSET_DPLLLTO (_U_(0x1) << OSCCTRL_INTENSET_DPLLLTO_Pos) 140 #define OSCCTRL_INTENSET_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTENSET) DPLL Ratio Ready Interrupt Enable */ 141 #define OSCCTRL_INTENSET_DPLLLDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLLLDRTO_Pos) 142 #define OSCCTRL_INTENSET_MASK _U_(0x000F1F11) /**< \brief (OSCCTRL_INTENSET) MASK Register */ 143 144 /* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 145 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 146 typedef union { // __I to avoid read-modify-write on write-to-clear register 147 struct { 148 __I uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ 149 __I uint32_t :3; /*!< bit: 1.. 3 Reserved */ 150 __I uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready */ 151 __I uint32_t :3; /*!< bit: 5.. 7 Reserved */ 152 __I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ 153 __I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ 154 __I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ 155 __I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ 156 __I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ 157 __I uint32_t :3; /*!< bit: 13..15 Reserved */ 158 __I uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise */ 159 __I uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall */ 160 __I uint32_t DPLLLTO:1; /*!< bit: 18 DPLL Timeout */ 161 __I uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready */ 162 __I uint32_t :12; /*!< bit: 20..31 Reserved */ 163 } bit; /*!< Structure used for bit access */ 164 uint32_t reg; /*!< Type used for register access */ 165 } OSCCTRL_INTFLAG_Type; 166 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 167 168 #define OSCCTRL_INTFLAG_OFFSET 0x08 /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 169 #define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 170 171 #define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC Ready */ 172 #define OSCCTRL_INTFLAG_XOSCRDY (_U_(0x1) << OSCCTRL_INTFLAG_XOSCRDY_Pos) 173 #define OSCCTRL_INTFLAG_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_INTFLAG) OSC16M Ready */ 174 #define OSCCTRL_INTFLAG_OSC16MRDY (_U_(0x1) << OSCCTRL_INTFLAG_OSC16MRDY_Pos) 175 #define OSCCTRL_INTFLAG_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */ 176 #define OSCCTRL_INTFLAG_DFLLRDY (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos) 177 #define OSCCTRL_INTFLAG_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */ 178 #define OSCCTRL_INTFLAG_DFLLOOB (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos) 179 #define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */ 180 #define OSCCTRL_INTFLAG_DFLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos) 181 #define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */ 182 #define OSCCTRL_INTFLAG_DFLLLCKC (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos) 183 #define OSCCTRL_INTFLAG_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */ 184 #define OSCCTRL_INTFLAG_DFLLRCS (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos) 185 #define OSCCTRL_INTFLAG_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Rise */ 186 #define OSCCTRL_INTFLAG_DPLLLCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLCKR_Pos) 187 #define OSCCTRL_INTFLAG_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_INTFLAG) DPLL Lock Fall */ 188 #define OSCCTRL_INTFLAG_DPLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLCKF_Pos) 189 #define OSCCTRL_INTFLAG_DPLLLTO_Pos 18 /**< \brief (OSCCTRL_INTFLAG) DPLL Timeout */ 190 #define OSCCTRL_INTFLAG_DPLLLTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLTO_Pos) 191 #define OSCCTRL_INTFLAG_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_INTFLAG) DPLL Ratio Ready */ 192 #define OSCCTRL_INTFLAG_DPLLLDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLLLDRTO_Pos) 193 #define OSCCTRL_INTFLAG_MASK _U_(0x000F1F11) /**< \brief (OSCCTRL_INTFLAG) MASK Register */ 194 195 /* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ 196 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 197 typedef union { 198 struct { 199 uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */ 200 uint32_t :3; /*!< bit: 1.. 3 Reserved */ 201 uint32_t OSC16MRDY:1; /*!< bit: 4 OSC16M Ready */ 202 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 203 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ 204 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ 205 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ 206 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ 207 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ 208 uint32_t :3; /*!< bit: 13..15 Reserved */ 209 uint32_t DPLLLCKR:1; /*!< bit: 16 DPLL Lock Rise */ 210 uint32_t DPLLLCKF:1; /*!< bit: 17 DPLL Lock Fall */ 211 uint32_t DPLLTO:1; /*!< bit: 18 DPLL Timeout */ 212 uint32_t DPLLLDRTO:1; /*!< bit: 19 DPLL Ratio Ready */ 213 uint32_t :12; /*!< bit: 20..31 Reserved */ 214 } bit; /*!< Structure used for bit access */ 215 uint32_t reg; /*!< Type used for register access */ 216 } OSCCTRL_STATUS_Type; 217 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 218 219 #define OSCCTRL_STATUS_OFFSET 0x0C /**< \brief (OSCCTRL_STATUS offset) Power and Clocks Status */ 220 #define OSCCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Power and Clocks Status */ 221 222 #define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC Ready */ 223 #define OSCCTRL_STATUS_XOSCRDY (_U_(0x1) << OSCCTRL_STATUS_XOSCRDY_Pos) 224 #define OSCCTRL_STATUS_OSC16MRDY_Pos 4 /**< \brief (OSCCTRL_STATUS) OSC16M Ready */ 225 #define OSCCTRL_STATUS_OSC16MRDY (_U_(0x1) << OSCCTRL_STATUS_OSC16MRDY_Pos) 226 #define OSCCTRL_STATUS_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_STATUS) DFLL Ready */ 227 #define OSCCTRL_STATUS_DFLLRDY (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos) 228 #define OSCCTRL_STATUS_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */ 229 #define OSCCTRL_STATUS_DFLLOOB (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos) 230 #define OSCCTRL_STATUS_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */ 231 #define OSCCTRL_STATUS_DFLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos) 232 #define OSCCTRL_STATUS_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */ 233 #define OSCCTRL_STATUS_DFLLLCKC (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos) 234 #define OSCCTRL_STATUS_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */ 235 #define OSCCTRL_STATUS_DFLLRCS (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos) 236 #define OSCCTRL_STATUS_DPLLLCKR_Pos 16 /**< \brief (OSCCTRL_STATUS) DPLL Lock Rise */ 237 #define OSCCTRL_STATUS_DPLLLCKR (_U_(0x1) << OSCCTRL_STATUS_DPLLLCKR_Pos) 238 #define OSCCTRL_STATUS_DPLLLCKF_Pos 17 /**< \brief (OSCCTRL_STATUS) DPLL Lock Fall */ 239 #define OSCCTRL_STATUS_DPLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DPLLLCKF_Pos) 240 #define OSCCTRL_STATUS_DPLLTO_Pos 18 /**< \brief (OSCCTRL_STATUS) DPLL Timeout */ 241 #define OSCCTRL_STATUS_DPLLTO (_U_(0x1) << OSCCTRL_STATUS_DPLLTO_Pos) 242 #define OSCCTRL_STATUS_DPLLLDRTO_Pos 19 /**< \brief (OSCCTRL_STATUS) DPLL Ratio Ready */ 243 #define OSCCTRL_STATUS_DPLLLDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLLLDRTO_Pos) 244 #define OSCCTRL_STATUS_MASK _U_(0x000F1F11) /**< \brief (OSCCTRL_STATUS) MASK Register */ 245 246 /* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */ 247 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 248 typedef union { 249 struct { 250 uint16_t :1; /*!< bit: 0 Reserved */ 251 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 252 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ 253 uint16_t :3; /*!< bit: 3.. 5 Reserved */ 254 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 255 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 256 uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */ 257 uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */ 258 uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */ 259 } bit; /*!< Structure used for bit access */ 260 uint16_t reg; /*!< Type used for register access */ 261 } OSCCTRL_XOSCCTRL_Type; 262 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 263 264 #define OSCCTRL_XOSCCTRL_OFFSET 0x10 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator (XOSC) Control */ 265 #define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x0080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator (XOSC) Control */ 266 267 #define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */ 268 #define OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos) 269 #define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */ 270 #define OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos) 271 #define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */ 272 #define OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) 273 #define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */ 274 #define OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) 275 #define OSCCTRL_XOSCCTRL_GAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Gain */ 276 #define OSCCTRL_XOSCCTRL_GAIN_Msk (_U_(0x7) << OSCCTRL_XOSCCTRL_GAIN_Pos) 277 #define OSCCTRL_XOSCCTRL_GAIN(value) (OSCCTRL_XOSCCTRL_GAIN_Msk & ((value) << OSCCTRL_XOSCCTRL_GAIN_Pos)) 278 #define OSCCTRL_XOSCCTRL_AMPGC_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Amplitude Gain Control */ 279 #define OSCCTRL_XOSCCTRL_AMPGC (_U_(0x1) << OSCCTRL_XOSCCTRL_AMPGC_Pos) 280 #define OSCCTRL_XOSCCTRL_STARTUP_Pos 12 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */ 281 #define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos) 282 #define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos)) 283 #define OSCCTRL_XOSCCTRL_MASK _U_(0xFFC6) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */ 284 285 /* -------- OSCCTRL_OSC16MCTRL : (OSCCTRL Offset: 0x14) (R/W 8) 16MHz Internal Oscillator (OSC16M) Control -------- */ 286 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 287 typedef union { 288 struct { 289 uint8_t :1; /*!< bit: 0 Reserved */ 290 uint8_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 291 uint8_t FSEL:2; /*!< bit: 2.. 3 Oscillator Frequency Select */ 292 uint8_t :2; /*!< bit: 4.. 5 Reserved */ 293 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 294 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 295 } bit; /*!< Structure used for bit access */ 296 uint8_t reg; /*!< Type used for register access */ 297 } OSCCTRL_OSC16MCTRL_Type; 298 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 299 300 #define OSCCTRL_OSC16MCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_OSC16MCTRL offset) 16MHz Internal Oscillator (OSC16M) Control */ 301 #define OSCCTRL_OSC16MCTRL_RESETVALUE _U_(0x82) /**< \brief (OSCCTRL_OSC16MCTRL reset_value) 16MHz Internal Oscillator (OSC16M) Control */ 302 303 #define OSCCTRL_OSC16MCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Enable */ 304 #define OSCCTRL_OSC16MCTRL_ENABLE (_U_(0x1) << OSCCTRL_OSC16MCTRL_ENABLE_Pos) 305 #define OSCCTRL_OSC16MCTRL_FSEL_Pos 2 /**< \brief (OSCCTRL_OSC16MCTRL) Oscillator Frequency Select */ 306 #define OSCCTRL_OSC16MCTRL_FSEL_Msk (_U_(0x3) << OSCCTRL_OSC16MCTRL_FSEL_Pos) 307 #define OSCCTRL_OSC16MCTRL_FSEL(value) (OSCCTRL_OSC16MCTRL_FSEL_Msk & ((value) << OSCCTRL_OSC16MCTRL_FSEL_Pos)) 308 #define OSCCTRL_OSC16MCTRL_FSEL_4_Val _U_(0x0) /**< \brief (OSCCTRL_OSC16MCTRL) 4MHz */ 309 #define OSCCTRL_OSC16MCTRL_FSEL_8_Val _U_(0x1) /**< \brief (OSCCTRL_OSC16MCTRL) 8MHz */ 310 #define OSCCTRL_OSC16MCTRL_FSEL_12_Val _U_(0x2) /**< \brief (OSCCTRL_OSC16MCTRL) 12MHz */ 311 #define OSCCTRL_OSC16MCTRL_FSEL_16_Val _U_(0x3) /**< \brief (OSCCTRL_OSC16MCTRL) 16MHz */ 312 #define OSCCTRL_OSC16MCTRL_FSEL_4 (OSCCTRL_OSC16MCTRL_FSEL_4_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) 313 #define OSCCTRL_OSC16MCTRL_FSEL_8 (OSCCTRL_OSC16MCTRL_FSEL_8_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) 314 #define OSCCTRL_OSC16MCTRL_FSEL_12 (OSCCTRL_OSC16MCTRL_FSEL_12_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) 315 #define OSCCTRL_OSC16MCTRL_FSEL_16 (OSCCTRL_OSC16MCTRL_FSEL_16_Val << OSCCTRL_OSC16MCTRL_FSEL_Pos) 316 #define OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_OSC16MCTRL) Run in Standby */ 317 #define OSCCTRL_OSC16MCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_OSC16MCTRL_RUNSTDBY_Pos) 318 #define OSCCTRL_OSC16MCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_OSC16MCTRL) On Demand Control */ 319 #define OSCCTRL_OSC16MCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_OSC16MCTRL_ONDEMAND_Pos) 320 #define OSCCTRL_OSC16MCTRL_MASK _U_(0xCE) /**< \brief (OSCCTRL_OSC16MCTRL) MASK Register */ 321 322 /* -------- OSCCTRL_DFLLCTRL : (OSCCTRL Offset: 0x18) (R/W 16) DFLL48M Control -------- */ 323 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 324 typedef union { 325 struct { 326 uint16_t :1; /*!< bit: 0 Reserved */ 327 uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */ 328 uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */ 329 uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */ 330 uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */ 331 uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */ 332 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 333 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 334 uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */ 335 uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */ 336 uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */ 337 uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */ 338 uint16_t :4; /*!< bit: 12..15 Reserved */ 339 } bit; /*!< Structure used for bit access */ 340 uint16_t reg; /*!< Type used for register access */ 341 } OSCCTRL_DFLLCTRL_Type; 342 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 343 344 #define OSCCTRL_DFLLCTRL_OFFSET 0x18 /**< \brief (OSCCTRL_DFLLCTRL offset) DFLL48M Control */ 345 #define OSCCTRL_DFLLCTRL_RESETVALUE _U_(0x0080) /**< \brief (OSCCTRL_DFLLCTRL reset_value) DFLL48M Control */ 346 347 #define OSCCTRL_DFLLCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRL) DFLL Enable */ 348 #define OSCCTRL_DFLLCTRL_ENABLE (_U_(0x1) << OSCCTRL_DFLLCTRL_ENABLE_Pos) 349 #define OSCCTRL_DFLLCTRL_MODE_Pos 2 /**< \brief (OSCCTRL_DFLLCTRL) Operating Mode Selection */ 350 #define OSCCTRL_DFLLCTRL_MODE (_U_(0x1) << OSCCTRL_DFLLCTRL_MODE_Pos) 351 #define OSCCTRL_DFLLCTRL_STABLE_Pos 3 /**< \brief (OSCCTRL_DFLLCTRL) Stable DFLL Frequency */ 352 #define OSCCTRL_DFLLCTRL_STABLE (_U_(0x1) << OSCCTRL_DFLLCTRL_STABLE_Pos) 353 #define OSCCTRL_DFLLCTRL_LLAW_Pos 4 /**< \brief (OSCCTRL_DFLLCTRL) Lose Lock After Wake */ 354 #define OSCCTRL_DFLLCTRL_LLAW (_U_(0x1) << OSCCTRL_DFLLCTRL_LLAW_Pos) 355 #define OSCCTRL_DFLLCTRL_USBCRM_Pos 5 /**< \brief (OSCCTRL_DFLLCTRL) USB Clock Recovery Mode */ 356 #define OSCCTRL_DFLLCTRL_USBCRM (_U_(0x1) << OSCCTRL_DFLLCTRL_USBCRM_Pos) 357 #define OSCCTRL_DFLLCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DFLLCTRL) Run in Standby */ 358 #define OSCCTRL_DFLLCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_DFLLCTRL_RUNSTDBY_Pos) 359 #define OSCCTRL_DFLLCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DFLLCTRL) On Demand Control */ 360 #define OSCCTRL_DFLLCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_DFLLCTRL_ONDEMAND_Pos) 361 #define OSCCTRL_DFLLCTRL_CCDIS_Pos 8 /**< \brief (OSCCTRL_DFLLCTRL) Chill Cycle Disable */ 362 #define OSCCTRL_DFLLCTRL_CCDIS (_U_(0x1) << OSCCTRL_DFLLCTRL_CCDIS_Pos) 363 #define OSCCTRL_DFLLCTRL_QLDIS_Pos 9 /**< \brief (OSCCTRL_DFLLCTRL) Quick Lock Disable */ 364 #define OSCCTRL_DFLLCTRL_QLDIS (_U_(0x1) << OSCCTRL_DFLLCTRL_QLDIS_Pos) 365 #define OSCCTRL_DFLLCTRL_BPLCKC_Pos 10 /**< \brief (OSCCTRL_DFLLCTRL) Bypass Coarse Lock */ 366 #define OSCCTRL_DFLLCTRL_BPLCKC (_U_(0x1) << OSCCTRL_DFLLCTRL_BPLCKC_Pos) 367 #define OSCCTRL_DFLLCTRL_WAITLOCK_Pos 11 /**< \brief (OSCCTRL_DFLLCTRL) Wait Lock */ 368 #define OSCCTRL_DFLLCTRL_WAITLOCK (_U_(0x1) << OSCCTRL_DFLLCTRL_WAITLOCK_Pos) 369 #define OSCCTRL_DFLLCTRL_MASK _U_(0x0FFE) /**< \brief (OSCCTRL_DFLLCTRL) MASK Register */ 370 371 /* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x1C) (R/W 32) DFLL48M Value -------- */ 372 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 373 typedef union { 374 struct { 375 uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */ 376 uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ 377 uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ 378 } bit; /*!< Structure used for bit access */ 379 uint32_t reg; /*!< Type used for register access */ 380 } OSCCTRL_DFLLVAL_Type; 381 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 382 383 #define OSCCTRL_DFLLVAL_OFFSET 0x1C /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */ 384 #define OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */ 385 386 #define OSCCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (OSCCTRL_DFLLVAL) Fine Value */ 387 #define OSCCTRL_DFLLVAL_FINE_Msk (_U_(0x3FF) << OSCCTRL_DFLLVAL_FINE_Pos) 388 #define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos)) 389 #define OSCCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */ 390 #define OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos) 391 #define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos)) 392 #define OSCCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */ 393 #define OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos) 394 #define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos)) 395 #define OSCCTRL_DFLLVAL_MASK _U_(0xFFFFFFFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */ 396 397 /* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x20) (R/W 32) DFLL48M Multiplier -------- */ 398 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 399 typedef union { 400 struct { 401 uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ 402 uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */ 403 uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ 404 } bit; /*!< Structure used for bit access */ 405 uint32_t reg; /*!< Type used for register access */ 406 } OSCCTRL_DFLLMUL_Type; 407 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 408 409 #define OSCCTRL_DFLLMUL_OFFSET 0x20 /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */ 410 #define OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */ 411 412 #define OSCCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */ 413 #define OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos) 414 #define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos)) 415 #define OSCCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */ 416 #define OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0x3FF) << OSCCTRL_DFLLMUL_FSTEP_Pos) 417 #define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos)) 418 #define OSCCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */ 419 #define OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos) 420 #define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos)) 421 #define OSCCTRL_DFLLMUL_MASK _U_(0xFFFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */ 422 423 /* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x24) (R/W 8) DFLL48M Synchronization -------- */ 424 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 425 typedef union { 426 struct { 427 uint8_t :7; /*!< bit: 0.. 6 Reserved */ 428 uint8_t READREQ:1; /*!< bit: 7 Read Request */ 429 } bit; /*!< Structure used for bit access */ 430 uint8_t reg; /*!< Type used for register access */ 431 } OSCCTRL_DFLLSYNC_Type; 432 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 433 434 #define OSCCTRL_DFLLSYNC_OFFSET 0x24 /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */ 435 #define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */ 436 437 #define OSCCTRL_DFLLSYNC_READREQ_Pos 7 /**< \brief (OSCCTRL_DFLLSYNC) Read Request */ 438 #define OSCCTRL_DFLLSYNC_READREQ (_U_(0x1) << OSCCTRL_DFLLSYNC_READREQ_Pos) 439 #define OSCCTRL_DFLLSYNC_MASK _U_(0x80) /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */ 440 441 /* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x28) (R/W 8) DPLL Control -------- */ 442 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 443 typedef union { 444 struct { 445 uint8_t :1; /*!< bit: 0 Reserved */ 446 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 447 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 448 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 449 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand */ 450 } bit; /*!< Structure used for bit access */ 451 uint8_t reg; /*!< Type used for register access */ 452 } OSCCTRL_DPLLCTRLA_Type; 453 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 454 455 #define OSCCTRL_DPLLCTRLA_OFFSET 0x28 /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control */ 456 #define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control */ 457 458 #define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) Enable */ 459 #define OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos) 460 #define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */ 461 #define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) 462 #define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand */ 463 #define OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) 464 #define OSCCTRL_DPLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */ 465 466 /* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x2C) (R/W 32) DPLL Ratio Control -------- */ 467 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 468 typedef union { 469 struct { 470 uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */ 471 uint32_t :4; /*!< bit: 12..15 Reserved */ 472 uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */ 473 uint32_t :12; /*!< bit: 20..31 Reserved */ 474 } bit; /*!< Structure used for bit access */ 475 uint32_t reg; /*!< Type used for register access */ 476 } OSCCTRL_DPLLRATIO_Type; 477 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 478 479 #define OSCCTRL_DPLLRATIO_OFFSET 0x2C /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */ 480 #define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ 481 482 #define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */ 483 #define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0xFFF) << OSCCTRL_DPLLRATIO_LDR_Pos) 484 #define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos)) 485 #define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ 486 #define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0xF) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos) 487 #define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)) 488 #define OSCCTRL_DPLLRATIO_MASK _U_(0x000F0FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */ 489 490 /* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x30) (R/W 32) Digital Core Configuration -------- */ 491 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 492 typedef union { 493 struct { 494 uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */ 495 uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */ 496 uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */ 497 uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */ 498 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 499 uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ 500 uint32_t :1; /*!< bit: 11 Reserved */ 501 uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */ 502 uint32_t :3; /*!< bit: 13..15 Reserved */ 503 uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ 504 uint32_t :5; /*!< bit: 27..31 Reserved */ 505 } bit; /*!< Structure used for bit access */ 506 uint32_t reg; /*!< Type used for register access */ 507 } OSCCTRL_DPLLCTRLB_Type; 508 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 509 510 #define OSCCTRL_DPLLCTRLB_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLCTRLB offset) Digital Core Configuration */ 511 #define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) Digital Core Configuration */ 512 513 #define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ 514 #define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0x3) << OSCCTRL_DPLLCTRLB_FILTER_Pos) 515 #define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos)) 516 #define OSCCTRL_DPLLCTRLB_LPEN_Pos 2 /**< \brief (OSCCTRL_DPLLCTRLB) Low-Power Enable */ 517 #define OSCCTRL_DPLLCTRLB_LPEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_LPEN_Pos) 518 #define OSCCTRL_DPLLCTRLB_WUF_Pos 3 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */ 519 #define OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos) 520 #define OSCCTRL_DPLLCTRLB_REFCLK_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */ 521 #define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x3) << OSCCTRL_DPLLCTRLB_REFCLK_Pos) 522 #define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)) 523 #define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */ 524 #define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos) 525 #define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos)) 526 #define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */ 527 #define OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) 528 #define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */ 529 #define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos) 530 #define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos)) 531 #define OSCCTRL_DPLLCTRLB_MASK _U_(0x07FF173F) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */ 532 533 /* -------- OSCCTRL_DPLLPRESC : (OSCCTRL Offset: 0x34) (R/W 8) DPLL Prescaler -------- */ 534 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 535 typedef union { 536 struct { 537 uint8_t PRESC:2; /*!< bit: 0.. 1 Output Clock Prescaler */ 538 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 539 } bit; /*!< Structure used for bit access */ 540 uint8_t reg; /*!< Type used for register access */ 541 } OSCCTRL_DPLLPRESC_Type; 542 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 543 544 #define OSCCTRL_DPLLPRESC_OFFSET 0x34 /**< \brief (OSCCTRL_DPLLPRESC offset) DPLL Prescaler */ 545 #define OSCCTRL_DPLLPRESC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DPLLPRESC reset_value) DPLL Prescaler */ 546 547 #define OSCCTRL_DPLLPRESC_PRESC_Pos 0 /**< \brief (OSCCTRL_DPLLPRESC) Output Clock Prescaler */ 548 #define OSCCTRL_DPLLPRESC_PRESC_Msk (_U_(0x3) << OSCCTRL_DPLLPRESC_PRESC_Pos) 549 #define OSCCTRL_DPLLPRESC_PRESC(value) (OSCCTRL_DPLLPRESC_PRESC_Msk & ((value) << OSCCTRL_DPLLPRESC_PRESC_Pos)) 550 #define OSCCTRL_DPLLPRESC_PRESC_DIV1_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 1 */ 551 #define OSCCTRL_DPLLPRESC_PRESC_DIV2_Val _U_(0x1) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 2 */ 552 #define OSCCTRL_DPLLPRESC_PRESC_DIV4_Val _U_(0x2) /**< \brief (OSCCTRL_DPLLPRESC) DPLL output is divided by 4 */ 553 #define OSCCTRL_DPLLPRESC_PRESC_DIV1 (OSCCTRL_DPLLPRESC_PRESC_DIV1_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) 554 #define OSCCTRL_DPLLPRESC_PRESC_DIV2 (OSCCTRL_DPLLPRESC_PRESC_DIV2_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) 555 #define OSCCTRL_DPLLPRESC_PRESC_DIV4 (OSCCTRL_DPLLPRESC_PRESC_DIV4_Val << OSCCTRL_DPLLPRESC_PRESC_Pos) 556 #define OSCCTRL_DPLLPRESC_MASK _U_(0x03) /**< \brief (OSCCTRL_DPLLPRESC) MASK Register */ 557 558 /* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x38) (R/ 8) DPLL Synchronization Busy -------- */ 559 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 560 typedef union { 561 struct { 562 uint8_t :1; /*!< bit: 0 Reserved */ 563 uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */ 564 uint8_t DPLLRATIO:1; /*!< bit: 2 DPLL Ratio Synchronization Status */ 565 uint8_t DPLLPRESC:1; /*!< bit: 3 DPLL Prescaler Synchronization Status */ 566 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 567 } bit; /*!< Structure used for bit access */ 568 uint8_t reg; /*!< Type used for register access */ 569 } OSCCTRL_DPLLSYNCBUSY_Type; 570 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 571 572 #define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x38 /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */ 573 #define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */ 574 575 #define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */ 576 #define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos) 577 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Ratio Synchronization Status */ 578 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos) 579 #define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos 3 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Prescaler Synchronization Status */ 580 #define OSCCTRL_DPLLSYNCBUSY_DPLLPRESC (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLPRESC_Pos) 581 #define OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x0E) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */ 582 583 /* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x3C) (R/ 8) DPLL Status -------- */ 584 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 585 typedef union { 586 struct { 587 uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ 588 uint8_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */ 589 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 590 } bit; /*!< Structure used for bit access */ 591 uint8_t reg; /*!< Type used for register access */ 592 } OSCCTRL_DPLLSTATUS_Type; 593 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 594 595 #define OSCCTRL_DPLLSTATUS_OFFSET 0x3C /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */ 596 #define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */ 597 598 #define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */ 599 #define OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos) 600 #define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */ 601 #define OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos) 602 #define OSCCTRL_DPLLSTATUS_MASK _U_(0x03) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */ 603 604 /** \brief OSCCTRL hardware registers */ 605 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 606 typedef struct { 607 __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 608 __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 609 __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 610 __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 611 __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */ 612 RoReg8 Reserved1[0x2]; 613 __IO OSCCTRL_OSC16MCTRL_Type OSC16MCTRL; /**< \brief Offset: 0x14 (R/W 8) 16MHz Internal Oscillator (OSC16M) Control */ 614 RoReg8 Reserved2[0x3]; 615 __IO OSCCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x18 (R/W 16) DFLL48M Control */ 616 RoReg8 Reserved3[0x2]; 617 __IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x1C (R/W 32) DFLL48M Value */ 618 __IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x20 (R/W 32) DFLL48M Multiplier */ 619 __IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x24 (R/W 8) DFLL48M Synchronization */ 620 RoReg8 Reserved4[0x3]; 621 __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x28 (R/W 8) DPLL Control */ 622 RoReg8 Reserved5[0x3]; 623 __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x2C (R/W 32) DPLL Ratio Control */ 624 __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x30 (R/W 32) Digital Core Configuration */ 625 __IO OSCCTRL_DPLLPRESC_Type DPLLPRESC; /**< \brief Offset: 0x34 (R/W 8) DPLL Prescaler */ 626 RoReg8 Reserved6[0x3]; 627 __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x38 (R/ 8) DPLL Synchronization Busy */ 628 RoReg8 Reserved7[0x3]; 629 __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x3C (R/ 8) DPLL Status */ 630 } Oscctrl; 631 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 632 633 /*@}*/ 634 635 #endif /* _SAML21_OSCCTRL_COMPONENT_ */ 636
