1 /** 2 * \file 3 * 4 * \brief Component description for TRNG 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME54_TRNG_COMPONENT_ 31 #define _SAME54_TRNG_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR TRNG */ 35 /* ========================================================================== */ 36 /** \addtogroup SAME54_TRNG True Random Generator */ 37 /*@{*/ 38 39 #define TRNG_U2242 40 #define REV_TRNG 0x110 41 42 /* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t :1; /*!< bit: 0 Reserved */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 49 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 50 uint8_t :1; /*!< bit: 7 Reserved */ 51 } bit; /*!< Structure used for bit access */ 52 uint8_t reg; /*!< Type used for register access */ 53 } TRNG_CTRLA_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define TRNG_CTRLA_OFFSET 0x00 /**< \brief (TRNG_CTRLA offset) Control A */ 57 #define TRNG_CTRLA_RESETVALUE _U_(0x00) /**< \brief (TRNG_CTRLA reset_value) Control A */ 58 59 #define TRNG_CTRLA_ENABLE_Pos 1 /**< \brief (TRNG_CTRLA) Enable */ 60 #define TRNG_CTRLA_ENABLE (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos) 61 #define TRNG_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TRNG_CTRLA) Run in Standby */ 62 #define TRNG_CTRLA_RUNSTDBY (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos) 63 #define TRNG_CTRLA_MASK _U_(0x42) /**< \brief (TRNG_CTRLA) MASK Register */ 64 65 /* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */ 66 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 67 typedef union { 68 struct { 69 uint8_t DATARDYEO:1; /*!< bit: 0 Data Ready Event Output */ 70 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 71 } bit; /*!< Structure used for bit access */ 72 uint8_t reg; /*!< Type used for register access */ 73 } TRNG_EVCTRL_Type; 74 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 75 76 #define TRNG_EVCTRL_OFFSET 0x04 /**< \brief (TRNG_EVCTRL offset) Event Control */ 77 #define TRNG_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (TRNG_EVCTRL reset_value) Event Control */ 78 79 #define TRNG_EVCTRL_DATARDYEO_Pos 0 /**< \brief (TRNG_EVCTRL) Data Ready Event Output */ 80 #define TRNG_EVCTRL_DATARDYEO (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos) 81 #define TRNG_EVCTRL_MASK _U_(0x01) /**< \brief (TRNG_EVCTRL) MASK Register */ 82 83 /* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 84 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 85 typedef union { 86 struct { 87 uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ 88 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 89 } bit; /*!< Structure used for bit access */ 90 uint8_t reg; /*!< Type used for register access */ 91 } TRNG_INTENCLR_Type; 92 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 93 94 #define TRNG_INTENCLR_OFFSET 0x08 /**< \brief (TRNG_INTENCLR offset) Interrupt Enable Clear */ 95 #define TRNG_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENCLR reset_value) Interrupt Enable Clear */ 96 97 #define TRNG_INTENCLR_DATARDY_Pos 0 /**< \brief (TRNG_INTENCLR) Data Ready Interrupt Enable */ 98 #define TRNG_INTENCLR_DATARDY (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos) 99 #define TRNG_INTENCLR_MASK _U_(0x01) /**< \brief (TRNG_INTENCLR) MASK Register */ 100 101 /* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 102 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 103 typedef union { 104 struct { 105 uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Enable */ 106 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 107 } bit; /*!< Structure used for bit access */ 108 uint8_t reg; /*!< Type used for register access */ 109 } TRNG_INTENSET_Type; 110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 111 112 #define TRNG_INTENSET_OFFSET 0x09 /**< \brief (TRNG_INTENSET offset) Interrupt Enable Set */ 113 #define TRNG_INTENSET_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTENSET reset_value) Interrupt Enable Set */ 114 115 #define TRNG_INTENSET_DATARDY_Pos 0 /**< \brief (TRNG_INTENSET) Data Ready Interrupt Enable */ 116 #define TRNG_INTENSET_DATARDY (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos) 117 #define TRNG_INTENSET_MASK _U_(0x01) /**< \brief (TRNG_INTENSET) MASK Register */ 118 119 /* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 120 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 121 typedef union { // __I to avoid read-modify-write on write-to-clear register 122 struct { 123 __I uint8_t DATARDY:1; /*!< bit: 0 Data Ready Interrupt Flag */ 124 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 125 } bit; /*!< Structure used for bit access */ 126 uint8_t reg; /*!< Type used for register access */ 127 } TRNG_INTFLAG_Type; 128 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 129 130 #define TRNG_INTFLAG_OFFSET 0x0A /**< \brief (TRNG_INTFLAG offset) Interrupt Flag Status and Clear */ 131 #define TRNG_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (TRNG_INTFLAG reset_value) Interrupt Flag Status and Clear */ 132 133 #define TRNG_INTFLAG_DATARDY_Pos 0 /**< \brief (TRNG_INTFLAG) Data Ready Interrupt Flag */ 134 #define TRNG_INTFLAG_DATARDY (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos) 135 #define TRNG_INTFLAG_MASK _U_(0x01) /**< \brief (TRNG_INTFLAG) MASK Register */ 136 137 /* -------- TRNG_DATA : (TRNG Offset: 0x20) (R/ 32) Output Data -------- */ 138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 139 typedef union { 140 struct { 141 uint32_t DATA:32; /*!< bit: 0..31 Output Data */ 142 } bit; /*!< Structure used for bit access */ 143 uint32_t reg; /*!< Type used for register access */ 144 } TRNG_DATA_Type; 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 146 147 #define TRNG_DATA_OFFSET 0x20 /**< \brief (TRNG_DATA offset) Output Data */ 148 #define TRNG_DATA_RESETVALUE _U_(0x00000000) /**< \brief (TRNG_DATA reset_value) Output Data */ 149 150 #define TRNG_DATA_DATA_Pos 0 /**< \brief (TRNG_DATA) Output Data */ 151 #define TRNG_DATA_DATA_Msk (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos) 152 #define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos)) 153 #define TRNG_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (TRNG_DATA) MASK Register */ 154 155 /** \brief TRNG hardware registers */ 156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 157 typedef struct { 158 __IO TRNG_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 159 RoReg8 Reserved1[0x3]; 160 __IO TRNG_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 8) Event Control */ 161 RoReg8 Reserved2[0x3]; 162 __IO TRNG_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 163 __IO TRNG_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 164 __IO TRNG_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 165 RoReg8 Reserved3[0x15]; 166 __I TRNG_DATA_Type DATA; /**< \brief Offset: 0x20 (R/ 32) Output Data */ 167 } Trng; 168 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 169 170 /*@}*/ 171 172 #endif /* _SAME54_TRNG_COMPONENT_ */ 173
