1 /** 2 * \file 3 * 4 * \brief Component description for DAC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME54_DAC_COMPONENT_ 31 #define _SAME54_DAC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR DAC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAME54_DAC Digital-to-Analog Converter */ 37 /*@{*/ 38 39 #define DAC_U2502 40 #define REV_DAC 0x100 41 42 /* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ 48 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint8_t reg; /*!< Type used for register access */ 51 } DAC_CTRLA_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 #define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ 55 #define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ 56 57 #define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ 58 #define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) 59 #define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ 60 #define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) 61 #define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ 62 63 /* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ 68 uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ 69 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 70 } bit; /*!< Structure used for bit access */ 71 uint8_t reg; /*!< Type used for register access */ 72 } DAC_CTRLB_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 #define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ 76 #define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ 77 78 #define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ 79 #define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) 80 #define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ 81 #define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) 82 #define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) 83 #define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ 84 #define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ 85 #define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ 86 #define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ 87 #define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) 88 #define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) 89 #define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) 90 #define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) 91 #define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ 92 93 /* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ 94 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 95 typedef union { 96 struct { 97 uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ 98 uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ 99 uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ 100 uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ 101 uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ 102 uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ 103 uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ 104 uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ 105 } bit; /*!< Structure used for bit access */ 106 struct { 107 uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ 108 uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ 109 uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ 110 uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ 111 } vec; /*!< Structure used for vec access */ 112 uint8_t reg; /*!< Type used for register access */ 113 } DAC_EVCTRL_Type; 114 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 115 116 #define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ 117 #define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ 118 119 #define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ 120 #define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) 121 #define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ 122 #define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) 123 #define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ 124 #define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) 125 #define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) 126 #define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ 127 #define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) 128 #define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ 129 #define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) 130 #define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ 131 #define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) 132 #define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) 133 #define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ 134 #define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) 135 #define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ 136 #define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) 137 #define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ 138 #define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) 139 #define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) 140 #define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ 141 #define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) 142 #define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ 143 #define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) 144 #define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ 145 #define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) 146 #define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) 147 #define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ 148 149 /* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 151 typedef union { 152 struct { 153 uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ 154 uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ 155 uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ 156 uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ 157 uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ 158 uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ 159 uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ 160 uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ 161 } bit; /*!< Structure used for bit access */ 162 struct { 163 uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ 164 uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ 165 uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ 166 uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ 167 } vec; /*!< Structure used for vec access */ 168 uint8_t reg; /*!< Type used for register access */ 169 } DAC_INTENCLR_Type; 170 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 171 172 #define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ 173 #define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ 174 175 #define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ 176 #define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) 177 #define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ 178 #define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) 179 #define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ 180 #define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) 181 #define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) 182 #define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ 183 #define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) 184 #define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ 185 #define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) 186 #define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ 187 #define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) 188 #define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) 189 #define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ 190 #define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) 191 #define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ 192 #define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) 193 #define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ 194 #define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) 195 #define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) 196 #define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ 197 #define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) 198 #define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ 199 #define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) 200 #define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ 201 #define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) 202 #define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) 203 #define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ 204 205 /* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 206 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 207 typedef union { 208 struct { 209 uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ 210 uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ 211 uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ 212 uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ 213 uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ 214 uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ 215 uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ 216 uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ 217 } bit; /*!< Structure used for bit access */ 218 struct { 219 uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ 220 uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ 221 uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ 222 uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ 223 } vec; /*!< Structure used for vec access */ 224 uint8_t reg; /*!< Type used for register access */ 225 } DAC_INTENSET_Type; 226 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 227 228 #define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ 229 #define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ 230 231 #define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ 232 #define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) 233 #define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ 234 #define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) 235 #define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ 236 #define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) 237 #define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) 238 #define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ 239 #define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) 240 #define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ 241 #define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) 242 #define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ 243 #define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) 244 #define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) 245 #define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ 246 #define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) 247 #define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ 248 #define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) 249 #define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ 250 #define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) 251 #define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) 252 #define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ 253 #define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) 254 #define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ 255 #define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) 256 #define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ 257 #define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) 258 #define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) 259 #define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ 260 261 /* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 262 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 263 typedef union { // __I to avoid read-modify-write on write-to-clear register 264 struct { 265 __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ 266 __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ 267 __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ 268 __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ 269 __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ 270 __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ 271 __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ 272 __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ 273 } bit; /*!< Structure used for bit access */ 274 struct { 275 __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ 276 __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ 277 __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ 278 __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ 279 } vec; /*!< Structure used for vec access */ 280 uint8_t reg; /*!< Type used for register access */ 281 } DAC_INTFLAG_Type; 282 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 283 284 #define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ 285 #define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 286 287 #define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ 288 #define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) 289 #define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ 290 #define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) 291 #define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ 292 #define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) 293 #define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) 294 #define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ 295 #define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) 296 #define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ 297 #define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) 298 #define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ 299 #define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) 300 #define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) 301 #define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ 302 #define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) 303 #define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ 304 #define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) 305 #define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ 306 #define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) 307 #define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) 308 #define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ 309 #define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) 310 #define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ 311 #define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) 312 #define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ 313 #define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) 314 #define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) 315 #define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ 316 317 /* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ 318 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 319 typedef union { 320 struct { 321 uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ 322 uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ 323 uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ 324 uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ 325 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 326 } bit; /*!< Structure used for bit access */ 327 struct { 328 uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ 329 uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ 330 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 331 } vec; /*!< Structure used for vec access */ 332 uint8_t reg; /*!< Type used for register access */ 333 } DAC_STATUS_Type; 334 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 335 336 #define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ 337 #define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ 338 339 #define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ 340 #define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) 341 #define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ 342 #define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) 343 #define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ 344 #define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) 345 #define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) 346 #define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ 347 #define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) 348 #define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ 349 #define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) 350 #define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ 351 #define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) 352 #define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) 353 #define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ 354 355 /* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ 356 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 357 typedef union { 358 struct { 359 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 360 uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ 361 uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ 362 uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ 363 uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ 364 uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ 365 uint32_t :26; /*!< bit: 6..31 Reserved */ 366 } bit; /*!< Structure used for bit access */ 367 struct { 368 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 369 uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ 370 uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ 371 uint32_t :26; /*!< bit: 6..31 Reserved */ 372 } vec; /*!< Structure used for vec access */ 373 uint32_t reg; /*!< Type used for register access */ 374 } DAC_SYNCBUSY_Type; 375 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 376 377 #define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ 378 #define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ 379 380 #define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ 381 #define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) 382 #define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ 383 #define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) 384 #define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ 385 #define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) 386 #define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ 387 #define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) 388 #define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ 389 #define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) 390 #define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) 391 #define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ 392 #define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) 393 #define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ 394 #define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) 395 #define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ 396 #define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) 397 #define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) 398 #define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ 399 400 /* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ 401 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 402 typedef union { 403 struct { 404 uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ 405 uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ 406 uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ 407 uint16_t :1; /*!< bit: 4 Reserved */ 408 uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ 409 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 410 uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ 411 uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ 412 uint16_t :1; /*!< bit: 12 Reserved */ 413 uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ 414 } bit; /*!< Structure used for bit access */ 415 uint16_t reg; /*!< Type used for register access */ 416 } DAC_DACCTRL_Type; 417 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 418 419 #define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ 420 #define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ 421 422 #define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ 423 #define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) 424 #define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ 425 #define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) 426 #define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ 427 #define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) 428 #define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) 429 #define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ 430 #define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ 431 #define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ 432 #define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) 433 #define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) 434 #define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) 435 #define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ 436 #define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) 437 #define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ 438 #define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) 439 #define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ 440 #define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) 441 #define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ 442 #define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) 443 #define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) 444 #define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ 445 #define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) 446 #define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) 447 #define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ 448 449 /* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ 450 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 451 typedef union { 452 struct { 453 uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ 454 } bit; /*!< Structure used for bit access */ 455 uint16_t reg; /*!< Type used for register access */ 456 } DAC_DATA_Type; 457 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 458 459 #define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ 460 #define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ 461 462 #define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ 463 #define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) 464 #define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) 465 #define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ 466 467 /* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ 468 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 469 typedef union { 470 struct { 471 uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ 472 } bit; /*!< Structure used for bit access */ 473 uint16_t reg; /*!< Type used for register access */ 474 } DAC_DATABUF_Type; 475 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 476 477 #define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ 478 #define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ 479 480 #define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ 481 #define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) 482 #define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) 483 #define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ 484 485 /* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ 486 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 487 typedef union { 488 struct { 489 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 490 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 491 } bit; /*!< Structure used for bit access */ 492 uint8_t reg; /*!< Type used for register access */ 493 } DAC_DBGCTRL_Type; 494 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 495 496 #define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ 497 #define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ 498 499 #define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ 500 #define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) 501 #define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ 502 503 /* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ 504 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 505 typedef union { 506 struct { 507 uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ 508 } bit; /*!< Structure used for bit access */ 509 uint16_t reg; /*!< Type used for register access */ 510 } DAC_RESULT_Type; 511 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 512 513 #define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ 514 #define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ 515 516 #define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ 517 #define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) 518 #define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) 519 #define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ 520 521 /** \brief DAC hardware registers */ 522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 523 typedef struct { 524 __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 525 __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ 526 __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ 527 RoReg8 Reserved1[0x1]; 528 __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 529 __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 530 __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 531 __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ 532 __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ 533 __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ 534 __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ 535 __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ 536 __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ 537 RoReg8 Reserved2[0x3]; 538 __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ 539 } Dac; 540 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 541 542 /*@}*/ 543 544 #endif /* _SAME54_DAC_COMPONENT_ */ 545
