1 /** 2 * \file 3 * 4 * \brief Component description for TCC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAME53_TCC_COMPONENT_ 31 #define _SAME53_TCC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR TCC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAME53_TCC Timer Counter Control */ 37 /*@{*/ 38 39 #define TCC_U2213 40 #define REV_TCC 0x310 41 42 /* -------- TCC_CTRLA : (TCC Offset: 0x00) (R/W 32) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint32_t :3; /*!< bit: 2.. 4 Reserved */ 49 uint32_t RESOLUTION:2; /*!< bit: 5.. 6 Enhanced Resolution */ 50 uint32_t :1; /*!< bit: 7 Reserved */ 51 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ 52 uint32_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */ 53 uint32_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization Selection */ 54 uint32_t ALOCK:1; /*!< bit: 14 Auto Lock */ 55 uint32_t MSYNC:1; /*!< bit: 15 Master Synchronization (only for TCC Slave Instance) */ 56 uint32_t :7; /*!< bit: 16..22 Reserved */ 57 uint32_t DMAOS:1; /*!< bit: 23 DMA One-shot Trigger Mode */ 58 uint32_t CPTEN0:1; /*!< bit: 24 Capture Channel 0 Enable */ 59 uint32_t CPTEN1:1; /*!< bit: 25 Capture Channel 1 Enable */ 60 uint32_t CPTEN2:1; /*!< bit: 26 Capture Channel 2 Enable */ 61 uint32_t CPTEN3:1; /*!< bit: 27 Capture Channel 3 Enable */ 62 uint32_t CPTEN4:1; /*!< bit: 28 Capture Channel 4 Enable */ 63 uint32_t CPTEN5:1; /*!< bit: 29 Capture Channel 5 Enable */ 64 uint32_t :2; /*!< bit: 30..31 Reserved */ 65 } bit; /*!< Structure used for bit access */ 66 struct { 67 uint32_t :24; /*!< bit: 0..23 Reserved */ 68 uint32_t CPTEN:6; /*!< bit: 24..29 Capture Channel x Enable */ 69 uint32_t :2; /*!< bit: 30..31 Reserved */ 70 } vec; /*!< Structure used for vec access */ 71 uint32_t reg; /*!< Type used for register access */ 72 } TCC_CTRLA_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 #define TCC_CTRLA_OFFSET 0x00 /**< \brief (TCC_CTRLA offset) Control A */ 76 #define TCC_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CTRLA reset_value) Control A */ 77 78 #define TCC_CTRLA_SWRST_Pos 0 /**< \brief (TCC_CTRLA) Software Reset */ 79 #define TCC_CTRLA_SWRST (_U_(0x1) << TCC_CTRLA_SWRST_Pos) 80 #define TCC_CTRLA_ENABLE_Pos 1 /**< \brief (TCC_CTRLA) Enable */ 81 #define TCC_CTRLA_ENABLE (_U_(0x1) << TCC_CTRLA_ENABLE_Pos) 82 #define TCC_CTRLA_RESOLUTION_Pos 5 /**< \brief (TCC_CTRLA) Enhanced Resolution */ 83 #define TCC_CTRLA_RESOLUTION_Msk (_U_(0x3) << TCC_CTRLA_RESOLUTION_Pos) 84 #define TCC_CTRLA_RESOLUTION(value) (TCC_CTRLA_RESOLUTION_Msk & ((value) << TCC_CTRLA_RESOLUTION_Pos)) 85 #define TCC_CTRLA_RESOLUTION_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLA) Dithering is disabled */ 86 #define TCC_CTRLA_RESOLUTION_DITH4_Val _U_(0x1) /**< \brief (TCC_CTRLA) Dithering is done every 16 PWM frames */ 87 #define TCC_CTRLA_RESOLUTION_DITH5_Val _U_(0x2) /**< \brief (TCC_CTRLA) Dithering is done every 32 PWM frames */ 88 #define TCC_CTRLA_RESOLUTION_DITH6_Val _U_(0x3) /**< \brief (TCC_CTRLA) Dithering is done every 64 PWM frames */ 89 #define TCC_CTRLA_RESOLUTION_NONE (TCC_CTRLA_RESOLUTION_NONE_Val << TCC_CTRLA_RESOLUTION_Pos) 90 #define TCC_CTRLA_RESOLUTION_DITH4 (TCC_CTRLA_RESOLUTION_DITH4_Val << TCC_CTRLA_RESOLUTION_Pos) 91 #define TCC_CTRLA_RESOLUTION_DITH5 (TCC_CTRLA_RESOLUTION_DITH5_Val << TCC_CTRLA_RESOLUTION_Pos) 92 #define TCC_CTRLA_RESOLUTION_DITH6 (TCC_CTRLA_RESOLUTION_DITH6_Val << TCC_CTRLA_RESOLUTION_Pos) 93 #define TCC_CTRLA_PRESCALER_Pos 8 /**< \brief (TCC_CTRLA) Prescaler */ 94 #define TCC_CTRLA_PRESCALER_Msk (_U_(0x7) << TCC_CTRLA_PRESCALER_Pos) 95 #define TCC_CTRLA_PRESCALER(value) (TCC_CTRLA_PRESCALER_Msk & ((value) << TCC_CTRLA_PRESCALER_Pos)) 96 #define TCC_CTRLA_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (TCC_CTRLA) No division */ 97 #define TCC_CTRLA_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (TCC_CTRLA) Divide by 2 */ 98 #define TCC_CTRLA_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (TCC_CTRLA) Divide by 4 */ 99 #define TCC_CTRLA_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (TCC_CTRLA) Divide by 8 */ 100 #define TCC_CTRLA_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (TCC_CTRLA) Divide by 16 */ 101 #define TCC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (TCC_CTRLA) Divide by 64 */ 102 #define TCC_CTRLA_PRESCALER_DIV256_Val _U_(0x6) /**< \brief (TCC_CTRLA) Divide by 256 */ 103 #define TCC_CTRLA_PRESCALER_DIV1024_Val _U_(0x7) /**< \brief (TCC_CTRLA) Divide by 1024 */ 104 #define TCC_CTRLA_PRESCALER_DIV1 (TCC_CTRLA_PRESCALER_DIV1_Val << TCC_CTRLA_PRESCALER_Pos) 105 #define TCC_CTRLA_PRESCALER_DIV2 (TCC_CTRLA_PRESCALER_DIV2_Val << TCC_CTRLA_PRESCALER_Pos) 106 #define TCC_CTRLA_PRESCALER_DIV4 (TCC_CTRLA_PRESCALER_DIV4_Val << TCC_CTRLA_PRESCALER_Pos) 107 #define TCC_CTRLA_PRESCALER_DIV8 (TCC_CTRLA_PRESCALER_DIV8_Val << TCC_CTRLA_PRESCALER_Pos) 108 #define TCC_CTRLA_PRESCALER_DIV16 (TCC_CTRLA_PRESCALER_DIV16_Val << TCC_CTRLA_PRESCALER_Pos) 109 #define TCC_CTRLA_PRESCALER_DIV64 (TCC_CTRLA_PRESCALER_DIV64_Val << TCC_CTRLA_PRESCALER_Pos) 110 #define TCC_CTRLA_PRESCALER_DIV256 (TCC_CTRLA_PRESCALER_DIV256_Val << TCC_CTRLA_PRESCALER_Pos) 111 #define TCC_CTRLA_PRESCALER_DIV1024 (TCC_CTRLA_PRESCALER_DIV1024_Val << TCC_CTRLA_PRESCALER_Pos) 112 #define TCC_CTRLA_RUNSTDBY_Pos 11 /**< \brief (TCC_CTRLA) Run in Standby */ 113 #define TCC_CTRLA_RUNSTDBY (_U_(0x1) << TCC_CTRLA_RUNSTDBY_Pos) 114 #define TCC_CTRLA_PRESCSYNC_Pos 12 /**< \brief (TCC_CTRLA) Prescaler and Counter Synchronization Selection */ 115 #define TCC_CTRLA_PRESCSYNC_Msk (_U_(0x3) << TCC_CTRLA_PRESCSYNC_Pos) 116 #define TCC_CTRLA_PRESCSYNC(value) (TCC_CTRLA_PRESCSYNC_Msk & ((value) << TCC_CTRLA_PRESCSYNC_Pos)) 117 #define TCC_CTRLA_PRESCSYNC_GCLK_Val _U_(0x0) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK */ 118 #define TCC_CTRLA_PRESCSYNC_PRESC_Val _U_(0x1) /**< \brief (TCC_CTRLA) Reload or reset counter on next prescaler clock */ 119 #define TCC_CTRLA_PRESCSYNC_RESYNC_Val _U_(0x2) /**< \brief (TCC_CTRLA) Reload or reset counter on next GCLK and reset prescaler counter */ 120 #define TCC_CTRLA_PRESCSYNC_GCLK (TCC_CTRLA_PRESCSYNC_GCLK_Val << TCC_CTRLA_PRESCSYNC_Pos) 121 #define TCC_CTRLA_PRESCSYNC_PRESC (TCC_CTRLA_PRESCSYNC_PRESC_Val << TCC_CTRLA_PRESCSYNC_Pos) 122 #define TCC_CTRLA_PRESCSYNC_RESYNC (TCC_CTRLA_PRESCSYNC_RESYNC_Val << TCC_CTRLA_PRESCSYNC_Pos) 123 #define TCC_CTRLA_ALOCK_Pos 14 /**< \brief (TCC_CTRLA) Auto Lock */ 124 #define TCC_CTRLA_ALOCK (_U_(0x1) << TCC_CTRLA_ALOCK_Pos) 125 #define TCC_CTRLA_MSYNC_Pos 15 /**< \brief (TCC_CTRLA) Master Synchronization (only for TCC Slave Instance) */ 126 #define TCC_CTRLA_MSYNC (_U_(0x1) << TCC_CTRLA_MSYNC_Pos) 127 #define TCC_CTRLA_DMAOS_Pos 23 /**< \brief (TCC_CTRLA) DMA One-shot Trigger Mode */ 128 #define TCC_CTRLA_DMAOS (_U_(0x1) << TCC_CTRLA_DMAOS_Pos) 129 #define TCC_CTRLA_CPTEN0_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel 0 Enable */ 130 #define TCC_CTRLA_CPTEN0 (_U_(1) << TCC_CTRLA_CPTEN0_Pos) 131 #define TCC_CTRLA_CPTEN1_Pos 25 /**< \brief (TCC_CTRLA) Capture Channel 1 Enable */ 132 #define TCC_CTRLA_CPTEN1 (_U_(1) << TCC_CTRLA_CPTEN1_Pos) 133 #define TCC_CTRLA_CPTEN2_Pos 26 /**< \brief (TCC_CTRLA) Capture Channel 2 Enable */ 134 #define TCC_CTRLA_CPTEN2 (_U_(1) << TCC_CTRLA_CPTEN2_Pos) 135 #define TCC_CTRLA_CPTEN3_Pos 27 /**< \brief (TCC_CTRLA) Capture Channel 3 Enable */ 136 #define TCC_CTRLA_CPTEN3 (_U_(1) << TCC_CTRLA_CPTEN3_Pos) 137 #define TCC_CTRLA_CPTEN4_Pos 28 /**< \brief (TCC_CTRLA) Capture Channel 4 Enable */ 138 #define TCC_CTRLA_CPTEN4 (_U_(1) << TCC_CTRLA_CPTEN4_Pos) 139 #define TCC_CTRLA_CPTEN5_Pos 29 /**< \brief (TCC_CTRLA) Capture Channel 5 Enable */ 140 #define TCC_CTRLA_CPTEN5 (_U_(1) << TCC_CTRLA_CPTEN5_Pos) 141 #define TCC_CTRLA_CPTEN_Pos 24 /**< \brief (TCC_CTRLA) Capture Channel x Enable */ 142 #define TCC_CTRLA_CPTEN_Msk (_U_(0x3F) << TCC_CTRLA_CPTEN_Pos) 143 #define TCC_CTRLA_CPTEN(value) (TCC_CTRLA_CPTEN_Msk & ((value) << TCC_CTRLA_CPTEN_Pos)) 144 #define TCC_CTRLA_MASK _U_(0x3F80FF63) /**< \brief (TCC_CTRLA) MASK Register */ 145 146 /* -------- TCC_CTRLBCLR : (TCC Offset: 0x04) (R/W 8) Control B Clear -------- */ 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 148 typedef union { 149 struct { 150 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 151 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 152 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ 153 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ 154 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ 155 } bit; /*!< Structure used for bit access */ 156 uint8_t reg; /*!< Type used for register access */ 157 } TCC_CTRLBCLR_Type; 158 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 159 160 #define TCC_CTRLBCLR_OFFSET 0x04 /**< \brief (TCC_CTRLBCLR offset) Control B Clear */ 161 #define TCC_CTRLBCLR_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBCLR reset_value) Control B Clear */ 162 163 #define TCC_CTRLBCLR_DIR_Pos 0 /**< \brief (TCC_CTRLBCLR) Counter Direction */ 164 #define TCC_CTRLBCLR_DIR (_U_(0x1) << TCC_CTRLBCLR_DIR_Pos) 165 #define TCC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TCC_CTRLBCLR) Lock Update */ 166 #define TCC_CTRLBCLR_LUPD (_U_(0x1) << TCC_CTRLBCLR_LUPD_Pos) 167 #define TCC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBCLR) One-Shot */ 168 #define TCC_CTRLBCLR_ONESHOT (_U_(0x1) << TCC_CTRLBCLR_ONESHOT_Pos) 169 #define TCC_CTRLBCLR_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBCLR) Ramp Index Command */ 170 #define TCC_CTRLBCLR_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBCLR_IDXCMD_Pos) 171 #define TCC_CTRLBCLR_IDXCMD(value) (TCC_CTRLBCLR_IDXCMD_Msk & ((value) << TCC_CTRLBCLR_IDXCMD_Pos)) 172 #define TCC_CTRLBCLR_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) Command disabled: Index toggles between cycles A and B */ 173 #define TCC_CTRLBCLR_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Set index: cycle B will be forced in the next cycle */ 174 #define TCC_CTRLBCLR_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Clear index: cycle A will be forced in the next cycle */ 175 #define TCC_CTRLBCLR_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Hold index: the next cycle will be the same as the current cycle */ 176 #define TCC_CTRLBCLR_IDXCMD_DISABLE (TCC_CTRLBCLR_IDXCMD_DISABLE_Val << TCC_CTRLBCLR_IDXCMD_Pos) 177 #define TCC_CTRLBCLR_IDXCMD_SET (TCC_CTRLBCLR_IDXCMD_SET_Val << TCC_CTRLBCLR_IDXCMD_Pos) 178 #define TCC_CTRLBCLR_IDXCMD_CLEAR (TCC_CTRLBCLR_IDXCMD_CLEAR_Val << TCC_CTRLBCLR_IDXCMD_Pos) 179 #define TCC_CTRLBCLR_IDXCMD_HOLD (TCC_CTRLBCLR_IDXCMD_HOLD_Val << TCC_CTRLBCLR_IDXCMD_Pos) 180 #define TCC_CTRLBCLR_CMD_Pos 5 /**< \brief (TCC_CTRLBCLR) TCC Command */ 181 #define TCC_CTRLBCLR_CMD_Msk (_U_(0x7) << TCC_CTRLBCLR_CMD_Pos) 182 #define TCC_CTRLBCLR_CMD(value) (TCC_CTRLBCLR_CMD_Msk & ((value) << TCC_CTRLBCLR_CMD_Pos)) 183 #define TCC_CTRLBCLR_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBCLR) No action */ 184 #define TCC_CTRLBCLR_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBCLR) Clear start, restart or retrigger */ 185 #define TCC_CTRLBCLR_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBCLR) Force stop */ 186 #define TCC_CTRLBCLR_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBCLR) Force update or double buffered registers */ 187 #define TCC_CTRLBCLR_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBCLR) Force COUNT read synchronization */ 188 #define TCC_CTRLBCLR_CMD_DMAOS_Val _U_(0x5) /**< \brief (TCC_CTRLBCLR) One-shot DMA trigger */ 189 #define TCC_CTRLBCLR_CMD_NONE (TCC_CTRLBCLR_CMD_NONE_Val << TCC_CTRLBCLR_CMD_Pos) 190 #define TCC_CTRLBCLR_CMD_RETRIGGER (TCC_CTRLBCLR_CMD_RETRIGGER_Val << TCC_CTRLBCLR_CMD_Pos) 191 #define TCC_CTRLBCLR_CMD_STOP (TCC_CTRLBCLR_CMD_STOP_Val << TCC_CTRLBCLR_CMD_Pos) 192 #define TCC_CTRLBCLR_CMD_UPDATE (TCC_CTRLBCLR_CMD_UPDATE_Val << TCC_CTRLBCLR_CMD_Pos) 193 #define TCC_CTRLBCLR_CMD_READSYNC (TCC_CTRLBCLR_CMD_READSYNC_Val << TCC_CTRLBCLR_CMD_Pos) 194 #define TCC_CTRLBCLR_CMD_DMAOS (TCC_CTRLBCLR_CMD_DMAOS_Val << TCC_CTRLBCLR_CMD_Pos) 195 #define TCC_CTRLBCLR_MASK _U_(0xFF) /**< \brief (TCC_CTRLBCLR) MASK Register */ 196 197 /* -------- TCC_CTRLBSET : (TCC Offset: 0x05) (R/W 8) Control B Set -------- */ 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 199 typedef union { 200 struct { 201 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 202 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 203 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */ 204 uint8_t IDXCMD:2; /*!< bit: 3.. 4 Ramp Index Command */ 205 uint8_t CMD:3; /*!< bit: 5.. 7 TCC Command */ 206 } bit; /*!< Structure used for bit access */ 207 uint8_t reg; /*!< Type used for register access */ 208 } TCC_CTRLBSET_Type; 209 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 210 211 #define TCC_CTRLBSET_OFFSET 0x05 /**< \brief (TCC_CTRLBSET offset) Control B Set */ 212 #define TCC_CTRLBSET_RESETVALUE _U_(0x00) /**< \brief (TCC_CTRLBSET reset_value) Control B Set */ 213 214 #define TCC_CTRLBSET_DIR_Pos 0 /**< \brief (TCC_CTRLBSET) Counter Direction */ 215 #define TCC_CTRLBSET_DIR (_U_(0x1) << TCC_CTRLBSET_DIR_Pos) 216 #define TCC_CTRLBSET_LUPD_Pos 1 /**< \brief (TCC_CTRLBSET) Lock Update */ 217 #define TCC_CTRLBSET_LUPD (_U_(0x1) << TCC_CTRLBSET_LUPD_Pos) 218 #define TCC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TCC_CTRLBSET) One-Shot */ 219 #define TCC_CTRLBSET_ONESHOT (_U_(0x1) << TCC_CTRLBSET_ONESHOT_Pos) 220 #define TCC_CTRLBSET_IDXCMD_Pos 3 /**< \brief (TCC_CTRLBSET) Ramp Index Command */ 221 #define TCC_CTRLBSET_IDXCMD_Msk (_U_(0x3) << TCC_CTRLBSET_IDXCMD_Pos) 222 #define TCC_CTRLBSET_IDXCMD(value) (TCC_CTRLBSET_IDXCMD_Msk & ((value) << TCC_CTRLBSET_IDXCMD_Pos)) 223 #define TCC_CTRLBSET_IDXCMD_DISABLE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) Command disabled: Index toggles between cycles A and B */ 224 #define TCC_CTRLBSET_IDXCMD_SET_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Set index: cycle B will be forced in the next cycle */ 225 #define TCC_CTRLBSET_IDXCMD_CLEAR_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Clear index: cycle A will be forced in the next cycle */ 226 #define TCC_CTRLBSET_IDXCMD_HOLD_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Hold index: the next cycle will be the same as the current cycle */ 227 #define TCC_CTRLBSET_IDXCMD_DISABLE (TCC_CTRLBSET_IDXCMD_DISABLE_Val << TCC_CTRLBSET_IDXCMD_Pos) 228 #define TCC_CTRLBSET_IDXCMD_SET (TCC_CTRLBSET_IDXCMD_SET_Val << TCC_CTRLBSET_IDXCMD_Pos) 229 #define TCC_CTRLBSET_IDXCMD_CLEAR (TCC_CTRLBSET_IDXCMD_CLEAR_Val << TCC_CTRLBSET_IDXCMD_Pos) 230 #define TCC_CTRLBSET_IDXCMD_HOLD (TCC_CTRLBSET_IDXCMD_HOLD_Val << TCC_CTRLBSET_IDXCMD_Pos) 231 #define TCC_CTRLBSET_CMD_Pos 5 /**< \brief (TCC_CTRLBSET) TCC Command */ 232 #define TCC_CTRLBSET_CMD_Msk (_U_(0x7) << TCC_CTRLBSET_CMD_Pos) 233 #define TCC_CTRLBSET_CMD(value) (TCC_CTRLBSET_CMD_Msk & ((value) << TCC_CTRLBSET_CMD_Pos)) 234 #define TCC_CTRLBSET_CMD_NONE_Val _U_(0x0) /**< \brief (TCC_CTRLBSET) No action */ 235 #define TCC_CTRLBSET_CMD_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_CTRLBSET) Clear start, restart or retrigger */ 236 #define TCC_CTRLBSET_CMD_STOP_Val _U_(0x2) /**< \brief (TCC_CTRLBSET) Force stop */ 237 #define TCC_CTRLBSET_CMD_UPDATE_Val _U_(0x3) /**< \brief (TCC_CTRLBSET) Force update or double buffered registers */ 238 #define TCC_CTRLBSET_CMD_READSYNC_Val _U_(0x4) /**< \brief (TCC_CTRLBSET) Force COUNT read synchronization */ 239 #define TCC_CTRLBSET_CMD_DMAOS_Val _U_(0x5) /**< \brief (TCC_CTRLBSET) One-shot DMA trigger */ 240 #define TCC_CTRLBSET_CMD_NONE (TCC_CTRLBSET_CMD_NONE_Val << TCC_CTRLBSET_CMD_Pos) 241 #define TCC_CTRLBSET_CMD_RETRIGGER (TCC_CTRLBSET_CMD_RETRIGGER_Val << TCC_CTRLBSET_CMD_Pos) 242 #define TCC_CTRLBSET_CMD_STOP (TCC_CTRLBSET_CMD_STOP_Val << TCC_CTRLBSET_CMD_Pos) 243 #define TCC_CTRLBSET_CMD_UPDATE (TCC_CTRLBSET_CMD_UPDATE_Val << TCC_CTRLBSET_CMD_Pos) 244 #define TCC_CTRLBSET_CMD_READSYNC (TCC_CTRLBSET_CMD_READSYNC_Val << TCC_CTRLBSET_CMD_Pos) 245 #define TCC_CTRLBSET_CMD_DMAOS (TCC_CTRLBSET_CMD_DMAOS_Val << TCC_CTRLBSET_CMD_Pos) 246 #define TCC_CTRLBSET_MASK _U_(0xFF) /**< \brief (TCC_CTRLBSET) MASK Register */ 247 248 /* -------- TCC_SYNCBUSY : (TCC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ 249 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 250 typedef union { 251 struct { 252 uint32_t SWRST:1; /*!< bit: 0 Swrst Busy */ 253 uint32_t ENABLE:1; /*!< bit: 1 Enable Busy */ 254 uint32_t CTRLB:1; /*!< bit: 2 Ctrlb Busy */ 255 uint32_t STATUS:1; /*!< bit: 3 Status Busy */ 256 uint32_t COUNT:1; /*!< bit: 4 Count Busy */ 257 uint32_t PATT:1; /*!< bit: 5 Pattern Busy */ 258 uint32_t WAVE:1; /*!< bit: 6 Wave Busy */ 259 uint32_t PER:1; /*!< bit: 7 Period Busy */ 260 uint32_t CC0:1; /*!< bit: 8 Compare Channel 0 Busy */ 261 uint32_t CC1:1; /*!< bit: 9 Compare Channel 1 Busy */ 262 uint32_t CC2:1; /*!< bit: 10 Compare Channel 2 Busy */ 263 uint32_t CC3:1; /*!< bit: 11 Compare Channel 3 Busy */ 264 uint32_t CC4:1; /*!< bit: 12 Compare Channel 4 Busy */ 265 uint32_t CC5:1; /*!< bit: 13 Compare Channel 5 Busy */ 266 uint32_t :18; /*!< bit: 14..31 Reserved */ 267 } bit; /*!< Structure used for bit access */ 268 struct { 269 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 270 uint32_t CC:6; /*!< bit: 8..13 Compare Channel x Busy */ 271 uint32_t :18; /*!< bit: 14..31 Reserved */ 272 } vec; /*!< Structure used for vec access */ 273 uint32_t reg; /*!< Type used for register access */ 274 } TCC_SYNCBUSY_Type; 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 276 277 #define TCC_SYNCBUSY_OFFSET 0x08 /**< \brief (TCC_SYNCBUSY offset) Synchronization Busy */ 278 #define TCC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (TCC_SYNCBUSY reset_value) Synchronization Busy */ 279 280 #define TCC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TCC_SYNCBUSY) Swrst Busy */ 281 #define TCC_SYNCBUSY_SWRST (_U_(0x1) << TCC_SYNCBUSY_SWRST_Pos) 282 #define TCC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TCC_SYNCBUSY) Enable Busy */ 283 #define TCC_SYNCBUSY_ENABLE (_U_(0x1) << TCC_SYNCBUSY_ENABLE_Pos) 284 #define TCC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TCC_SYNCBUSY) Ctrlb Busy */ 285 #define TCC_SYNCBUSY_CTRLB (_U_(0x1) << TCC_SYNCBUSY_CTRLB_Pos) 286 #define TCC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TCC_SYNCBUSY) Status Busy */ 287 #define TCC_SYNCBUSY_STATUS (_U_(0x1) << TCC_SYNCBUSY_STATUS_Pos) 288 #define TCC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TCC_SYNCBUSY) Count Busy */ 289 #define TCC_SYNCBUSY_COUNT (_U_(0x1) << TCC_SYNCBUSY_COUNT_Pos) 290 #define TCC_SYNCBUSY_PATT_Pos 5 /**< \brief (TCC_SYNCBUSY) Pattern Busy */ 291 #define TCC_SYNCBUSY_PATT (_U_(0x1) << TCC_SYNCBUSY_PATT_Pos) 292 #define TCC_SYNCBUSY_WAVE_Pos 6 /**< \brief (TCC_SYNCBUSY) Wave Busy */ 293 #define TCC_SYNCBUSY_WAVE (_U_(0x1) << TCC_SYNCBUSY_WAVE_Pos) 294 #define TCC_SYNCBUSY_PER_Pos 7 /**< \brief (TCC_SYNCBUSY) Period Busy */ 295 #define TCC_SYNCBUSY_PER (_U_(0x1) << TCC_SYNCBUSY_PER_Pos) 296 #define TCC_SYNCBUSY_CC0_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel 0 Busy */ 297 #define TCC_SYNCBUSY_CC0 (_U_(1) << TCC_SYNCBUSY_CC0_Pos) 298 #define TCC_SYNCBUSY_CC1_Pos 9 /**< \brief (TCC_SYNCBUSY) Compare Channel 1 Busy */ 299 #define TCC_SYNCBUSY_CC1 (_U_(1) << TCC_SYNCBUSY_CC1_Pos) 300 #define TCC_SYNCBUSY_CC2_Pos 10 /**< \brief (TCC_SYNCBUSY) Compare Channel 2 Busy */ 301 #define TCC_SYNCBUSY_CC2 (_U_(1) << TCC_SYNCBUSY_CC2_Pos) 302 #define TCC_SYNCBUSY_CC3_Pos 11 /**< \brief (TCC_SYNCBUSY) Compare Channel 3 Busy */ 303 #define TCC_SYNCBUSY_CC3 (_U_(1) << TCC_SYNCBUSY_CC3_Pos) 304 #define TCC_SYNCBUSY_CC4_Pos 12 /**< \brief (TCC_SYNCBUSY) Compare Channel 4 Busy */ 305 #define TCC_SYNCBUSY_CC4 (_U_(1) << TCC_SYNCBUSY_CC4_Pos) 306 #define TCC_SYNCBUSY_CC5_Pos 13 /**< \brief (TCC_SYNCBUSY) Compare Channel 5 Busy */ 307 #define TCC_SYNCBUSY_CC5 (_U_(1) << TCC_SYNCBUSY_CC5_Pos) 308 #define TCC_SYNCBUSY_CC_Pos 8 /**< \brief (TCC_SYNCBUSY) Compare Channel x Busy */ 309 #define TCC_SYNCBUSY_CC_Msk (_U_(0x3F) << TCC_SYNCBUSY_CC_Pos) 310 #define TCC_SYNCBUSY_CC(value) (TCC_SYNCBUSY_CC_Msk & ((value) << TCC_SYNCBUSY_CC_Pos)) 311 #define TCC_SYNCBUSY_MASK _U_(0x00003FFF) /**< \brief (TCC_SYNCBUSY) MASK Register */ 312 313 /* -------- TCC_FCTRLA : (TCC Offset: 0x0C) (R/W 32) Recoverable Fault A Configuration -------- */ 314 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 315 typedef union { 316 struct { 317 uint32_t SRC:2; /*!< bit: 0.. 1 Fault A Source */ 318 uint32_t :1; /*!< bit: 2 Reserved */ 319 uint32_t KEEP:1; /*!< bit: 3 Fault A Keeper */ 320 uint32_t QUAL:1; /*!< bit: 4 Fault A Qualification */ 321 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault A Blanking Mode */ 322 uint32_t RESTART:1; /*!< bit: 7 Fault A Restart */ 323 uint32_t HALT:2; /*!< bit: 8.. 9 Fault A Halt Mode */ 324 uint32_t CHSEL:2; /*!< bit: 10..11 Fault A Capture Channel */ 325 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault A Capture Action */ 326 uint32_t BLANKPRESC:1; /*!< bit: 15 Fault A Blanking Prescaler */ 327 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault A Blanking Time */ 328 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault A Filter Value */ 329 uint32_t :4; /*!< bit: 28..31 Reserved */ 330 } bit; /*!< Structure used for bit access */ 331 uint32_t reg; /*!< Type used for register access */ 332 } TCC_FCTRLA_Type; 333 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 334 335 #define TCC_FCTRLA_OFFSET 0x0C /**< \brief (TCC_FCTRLA offset) Recoverable Fault A Configuration */ 336 #define TCC_FCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLA reset_value) Recoverable Fault A Configuration */ 337 338 #define TCC_FCTRLA_SRC_Pos 0 /**< \brief (TCC_FCTRLA) Fault A Source */ 339 #define TCC_FCTRLA_SRC_Msk (_U_(0x3) << TCC_FCTRLA_SRC_Pos) 340 #define TCC_FCTRLA_SRC(value) (TCC_FCTRLA_SRC_Msk & ((value) << TCC_FCTRLA_SRC_Pos)) 341 #define TCC_FCTRLA_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Fault input disabled */ 342 #define TCC_FCTRLA_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) MCEx (x=0,1) event input */ 343 #define TCC_FCTRLA_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Inverted MCEx (x=0,1) event input */ 344 #define TCC_FCTRLA_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Alternate fault (A or B) state at the end of the previous period */ 345 #define TCC_FCTRLA_SRC_DISABLE (TCC_FCTRLA_SRC_DISABLE_Val << TCC_FCTRLA_SRC_Pos) 346 #define TCC_FCTRLA_SRC_ENABLE (TCC_FCTRLA_SRC_ENABLE_Val << TCC_FCTRLA_SRC_Pos) 347 #define TCC_FCTRLA_SRC_INVERT (TCC_FCTRLA_SRC_INVERT_Val << TCC_FCTRLA_SRC_Pos) 348 #define TCC_FCTRLA_SRC_ALTFAULT (TCC_FCTRLA_SRC_ALTFAULT_Val << TCC_FCTRLA_SRC_Pos) 349 #define TCC_FCTRLA_KEEP_Pos 3 /**< \brief (TCC_FCTRLA) Fault A Keeper */ 350 #define TCC_FCTRLA_KEEP (_U_(0x1) << TCC_FCTRLA_KEEP_Pos) 351 #define TCC_FCTRLA_QUAL_Pos 4 /**< \brief (TCC_FCTRLA) Fault A Qualification */ 352 #define TCC_FCTRLA_QUAL (_U_(0x1) << TCC_FCTRLA_QUAL_Pos) 353 #define TCC_FCTRLA_BLANK_Pos 5 /**< \brief (TCC_FCTRLA) Fault A Blanking Mode */ 354 #define TCC_FCTRLA_BLANK_Msk (_U_(0x3) << TCC_FCTRLA_BLANK_Pos) 355 #define TCC_FCTRLA_BLANK(value) (TCC_FCTRLA_BLANK_Msk & ((value) << TCC_FCTRLA_BLANK_Pos)) 356 #define TCC_FCTRLA_BLANK_START_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Blanking applied from start of the ramp */ 357 #define TCC_FCTRLA_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Blanking applied from rising edge of the output waveform */ 358 #define TCC_FCTRLA_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Blanking applied from falling edge of the output waveform */ 359 #define TCC_FCTRLA_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Blanking applied from each toggle of the output waveform */ 360 #define TCC_FCTRLA_BLANK_START (TCC_FCTRLA_BLANK_START_Val << TCC_FCTRLA_BLANK_Pos) 361 #define TCC_FCTRLA_BLANK_RISE (TCC_FCTRLA_BLANK_RISE_Val << TCC_FCTRLA_BLANK_Pos) 362 #define TCC_FCTRLA_BLANK_FALL (TCC_FCTRLA_BLANK_FALL_Val << TCC_FCTRLA_BLANK_Pos) 363 #define TCC_FCTRLA_BLANK_BOTH (TCC_FCTRLA_BLANK_BOTH_Val << TCC_FCTRLA_BLANK_Pos) 364 #define TCC_FCTRLA_RESTART_Pos 7 /**< \brief (TCC_FCTRLA) Fault A Restart */ 365 #define TCC_FCTRLA_RESTART (_U_(0x1) << TCC_FCTRLA_RESTART_Pos) 366 #define TCC_FCTRLA_HALT_Pos 8 /**< \brief (TCC_FCTRLA) Fault A Halt Mode */ 367 #define TCC_FCTRLA_HALT_Msk (_U_(0x3) << TCC_FCTRLA_HALT_Pos) 368 #define TCC_FCTRLA_HALT(value) (TCC_FCTRLA_HALT_Msk & ((value) << TCC_FCTRLA_HALT_Pos)) 369 #define TCC_FCTRLA_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Halt action disabled */ 370 #define TCC_FCTRLA_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Hardware halt action */ 371 #define TCC_FCTRLA_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Software halt action */ 372 #define TCC_FCTRLA_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Non-recoverable fault */ 373 #define TCC_FCTRLA_HALT_DISABLE (TCC_FCTRLA_HALT_DISABLE_Val << TCC_FCTRLA_HALT_Pos) 374 #define TCC_FCTRLA_HALT_HW (TCC_FCTRLA_HALT_HW_Val << TCC_FCTRLA_HALT_Pos) 375 #define TCC_FCTRLA_HALT_SW (TCC_FCTRLA_HALT_SW_Val << TCC_FCTRLA_HALT_Pos) 376 #define TCC_FCTRLA_HALT_NR (TCC_FCTRLA_HALT_NR_Val << TCC_FCTRLA_HALT_Pos) 377 #define TCC_FCTRLA_CHSEL_Pos 10 /**< \brief (TCC_FCTRLA) Fault A Capture Channel */ 378 #define TCC_FCTRLA_CHSEL_Msk (_U_(0x3) << TCC_FCTRLA_CHSEL_Pos) 379 #define TCC_FCTRLA_CHSEL(value) (TCC_FCTRLA_CHSEL_Msk & ((value) << TCC_FCTRLA_CHSEL_Pos)) 380 #define TCC_FCTRLA_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLA) Capture value stored in channel 0 */ 381 #define TCC_FCTRLA_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture value stored in channel 1 */ 382 #define TCC_FCTRLA_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Capture value stored in channel 2 */ 383 #define TCC_FCTRLA_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Capture value stored in channel 3 */ 384 #define TCC_FCTRLA_CHSEL_CC0 (TCC_FCTRLA_CHSEL_CC0_Val << TCC_FCTRLA_CHSEL_Pos) 385 #define TCC_FCTRLA_CHSEL_CC1 (TCC_FCTRLA_CHSEL_CC1_Val << TCC_FCTRLA_CHSEL_Pos) 386 #define TCC_FCTRLA_CHSEL_CC2 (TCC_FCTRLA_CHSEL_CC2_Val << TCC_FCTRLA_CHSEL_Pos) 387 #define TCC_FCTRLA_CHSEL_CC3 (TCC_FCTRLA_CHSEL_CC3_Val << TCC_FCTRLA_CHSEL_Pos) 388 #define TCC_FCTRLA_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLA) Fault A Capture Action */ 389 #define TCC_FCTRLA_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLA_CAPTURE_Pos) 390 #define TCC_FCTRLA_CAPTURE(value) (TCC_FCTRLA_CAPTURE_Msk & ((value) << TCC_FCTRLA_CAPTURE_Pos)) 391 #define TCC_FCTRLA_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLA) No capture */ 392 #define TCC_FCTRLA_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLA) Capture on fault */ 393 #define TCC_FCTRLA_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLA) Minimum capture */ 394 #define TCC_FCTRLA_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLA) Maximum capture */ 395 #define TCC_FCTRLA_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLA) Minimum local detection */ 396 #define TCC_FCTRLA_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLA) Maximum local detection */ 397 #define TCC_FCTRLA_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLA) Minimum and maximum local detection */ 398 #define TCC_FCTRLA_CAPTURE_CAPTMARK_Val _U_(0x7) /**< \brief (TCC_FCTRLA) Capture with ramp index as MSB value */ 399 #define TCC_FCTRLA_CAPTURE_DISABLE (TCC_FCTRLA_CAPTURE_DISABLE_Val << TCC_FCTRLA_CAPTURE_Pos) 400 #define TCC_FCTRLA_CAPTURE_CAPT (TCC_FCTRLA_CAPTURE_CAPT_Val << TCC_FCTRLA_CAPTURE_Pos) 401 #define TCC_FCTRLA_CAPTURE_CAPTMIN (TCC_FCTRLA_CAPTURE_CAPTMIN_Val << TCC_FCTRLA_CAPTURE_Pos) 402 #define TCC_FCTRLA_CAPTURE_CAPTMAX (TCC_FCTRLA_CAPTURE_CAPTMAX_Val << TCC_FCTRLA_CAPTURE_Pos) 403 #define TCC_FCTRLA_CAPTURE_LOCMIN (TCC_FCTRLA_CAPTURE_LOCMIN_Val << TCC_FCTRLA_CAPTURE_Pos) 404 #define TCC_FCTRLA_CAPTURE_LOCMAX (TCC_FCTRLA_CAPTURE_LOCMAX_Val << TCC_FCTRLA_CAPTURE_Pos) 405 #define TCC_FCTRLA_CAPTURE_DERIV0 (TCC_FCTRLA_CAPTURE_DERIV0_Val << TCC_FCTRLA_CAPTURE_Pos) 406 #define TCC_FCTRLA_CAPTURE_CAPTMARK (TCC_FCTRLA_CAPTURE_CAPTMARK_Val << TCC_FCTRLA_CAPTURE_Pos) 407 #define TCC_FCTRLA_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLA) Fault A Blanking Prescaler */ 408 #define TCC_FCTRLA_BLANKPRESC (_U_(0x1) << TCC_FCTRLA_BLANKPRESC_Pos) 409 #define TCC_FCTRLA_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLA) Fault A Blanking Time */ 410 #define TCC_FCTRLA_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLA_BLANKVAL_Pos) 411 #define TCC_FCTRLA_BLANKVAL(value) (TCC_FCTRLA_BLANKVAL_Msk & ((value) << TCC_FCTRLA_BLANKVAL_Pos)) 412 #define TCC_FCTRLA_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLA) Fault A Filter Value */ 413 #define TCC_FCTRLA_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLA_FILTERVAL_Pos) 414 #define TCC_FCTRLA_FILTERVAL(value) (TCC_FCTRLA_FILTERVAL_Msk & ((value) << TCC_FCTRLA_FILTERVAL_Pos)) 415 #define TCC_FCTRLA_MASK _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLA) MASK Register */ 416 417 /* -------- TCC_FCTRLB : (TCC Offset: 0x10) (R/W 32) Recoverable Fault B Configuration -------- */ 418 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 419 typedef union { 420 struct { 421 uint32_t SRC:2; /*!< bit: 0.. 1 Fault B Source */ 422 uint32_t :1; /*!< bit: 2 Reserved */ 423 uint32_t KEEP:1; /*!< bit: 3 Fault B Keeper */ 424 uint32_t QUAL:1; /*!< bit: 4 Fault B Qualification */ 425 uint32_t BLANK:2; /*!< bit: 5.. 6 Fault B Blanking Mode */ 426 uint32_t RESTART:1; /*!< bit: 7 Fault B Restart */ 427 uint32_t HALT:2; /*!< bit: 8.. 9 Fault B Halt Mode */ 428 uint32_t CHSEL:2; /*!< bit: 10..11 Fault B Capture Channel */ 429 uint32_t CAPTURE:3; /*!< bit: 12..14 Fault B Capture Action */ 430 uint32_t BLANKPRESC:1; /*!< bit: 15 Fault B Blanking Prescaler */ 431 uint32_t BLANKVAL:8; /*!< bit: 16..23 Fault B Blanking Time */ 432 uint32_t FILTERVAL:4; /*!< bit: 24..27 Fault B Filter Value */ 433 uint32_t :4; /*!< bit: 28..31 Reserved */ 434 } bit; /*!< Structure used for bit access */ 435 uint32_t reg; /*!< Type used for register access */ 436 } TCC_FCTRLB_Type; 437 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 438 439 #define TCC_FCTRLB_OFFSET 0x10 /**< \brief (TCC_FCTRLB offset) Recoverable Fault B Configuration */ 440 #define TCC_FCTRLB_RESETVALUE _U_(0x00000000) /**< \brief (TCC_FCTRLB reset_value) Recoverable Fault B Configuration */ 441 442 #define TCC_FCTRLB_SRC_Pos 0 /**< \brief (TCC_FCTRLB) Fault B Source */ 443 #define TCC_FCTRLB_SRC_Msk (_U_(0x3) << TCC_FCTRLB_SRC_Pos) 444 #define TCC_FCTRLB_SRC(value) (TCC_FCTRLB_SRC_Msk & ((value) << TCC_FCTRLB_SRC_Pos)) 445 #define TCC_FCTRLB_SRC_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Fault input disabled */ 446 #define TCC_FCTRLB_SRC_ENABLE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) MCEx (x=0,1) event input */ 447 #define TCC_FCTRLB_SRC_INVERT_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Inverted MCEx (x=0,1) event input */ 448 #define TCC_FCTRLB_SRC_ALTFAULT_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Alternate fault (A or B) state at the end of the previous period */ 449 #define TCC_FCTRLB_SRC_DISABLE (TCC_FCTRLB_SRC_DISABLE_Val << TCC_FCTRLB_SRC_Pos) 450 #define TCC_FCTRLB_SRC_ENABLE (TCC_FCTRLB_SRC_ENABLE_Val << TCC_FCTRLB_SRC_Pos) 451 #define TCC_FCTRLB_SRC_INVERT (TCC_FCTRLB_SRC_INVERT_Val << TCC_FCTRLB_SRC_Pos) 452 #define TCC_FCTRLB_SRC_ALTFAULT (TCC_FCTRLB_SRC_ALTFAULT_Val << TCC_FCTRLB_SRC_Pos) 453 #define TCC_FCTRLB_KEEP_Pos 3 /**< \brief (TCC_FCTRLB) Fault B Keeper */ 454 #define TCC_FCTRLB_KEEP (_U_(0x1) << TCC_FCTRLB_KEEP_Pos) 455 #define TCC_FCTRLB_QUAL_Pos 4 /**< \brief (TCC_FCTRLB) Fault B Qualification */ 456 #define TCC_FCTRLB_QUAL (_U_(0x1) << TCC_FCTRLB_QUAL_Pos) 457 #define TCC_FCTRLB_BLANK_Pos 5 /**< \brief (TCC_FCTRLB) Fault B Blanking Mode */ 458 #define TCC_FCTRLB_BLANK_Msk (_U_(0x3) << TCC_FCTRLB_BLANK_Pos) 459 #define TCC_FCTRLB_BLANK(value) (TCC_FCTRLB_BLANK_Msk & ((value) << TCC_FCTRLB_BLANK_Pos)) 460 #define TCC_FCTRLB_BLANK_START_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Blanking applied from start of the ramp */ 461 #define TCC_FCTRLB_BLANK_RISE_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Blanking applied from rising edge of the output waveform */ 462 #define TCC_FCTRLB_BLANK_FALL_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Blanking applied from falling edge of the output waveform */ 463 #define TCC_FCTRLB_BLANK_BOTH_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Blanking applied from each toggle of the output waveform */ 464 #define TCC_FCTRLB_BLANK_START (TCC_FCTRLB_BLANK_START_Val << TCC_FCTRLB_BLANK_Pos) 465 #define TCC_FCTRLB_BLANK_RISE (TCC_FCTRLB_BLANK_RISE_Val << TCC_FCTRLB_BLANK_Pos) 466 #define TCC_FCTRLB_BLANK_FALL (TCC_FCTRLB_BLANK_FALL_Val << TCC_FCTRLB_BLANK_Pos) 467 #define TCC_FCTRLB_BLANK_BOTH (TCC_FCTRLB_BLANK_BOTH_Val << TCC_FCTRLB_BLANK_Pos) 468 #define TCC_FCTRLB_RESTART_Pos 7 /**< \brief (TCC_FCTRLB) Fault B Restart */ 469 #define TCC_FCTRLB_RESTART (_U_(0x1) << TCC_FCTRLB_RESTART_Pos) 470 #define TCC_FCTRLB_HALT_Pos 8 /**< \brief (TCC_FCTRLB) Fault B Halt Mode */ 471 #define TCC_FCTRLB_HALT_Msk (_U_(0x3) << TCC_FCTRLB_HALT_Pos) 472 #define TCC_FCTRLB_HALT(value) (TCC_FCTRLB_HALT_Msk & ((value) << TCC_FCTRLB_HALT_Pos)) 473 #define TCC_FCTRLB_HALT_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Halt action disabled */ 474 #define TCC_FCTRLB_HALT_HW_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Hardware halt action */ 475 #define TCC_FCTRLB_HALT_SW_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Software halt action */ 476 #define TCC_FCTRLB_HALT_NR_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Non-recoverable fault */ 477 #define TCC_FCTRLB_HALT_DISABLE (TCC_FCTRLB_HALT_DISABLE_Val << TCC_FCTRLB_HALT_Pos) 478 #define TCC_FCTRLB_HALT_HW (TCC_FCTRLB_HALT_HW_Val << TCC_FCTRLB_HALT_Pos) 479 #define TCC_FCTRLB_HALT_SW (TCC_FCTRLB_HALT_SW_Val << TCC_FCTRLB_HALT_Pos) 480 #define TCC_FCTRLB_HALT_NR (TCC_FCTRLB_HALT_NR_Val << TCC_FCTRLB_HALT_Pos) 481 #define TCC_FCTRLB_CHSEL_Pos 10 /**< \brief (TCC_FCTRLB) Fault B Capture Channel */ 482 #define TCC_FCTRLB_CHSEL_Msk (_U_(0x3) << TCC_FCTRLB_CHSEL_Pos) 483 #define TCC_FCTRLB_CHSEL(value) (TCC_FCTRLB_CHSEL_Msk & ((value) << TCC_FCTRLB_CHSEL_Pos)) 484 #define TCC_FCTRLB_CHSEL_CC0_Val _U_(0x0) /**< \brief (TCC_FCTRLB) Capture value stored in channel 0 */ 485 #define TCC_FCTRLB_CHSEL_CC1_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture value stored in channel 1 */ 486 #define TCC_FCTRLB_CHSEL_CC2_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Capture value stored in channel 2 */ 487 #define TCC_FCTRLB_CHSEL_CC3_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Capture value stored in channel 3 */ 488 #define TCC_FCTRLB_CHSEL_CC0 (TCC_FCTRLB_CHSEL_CC0_Val << TCC_FCTRLB_CHSEL_Pos) 489 #define TCC_FCTRLB_CHSEL_CC1 (TCC_FCTRLB_CHSEL_CC1_Val << TCC_FCTRLB_CHSEL_Pos) 490 #define TCC_FCTRLB_CHSEL_CC2 (TCC_FCTRLB_CHSEL_CC2_Val << TCC_FCTRLB_CHSEL_Pos) 491 #define TCC_FCTRLB_CHSEL_CC3 (TCC_FCTRLB_CHSEL_CC3_Val << TCC_FCTRLB_CHSEL_Pos) 492 #define TCC_FCTRLB_CAPTURE_Pos 12 /**< \brief (TCC_FCTRLB) Fault B Capture Action */ 493 #define TCC_FCTRLB_CAPTURE_Msk (_U_(0x7) << TCC_FCTRLB_CAPTURE_Pos) 494 #define TCC_FCTRLB_CAPTURE(value) (TCC_FCTRLB_CAPTURE_Msk & ((value) << TCC_FCTRLB_CAPTURE_Pos)) 495 #define TCC_FCTRLB_CAPTURE_DISABLE_Val _U_(0x0) /**< \brief (TCC_FCTRLB) No capture */ 496 #define TCC_FCTRLB_CAPTURE_CAPT_Val _U_(0x1) /**< \brief (TCC_FCTRLB) Capture on fault */ 497 #define TCC_FCTRLB_CAPTURE_CAPTMIN_Val _U_(0x2) /**< \brief (TCC_FCTRLB) Minimum capture */ 498 #define TCC_FCTRLB_CAPTURE_CAPTMAX_Val _U_(0x3) /**< \brief (TCC_FCTRLB) Maximum capture */ 499 #define TCC_FCTRLB_CAPTURE_LOCMIN_Val _U_(0x4) /**< \brief (TCC_FCTRLB) Minimum local detection */ 500 #define TCC_FCTRLB_CAPTURE_LOCMAX_Val _U_(0x5) /**< \brief (TCC_FCTRLB) Maximum local detection */ 501 #define TCC_FCTRLB_CAPTURE_DERIV0_Val _U_(0x6) /**< \brief (TCC_FCTRLB) Minimum and maximum local detection */ 502 #define TCC_FCTRLB_CAPTURE_CAPTMARK_Val _U_(0x7) /**< \brief (TCC_FCTRLB) Capture with ramp index as MSB value */ 503 #define TCC_FCTRLB_CAPTURE_DISABLE (TCC_FCTRLB_CAPTURE_DISABLE_Val << TCC_FCTRLB_CAPTURE_Pos) 504 #define TCC_FCTRLB_CAPTURE_CAPT (TCC_FCTRLB_CAPTURE_CAPT_Val << TCC_FCTRLB_CAPTURE_Pos) 505 #define TCC_FCTRLB_CAPTURE_CAPTMIN (TCC_FCTRLB_CAPTURE_CAPTMIN_Val << TCC_FCTRLB_CAPTURE_Pos) 506 #define TCC_FCTRLB_CAPTURE_CAPTMAX (TCC_FCTRLB_CAPTURE_CAPTMAX_Val << TCC_FCTRLB_CAPTURE_Pos) 507 #define TCC_FCTRLB_CAPTURE_LOCMIN (TCC_FCTRLB_CAPTURE_LOCMIN_Val << TCC_FCTRLB_CAPTURE_Pos) 508 #define TCC_FCTRLB_CAPTURE_LOCMAX (TCC_FCTRLB_CAPTURE_LOCMAX_Val << TCC_FCTRLB_CAPTURE_Pos) 509 #define TCC_FCTRLB_CAPTURE_DERIV0 (TCC_FCTRLB_CAPTURE_DERIV0_Val << TCC_FCTRLB_CAPTURE_Pos) 510 #define TCC_FCTRLB_CAPTURE_CAPTMARK (TCC_FCTRLB_CAPTURE_CAPTMARK_Val << TCC_FCTRLB_CAPTURE_Pos) 511 #define TCC_FCTRLB_BLANKPRESC_Pos 15 /**< \brief (TCC_FCTRLB) Fault B Blanking Prescaler */ 512 #define TCC_FCTRLB_BLANKPRESC (_U_(0x1) << TCC_FCTRLB_BLANKPRESC_Pos) 513 #define TCC_FCTRLB_BLANKVAL_Pos 16 /**< \brief (TCC_FCTRLB) Fault B Blanking Time */ 514 #define TCC_FCTRLB_BLANKVAL_Msk (_U_(0xFF) << TCC_FCTRLB_BLANKVAL_Pos) 515 #define TCC_FCTRLB_BLANKVAL(value) (TCC_FCTRLB_BLANKVAL_Msk & ((value) << TCC_FCTRLB_BLANKVAL_Pos)) 516 #define TCC_FCTRLB_FILTERVAL_Pos 24 /**< \brief (TCC_FCTRLB) Fault B Filter Value */ 517 #define TCC_FCTRLB_FILTERVAL_Msk (_U_(0xF) << TCC_FCTRLB_FILTERVAL_Pos) 518 #define TCC_FCTRLB_FILTERVAL(value) (TCC_FCTRLB_FILTERVAL_Msk & ((value) << TCC_FCTRLB_FILTERVAL_Pos)) 519 #define TCC_FCTRLB_MASK _U_(0x0FFFFFFB) /**< \brief (TCC_FCTRLB) MASK Register */ 520 521 /* -------- TCC_WEXCTRL : (TCC Offset: 0x14) (R/W 32) Waveform Extension Configuration -------- */ 522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 523 typedef union { 524 struct { 525 uint32_t OTMX:2; /*!< bit: 0.. 1 Output Matrix */ 526 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 527 uint32_t DTIEN0:1; /*!< bit: 8 Dead-time Insertion Generator 0 Enable */ 528 uint32_t DTIEN1:1; /*!< bit: 9 Dead-time Insertion Generator 1 Enable */ 529 uint32_t DTIEN2:1; /*!< bit: 10 Dead-time Insertion Generator 2 Enable */ 530 uint32_t DTIEN3:1; /*!< bit: 11 Dead-time Insertion Generator 3 Enable */ 531 uint32_t :4; /*!< bit: 12..15 Reserved */ 532 uint32_t DTLS:8; /*!< bit: 16..23 Dead-time Low Side Outputs Value */ 533 uint32_t DTHS:8; /*!< bit: 24..31 Dead-time High Side Outputs Value */ 534 } bit; /*!< Structure used for bit access */ 535 struct { 536 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 537 uint32_t DTIEN:4; /*!< bit: 8..11 Dead-time Insertion Generator x Enable */ 538 uint32_t :20; /*!< bit: 12..31 Reserved */ 539 } vec; /*!< Structure used for vec access */ 540 uint32_t reg; /*!< Type used for register access */ 541 } TCC_WEXCTRL_Type; 542 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 543 544 #define TCC_WEXCTRL_OFFSET 0x14 /**< \brief (TCC_WEXCTRL offset) Waveform Extension Configuration */ 545 #define TCC_WEXCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WEXCTRL reset_value) Waveform Extension Configuration */ 546 547 #define TCC_WEXCTRL_OTMX_Pos 0 /**< \brief (TCC_WEXCTRL) Output Matrix */ 548 #define TCC_WEXCTRL_OTMX_Msk (_U_(0x3) << TCC_WEXCTRL_OTMX_Pos) 549 #define TCC_WEXCTRL_OTMX(value) (TCC_WEXCTRL_OTMX_Msk & ((value) << TCC_WEXCTRL_OTMX_Pos)) 550 #define TCC_WEXCTRL_DTIEN0_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 0 Enable */ 551 #define TCC_WEXCTRL_DTIEN0 (_U_(1) << TCC_WEXCTRL_DTIEN0_Pos) 552 #define TCC_WEXCTRL_DTIEN1_Pos 9 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 1 Enable */ 553 #define TCC_WEXCTRL_DTIEN1 (_U_(1) << TCC_WEXCTRL_DTIEN1_Pos) 554 #define TCC_WEXCTRL_DTIEN2_Pos 10 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 2 Enable */ 555 #define TCC_WEXCTRL_DTIEN2 (_U_(1) << TCC_WEXCTRL_DTIEN2_Pos) 556 #define TCC_WEXCTRL_DTIEN3_Pos 11 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator 3 Enable */ 557 #define TCC_WEXCTRL_DTIEN3 (_U_(1) << TCC_WEXCTRL_DTIEN3_Pos) 558 #define TCC_WEXCTRL_DTIEN_Pos 8 /**< \brief (TCC_WEXCTRL) Dead-time Insertion Generator x Enable */ 559 #define TCC_WEXCTRL_DTIEN_Msk (_U_(0xF) << TCC_WEXCTRL_DTIEN_Pos) 560 #define TCC_WEXCTRL_DTIEN(value) (TCC_WEXCTRL_DTIEN_Msk & ((value) << TCC_WEXCTRL_DTIEN_Pos)) 561 #define TCC_WEXCTRL_DTLS_Pos 16 /**< \brief (TCC_WEXCTRL) Dead-time Low Side Outputs Value */ 562 #define TCC_WEXCTRL_DTLS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTLS_Pos) 563 #define TCC_WEXCTRL_DTLS(value) (TCC_WEXCTRL_DTLS_Msk & ((value) << TCC_WEXCTRL_DTLS_Pos)) 564 #define TCC_WEXCTRL_DTHS_Pos 24 /**< \brief (TCC_WEXCTRL) Dead-time High Side Outputs Value */ 565 #define TCC_WEXCTRL_DTHS_Msk (_U_(0xFF) << TCC_WEXCTRL_DTHS_Pos) 566 #define TCC_WEXCTRL_DTHS(value) (TCC_WEXCTRL_DTHS_Msk & ((value) << TCC_WEXCTRL_DTHS_Pos)) 567 #define TCC_WEXCTRL_MASK _U_(0xFFFF0F03) /**< \brief (TCC_WEXCTRL) MASK Register */ 568 569 /* -------- TCC_DRVCTRL : (TCC Offset: 0x18) (R/W 32) Driver Control -------- */ 570 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 571 typedef union { 572 struct { 573 uint32_t NRE0:1; /*!< bit: 0 Non-Recoverable State 0 Output Enable */ 574 uint32_t NRE1:1; /*!< bit: 1 Non-Recoverable State 1 Output Enable */ 575 uint32_t NRE2:1; /*!< bit: 2 Non-Recoverable State 2 Output Enable */ 576 uint32_t NRE3:1; /*!< bit: 3 Non-Recoverable State 3 Output Enable */ 577 uint32_t NRE4:1; /*!< bit: 4 Non-Recoverable State 4 Output Enable */ 578 uint32_t NRE5:1; /*!< bit: 5 Non-Recoverable State 5 Output Enable */ 579 uint32_t NRE6:1; /*!< bit: 6 Non-Recoverable State 6 Output Enable */ 580 uint32_t NRE7:1; /*!< bit: 7 Non-Recoverable State 7 Output Enable */ 581 uint32_t NRV0:1; /*!< bit: 8 Non-Recoverable State 0 Output Value */ 582 uint32_t NRV1:1; /*!< bit: 9 Non-Recoverable State 1 Output Value */ 583 uint32_t NRV2:1; /*!< bit: 10 Non-Recoverable State 2 Output Value */ 584 uint32_t NRV3:1; /*!< bit: 11 Non-Recoverable State 3 Output Value */ 585 uint32_t NRV4:1; /*!< bit: 12 Non-Recoverable State 4 Output Value */ 586 uint32_t NRV5:1; /*!< bit: 13 Non-Recoverable State 5 Output Value */ 587 uint32_t NRV6:1; /*!< bit: 14 Non-Recoverable State 6 Output Value */ 588 uint32_t NRV7:1; /*!< bit: 15 Non-Recoverable State 7 Output Value */ 589 uint32_t INVEN0:1; /*!< bit: 16 Output Waveform 0 Inversion */ 590 uint32_t INVEN1:1; /*!< bit: 17 Output Waveform 1 Inversion */ 591 uint32_t INVEN2:1; /*!< bit: 18 Output Waveform 2 Inversion */ 592 uint32_t INVEN3:1; /*!< bit: 19 Output Waveform 3 Inversion */ 593 uint32_t INVEN4:1; /*!< bit: 20 Output Waveform 4 Inversion */ 594 uint32_t INVEN5:1; /*!< bit: 21 Output Waveform 5 Inversion */ 595 uint32_t INVEN6:1; /*!< bit: 22 Output Waveform 6 Inversion */ 596 uint32_t INVEN7:1; /*!< bit: 23 Output Waveform 7 Inversion */ 597 uint32_t FILTERVAL0:4; /*!< bit: 24..27 Non-Recoverable Fault Input 0 Filter Value */ 598 uint32_t FILTERVAL1:4; /*!< bit: 28..31 Non-Recoverable Fault Input 1 Filter Value */ 599 } bit; /*!< Structure used for bit access */ 600 struct { 601 uint32_t NRE:8; /*!< bit: 0.. 7 Non-Recoverable State x Output Enable */ 602 uint32_t NRV:8; /*!< bit: 8..15 Non-Recoverable State x Output Value */ 603 uint32_t INVEN:8; /*!< bit: 16..23 Output Waveform x Inversion */ 604 uint32_t :8; /*!< bit: 24..31 Reserved */ 605 } vec; /*!< Structure used for vec access */ 606 uint32_t reg; /*!< Type used for register access */ 607 } TCC_DRVCTRL_Type; 608 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 609 610 #define TCC_DRVCTRL_OFFSET 0x18 /**< \brief (TCC_DRVCTRL offset) Driver Control */ 611 #define TCC_DRVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_DRVCTRL reset_value) Driver Control */ 612 613 #define TCC_DRVCTRL_NRE0_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Enable */ 614 #define TCC_DRVCTRL_NRE0 (_U_(1) << TCC_DRVCTRL_NRE0_Pos) 615 #define TCC_DRVCTRL_NRE1_Pos 1 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Enable */ 616 #define TCC_DRVCTRL_NRE1 (_U_(1) << TCC_DRVCTRL_NRE1_Pos) 617 #define TCC_DRVCTRL_NRE2_Pos 2 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Enable */ 618 #define TCC_DRVCTRL_NRE2 (_U_(1) << TCC_DRVCTRL_NRE2_Pos) 619 #define TCC_DRVCTRL_NRE3_Pos 3 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Enable */ 620 #define TCC_DRVCTRL_NRE3 (_U_(1) << TCC_DRVCTRL_NRE3_Pos) 621 #define TCC_DRVCTRL_NRE4_Pos 4 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Enable */ 622 #define TCC_DRVCTRL_NRE4 (_U_(1) << TCC_DRVCTRL_NRE4_Pos) 623 #define TCC_DRVCTRL_NRE5_Pos 5 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Enable */ 624 #define TCC_DRVCTRL_NRE5 (_U_(1) << TCC_DRVCTRL_NRE5_Pos) 625 #define TCC_DRVCTRL_NRE6_Pos 6 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Enable */ 626 #define TCC_DRVCTRL_NRE6 (_U_(1) << TCC_DRVCTRL_NRE6_Pos) 627 #define TCC_DRVCTRL_NRE7_Pos 7 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Enable */ 628 #define TCC_DRVCTRL_NRE7 (_U_(1) << TCC_DRVCTRL_NRE7_Pos) 629 #define TCC_DRVCTRL_NRE_Pos 0 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Enable */ 630 #define TCC_DRVCTRL_NRE_Msk (_U_(0xFF) << TCC_DRVCTRL_NRE_Pos) 631 #define TCC_DRVCTRL_NRE(value) (TCC_DRVCTRL_NRE_Msk & ((value) << TCC_DRVCTRL_NRE_Pos)) 632 #define TCC_DRVCTRL_NRV0_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 0 Output Value */ 633 #define TCC_DRVCTRL_NRV0 (_U_(1) << TCC_DRVCTRL_NRV0_Pos) 634 #define TCC_DRVCTRL_NRV1_Pos 9 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 1 Output Value */ 635 #define TCC_DRVCTRL_NRV1 (_U_(1) << TCC_DRVCTRL_NRV1_Pos) 636 #define TCC_DRVCTRL_NRV2_Pos 10 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 2 Output Value */ 637 #define TCC_DRVCTRL_NRV2 (_U_(1) << TCC_DRVCTRL_NRV2_Pos) 638 #define TCC_DRVCTRL_NRV3_Pos 11 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 3 Output Value */ 639 #define TCC_DRVCTRL_NRV3 (_U_(1) << TCC_DRVCTRL_NRV3_Pos) 640 #define TCC_DRVCTRL_NRV4_Pos 12 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 4 Output Value */ 641 #define TCC_DRVCTRL_NRV4 (_U_(1) << TCC_DRVCTRL_NRV4_Pos) 642 #define TCC_DRVCTRL_NRV5_Pos 13 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 5 Output Value */ 643 #define TCC_DRVCTRL_NRV5 (_U_(1) << TCC_DRVCTRL_NRV5_Pos) 644 #define TCC_DRVCTRL_NRV6_Pos 14 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 6 Output Value */ 645 #define TCC_DRVCTRL_NRV6 (_U_(1) << TCC_DRVCTRL_NRV6_Pos) 646 #define TCC_DRVCTRL_NRV7_Pos 15 /**< \brief (TCC_DRVCTRL) Non-Recoverable State 7 Output Value */ 647 #define TCC_DRVCTRL_NRV7 (_U_(1) << TCC_DRVCTRL_NRV7_Pos) 648 #define TCC_DRVCTRL_NRV_Pos 8 /**< \brief (TCC_DRVCTRL) Non-Recoverable State x Output Value */ 649 #define TCC_DRVCTRL_NRV_Msk (_U_(0xFF) << TCC_DRVCTRL_NRV_Pos) 650 #define TCC_DRVCTRL_NRV(value) (TCC_DRVCTRL_NRV_Msk & ((value) << TCC_DRVCTRL_NRV_Pos)) 651 #define TCC_DRVCTRL_INVEN0_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform 0 Inversion */ 652 #define TCC_DRVCTRL_INVEN0 (_U_(1) << TCC_DRVCTRL_INVEN0_Pos) 653 #define TCC_DRVCTRL_INVEN1_Pos 17 /**< \brief (TCC_DRVCTRL) Output Waveform 1 Inversion */ 654 #define TCC_DRVCTRL_INVEN1 (_U_(1) << TCC_DRVCTRL_INVEN1_Pos) 655 #define TCC_DRVCTRL_INVEN2_Pos 18 /**< \brief (TCC_DRVCTRL) Output Waveform 2 Inversion */ 656 #define TCC_DRVCTRL_INVEN2 (_U_(1) << TCC_DRVCTRL_INVEN2_Pos) 657 #define TCC_DRVCTRL_INVEN3_Pos 19 /**< \brief (TCC_DRVCTRL) Output Waveform 3 Inversion */ 658 #define TCC_DRVCTRL_INVEN3 (_U_(1) << TCC_DRVCTRL_INVEN3_Pos) 659 #define TCC_DRVCTRL_INVEN4_Pos 20 /**< \brief (TCC_DRVCTRL) Output Waveform 4 Inversion */ 660 #define TCC_DRVCTRL_INVEN4 (_U_(1) << TCC_DRVCTRL_INVEN4_Pos) 661 #define TCC_DRVCTRL_INVEN5_Pos 21 /**< \brief (TCC_DRVCTRL) Output Waveform 5 Inversion */ 662 #define TCC_DRVCTRL_INVEN5 (_U_(1) << TCC_DRVCTRL_INVEN5_Pos) 663 #define TCC_DRVCTRL_INVEN6_Pos 22 /**< \brief (TCC_DRVCTRL) Output Waveform 6 Inversion */ 664 #define TCC_DRVCTRL_INVEN6 (_U_(1) << TCC_DRVCTRL_INVEN6_Pos) 665 #define TCC_DRVCTRL_INVEN7_Pos 23 /**< \brief (TCC_DRVCTRL) Output Waveform 7 Inversion */ 666 #define TCC_DRVCTRL_INVEN7 (_U_(1) << TCC_DRVCTRL_INVEN7_Pos) 667 #define TCC_DRVCTRL_INVEN_Pos 16 /**< \brief (TCC_DRVCTRL) Output Waveform x Inversion */ 668 #define TCC_DRVCTRL_INVEN_Msk (_U_(0xFF) << TCC_DRVCTRL_INVEN_Pos) 669 #define TCC_DRVCTRL_INVEN(value) (TCC_DRVCTRL_INVEN_Msk & ((value) << TCC_DRVCTRL_INVEN_Pos)) 670 #define TCC_DRVCTRL_FILTERVAL0_Pos 24 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 0 Filter Value */ 671 #define TCC_DRVCTRL_FILTERVAL0_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL0_Pos) 672 #define TCC_DRVCTRL_FILTERVAL0(value) (TCC_DRVCTRL_FILTERVAL0_Msk & ((value) << TCC_DRVCTRL_FILTERVAL0_Pos)) 673 #define TCC_DRVCTRL_FILTERVAL1_Pos 28 /**< \brief (TCC_DRVCTRL) Non-Recoverable Fault Input 1 Filter Value */ 674 #define TCC_DRVCTRL_FILTERVAL1_Msk (_U_(0xF) << TCC_DRVCTRL_FILTERVAL1_Pos) 675 #define TCC_DRVCTRL_FILTERVAL1(value) (TCC_DRVCTRL_FILTERVAL1_Msk & ((value) << TCC_DRVCTRL_FILTERVAL1_Pos)) 676 #define TCC_DRVCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (TCC_DRVCTRL) MASK Register */ 677 678 /* -------- TCC_DBGCTRL : (TCC Offset: 0x1E) (R/W 8) Debug Control -------- */ 679 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 680 typedef union { 681 struct { 682 uint8_t DBGRUN:1; /*!< bit: 0 Debug Running Mode */ 683 uint8_t :1; /*!< bit: 1 Reserved */ 684 uint8_t FDDBD:1; /*!< bit: 2 Fault Detection on Debug Break Detection */ 685 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 686 } bit; /*!< Structure used for bit access */ 687 uint8_t reg; /*!< Type used for register access */ 688 } TCC_DBGCTRL_Type; 689 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 690 691 #define TCC_DBGCTRL_OFFSET 0x1E /**< \brief (TCC_DBGCTRL offset) Debug Control */ 692 #define TCC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (TCC_DBGCTRL reset_value) Debug Control */ 693 694 #define TCC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TCC_DBGCTRL) Debug Running Mode */ 695 #define TCC_DBGCTRL_DBGRUN (_U_(0x1) << TCC_DBGCTRL_DBGRUN_Pos) 696 #define TCC_DBGCTRL_FDDBD_Pos 2 /**< \brief (TCC_DBGCTRL) Fault Detection on Debug Break Detection */ 697 #define TCC_DBGCTRL_FDDBD (_U_(0x1) << TCC_DBGCTRL_FDDBD_Pos) 698 #define TCC_DBGCTRL_MASK _U_(0x05) /**< \brief (TCC_DBGCTRL) MASK Register */ 699 700 /* -------- TCC_EVCTRL : (TCC Offset: 0x20) (R/W 32) Event Control -------- */ 701 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 702 typedef union { 703 struct { 704 uint32_t EVACT0:3; /*!< bit: 0.. 2 Timer/counter Input Event0 Action */ 705 uint32_t EVACT1:3; /*!< bit: 3.. 5 Timer/counter Input Event1 Action */ 706 uint32_t CNTSEL:2; /*!< bit: 6.. 7 Timer/counter Output Event Mode */ 707 uint32_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ 708 uint32_t TRGEO:1; /*!< bit: 9 Retrigger Output Event Enable */ 709 uint32_t CNTEO:1; /*!< bit: 10 Timer/counter Output Event Enable */ 710 uint32_t :1; /*!< bit: 11 Reserved */ 711 uint32_t TCINV0:1; /*!< bit: 12 Inverted Event 0 Input Enable */ 712 uint32_t TCINV1:1; /*!< bit: 13 Inverted Event 1 Input Enable */ 713 uint32_t TCEI0:1; /*!< bit: 14 Timer/counter Event 0 Input Enable */ 714 uint32_t TCEI1:1; /*!< bit: 15 Timer/counter Event 1 Input Enable */ 715 uint32_t MCEI0:1; /*!< bit: 16 Match or Capture Channel 0 Event Input Enable */ 716 uint32_t MCEI1:1; /*!< bit: 17 Match or Capture Channel 1 Event Input Enable */ 717 uint32_t MCEI2:1; /*!< bit: 18 Match or Capture Channel 2 Event Input Enable */ 718 uint32_t MCEI3:1; /*!< bit: 19 Match or Capture Channel 3 Event Input Enable */ 719 uint32_t MCEI4:1; /*!< bit: 20 Match or Capture Channel 4 Event Input Enable */ 720 uint32_t MCEI5:1; /*!< bit: 21 Match or Capture Channel 5 Event Input Enable */ 721 uint32_t :2; /*!< bit: 22..23 Reserved */ 722 uint32_t MCEO0:1; /*!< bit: 24 Match or Capture Channel 0 Event Output Enable */ 723 uint32_t MCEO1:1; /*!< bit: 25 Match or Capture Channel 1 Event Output Enable */ 724 uint32_t MCEO2:1; /*!< bit: 26 Match or Capture Channel 2 Event Output Enable */ 725 uint32_t MCEO3:1; /*!< bit: 27 Match or Capture Channel 3 Event Output Enable */ 726 uint32_t MCEO4:1; /*!< bit: 28 Match or Capture Channel 4 Event Output Enable */ 727 uint32_t MCEO5:1; /*!< bit: 29 Match or Capture Channel 5 Event Output Enable */ 728 uint32_t :2; /*!< bit: 30..31 Reserved */ 729 } bit; /*!< Structure used for bit access */ 730 struct { 731 uint32_t :12; /*!< bit: 0..11 Reserved */ 732 uint32_t TCINV:2; /*!< bit: 12..13 Inverted Event x Input Enable */ 733 uint32_t TCEI:2; /*!< bit: 14..15 Timer/counter Event x Input Enable */ 734 uint32_t MCEI:6; /*!< bit: 16..21 Match or Capture Channel x Event Input Enable */ 735 uint32_t :2; /*!< bit: 22..23 Reserved */ 736 uint32_t MCEO:6; /*!< bit: 24..29 Match or Capture Channel x Event Output Enable */ 737 uint32_t :2; /*!< bit: 30..31 Reserved */ 738 } vec; /*!< Structure used for vec access */ 739 uint32_t reg; /*!< Type used for register access */ 740 } TCC_EVCTRL_Type; 741 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 742 743 #define TCC_EVCTRL_OFFSET 0x20 /**< \brief (TCC_EVCTRL offset) Event Control */ 744 #define TCC_EVCTRL_RESETVALUE _U_(0x00000000) /**< \brief (TCC_EVCTRL reset_value) Event Control */ 745 746 #define TCC_EVCTRL_EVACT0_Pos 0 /**< \brief (TCC_EVCTRL) Timer/counter Input Event0 Action */ 747 #define TCC_EVCTRL_EVACT0_Msk (_U_(0x7) << TCC_EVCTRL_EVACT0_Pos) 748 #define TCC_EVCTRL_EVACT0(value) (TCC_EVCTRL_EVACT0_Msk & ((value) << TCC_EVCTRL_EVACT0_Pos)) 749 #define TCC_EVCTRL_EVACT0_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */ 750 #define TCC_EVCTRL_EVACT0_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Start, restart or re-trigger counter on event */ 751 #define TCC_EVCTRL_EVACT0_COUNTEV_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Count on event */ 752 #define TCC_EVCTRL_EVACT0_START_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Start counter on event */ 753 #define TCC_EVCTRL_EVACT0_INC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Increment counter on event */ 754 #define TCC_EVCTRL_EVACT0_COUNT_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Count on active state of asynchronous event */ 755 #define TCC_EVCTRL_EVACT0_STAMP_Val _U_(0x6) /**< \brief (TCC_EVCTRL) Stamp capture */ 756 #define TCC_EVCTRL_EVACT0_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */ 757 #define TCC_EVCTRL_EVACT0_OFF (TCC_EVCTRL_EVACT0_OFF_Val << TCC_EVCTRL_EVACT0_Pos) 758 #define TCC_EVCTRL_EVACT0_RETRIGGER (TCC_EVCTRL_EVACT0_RETRIGGER_Val << TCC_EVCTRL_EVACT0_Pos) 759 #define TCC_EVCTRL_EVACT0_COUNTEV (TCC_EVCTRL_EVACT0_COUNTEV_Val << TCC_EVCTRL_EVACT0_Pos) 760 #define TCC_EVCTRL_EVACT0_START (TCC_EVCTRL_EVACT0_START_Val << TCC_EVCTRL_EVACT0_Pos) 761 #define TCC_EVCTRL_EVACT0_INC (TCC_EVCTRL_EVACT0_INC_Val << TCC_EVCTRL_EVACT0_Pos) 762 #define TCC_EVCTRL_EVACT0_COUNT (TCC_EVCTRL_EVACT0_COUNT_Val << TCC_EVCTRL_EVACT0_Pos) 763 #define TCC_EVCTRL_EVACT0_STAMP (TCC_EVCTRL_EVACT0_STAMP_Val << TCC_EVCTRL_EVACT0_Pos) 764 #define TCC_EVCTRL_EVACT0_FAULT (TCC_EVCTRL_EVACT0_FAULT_Val << TCC_EVCTRL_EVACT0_Pos) 765 #define TCC_EVCTRL_EVACT1_Pos 3 /**< \brief (TCC_EVCTRL) Timer/counter Input Event1 Action */ 766 #define TCC_EVCTRL_EVACT1_Msk (_U_(0x7) << TCC_EVCTRL_EVACT1_Pos) 767 #define TCC_EVCTRL_EVACT1(value) (TCC_EVCTRL_EVACT1_Msk & ((value) << TCC_EVCTRL_EVACT1_Pos)) 768 #define TCC_EVCTRL_EVACT1_OFF_Val _U_(0x0) /**< \brief (TCC_EVCTRL) Event action disabled */ 769 #define TCC_EVCTRL_EVACT1_RETRIGGER_Val _U_(0x1) /**< \brief (TCC_EVCTRL) Re-trigger counter on event */ 770 #define TCC_EVCTRL_EVACT1_DIR_Val _U_(0x2) /**< \brief (TCC_EVCTRL) Direction control */ 771 #define TCC_EVCTRL_EVACT1_STOP_Val _U_(0x3) /**< \brief (TCC_EVCTRL) Stop counter on event */ 772 #define TCC_EVCTRL_EVACT1_DEC_Val _U_(0x4) /**< \brief (TCC_EVCTRL) Decrement counter on event */ 773 #define TCC_EVCTRL_EVACT1_PPW_Val _U_(0x5) /**< \brief (TCC_EVCTRL) Period capture value in CC0 register, pulse width capture value in CC1 register */ 774 #define TCC_EVCTRL_EVACT1_PWP_Val _U_(0x6) /**< \brief (TCC_EVCTRL) Period capture value in CC1 register, pulse width capture value in CC0 register */ 775 #define TCC_EVCTRL_EVACT1_FAULT_Val _U_(0x7) /**< \brief (TCC_EVCTRL) Non-recoverable fault */ 776 #define TCC_EVCTRL_EVACT1_OFF (TCC_EVCTRL_EVACT1_OFF_Val << TCC_EVCTRL_EVACT1_Pos) 777 #define TCC_EVCTRL_EVACT1_RETRIGGER (TCC_EVCTRL_EVACT1_RETRIGGER_Val << TCC_EVCTRL_EVACT1_Pos) 778 #define TCC_EVCTRL_EVACT1_DIR (TCC_EVCTRL_EVACT1_DIR_Val << TCC_EVCTRL_EVACT1_Pos) 779 #define TCC_EVCTRL_EVACT1_STOP (TCC_EVCTRL_EVACT1_STOP_Val << TCC_EVCTRL_EVACT1_Pos) 780 #define TCC_EVCTRL_EVACT1_DEC (TCC_EVCTRL_EVACT1_DEC_Val << TCC_EVCTRL_EVACT1_Pos) 781 #define TCC_EVCTRL_EVACT1_PPW (TCC_EVCTRL_EVACT1_PPW_Val << TCC_EVCTRL_EVACT1_Pos) 782 #define TCC_EVCTRL_EVACT1_PWP (TCC_EVCTRL_EVACT1_PWP_Val << TCC_EVCTRL_EVACT1_Pos) 783 #define TCC_EVCTRL_EVACT1_FAULT (TCC_EVCTRL_EVACT1_FAULT_Val << TCC_EVCTRL_EVACT1_Pos) 784 #define TCC_EVCTRL_CNTSEL_Pos 6 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Mode */ 785 #define TCC_EVCTRL_CNTSEL_Msk (_U_(0x3) << TCC_EVCTRL_CNTSEL_Pos) 786 #define TCC_EVCTRL_CNTSEL(value) (TCC_EVCTRL_CNTSEL_Msk & ((value) << TCC_EVCTRL_CNTSEL_Pos)) 787 #define TCC_EVCTRL_CNTSEL_START_Val _U_(0x0) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts */ 788 #define TCC_EVCTRL_CNTSEL_END_Val _U_(0x1) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends */ 789 #define TCC_EVCTRL_CNTSEL_BETWEEN_Val _U_(0x2) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a counter cycle ends, except for the first and last cycles */ 790 #define TCC_EVCTRL_CNTSEL_BOUNDARY_Val _U_(0x3) /**< \brief (TCC_EVCTRL) An interrupt/event is generated when a new counter cycle starts or a counter cycle ends */ 791 #define TCC_EVCTRL_CNTSEL_START (TCC_EVCTRL_CNTSEL_START_Val << TCC_EVCTRL_CNTSEL_Pos) 792 #define TCC_EVCTRL_CNTSEL_END (TCC_EVCTRL_CNTSEL_END_Val << TCC_EVCTRL_CNTSEL_Pos) 793 #define TCC_EVCTRL_CNTSEL_BETWEEN (TCC_EVCTRL_CNTSEL_BETWEEN_Val << TCC_EVCTRL_CNTSEL_Pos) 794 #define TCC_EVCTRL_CNTSEL_BOUNDARY (TCC_EVCTRL_CNTSEL_BOUNDARY_Val << TCC_EVCTRL_CNTSEL_Pos) 795 #define TCC_EVCTRL_OVFEO_Pos 8 /**< \brief (TCC_EVCTRL) Overflow/Underflow Output Event Enable */ 796 #define TCC_EVCTRL_OVFEO (_U_(0x1) << TCC_EVCTRL_OVFEO_Pos) 797 #define TCC_EVCTRL_TRGEO_Pos 9 /**< \brief (TCC_EVCTRL) Retrigger Output Event Enable */ 798 #define TCC_EVCTRL_TRGEO (_U_(0x1) << TCC_EVCTRL_TRGEO_Pos) 799 #define TCC_EVCTRL_CNTEO_Pos 10 /**< \brief (TCC_EVCTRL) Timer/counter Output Event Enable */ 800 #define TCC_EVCTRL_CNTEO (_U_(0x1) << TCC_EVCTRL_CNTEO_Pos) 801 #define TCC_EVCTRL_TCINV0_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event 0 Input Enable */ 802 #define TCC_EVCTRL_TCINV0 (_U_(1) << TCC_EVCTRL_TCINV0_Pos) 803 #define TCC_EVCTRL_TCINV1_Pos 13 /**< \brief (TCC_EVCTRL) Inverted Event 1 Input Enable */ 804 #define TCC_EVCTRL_TCINV1 (_U_(1) << TCC_EVCTRL_TCINV1_Pos) 805 #define TCC_EVCTRL_TCINV_Pos 12 /**< \brief (TCC_EVCTRL) Inverted Event x Input Enable */ 806 #define TCC_EVCTRL_TCINV_Msk (_U_(0x3) << TCC_EVCTRL_TCINV_Pos) 807 #define TCC_EVCTRL_TCINV(value) (TCC_EVCTRL_TCINV_Msk & ((value) << TCC_EVCTRL_TCINV_Pos)) 808 #define TCC_EVCTRL_TCEI0_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event 0 Input Enable */ 809 #define TCC_EVCTRL_TCEI0 (_U_(1) << TCC_EVCTRL_TCEI0_Pos) 810 #define TCC_EVCTRL_TCEI1_Pos 15 /**< \brief (TCC_EVCTRL) Timer/counter Event 1 Input Enable */ 811 #define TCC_EVCTRL_TCEI1 (_U_(1) << TCC_EVCTRL_TCEI1_Pos) 812 #define TCC_EVCTRL_TCEI_Pos 14 /**< \brief (TCC_EVCTRL) Timer/counter Event x Input Enable */ 813 #define TCC_EVCTRL_TCEI_Msk (_U_(0x3) << TCC_EVCTRL_TCEI_Pos) 814 #define TCC_EVCTRL_TCEI(value) (TCC_EVCTRL_TCEI_Msk & ((value) << TCC_EVCTRL_TCEI_Pos)) 815 #define TCC_EVCTRL_MCEI0_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Input Enable */ 816 #define TCC_EVCTRL_MCEI0 (_U_(1) << TCC_EVCTRL_MCEI0_Pos) 817 #define TCC_EVCTRL_MCEI1_Pos 17 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Input Enable */ 818 #define TCC_EVCTRL_MCEI1 (_U_(1) << TCC_EVCTRL_MCEI1_Pos) 819 #define TCC_EVCTRL_MCEI2_Pos 18 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Input Enable */ 820 #define TCC_EVCTRL_MCEI2 (_U_(1) << TCC_EVCTRL_MCEI2_Pos) 821 #define TCC_EVCTRL_MCEI3_Pos 19 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Input Enable */ 822 #define TCC_EVCTRL_MCEI3 (_U_(1) << TCC_EVCTRL_MCEI3_Pos) 823 #define TCC_EVCTRL_MCEI4_Pos 20 /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Input Enable */ 824 #define TCC_EVCTRL_MCEI4 (_U_(1) << TCC_EVCTRL_MCEI4_Pos) 825 #define TCC_EVCTRL_MCEI5_Pos 21 /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Input Enable */ 826 #define TCC_EVCTRL_MCEI5 (_U_(1) << TCC_EVCTRL_MCEI5_Pos) 827 #define TCC_EVCTRL_MCEI_Pos 16 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Input Enable */ 828 #define TCC_EVCTRL_MCEI_Msk (_U_(0x3F) << TCC_EVCTRL_MCEI_Pos) 829 #define TCC_EVCTRL_MCEI(value) (TCC_EVCTRL_MCEI_Msk & ((value) << TCC_EVCTRL_MCEI_Pos)) 830 #define TCC_EVCTRL_MCEO0_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel 0 Event Output Enable */ 831 #define TCC_EVCTRL_MCEO0 (_U_(1) << TCC_EVCTRL_MCEO0_Pos) 832 #define TCC_EVCTRL_MCEO1_Pos 25 /**< \brief (TCC_EVCTRL) Match or Capture Channel 1 Event Output Enable */ 833 #define TCC_EVCTRL_MCEO1 (_U_(1) << TCC_EVCTRL_MCEO1_Pos) 834 #define TCC_EVCTRL_MCEO2_Pos 26 /**< \brief (TCC_EVCTRL) Match or Capture Channel 2 Event Output Enable */ 835 #define TCC_EVCTRL_MCEO2 (_U_(1) << TCC_EVCTRL_MCEO2_Pos) 836 #define TCC_EVCTRL_MCEO3_Pos 27 /**< \brief (TCC_EVCTRL) Match or Capture Channel 3 Event Output Enable */ 837 #define TCC_EVCTRL_MCEO3 (_U_(1) << TCC_EVCTRL_MCEO3_Pos) 838 #define TCC_EVCTRL_MCEO4_Pos 28 /**< \brief (TCC_EVCTRL) Match or Capture Channel 4 Event Output Enable */ 839 #define TCC_EVCTRL_MCEO4 (_U_(1) << TCC_EVCTRL_MCEO4_Pos) 840 #define TCC_EVCTRL_MCEO5_Pos 29 /**< \brief (TCC_EVCTRL) Match or Capture Channel 5 Event Output Enable */ 841 #define TCC_EVCTRL_MCEO5 (_U_(1) << TCC_EVCTRL_MCEO5_Pos) 842 #define TCC_EVCTRL_MCEO_Pos 24 /**< \brief (TCC_EVCTRL) Match or Capture Channel x Event Output Enable */ 843 #define TCC_EVCTRL_MCEO_Msk (_U_(0x3F) << TCC_EVCTRL_MCEO_Pos) 844 #define TCC_EVCTRL_MCEO(value) (TCC_EVCTRL_MCEO_Msk & ((value) << TCC_EVCTRL_MCEO_Pos)) 845 #define TCC_EVCTRL_MASK _U_(0x3F3FF7FF) /**< \brief (TCC_EVCTRL) MASK Register */ 846 847 /* -------- TCC_INTENCLR : (TCC Offset: 0x24) (R/W 32) Interrupt Enable Clear -------- */ 848 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 849 typedef union { 850 struct { 851 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 852 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ 853 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ 854 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ 855 uint32_t :6; /*!< bit: 4.. 9 Reserved */ 856 uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ 857 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ 858 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ 859 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ 860 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ 861 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ 862 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ 863 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ 864 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ 865 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ 866 uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */ 867 uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */ 868 uint32_t :10; /*!< bit: 22..31 Reserved */ 869 } bit; /*!< Structure used for bit access */ 870 struct { 871 uint32_t :16; /*!< bit: 0..15 Reserved */ 872 uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */ 873 uint32_t :10; /*!< bit: 22..31 Reserved */ 874 } vec; /*!< Structure used for vec access */ 875 uint32_t reg; /*!< Type used for register access */ 876 } TCC_INTENCLR_Type; 877 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 878 879 #define TCC_INTENCLR_OFFSET 0x24 /**< \brief (TCC_INTENCLR offset) Interrupt Enable Clear */ 880 #define TCC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENCLR reset_value) Interrupt Enable Clear */ 881 882 #define TCC_INTENCLR_OVF_Pos 0 /**< \brief (TCC_INTENCLR) Overflow Interrupt Enable */ 883 #define TCC_INTENCLR_OVF (_U_(0x1) << TCC_INTENCLR_OVF_Pos) 884 #define TCC_INTENCLR_TRG_Pos 1 /**< \brief (TCC_INTENCLR) Retrigger Interrupt Enable */ 885 #define TCC_INTENCLR_TRG (_U_(0x1) << TCC_INTENCLR_TRG_Pos) 886 #define TCC_INTENCLR_CNT_Pos 2 /**< \brief (TCC_INTENCLR) Counter Interrupt Enable */ 887 #define TCC_INTENCLR_CNT (_U_(0x1) << TCC_INTENCLR_CNT_Pos) 888 #define TCC_INTENCLR_ERR_Pos 3 /**< \brief (TCC_INTENCLR) Error Interrupt Enable */ 889 #define TCC_INTENCLR_ERR (_U_(0x1) << TCC_INTENCLR_ERR_Pos) 890 #define TCC_INTENCLR_UFS_Pos 10 /**< \brief (TCC_INTENCLR) Non-Recoverable Update Fault Interrupt Enable */ 891 #define TCC_INTENCLR_UFS (_U_(0x1) << TCC_INTENCLR_UFS_Pos) 892 #define TCC_INTENCLR_DFS_Pos 11 /**< \brief (TCC_INTENCLR) Non-Recoverable Debug Fault Interrupt Enable */ 893 #define TCC_INTENCLR_DFS (_U_(0x1) << TCC_INTENCLR_DFS_Pos) 894 #define TCC_INTENCLR_FAULTA_Pos 12 /**< \brief (TCC_INTENCLR) Recoverable Fault A Interrupt Enable */ 895 #define TCC_INTENCLR_FAULTA (_U_(0x1) << TCC_INTENCLR_FAULTA_Pos) 896 #define TCC_INTENCLR_FAULTB_Pos 13 /**< \brief (TCC_INTENCLR) Recoverable Fault B Interrupt Enable */ 897 #define TCC_INTENCLR_FAULTB (_U_(0x1) << TCC_INTENCLR_FAULTB_Pos) 898 #define TCC_INTENCLR_FAULT0_Pos 14 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 0 Interrupt Enable */ 899 #define TCC_INTENCLR_FAULT0 (_U_(0x1) << TCC_INTENCLR_FAULT0_Pos) 900 #define TCC_INTENCLR_FAULT1_Pos 15 /**< \brief (TCC_INTENCLR) Non-Recoverable Fault 1 Interrupt Enable */ 901 #define TCC_INTENCLR_FAULT1 (_U_(0x1) << TCC_INTENCLR_FAULT1_Pos) 902 #define TCC_INTENCLR_MC0_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel 0 Interrupt Enable */ 903 #define TCC_INTENCLR_MC0 (_U_(1) << TCC_INTENCLR_MC0_Pos) 904 #define TCC_INTENCLR_MC1_Pos 17 /**< \brief (TCC_INTENCLR) Match or Capture Channel 1 Interrupt Enable */ 905 #define TCC_INTENCLR_MC1 (_U_(1) << TCC_INTENCLR_MC1_Pos) 906 #define TCC_INTENCLR_MC2_Pos 18 /**< \brief (TCC_INTENCLR) Match or Capture Channel 2 Interrupt Enable */ 907 #define TCC_INTENCLR_MC2 (_U_(1) << TCC_INTENCLR_MC2_Pos) 908 #define TCC_INTENCLR_MC3_Pos 19 /**< \brief (TCC_INTENCLR) Match or Capture Channel 3 Interrupt Enable */ 909 #define TCC_INTENCLR_MC3 (_U_(1) << TCC_INTENCLR_MC3_Pos) 910 #define TCC_INTENCLR_MC4_Pos 20 /**< \brief (TCC_INTENCLR) Match or Capture Channel 4 Interrupt Enable */ 911 #define TCC_INTENCLR_MC4 (_U_(1) << TCC_INTENCLR_MC4_Pos) 912 #define TCC_INTENCLR_MC5_Pos 21 /**< \brief (TCC_INTENCLR) Match or Capture Channel 5 Interrupt Enable */ 913 #define TCC_INTENCLR_MC5 (_U_(1) << TCC_INTENCLR_MC5_Pos) 914 #define TCC_INTENCLR_MC_Pos 16 /**< \brief (TCC_INTENCLR) Match or Capture Channel x Interrupt Enable */ 915 #define TCC_INTENCLR_MC_Msk (_U_(0x3F) << TCC_INTENCLR_MC_Pos) 916 #define TCC_INTENCLR_MC(value) (TCC_INTENCLR_MC_Msk & ((value) << TCC_INTENCLR_MC_Pos)) 917 #define TCC_INTENCLR_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTENCLR) MASK Register */ 918 919 /* -------- TCC_INTENSET : (TCC Offset: 0x28) (R/W 32) Interrupt Enable Set -------- */ 920 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 921 typedef union { 922 struct { 923 uint32_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */ 924 uint32_t TRG:1; /*!< bit: 1 Retrigger Interrupt Enable */ 925 uint32_t CNT:1; /*!< bit: 2 Counter Interrupt Enable */ 926 uint32_t ERR:1; /*!< bit: 3 Error Interrupt Enable */ 927 uint32_t :6; /*!< bit: 4.. 9 Reserved */ 928 uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault Interrupt Enable */ 929 uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault Interrupt Enable */ 930 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A Interrupt Enable */ 931 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B Interrupt Enable */ 932 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 Interrupt Enable */ 933 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 Interrupt Enable */ 934 uint32_t MC0:1; /*!< bit: 16 Match or Capture Channel 0 Interrupt Enable */ 935 uint32_t MC1:1; /*!< bit: 17 Match or Capture Channel 1 Interrupt Enable */ 936 uint32_t MC2:1; /*!< bit: 18 Match or Capture Channel 2 Interrupt Enable */ 937 uint32_t MC3:1; /*!< bit: 19 Match or Capture Channel 3 Interrupt Enable */ 938 uint32_t MC4:1; /*!< bit: 20 Match or Capture Channel 4 Interrupt Enable */ 939 uint32_t MC5:1; /*!< bit: 21 Match or Capture Channel 5 Interrupt Enable */ 940 uint32_t :10; /*!< bit: 22..31 Reserved */ 941 } bit; /*!< Structure used for bit access */ 942 struct { 943 uint32_t :16; /*!< bit: 0..15 Reserved */ 944 uint32_t MC:6; /*!< bit: 16..21 Match or Capture Channel x Interrupt Enable */ 945 uint32_t :10; /*!< bit: 22..31 Reserved */ 946 } vec; /*!< Structure used for vec access */ 947 uint32_t reg; /*!< Type used for register access */ 948 } TCC_INTENSET_Type; 949 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 950 951 #define TCC_INTENSET_OFFSET 0x28 /**< \brief (TCC_INTENSET offset) Interrupt Enable Set */ 952 #define TCC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTENSET reset_value) Interrupt Enable Set */ 953 954 #define TCC_INTENSET_OVF_Pos 0 /**< \brief (TCC_INTENSET) Overflow Interrupt Enable */ 955 #define TCC_INTENSET_OVF (_U_(0x1) << TCC_INTENSET_OVF_Pos) 956 #define TCC_INTENSET_TRG_Pos 1 /**< \brief (TCC_INTENSET) Retrigger Interrupt Enable */ 957 #define TCC_INTENSET_TRG (_U_(0x1) << TCC_INTENSET_TRG_Pos) 958 #define TCC_INTENSET_CNT_Pos 2 /**< \brief (TCC_INTENSET) Counter Interrupt Enable */ 959 #define TCC_INTENSET_CNT (_U_(0x1) << TCC_INTENSET_CNT_Pos) 960 #define TCC_INTENSET_ERR_Pos 3 /**< \brief (TCC_INTENSET) Error Interrupt Enable */ 961 #define TCC_INTENSET_ERR (_U_(0x1) << TCC_INTENSET_ERR_Pos) 962 #define TCC_INTENSET_UFS_Pos 10 /**< \brief (TCC_INTENSET) Non-Recoverable Update Fault Interrupt Enable */ 963 #define TCC_INTENSET_UFS (_U_(0x1) << TCC_INTENSET_UFS_Pos) 964 #define TCC_INTENSET_DFS_Pos 11 /**< \brief (TCC_INTENSET) Non-Recoverable Debug Fault Interrupt Enable */ 965 #define TCC_INTENSET_DFS (_U_(0x1) << TCC_INTENSET_DFS_Pos) 966 #define TCC_INTENSET_FAULTA_Pos 12 /**< \brief (TCC_INTENSET) Recoverable Fault A Interrupt Enable */ 967 #define TCC_INTENSET_FAULTA (_U_(0x1) << TCC_INTENSET_FAULTA_Pos) 968 #define TCC_INTENSET_FAULTB_Pos 13 /**< \brief (TCC_INTENSET) Recoverable Fault B Interrupt Enable */ 969 #define TCC_INTENSET_FAULTB (_U_(0x1) << TCC_INTENSET_FAULTB_Pos) 970 #define TCC_INTENSET_FAULT0_Pos 14 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 0 Interrupt Enable */ 971 #define TCC_INTENSET_FAULT0 (_U_(0x1) << TCC_INTENSET_FAULT0_Pos) 972 #define TCC_INTENSET_FAULT1_Pos 15 /**< \brief (TCC_INTENSET) Non-Recoverable Fault 1 Interrupt Enable */ 973 #define TCC_INTENSET_FAULT1 (_U_(0x1) << TCC_INTENSET_FAULT1_Pos) 974 #define TCC_INTENSET_MC0_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel 0 Interrupt Enable */ 975 #define TCC_INTENSET_MC0 (_U_(1) << TCC_INTENSET_MC0_Pos) 976 #define TCC_INTENSET_MC1_Pos 17 /**< \brief (TCC_INTENSET) Match or Capture Channel 1 Interrupt Enable */ 977 #define TCC_INTENSET_MC1 (_U_(1) << TCC_INTENSET_MC1_Pos) 978 #define TCC_INTENSET_MC2_Pos 18 /**< \brief (TCC_INTENSET) Match or Capture Channel 2 Interrupt Enable */ 979 #define TCC_INTENSET_MC2 (_U_(1) << TCC_INTENSET_MC2_Pos) 980 #define TCC_INTENSET_MC3_Pos 19 /**< \brief (TCC_INTENSET) Match or Capture Channel 3 Interrupt Enable */ 981 #define TCC_INTENSET_MC3 (_U_(1) << TCC_INTENSET_MC3_Pos) 982 #define TCC_INTENSET_MC4_Pos 20 /**< \brief (TCC_INTENSET) Match or Capture Channel 4 Interrupt Enable */ 983 #define TCC_INTENSET_MC4 (_U_(1) << TCC_INTENSET_MC4_Pos) 984 #define TCC_INTENSET_MC5_Pos 21 /**< \brief (TCC_INTENSET) Match or Capture Channel 5 Interrupt Enable */ 985 #define TCC_INTENSET_MC5 (_U_(1) << TCC_INTENSET_MC5_Pos) 986 #define TCC_INTENSET_MC_Pos 16 /**< \brief (TCC_INTENSET) Match or Capture Channel x Interrupt Enable */ 987 #define TCC_INTENSET_MC_Msk (_U_(0x3F) << TCC_INTENSET_MC_Pos) 988 #define TCC_INTENSET_MC(value) (TCC_INTENSET_MC_Msk & ((value) << TCC_INTENSET_MC_Pos)) 989 #define TCC_INTENSET_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTENSET) MASK Register */ 990 991 /* -------- TCC_INTFLAG : (TCC Offset: 0x2C) (R/W 32) Interrupt Flag Status and Clear -------- */ 992 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 993 typedef union { // __I to avoid read-modify-write on write-to-clear register 994 struct { 995 __I uint32_t OVF:1; /*!< bit: 0 Overflow */ 996 __I uint32_t TRG:1; /*!< bit: 1 Retrigger */ 997 __I uint32_t CNT:1; /*!< bit: 2 Counter */ 998 __I uint32_t ERR:1; /*!< bit: 3 Error */ 999 __I uint32_t :6; /*!< bit: 4.. 9 Reserved */ 1000 __I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */ 1001 __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */ 1002 __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */ 1003 __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */ 1004 __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */ 1005 __I uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 */ 1006 __I uint32_t MC0:1; /*!< bit: 16 Match or Capture 0 */ 1007 __I uint32_t MC1:1; /*!< bit: 17 Match or Capture 1 */ 1008 __I uint32_t MC2:1; /*!< bit: 18 Match or Capture 2 */ 1009 __I uint32_t MC3:1; /*!< bit: 19 Match or Capture 3 */ 1010 __I uint32_t MC4:1; /*!< bit: 20 Match or Capture 4 */ 1011 __I uint32_t MC5:1; /*!< bit: 21 Match or Capture 5 */ 1012 __I uint32_t :10; /*!< bit: 22..31 Reserved */ 1013 } bit; /*!< Structure used for bit access */ 1014 struct { 1015 __I uint32_t :16; /*!< bit: 0..15 Reserved */ 1016 __I uint32_t MC:6; /*!< bit: 16..21 Match or Capture x */ 1017 __I uint32_t :10; /*!< bit: 22..31 Reserved */ 1018 } vec; /*!< Structure used for vec access */ 1019 uint32_t reg; /*!< Type used for register access */ 1020 } TCC_INTFLAG_Type; 1021 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1022 1023 #define TCC_INTFLAG_OFFSET 0x2C /**< \brief (TCC_INTFLAG offset) Interrupt Flag Status and Clear */ 1024 #define TCC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (TCC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 1025 1026 #define TCC_INTFLAG_OVF_Pos 0 /**< \brief (TCC_INTFLAG) Overflow */ 1027 #define TCC_INTFLAG_OVF (_U_(0x1) << TCC_INTFLAG_OVF_Pos) 1028 #define TCC_INTFLAG_TRG_Pos 1 /**< \brief (TCC_INTFLAG) Retrigger */ 1029 #define TCC_INTFLAG_TRG (_U_(0x1) << TCC_INTFLAG_TRG_Pos) 1030 #define TCC_INTFLAG_CNT_Pos 2 /**< \brief (TCC_INTFLAG) Counter */ 1031 #define TCC_INTFLAG_CNT (_U_(0x1) << TCC_INTFLAG_CNT_Pos) 1032 #define TCC_INTFLAG_ERR_Pos 3 /**< \brief (TCC_INTFLAG) Error */ 1033 #define TCC_INTFLAG_ERR (_U_(0x1) << TCC_INTFLAG_ERR_Pos) 1034 #define TCC_INTFLAG_UFS_Pos 10 /**< \brief (TCC_INTFLAG) Non-Recoverable Update Fault */ 1035 #define TCC_INTFLAG_UFS (_U_(0x1) << TCC_INTFLAG_UFS_Pos) 1036 #define TCC_INTFLAG_DFS_Pos 11 /**< \brief (TCC_INTFLAG) Non-Recoverable Debug Fault */ 1037 #define TCC_INTFLAG_DFS (_U_(0x1) << TCC_INTFLAG_DFS_Pos) 1038 #define TCC_INTFLAG_FAULTA_Pos 12 /**< \brief (TCC_INTFLAG) Recoverable Fault A */ 1039 #define TCC_INTFLAG_FAULTA (_U_(0x1) << TCC_INTFLAG_FAULTA_Pos) 1040 #define TCC_INTFLAG_FAULTB_Pos 13 /**< \brief (TCC_INTFLAG) Recoverable Fault B */ 1041 #define TCC_INTFLAG_FAULTB (_U_(0x1) << TCC_INTFLAG_FAULTB_Pos) 1042 #define TCC_INTFLAG_FAULT0_Pos 14 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 0 */ 1043 #define TCC_INTFLAG_FAULT0 (_U_(0x1) << TCC_INTFLAG_FAULT0_Pos) 1044 #define TCC_INTFLAG_FAULT1_Pos 15 /**< \brief (TCC_INTFLAG) Non-Recoverable Fault 1 */ 1045 #define TCC_INTFLAG_FAULT1 (_U_(0x1) << TCC_INTFLAG_FAULT1_Pos) 1046 #define TCC_INTFLAG_MC0_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture 0 */ 1047 #define TCC_INTFLAG_MC0 (_U_(1) << TCC_INTFLAG_MC0_Pos) 1048 #define TCC_INTFLAG_MC1_Pos 17 /**< \brief (TCC_INTFLAG) Match or Capture 1 */ 1049 #define TCC_INTFLAG_MC1 (_U_(1) << TCC_INTFLAG_MC1_Pos) 1050 #define TCC_INTFLAG_MC2_Pos 18 /**< \brief (TCC_INTFLAG) Match or Capture 2 */ 1051 #define TCC_INTFLAG_MC2 (_U_(1) << TCC_INTFLAG_MC2_Pos) 1052 #define TCC_INTFLAG_MC3_Pos 19 /**< \brief (TCC_INTFLAG) Match or Capture 3 */ 1053 #define TCC_INTFLAG_MC3 (_U_(1) << TCC_INTFLAG_MC3_Pos) 1054 #define TCC_INTFLAG_MC4_Pos 20 /**< \brief (TCC_INTFLAG) Match or Capture 4 */ 1055 #define TCC_INTFLAG_MC4 (_U_(1) << TCC_INTFLAG_MC4_Pos) 1056 #define TCC_INTFLAG_MC5_Pos 21 /**< \brief (TCC_INTFLAG) Match or Capture 5 */ 1057 #define TCC_INTFLAG_MC5 (_U_(1) << TCC_INTFLAG_MC5_Pos) 1058 #define TCC_INTFLAG_MC_Pos 16 /**< \brief (TCC_INTFLAG) Match or Capture x */ 1059 #define TCC_INTFLAG_MC_Msk (_U_(0x3F) << TCC_INTFLAG_MC_Pos) 1060 #define TCC_INTFLAG_MC(value) (TCC_INTFLAG_MC_Msk & ((value) << TCC_INTFLAG_MC_Pos)) 1061 #define TCC_INTFLAG_MASK _U_(0x003FFC0F) /**< \brief (TCC_INTFLAG) MASK Register */ 1062 1063 /* -------- TCC_STATUS : (TCC Offset: 0x30) (R/W 32) Status -------- */ 1064 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1065 typedef union { 1066 struct { 1067 uint32_t STOP:1; /*!< bit: 0 Stop */ 1068 uint32_t IDX:1; /*!< bit: 1 Ramp */ 1069 uint32_t UFS:1; /*!< bit: 2 Non-recoverable Update Fault State */ 1070 uint32_t DFS:1; /*!< bit: 3 Non-Recoverable Debug Fault State */ 1071 uint32_t SLAVE:1; /*!< bit: 4 Slave */ 1072 uint32_t PATTBUFV:1; /*!< bit: 5 Pattern Buffer Valid */ 1073 uint32_t :1; /*!< bit: 6 Reserved */ 1074 uint32_t PERBUFV:1; /*!< bit: 7 Period Buffer Valid */ 1075 uint32_t FAULTAIN:1; /*!< bit: 8 Recoverable Fault A Input */ 1076 uint32_t FAULTBIN:1; /*!< bit: 9 Recoverable Fault B Input */ 1077 uint32_t FAULT0IN:1; /*!< bit: 10 Non-Recoverable Fault0 Input */ 1078 uint32_t FAULT1IN:1; /*!< bit: 11 Non-Recoverable Fault1 Input */ 1079 uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A State */ 1080 uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B State */ 1081 uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 State */ 1082 uint32_t FAULT1:1; /*!< bit: 15 Non-Recoverable Fault 1 State */ 1083 uint32_t CCBUFV0:1; /*!< bit: 16 Compare Channel 0 Buffer Valid */ 1084 uint32_t CCBUFV1:1; /*!< bit: 17 Compare Channel 1 Buffer Valid */ 1085 uint32_t CCBUFV2:1; /*!< bit: 18 Compare Channel 2 Buffer Valid */ 1086 uint32_t CCBUFV3:1; /*!< bit: 19 Compare Channel 3 Buffer Valid */ 1087 uint32_t CCBUFV4:1; /*!< bit: 20 Compare Channel 4 Buffer Valid */ 1088 uint32_t CCBUFV5:1; /*!< bit: 21 Compare Channel 5 Buffer Valid */ 1089 uint32_t :2; /*!< bit: 22..23 Reserved */ 1090 uint32_t CMP0:1; /*!< bit: 24 Compare Channel 0 Value */ 1091 uint32_t CMP1:1; /*!< bit: 25 Compare Channel 1 Value */ 1092 uint32_t CMP2:1; /*!< bit: 26 Compare Channel 2 Value */ 1093 uint32_t CMP3:1; /*!< bit: 27 Compare Channel 3 Value */ 1094 uint32_t CMP4:1; /*!< bit: 28 Compare Channel 4 Value */ 1095 uint32_t CMP5:1; /*!< bit: 29 Compare Channel 5 Value */ 1096 uint32_t :2; /*!< bit: 30..31 Reserved */ 1097 } bit; /*!< Structure used for bit access */ 1098 struct { 1099 uint32_t :16; /*!< bit: 0..15 Reserved */ 1100 uint32_t CCBUFV:6; /*!< bit: 16..21 Compare Channel x Buffer Valid */ 1101 uint32_t :2; /*!< bit: 22..23 Reserved */ 1102 uint32_t CMP:6; /*!< bit: 24..29 Compare Channel x Value */ 1103 uint32_t :2; /*!< bit: 30..31 Reserved */ 1104 } vec; /*!< Structure used for vec access */ 1105 uint32_t reg; /*!< Type used for register access */ 1106 } TCC_STATUS_Type; 1107 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1108 1109 #define TCC_STATUS_OFFSET 0x30 /**< \brief (TCC_STATUS offset) Status */ 1110 #define TCC_STATUS_RESETVALUE _U_(0x00000001) /**< \brief (TCC_STATUS reset_value) Status */ 1111 1112 #define TCC_STATUS_STOP_Pos 0 /**< \brief (TCC_STATUS) Stop */ 1113 #define TCC_STATUS_STOP (_U_(0x1) << TCC_STATUS_STOP_Pos) 1114 #define TCC_STATUS_IDX_Pos 1 /**< \brief (TCC_STATUS) Ramp */ 1115 #define TCC_STATUS_IDX (_U_(0x1) << TCC_STATUS_IDX_Pos) 1116 #define TCC_STATUS_UFS_Pos 2 /**< \brief (TCC_STATUS) Non-recoverable Update Fault State */ 1117 #define TCC_STATUS_UFS (_U_(0x1) << TCC_STATUS_UFS_Pos) 1118 #define TCC_STATUS_DFS_Pos 3 /**< \brief (TCC_STATUS) Non-Recoverable Debug Fault State */ 1119 #define TCC_STATUS_DFS (_U_(0x1) << TCC_STATUS_DFS_Pos) 1120 #define TCC_STATUS_SLAVE_Pos 4 /**< \brief (TCC_STATUS) Slave */ 1121 #define TCC_STATUS_SLAVE (_U_(0x1) << TCC_STATUS_SLAVE_Pos) 1122 #define TCC_STATUS_PATTBUFV_Pos 5 /**< \brief (TCC_STATUS) Pattern Buffer Valid */ 1123 #define TCC_STATUS_PATTBUFV (_U_(0x1) << TCC_STATUS_PATTBUFV_Pos) 1124 #define TCC_STATUS_PERBUFV_Pos 7 /**< \brief (TCC_STATUS) Period Buffer Valid */ 1125 #define TCC_STATUS_PERBUFV (_U_(0x1) << TCC_STATUS_PERBUFV_Pos) 1126 #define TCC_STATUS_FAULTAIN_Pos 8 /**< \brief (TCC_STATUS) Recoverable Fault A Input */ 1127 #define TCC_STATUS_FAULTAIN (_U_(0x1) << TCC_STATUS_FAULTAIN_Pos) 1128 #define TCC_STATUS_FAULTBIN_Pos 9 /**< \brief (TCC_STATUS) Recoverable Fault B Input */ 1129 #define TCC_STATUS_FAULTBIN (_U_(0x1) << TCC_STATUS_FAULTBIN_Pos) 1130 #define TCC_STATUS_FAULT0IN_Pos 10 /**< \brief (TCC_STATUS) Non-Recoverable Fault0 Input */ 1131 #define TCC_STATUS_FAULT0IN (_U_(0x1) << TCC_STATUS_FAULT0IN_Pos) 1132 #define TCC_STATUS_FAULT1IN_Pos 11 /**< \brief (TCC_STATUS) Non-Recoverable Fault1 Input */ 1133 #define TCC_STATUS_FAULT1IN (_U_(0x1) << TCC_STATUS_FAULT1IN_Pos) 1134 #define TCC_STATUS_FAULTA_Pos 12 /**< \brief (TCC_STATUS) Recoverable Fault A State */ 1135 #define TCC_STATUS_FAULTA (_U_(0x1) << TCC_STATUS_FAULTA_Pos) 1136 #define TCC_STATUS_FAULTB_Pos 13 /**< \brief (TCC_STATUS) Recoverable Fault B State */ 1137 #define TCC_STATUS_FAULTB (_U_(0x1) << TCC_STATUS_FAULTB_Pos) 1138 #define TCC_STATUS_FAULT0_Pos 14 /**< \brief (TCC_STATUS) Non-Recoverable Fault 0 State */ 1139 #define TCC_STATUS_FAULT0 (_U_(0x1) << TCC_STATUS_FAULT0_Pos) 1140 #define TCC_STATUS_FAULT1_Pos 15 /**< \brief (TCC_STATUS) Non-Recoverable Fault 1 State */ 1141 #define TCC_STATUS_FAULT1 (_U_(0x1) << TCC_STATUS_FAULT1_Pos) 1142 #define TCC_STATUS_CCBUFV0_Pos 16 /**< \brief (TCC_STATUS) Compare Channel 0 Buffer Valid */ 1143 #define TCC_STATUS_CCBUFV0 (_U_(1) << TCC_STATUS_CCBUFV0_Pos) 1144 #define TCC_STATUS_CCBUFV1_Pos 17 /**< \brief (TCC_STATUS) Compare Channel 1 Buffer Valid */ 1145 #define TCC_STATUS_CCBUFV1 (_U_(1) << TCC_STATUS_CCBUFV1_Pos) 1146 #define TCC_STATUS_CCBUFV2_Pos 18 /**< \brief (TCC_STATUS) Compare Channel 2 Buffer Valid */ 1147 #define TCC_STATUS_CCBUFV2 (_U_(1) << TCC_STATUS_CCBUFV2_Pos) 1148 #define TCC_STATUS_CCBUFV3_Pos 19 /**< \brief (TCC_STATUS) Compare Channel 3 Buffer Valid */ 1149 #define TCC_STATUS_CCBUFV3 (_U_(1) << TCC_STATUS_CCBUFV3_Pos) 1150 #define TCC_STATUS_CCBUFV4_Pos 20 /**< \brief (TCC_STATUS) Compare Channel 4 Buffer Valid */ 1151 #define TCC_STATUS_CCBUFV4 (_U_(1) << TCC_STATUS_CCBUFV4_Pos) 1152 #define TCC_STATUS_CCBUFV5_Pos 21 /**< \brief (TCC_STATUS) Compare Channel 5 Buffer Valid */ 1153 #define TCC_STATUS_CCBUFV5 (_U_(1) << TCC_STATUS_CCBUFV5_Pos) 1154 #define TCC_STATUS_CCBUFV_Pos 16 /**< \brief (TCC_STATUS) Compare Channel x Buffer Valid */ 1155 #define TCC_STATUS_CCBUFV_Msk (_U_(0x3F) << TCC_STATUS_CCBUFV_Pos) 1156 #define TCC_STATUS_CCBUFV(value) (TCC_STATUS_CCBUFV_Msk & ((value) << TCC_STATUS_CCBUFV_Pos)) 1157 #define TCC_STATUS_CMP0_Pos 24 /**< \brief (TCC_STATUS) Compare Channel 0 Value */ 1158 #define TCC_STATUS_CMP0 (_U_(1) << TCC_STATUS_CMP0_Pos) 1159 #define TCC_STATUS_CMP1_Pos 25 /**< \brief (TCC_STATUS) Compare Channel 1 Value */ 1160 #define TCC_STATUS_CMP1 (_U_(1) << TCC_STATUS_CMP1_Pos) 1161 #define TCC_STATUS_CMP2_Pos 26 /**< \brief (TCC_STATUS) Compare Channel 2 Value */ 1162 #define TCC_STATUS_CMP2 (_U_(1) << TCC_STATUS_CMP2_Pos) 1163 #define TCC_STATUS_CMP3_Pos 27 /**< \brief (TCC_STATUS) Compare Channel 3 Value */ 1164 #define TCC_STATUS_CMP3 (_U_(1) << TCC_STATUS_CMP3_Pos) 1165 #define TCC_STATUS_CMP4_Pos 28 /**< \brief (TCC_STATUS) Compare Channel 4 Value */ 1166 #define TCC_STATUS_CMP4 (_U_(1) << TCC_STATUS_CMP4_Pos) 1167 #define TCC_STATUS_CMP5_Pos 29 /**< \brief (TCC_STATUS) Compare Channel 5 Value */ 1168 #define TCC_STATUS_CMP5 (_U_(1) << TCC_STATUS_CMP5_Pos) 1169 #define TCC_STATUS_CMP_Pos 24 /**< \brief (TCC_STATUS) Compare Channel x Value */ 1170 #define TCC_STATUS_CMP_Msk (_U_(0x3F) << TCC_STATUS_CMP_Pos) 1171 #define TCC_STATUS_CMP(value) (TCC_STATUS_CMP_Msk & ((value) << TCC_STATUS_CMP_Pos)) 1172 #define TCC_STATUS_MASK _U_(0x3F3FFFBF) /**< \brief (TCC_STATUS) MASK Register */ 1173 1174 /* -------- TCC_COUNT : (TCC Offset: 0x34) (R/W 32) Count -------- */ 1175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1176 typedef union { 1177 struct { // DITH4 mode 1178 uint32_t :4; /*!< bit: 0.. 3 Reserved */ 1179 uint32_t COUNT:20; /*!< bit: 4..23 Counter Value */ 1180 uint32_t :8; /*!< bit: 24..31 Reserved */ 1181 } DITH4; /*!< Structure used for DITH4 */ 1182 struct { // DITH5 mode 1183 uint32_t :5; /*!< bit: 0.. 4 Reserved */ 1184 uint32_t COUNT:19; /*!< bit: 5..23 Counter Value */ 1185 uint32_t :8; /*!< bit: 24..31 Reserved */ 1186 } DITH5; /*!< Structure used for DITH5 */ 1187 struct { // DITH6 mode 1188 uint32_t :6; /*!< bit: 0.. 5 Reserved */ 1189 uint32_t COUNT:18; /*!< bit: 6..23 Counter Value */ 1190 uint32_t :8; /*!< bit: 24..31 Reserved */ 1191 } DITH6; /*!< Structure used for DITH6 */ 1192 struct { 1193 uint32_t COUNT:24; /*!< bit: 0..23 Counter Value */ 1194 uint32_t :8; /*!< bit: 24..31 Reserved */ 1195 } bit; /*!< Structure used for bit access */ 1196 uint32_t reg; /*!< Type used for register access */ 1197 } TCC_COUNT_Type; 1198 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1199 1200 #define TCC_COUNT_OFFSET 0x34 /**< \brief (TCC_COUNT offset) Count */ 1201 #define TCC_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (TCC_COUNT reset_value) Count */ 1202 1203 // DITH4 mode 1204 #define TCC_COUNT_DITH4_COUNT_Pos 4 /**< \brief (TCC_COUNT_DITH4) Counter Value */ 1205 #define TCC_COUNT_DITH4_COUNT_Msk (_U_(0xFFFFF) << TCC_COUNT_DITH4_COUNT_Pos) 1206 #define TCC_COUNT_DITH4_COUNT(value) (TCC_COUNT_DITH4_COUNT_Msk & ((value) << TCC_COUNT_DITH4_COUNT_Pos)) 1207 #define TCC_COUNT_DITH4_MASK _U_(0x00FFFFF0) /**< \brief (TCC_COUNT_DITH4) MASK Register */ 1208 1209 // DITH5 mode 1210 #define TCC_COUNT_DITH5_COUNT_Pos 5 /**< \brief (TCC_COUNT_DITH5) Counter Value */ 1211 #define TCC_COUNT_DITH5_COUNT_Msk (_U_(0x7FFFF) << TCC_COUNT_DITH5_COUNT_Pos) 1212 #define TCC_COUNT_DITH5_COUNT(value) (TCC_COUNT_DITH5_COUNT_Msk & ((value) << TCC_COUNT_DITH5_COUNT_Pos)) 1213 #define TCC_COUNT_DITH5_MASK _U_(0x00FFFFE0) /**< \brief (TCC_COUNT_DITH5) MASK Register */ 1214 1215 // DITH6 mode 1216 #define TCC_COUNT_DITH6_COUNT_Pos 6 /**< \brief (TCC_COUNT_DITH6) Counter Value */ 1217 #define TCC_COUNT_DITH6_COUNT_Msk (_U_(0x3FFFF) << TCC_COUNT_DITH6_COUNT_Pos) 1218 #define TCC_COUNT_DITH6_COUNT(value) (TCC_COUNT_DITH6_COUNT_Msk & ((value) << TCC_COUNT_DITH6_COUNT_Pos)) 1219 #define TCC_COUNT_DITH6_MASK _U_(0x00FFFFC0) /**< \brief (TCC_COUNT_DITH6) MASK Register */ 1220 1221 #define TCC_COUNT_COUNT_Pos 0 /**< \brief (TCC_COUNT) Counter Value */ 1222 #define TCC_COUNT_COUNT_Msk (_U_(0xFFFFFF) << TCC_COUNT_COUNT_Pos) 1223 #define TCC_COUNT_COUNT(value) (TCC_COUNT_COUNT_Msk & ((value) << TCC_COUNT_COUNT_Pos)) 1224 #define TCC_COUNT_MASK _U_(0x00FFFFFF) /**< \brief (TCC_COUNT) MASK Register */ 1225 1226 /* -------- TCC_PATT : (TCC Offset: 0x38) (R/W 16) Pattern -------- */ 1227 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1228 typedef union { 1229 struct { 1230 uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */ 1231 uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */ 1232 uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */ 1233 uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */ 1234 uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */ 1235 uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */ 1236 uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */ 1237 uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */ 1238 uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */ 1239 uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */ 1240 uint16_t PGV2:1; /*!< bit: 10 Pattern Generator 2 Output Value */ 1241 uint16_t PGV3:1; /*!< bit: 11 Pattern Generator 3 Output Value */ 1242 uint16_t PGV4:1; /*!< bit: 12 Pattern Generator 4 Output Value */ 1243 uint16_t PGV5:1; /*!< bit: 13 Pattern Generator 5 Output Value */ 1244 uint16_t PGV6:1; /*!< bit: 14 Pattern Generator 6 Output Value */ 1245 uint16_t PGV7:1; /*!< bit: 15 Pattern Generator 7 Output Value */ 1246 } bit; /*!< Structure used for bit access */ 1247 struct { 1248 uint16_t PGE:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable */ 1249 uint16_t PGV:8; /*!< bit: 8..15 Pattern Generator x Output Value */ 1250 } vec; /*!< Structure used for vec access */ 1251 uint16_t reg; /*!< Type used for register access */ 1252 } TCC_PATT_Type; 1253 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1254 1255 #define TCC_PATT_OFFSET 0x38 /**< \brief (TCC_PATT offset) Pattern */ 1256 #define TCC_PATT_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATT reset_value) Pattern */ 1257 1258 #define TCC_PATT_PGE0_Pos 0 /**< \brief (TCC_PATT) Pattern Generator 0 Output Enable */ 1259 #define TCC_PATT_PGE0 (_U_(1) << TCC_PATT_PGE0_Pos) 1260 #define TCC_PATT_PGE1_Pos 1 /**< \brief (TCC_PATT) Pattern Generator 1 Output Enable */ 1261 #define TCC_PATT_PGE1 (_U_(1) << TCC_PATT_PGE1_Pos) 1262 #define TCC_PATT_PGE2_Pos 2 /**< \brief (TCC_PATT) Pattern Generator 2 Output Enable */ 1263 #define TCC_PATT_PGE2 (_U_(1) << TCC_PATT_PGE2_Pos) 1264 #define TCC_PATT_PGE3_Pos 3 /**< \brief (TCC_PATT) Pattern Generator 3 Output Enable */ 1265 #define TCC_PATT_PGE3 (_U_(1) << TCC_PATT_PGE3_Pos) 1266 #define TCC_PATT_PGE4_Pos 4 /**< \brief (TCC_PATT) Pattern Generator 4 Output Enable */ 1267 #define TCC_PATT_PGE4 (_U_(1) << TCC_PATT_PGE4_Pos) 1268 #define TCC_PATT_PGE5_Pos 5 /**< \brief (TCC_PATT) Pattern Generator 5 Output Enable */ 1269 #define TCC_PATT_PGE5 (_U_(1) << TCC_PATT_PGE5_Pos) 1270 #define TCC_PATT_PGE6_Pos 6 /**< \brief (TCC_PATT) Pattern Generator 6 Output Enable */ 1271 #define TCC_PATT_PGE6 (_U_(1) << TCC_PATT_PGE6_Pos) 1272 #define TCC_PATT_PGE7_Pos 7 /**< \brief (TCC_PATT) Pattern Generator 7 Output Enable */ 1273 #define TCC_PATT_PGE7 (_U_(1) << TCC_PATT_PGE7_Pos) 1274 #define TCC_PATT_PGE_Pos 0 /**< \brief (TCC_PATT) Pattern Generator x Output Enable */ 1275 #define TCC_PATT_PGE_Msk (_U_(0xFF) << TCC_PATT_PGE_Pos) 1276 #define TCC_PATT_PGE(value) (TCC_PATT_PGE_Msk & ((value) << TCC_PATT_PGE_Pos)) 1277 #define TCC_PATT_PGV0_Pos 8 /**< \brief (TCC_PATT) Pattern Generator 0 Output Value */ 1278 #define TCC_PATT_PGV0 (_U_(1) << TCC_PATT_PGV0_Pos) 1279 #define TCC_PATT_PGV1_Pos 9 /**< \brief (TCC_PATT) Pattern Generator 1 Output Value */ 1280 #define TCC_PATT_PGV1 (_U_(1) << TCC_PATT_PGV1_Pos) 1281 #define TCC_PATT_PGV2_Pos 10 /**< \brief (TCC_PATT) Pattern Generator 2 Output Value */ 1282 #define TCC_PATT_PGV2 (_U_(1) << TCC_PATT_PGV2_Pos) 1283 #define TCC_PATT_PGV3_Pos 11 /**< \brief (TCC_PATT) Pattern Generator 3 Output Value */ 1284 #define TCC_PATT_PGV3 (_U_(1) << TCC_PATT_PGV3_Pos) 1285 #define TCC_PATT_PGV4_Pos 12 /**< \brief (TCC_PATT) Pattern Generator 4 Output Value */ 1286 #define TCC_PATT_PGV4 (_U_(1) << TCC_PATT_PGV4_Pos) 1287 #define TCC_PATT_PGV5_Pos 13 /**< \brief (TCC_PATT) Pattern Generator 5 Output Value */ 1288 #define TCC_PATT_PGV5 (_U_(1) << TCC_PATT_PGV5_Pos) 1289 #define TCC_PATT_PGV6_Pos 14 /**< \brief (TCC_PATT) Pattern Generator 6 Output Value */ 1290 #define TCC_PATT_PGV6 (_U_(1) << TCC_PATT_PGV6_Pos) 1291 #define TCC_PATT_PGV7_Pos 15 /**< \brief (TCC_PATT) Pattern Generator 7 Output Value */ 1292 #define TCC_PATT_PGV7 (_U_(1) << TCC_PATT_PGV7_Pos) 1293 #define TCC_PATT_PGV_Pos 8 /**< \brief (TCC_PATT) Pattern Generator x Output Value */ 1294 #define TCC_PATT_PGV_Msk (_U_(0xFF) << TCC_PATT_PGV_Pos) 1295 #define TCC_PATT_PGV(value) (TCC_PATT_PGV_Msk & ((value) << TCC_PATT_PGV_Pos)) 1296 #define TCC_PATT_MASK _U_(0xFFFF) /**< \brief (TCC_PATT) MASK Register */ 1297 1298 /* -------- TCC_WAVE : (TCC Offset: 0x3C) (R/W 32) Waveform Control -------- */ 1299 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1300 typedef union { 1301 struct { 1302 uint32_t WAVEGEN:3; /*!< bit: 0.. 2 Waveform Generation */ 1303 uint32_t :1; /*!< bit: 3 Reserved */ 1304 uint32_t RAMP:2; /*!< bit: 4.. 5 Ramp Mode */ 1305 uint32_t :1; /*!< bit: 6 Reserved */ 1306 uint32_t CIPEREN:1; /*!< bit: 7 Circular period Enable */ 1307 uint32_t CICCEN0:1; /*!< bit: 8 Circular Channel 0 Enable */ 1308 uint32_t CICCEN1:1; /*!< bit: 9 Circular Channel 1 Enable */ 1309 uint32_t CICCEN2:1; /*!< bit: 10 Circular Channel 2 Enable */ 1310 uint32_t CICCEN3:1; /*!< bit: 11 Circular Channel 3 Enable */ 1311 uint32_t :4; /*!< bit: 12..15 Reserved */ 1312 uint32_t POL0:1; /*!< bit: 16 Channel 0 Polarity */ 1313 uint32_t POL1:1; /*!< bit: 17 Channel 1 Polarity */ 1314 uint32_t POL2:1; /*!< bit: 18 Channel 2 Polarity */ 1315 uint32_t POL3:1; /*!< bit: 19 Channel 3 Polarity */ 1316 uint32_t POL4:1; /*!< bit: 20 Channel 4 Polarity */ 1317 uint32_t POL5:1; /*!< bit: 21 Channel 5 Polarity */ 1318 uint32_t :2; /*!< bit: 22..23 Reserved */ 1319 uint32_t SWAP0:1; /*!< bit: 24 Swap DTI Output Pair 0 */ 1320 uint32_t SWAP1:1; /*!< bit: 25 Swap DTI Output Pair 1 */ 1321 uint32_t SWAP2:1; /*!< bit: 26 Swap DTI Output Pair 2 */ 1322 uint32_t SWAP3:1; /*!< bit: 27 Swap DTI Output Pair 3 */ 1323 uint32_t :4; /*!< bit: 28..31 Reserved */ 1324 } bit; /*!< Structure used for bit access */ 1325 struct { 1326 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 1327 uint32_t CICCEN:4; /*!< bit: 8..11 Circular Channel x Enable */ 1328 uint32_t :4; /*!< bit: 12..15 Reserved */ 1329 uint32_t POL:6; /*!< bit: 16..21 Channel x Polarity */ 1330 uint32_t :2; /*!< bit: 22..23 Reserved */ 1331 uint32_t SWAP:4; /*!< bit: 24..27 Swap DTI Output Pair x */ 1332 uint32_t :4; /*!< bit: 28..31 Reserved */ 1333 } vec; /*!< Structure used for vec access */ 1334 uint32_t reg; /*!< Type used for register access */ 1335 } TCC_WAVE_Type; 1336 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1337 1338 #define TCC_WAVE_OFFSET 0x3C /**< \brief (TCC_WAVE offset) Waveform Control */ 1339 #define TCC_WAVE_RESETVALUE _U_(0x00000000) /**< \brief (TCC_WAVE reset_value) Waveform Control */ 1340 1341 #define TCC_WAVE_WAVEGEN_Pos 0 /**< \brief (TCC_WAVE) Waveform Generation */ 1342 #define TCC_WAVE_WAVEGEN_Msk (_U_(0x7) << TCC_WAVE_WAVEGEN_Pos) 1343 #define TCC_WAVE_WAVEGEN(value) (TCC_WAVE_WAVEGEN_Msk & ((value) << TCC_WAVE_WAVEGEN_Pos)) 1344 #define TCC_WAVE_WAVEGEN_NFRQ_Val _U_(0x0) /**< \brief (TCC_WAVE) Normal frequency */ 1345 #define TCC_WAVE_WAVEGEN_MFRQ_Val _U_(0x1) /**< \brief (TCC_WAVE) Match frequency */ 1346 #define TCC_WAVE_WAVEGEN_NPWM_Val _U_(0x2) /**< \brief (TCC_WAVE) Normal PWM */ 1347 #define TCC_WAVE_WAVEGEN_DSCRITICAL_Val _U_(0x4) /**< \brief (TCC_WAVE) Dual-slope critical */ 1348 #define TCC_WAVE_WAVEGEN_DSBOTTOM_Val _U_(0x5) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO */ 1349 #define TCC_WAVE_WAVEGEN_DSBOTH_Val _U_(0x6) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP */ 1350 #define TCC_WAVE_WAVEGEN_DSTOP_Val _U_(0x7) /**< \brief (TCC_WAVE) Dual-slope with interrupt/event condition when COUNT reaches TOP */ 1351 #define TCC_WAVE_WAVEGEN_NFRQ (TCC_WAVE_WAVEGEN_NFRQ_Val << TCC_WAVE_WAVEGEN_Pos) 1352 #define TCC_WAVE_WAVEGEN_MFRQ (TCC_WAVE_WAVEGEN_MFRQ_Val << TCC_WAVE_WAVEGEN_Pos) 1353 #define TCC_WAVE_WAVEGEN_NPWM (TCC_WAVE_WAVEGEN_NPWM_Val << TCC_WAVE_WAVEGEN_Pos) 1354 #define TCC_WAVE_WAVEGEN_DSCRITICAL (TCC_WAVE_WAVEGEN_DSCRITICAL_Val << TCC_WAVE_WAVEGEN_Pos) 1355 #define TCC_WAVE_WAVEGEN_DSBOTTOM (TCC_WAVE_WAVEGEN_DSBOTTOM_Val << TCC_WAVE_WAVEGEN_Pos) 1356 #define TCC_WAVE_WAVEGEN_DSBOTH (TCC_WAVE_WAVEGEN_DSBOTH_Val << TCC_WAVE_WAVEGEN_Pos) 1357 #define TCC_WAVE_WAVEGEN_DSTOP (TCC_WAVE_WAVEGEN_DSTOP_Val << TCC_WAVE_WAVEGEN_Pos) 1358 #define TCC_WAVE_RAMP_Pos 4 /**< \brief (TCC_WAVE) Ramp Mode */ 1359 #define TCC_WAVE_RAMP_Msk (_U_(0x3) << TCC_WAVE_RAMP_Pos) 1360 #define TCC_WAVE_RAMP(value) (TCC_WAVE_RAMP_Msk & ((value) << TCC_WAVE_RAMP_Pos)) 1361 #define TCC_WAVE_RAMP_RAMP1_Val _U_(0x0) /**< \brief (TCC_WAVE) RAMP1 operation */ 1362 #define TCC_WAVE_RAMP_RAMP2A_Val _U_(0x1) /**< \brief (TCC_WAVE) Alternative RAMP2 operation */ 1363 #define TCC_WAVE_RAMP_RAMP2_Val _U_(0x2) /**< \brief (TCC_WAVE) RAMP2 operation */ 1364 #define TCC_WAVE_RAMP_RAMP2C_Val _U_(0x3) /**< \brief (TCC_WAVE) Critical RAMP2 operation */ 1365 #define TCC_WAVE_RAMP_RAMP1 (TCC_WAVE_RAMP_RAMP1_Val << TCC_WAVE_RAMP_Pos) 1366 #define TCC_WAVE_RAMP_RAMP2A (TCC_WAVE_RAMP_RAMP2A_Val << TCC_WAVE_RAMP_Pos) 1367 #define TCC_WAVE_RAMP_RAMP2 (TCC_WAVE_RAMP_RAMP2_Val << TCC_WAVE_RAMP_Pos) 1368 #define TCC_WAVE_RAMP_RAMP2C (TCC_WAVE_RAMP_RAMP2C_Val << TCC_WAVE_RAMP_Pos) 1369 #define TCC_WAVE_CIPEREN_Pos 7 /**< \brief (TCC_WAVE) Circular period Enable */ 1370 #define TCC_WAVE_CIPEREN (_U_(0x1) << TCC_WAVE_CIPEREN_Pos) 1371 #define TCC_WAVE_CICCEN0_Pos 8 /**< \brief (TCC_WAVE) Circular Channel 0 Enable */ 1372 #define TCC_WAVE_CICCEN0 (_U_(1) << TCC_WAVE_CICCEN0_Pos) 1373 #define TCC_WAVE_CICCEN1_Pos 9 /**< \brief (TCC_WAVE) Circular Channel 1 Enable */ 1374 #define TCC_WAVE_CICCEN1 (_U_(1) << TCC_WAVE_CICCEN1_Pos) 1375 #define TCC_WAVE_CICCEN2_Pos 10 /**< \brief (TCC_WAVE) Circular Channel 2 Enable */ 1376 #define TCC_WAVE_CICCEN2 (_U_(1) << TCC_WAVE_CICCEN2_Pos) 1377 #define TCC_WAVE_CICCEN3_Pos 11 /**< \brief (TCC_WAVE) Circular Channel 3 Enable */ 1378 #define TCC_WAVE_CICCEN3 (_U_(1) << TCC_WAVE_CICCEN3_Pos) 1379 #define TCC_WAVE_CICCEN_Pos 8 /**< \brief (TCC_WAVE) Circular Channel x Enable */ 1380 #define TCC_WAVE_CICCEN_Msk (_U_(0xF) << TCC_WAVE_CICCEN_Pos) 1381 #define TCC_WAVE_CICCEN(value) (TCC_WAVE_CICCEN_Msk & ((value) << TCC_WAVE_CICCEN_Pos)) 1382 #define TCC_WAVE_POL0_Pos 16 /**< \brief (TCC_WAVE) Channel 0 Polarity */ 1383 #define TCC_WAVE_POL0 (_U_(1) << TCC_WAVE_POL0_Pos) 1384 #define TCC_WAVE_POL1_Pos 17 /**< \brief (TCC_WAVE) Channel 1 Polarity */ 1385 #define TCC_WAVE_POL1 (_U_(1) << TCC_WAVE_POL1_Pos) 1386 #define TCC_WAVE_POL2_Pos 18 /**< \brief (TCC_WAVE) Channel 2 Polarity */ 1387 #define TCC_WAVE_POL2 (_U_(1) << TCC_WAVE_POL2_Pos) 1388 #define TCC_WAVE_POL3_Pos 19 /**< \brief (TCC_WAVE) Channel 3 Polarity */ 1389 #define TCC_WAVE_POL3 (_U_(1) << TCC_WAVE_POL3_Pos) 1390 #define TCC_WAVE_POL4_Pos 20 /**< \brief (TCC_WAVE) Channel 4 Polarity */ 1391 #define TCC_WAVE_POL4 (_U_(1) << TCC_WAVE_POL4_Pos) 1392 #define TCC_WAVE_POL5_Pos 21 /**< \brief (TCC_WAVE) Channel 5 Polarity */ 1393 #define TCC_WAVE_POL5 (_U_(1) << TCC_WAVE_POL5_Pos) 1394 #define TCC_WAVE_POL_Pos 16 /**< \brief (TCC_WAVE) Channel x Polarity */ 1395 #define TCC_WAVE_POL_Msk (_U_(0x3F) << TCC_WAVE_POL_Pos) 1396 #define TCC_WAVE_POL(value) (TCC_WAVE_POL_Msk & ((value) << TCC_WAVE_POL_Pos)) 1397 #define TCC_WAVE_SWAP0_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair 0 */ 1398 #define TCC_WAVE_SWAP0 (_U_(1) << TCC_WAVE_SWAP0_Pos) 1399 #define TCC_WAVE_SWAP1_Pos 25 /**< \brief (TCC_WAVE) Swap DTI Output Pair 1 */ 1400 #define TCC_WAVE_SWAP1 (_U_(1) << TCC_WAVE_SWAP1_Pos) 1401 #define TCC_WAVE_SWAP2_Pos 26 /**< \brief (TCC_WAVE) Swap DTI Output Pair 2 */ 1402 #define TCC_WAVE_SWAP2 (_U_(1) << TCC_WAVE_SWAP2_Pos) 1403 #define TCC_WAVE_SWAP3_Pos 27 /**< \brief (TCC_WAVE) Swap DTI Output Pair 3 */ 1404 #define TCC_WAVE_SWAP3 (_U_(1) << TCC_WAVE_SWAP3_Pos) 1405 #define TCC_WAVE_SWAP_Pos 24 /**< \brief (TCC_WAVE) Swap DTI Output Pair x */ 1406 #define TCC_WAVE_SWAP_Msk (_U_(0xF) << TCC_WAVE_SWAP_Pos) 1407 #define TCC_WAVE_SWAP(value) (TCC_WAVE_SWAP_Msk & ((value) << TCC_WAVE_SWAP_Pos)) 1408 #define TCC_WAVE_MASK _U_(0x0F3F0FB7) /**< \brief (TCC_WAVE) MASK Register */ 1409 1410 /* -------- TCC_PER : (TCC Offset: 0x40) (R/W 32) Period -------- */ 1411 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1412 typedef union { 1413 struct { // DITH4 mode 1414 uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */ 1415 uint32_t PER:20; /*!< bit: 4..23 Period Value */ 1416 uint32_t :8; /*!< bit: 24..31 Reserved */ 1417 } DITH4; /*!< Structure used for DITH4 */ 1418 struct { // DITH5 mode 1419 uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */ 1420 uint32_t PER:19; /*!< bit: 5..23 Period Value */ 1421 uint32_t :8; /*!< bit: 24..31 Reserved */ 1422 } DITH5; /*!< Structure used for DITH5 */ 1423 struct { // DITH6 mode 1424 uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */ 1425 uint32_t PER:18; /*!< bit: 6..23 Period Value */ 1426 uint32_t :8; /*!< bit: 24..31 Reserved */ 1427 } DITH6; /*!< Structure used for DITH6 */ 1428 struct { 1429 uint32_t PER:24; /*!< bit: 0..23 Period Value */ 1430 uint32_t :8; /*!< bit: 24..31 Reserved */ 1431 } bit; /*!< Structure used for bit access */ 1432 uint32_t reg; /*!< Type used for register access */ 1433 } TCC_PER_Type; 1434 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1435 1436 #define TCC_PER_OFFSET 0x40 /**< \brief (TCC_PER offset) Period */ 1437 #define TCC_PER_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PER reset_value) Period */ 1438 1439 // DITH4 mode 1440 #define TCC_PER_DITH4_DITHER_Pos 0 /**< \brief (TCC_PER_DITH4) Dithering Cycle Number */ 1441 #define TCC_PER_DITH4_DITHER_Msk (_U_(0xF) << TCC_PER_DITH4_DITHER_Pos) 1442 #define TCC_PER_DITH4_DITHER(value) (TCC_PER_DITH4_DITHER_Msk & ((value) << TCC_PER_DITH4_DITHER_Pos)) 1443 #define TCC_PER_DITH4_PER_Pos 4 /**< \brief (TCC_PER_DITH4) Period Value */ 1444 #define TCC_PER_DITH4_PER_Msk (_U_(0xFFFFF) << TCC_PER_DITH4_PER_Pos) 1445 #define TCC_PER_DITH4_PER(value) (TCC_PER_DITH4_PER_Msk & ((value) << TCC_PER_DITH4_PER_Pos)) 1446 #define TCC_PER_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH4) MASK Register */ 1447 1448 // DITH5 mode 1449 #define TCC_PER_DITH5_DITHER_Pos 0 /**< \brief (TCC_PER_DITH5) Dithering Cycle Number */ 1450 #define TCC_PER_DITH5_DITHER_Msk (_U_(0x1F) << TCC_PER_DITH5_DITHER_Pos) 1451 #define TCC_PER_DITH5_DITHER(value) (TCC_PER_DITH5_DITHER_Msk & ((value) << TCC_PER_DITH5_DITHER_Pos)) 1452 #define TCC_PER_DITH5_PER_Pos 5 /**< \brief (TCC_PER_DITH5) Period Value */ 1453 #define TCC_PER_DITH5_PER_Msk (_U_(0x7FFFF) << TCC_PER_DITH5_PER_Pos) 1454 #define TCC_PER_DITH5_PER(value) (TCC_PER_DITH5_PER_Msk & ((value) << TCC_PER_DITH5_PER_Pos)) 1455 #define TCC_PER_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH5) MASK Register */ 1456 1457 // DITH6 mode 1458 #define TCC_PER_DITH6_DITHER_Pos 0 /**< \brief (TCC_PER_DITH6) Dithering Cycle Number */ 1459 #define TCC_PER_DITH6_DITHER_Msk (_U_(0x3F) << TCC_PER_DITH6_DITHER_Pos) 1460 #define TCC_PER_DITH6_DITHER(value) (TCC_PER_DITH6_DITHER_Msk & ((value) << TCC_PER_DITH6_DITHER_Pos)) 1461 #define TCC_PER_DITH6_PER_Pos 6 /**< \brief (TCC_PER_DITH6) Period Value */ 1462 #define TCC_PER_DITH6_PER_Msk (_U_(0x3FFFF) << TCC_PER_DITH6_PER_Pos) 1463 #define TCC_PER_DITH6_PER(value) (TCC_PER_DITH6_PER_Msk & ((value) << TCC_PER_DITH6_PER_Pos)) 1464 #define TCC_PER_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER_DITH6) MASK Register */ 1465 1466 #define TCC_PER_PER_Pos 0 /**< \brief (TCC_PER) Period Value */ 1467 #define TCC_PER_PER_Msk (_U_(0xFFFFFF) << TCC_PER_PER_Pos) 1468 #define TCC_PER_PER(value) (TCC_PER_PER_Msk & ((value) << TCC_PER_PER_Pos)) 1469 #define TCC_PER_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PER) MASK Register */ 1470 1471 /* -------- TCC_CC : (TCC Offset: 0x44) (R/W 32) Compare and Capture -------- */ 1472 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1473 typedef union { 1474 struct { // DITH4 mode 1475 uint32_t DITHER:4; /*!< bit: 0.. 3 Dithering Cycle Number */ 1476 uint32_t CC:20; /*!< bit: 4..23 Channel Compare/Capture Value */ 1477 uint32_t :8; /*!< bit: 24..31 Reserved */ 1478 } DITH4; /*!< Structure used for DITH4 */ 1479 struct { // DITH5 mode 1480 uint32_t DITHER:5; /*!< bit: 0.. 4 Dithering Cycle Number */ 1481 uint32_t CC:19; /*!< bit: 5..23 Channel Compare/Capture Value */ 1482 uint32_t :8; /*!< bit: 24..31 Reserved */ 1483 } DITH5; /*!< Structure used for DITH5 */ 1484 struct { // DITH6 mode 1485 uint32_t DITHER:6; /*!< bit: 0.. 5 Dithering Cycle Number */ 1486 uint32_t CC:18; /*!< bit: 6..23 Channel Compare/Capture Value */ 1487 uint32_t :8; /*!< bit: 24..31 Reserved */ 1488 } DITH6; /*!< Structure used for DITH6 */ 1489 struct { 1490 uint32_t CC:24; /*!< bit: 0..23 Channel Compare/Capture Value */ 1491 uint32_t :8; /*!< bit: 24..31 Reserved */ 1492 } bit; /*!< Structure used for bit access */ 1493 uint32_t reg; /*!< Type used for register access */ 1494 } TCC_CC_Type; 1495 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1496 1497 #define TCC_CC_OFFSET 0x44 /**< \brief (TCC_CC offset) Compare and Capture */ 1498 #define TCC_CC_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CC reset_value) Compare and Capture */ 1499 1500 // DITH4 mode 1501 #define TCC_CC_DITH4_DITHER_Pos 0 /**< \brief (TCC_CC_DITH4) Dithering Cycle Number */ 1502 #define TCC_CC_DITH4_DITHER_Msk (_U_(0xF) << TCC_CC_DITH4_DITHER_Pos) 1503 #define TCC_CC_DITH4_DITHER(value) (TCC_CC_DITH4_DITHER_Msk & ((value) << TCC_CC_DITH4_DITHER_Pos)) 1504 #define TCC_CC_DITH4_CC_Pos 4 /**< \brief (TCC_CC_DITH4) Channel Compare/Capture Value */ 1505 #define TCC_CC_DITH4_CC_Msk (_U_(0xFFFFF) << TCC_CC_DITH4_CC_Pos) 1506 #define TCC_CC_DITH4_CC(value) (TCC_CC_DITH4_CC_Msk & ((value) << TCC_CC_DITH4_CC_Pos)) 1507 #define TCC_CC_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH4) MASK Register */ 1508 1509 // DITH5 mode 1510 #define TCC_CC_DITH5_DITHER_Pos 0 /**< \brief (TCC_CC_DITH5) Dithering Cycle Number */ 1511 #define TCC_CC_DITH5_DITHER_Msk (_U_(0x1F) << TCC_CC_DITH5_DITHER_Pos) 1512 #define TCC_CC_DITH5_DITHER(value) (TCC_CC_DITH5_DITHER_Msk & ((value) << TCC_CC_DITH5_DITHER_Pos)) 1513 #define TCC_CC_DITH5_CC_Pos 5 /**< \brief (TCC_CC_DITH5) Channel Compare/Capture Value */ 1514 #define TCC_CC_DITH5_CC_Msk (_U_(0x7FFFF) << TCC_CC_DITH5_CC_Pos) 1515 #define TCC_CC_DITH5_CC(value) (TCC_CC_DITH5_CC_Msk & ((value) << TCC_CC_DITH5_CC_Pos)) 1516 #define TCC_CC_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH5) MASK Register */ 1517 1518 // DITH6 mode 1519 #define TCC_CC_DITH6_DITHER_Pos 0 /**< \brief (TCC_CC_DITH6) Dithering Cycle Number */ 1520 #define TCC_CC_DITH6_DITHER_Msk (_U_(0x3F) << TCC_CC_DITH6_DITHER_Pos) 1521 #define TCC_CC_DITH6_DITHER(value) (TCC_CC_DITH6_DITHER_Msk & ((value) << TCC_CC_DITH6_DITHER_Pos)) 1522 #define TCC_CC_DITH6_CC_Pos 6 /**< \brief (TCC_CC_DITH6) Channel Compare/Capture Value */ 1523 #define TCC_CC_DITH6_CC_Msk (_U_(0x3FFFF) << TCC_CC_DITH6_CC_Pos) 1524 #define TCC_CC_DITH6_CC(value) (TCC_CC_DITH6_CC_Msk & ((value) << TCC_CC_DITH6_CC_Pos)) 1525 #define TCC_CC_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC_DITH6) MASK Register */ 1526 1527 #define TCC_CC_CC_Pos 0 /**< \brief (TCC_CC) Channel Compare/Capture Value */ 1528 #define TCC_CC_CC_Msk (_U_(0xFFFFFF) << TCC_CC_CC_Pos) 1529 #define TCC_CC_CC(value) (TCC_CC_CC_Msk & ((value) << TCC_CC_CC_Pos)) 1530 #define TCC_CC_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CC) MASK Register */ 1531 1532 /* -------- TCC_PATTBUF : (TCC Offset: 0x64) (R/W 16) Pattern Buffer -------- */ 1533 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1534 typedef union { 1535 struct { 1536 uint16_t PGEB0:1; /*!< bit: 0 Pattern Generator 0 Output Enable Buffer */ 1537 uint16_t PGEB1:1; /*!< bit: 1 Pattern Generator 1 Output Enable Buffer */ 1538 uint16_t PGEB2:1; /*!< bit: 2 Pattern Generator 2 Output Enable Buffer */ 1539 uint16_t PGEB3:1; /*!< bit: 3 Pattern Generator 3 Output Enable Buffer */ 1540 uint16_t PGEB4:1; /*!< bit: 4 Pattern Generator 4 Output Enable Buffer */ 1541 uint16_t PGEB5:1; /*!< bit: 5 Pattern Generator 5 Output Enable Buffer */ 1542 uint16_t PGEB6:1; /*!< bit: 6 Pattern Generator 6 Output Enable Buffer */ 1543 uint16_t PGEB7:1; /*!< bit: 7 Pattern Generator 7 Output Enable Buffer */ 1544 uint16_t PGVB0:1; /*!< bit: 8 Pattern Generator 0 Output Enable */ 1545 uint16_t PGVB1:1; /*!< bit: 9 Pattern Generator 1 Output Enable */ 1546 uint16_t PGVB2:1; /*!< bit: 10 Pattern Generator 2 Output Enable */ 1547 uint16_t PGVB3:1; /*!< bit: 11 Pattern Generator 3 Output Enable */ 1548 uint16_t PGVB4:1; /*!< bit: 12 Pattern Generator 4 Output Enable */ 1549 uint16_t PGVB5:1; /*!< bit: 13 Pattern Generator 5 Output Enable */ 1550 uint16_t PGVB6:1; /*!< bit: 14 Pattern Generator 6 Output Enable */ 1551 uint16_t PGVB7:1; /*!< bit: 15 Pattern Generator 7 Output Enable */ 1552 } bit; /*!< Structure used for bit access */ 1553 struct { 1554 uint16_t PGEB:8; /*!< bit: 0.. 7 Pattern Generator x Output Enable Buffer */ 1555 uint16_t PGVB:8; /*!< bit: 8..15 Pattern Generator x Output Enable */ 1556 } vec; /*!< Structure used for vec access */ 1557 uint16_t reg; /*!< Type used for register access */ 1558 } TCC_PATTBUF_Type; 1559 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1560 1561 #define TCC_PATTBUF_OFFSET 0x64 /**< \brief (TCC_PATTBUF offset) Pattern Buffer */ 1562 #define TCC_PATTBUF_RESETVALUE _U_(0x0000) /**< \brief (TCC_PATTBUF reset_value) Pattern Buffer */ 1563 1564 #define TCC_PATTBUF_PGEB0_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable Buffer */ 1565 #define TCC_PATTBUF_PGEB0 (_U_(1) << TCC_PATTBUF_PGEB0_Pos) 1566 #define TCC_PATTBUF_PGEB1_Pos 1 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable Buffer */ 1567 #define TCC_PATTBUF_PGEB1 (_U_(1) << TCC_PATTBUF_PGEB1_Pos) 1568 #define TCC_PATTBUF_PGEB2_Pos 2 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable Buffer */ 1569 #define TCC_PATTBUF_PGEB2 (_U_(1) << TCC_PATTBUF_PGEB2_Pos) 1570 #define TCC_PATTBUF_PGEB3_Pos 3 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable Buffer */ 1571 #define TCC_PATTBUF_PGEB3 (_U_(1) << TCC_PATTBUF_PGEB3_Pos) 1572 #define TCC_PATTBUF_PGEB4_Pos 4 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable Buffer */ 1573 #define TCC_PATTBUF_PGEB4 (_U_(1) << TCC_PATTBUF_PGEB4_Pos) 1574 #define TCC_PATTBUF_PGEB5_Pos 5 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable Buffer */ 1575 #define TCC_PATTBUF_PGEB5 (_U_(1) << TCC_PATTBUF_PGEB5_Pos) 1576 #define TCC_PATTBUF_PGEB6_Pos 6 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable Buffer */ 1577 #define TCC_PATTBUF_PGEB6 (_U_(1) << TCC_PATTBUF_PGEB6_Pos) 1578 #define TCC_PATTBUF_PGEB7_Pos 7 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable Buffer */ 1579 #define TCC_PATTBUF_PGEB7 (_U_(1) << TCC_PATTBUF_PGEB7_Pos) 1580 #define TCC_PATTBUF_PGEB_Pos 0 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable Buffer */ 1581 #define TCC_PATTBUF_PGEB_Msk (_U_(0xFF) << TCC_PATTBUF_PGEB_Pos) 1582 #define TCC_PATTBUF_PGEB(value) (TCC_PATTBUF_PGEB_Msk & ((value) << TCC_PATTBUF_PGEB_Pos)) 1583 #define TCC_PATTBUF_PGVB0_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator 0 Output Enable */ 1584 #define TCC_PATTBUF_PGVB0 (_U_(1) << TCC_PATTBUF_PGVB0_Pos) 1585 #define TCC_PATTBUF_PGVB1_Pos 9 /**< \brief (TCC_PATTBUF) Pattern Generator 1 Output Enable */ 1586 #define TCC_PATTBUF_PGVB1 (_U_(1) << TCC_PATTBUF_PGVB1_Pos) 1587 #define TCC_PATTBUF_PGVB2_Pos 10 /**< \brief (TCC_PATTBUF) Pattern Generator 2 Output Enable */ 1588 #define TCC_PATTBUF_PGVB2 (_U_(1) << TCC_PATTBUF_PGVB2_Pos) 1589 #define TCC_PATTBUF_PGVB3_Pos 11 /**< \brief (TCC_PATTBUF) Pattern Generator 3 Output Enable */ 1590 #define TCC_PATTBUF_PGVB3 (_U_(1) << TCC_PATTBUF_PGVB3_Pos) 1591 #define TCC_PATTBUF_PGVB4_Pos 12 /**< \brief (TCC_PATTBUF) Pattern Generator 4 Output Enable */ 1592 #define TCC_PATTBUF_PGVB4 (_U_(1) << TCC_PATTBUF_PGVB4_Pos) 1593 #define TCC_PATTBUF_PGVB5_Pos 13 /**< \brief (TCC_PATTBUF) Pattern Generator 5 Output Enable */ 1594 #define TCC_PATTBUF_PGVB5 (_U_(1) << TCC_PATTBUF_PGVB5_Pos) 1595 #define TCC_PATTBUF_PGVB6_Pos 14 /**< \brief (TCC_PATTBUF) Pattern Generator 6 Output Enable */ 1596 #define TCC_PATTBUF_PGVB6 (_U_(1) << TCC_PATTBUF_PGVB6_Pos) 1597 #define TCC_PATTBUF_PGVB7_Pos 15 /**< \brief (TCC_PATTBUF) Pattern Generator 7 Output Enable */ 1598 #define TCC_PATTBUF_PGVB7 (_U_(1) << TCC_PATTBUF_PGVB7_Pos) 1599 #define TCC_PATTBUF_PGVB_Pos 8 /**< \brief (TCC_PATTBUF) Pattern Generator x Output Enable */ 1600 #define TCC_PATTBUF_PGVB_Msk (_U_(0xFF) << TCC_PATTBUF_PGVB_Pos) 1601 #define TCC_PATTBUF_PGVB(value) (TCC_PATTBUF_PGVB_Msk & ((value) << TCC_PATTBUF_PGVB_Pos)) 1602 #define TCC_PATTBUF_MASK _U_(0xFFFF) /**< \brief (TCC_PATTBUF) MASK Register */ 1603 1604 /* -------- TCC_PERBUF : (TCC Offset: 0x6C) (R/W 32) Period Buffer -------- */ 1605 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1606 typedef union { 1607 struct { // DITH4 mode 1608 uint32_t DITHERBUF:4; /*!< bit: 0.. 3 Dithering Buffer Cycle Number */ 1609 uint32_t PERBUF:20; /*!< bit: 4..23 Period Buffer Value */ 1610 uint32_t :8; /*!< bit: 24..31 Reserved */ 1611 } DITH4; /*!< Structure used for DITH4 */ 1612 struct { // DITH5 mode 1613 uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ 1614 uint32_t PERBUF:19; /*!< bit: 5..23 Period Buffer Value */ 1615 uint32_t :8; /*!< bit: 24..31 Reserved */ 1616 } DITH5; /*!< Structure used for DITH5 */ 1617 struct { // DITH6 mode 1618 uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ 1619 uint32_t PERBUF:18; /*!< bit: 6..23 Period Buffer Value */ 1620 uint32_t :8; /*!< bit: 24..31 Reserved */ 1621 } DITH6; /*!< Structure used for DITH6 */ 1622 struct { 1623 uint32_t PERBUF:24; /*!< bit: 0..23 Period Buffer Value */ 1624 uint32_t :8; /*!< bit: 24..31 Reserved */ 1625 } bit; /*!< Structure used for bit access */ 1626 uint32_t reg; /*!< Type used for register access */ 1627 } TCC_PERBUF_Type; 1628 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1629 1630 #define TCC_PERBUF_OFFSET 0x6C /**< \brief (TCC_PERBUF offset) Period Buffer */ 1631 #define TCC_PERBUF_RESETVALUE _U_(0xFFFFFFFF) /**< \brief (TCC_PERBUF reset_value) Period Buffer */ 1632 1633 // DITH4 mode 1634 #define TCC_PERBUF_DITH4_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH4) Dithering Buffer Cycle Number */ 1635 #define TCC_PERBUF_DITH4_DITHERBUF_Msk (_U_(0xF) << TCC_PERBUF_DITH4_DITHERBUF_Pos) 1636 #define TCC_PERBUF_DITH4_DITHERBUF(value) (TCC_PERBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH4_DITHERBUF_Pos)) 1637 #define TCC_PERBUF_DITH4_PERBUF_Pos 4 /**< \brief (TCC_PERBUF_DITH4) Period Buffer Value */ 1638 #define TCC_PERBUF_DITH4_PERBUF_Msk (_U_(0xFFFFF) << TCC_PERBUF_DITH4_PERBUF_Pos) 1639 #define TCC_PERBUF_DITH4_PERBUF(value) (TCC_PERBUF_DITH4_PERBUF_Msk & ((value) << TCC_PERBUF_DITH4_PERBUF_Pos)) 1640 #define TCC_PERBUF_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH4) MASK Register */ 1641 1642 // DITH5 mode 1643 #define TCC_PERBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH5) Dithering Buffer Cycle Number */ 1644 #define TCC_PERBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_PERBUF_DITH5_DITHERBUF_Pos) 1645 #define TCC_PERBUF_DITH5_DITHERBUF(value) (TCC_PERBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH5_DITHERBUF_Pos)) 1646 #define TCC_PERBUF_DITH5_PERBUF_Pos 5 /**< \brief (TCC_PERBUF_DITH5) Period Buffer Value */ 1647 #define TCC_PERBUF_DITH5_PERBUF_Msk (_U_(0x7FFFF) << TCC_PERBUF_DITH5_PERBUF_Pos) 1648 #define TCC_PERBUF_DITH5_PERBUF(value) (TCC_PERBUF_DITH5_PERBUF_Msk & ((value) << TCC_PERBUF_DITH5_PERBUF_Pos)) 1649 #define TCC_PERBUF_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH5) MASK Register */ 1650 1651 // DITH6 mode 1652 #define TCC_PERBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_PERBUF_DITH6) Dithering Buffer Cycle Number */ 1653 #define TCC_PERBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_PERBUF_DITH6_DITHERBUF_Pos) 1654 #define TCC_PERBUF_DITH6_DITHERBUF(value) (TCC_PERBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_PERBUF_DITH6_DITHERBUF_Pos)) 1655 #define TCC_PERBUF_DITH6_PERBUF_Pos 6 /**< \brief (TCC_PERBUF_DITH6) Period Buffer Value */ 1656 #define TCC_PERBUF_DITH6_PERBUF_Msk (_U_(0x3FFFF) << TCC_PERBUF_DITH6_PERBUF_Pos) 1657 #define TCC_PERBUF_DITH6_PERBUF(value) (TCC_PERBUF_DITH6_PERBUF_Msk & ((value) << TCC_PERBUF_DITH6_PERBUF_Pos)) 1658 #define TCC_PERBUF_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF_DITH6) MASK Register */ 1659 1660 #define TCC_PERBUF_PERBUF_Pos 0 /**< \brief (TCC_PERBUF) Period Buffer Value */ 1661 #define TCC_PERBUF_PERBUF_Msk (_U_(0xFFFFFF) << TCC_PERBUF_PERBUF_Pos) 1662 #define TCC_PERBUF_PERBUF(value) (TCC_PERBUF_PERBUF_Msk & ((value) << TCC_PERBUF_PERBUF_Pos)) 1663 #define TCC_PERBUF_MASK _U_(0x00FFFFFF) /**< \brief (TCC_PERBUF) MASK Register */ 1664 1665 /* -------- TCC_CCBUF : (TCC Offset: 0x70) (R/W 32) Compare and Capture Buffer -------- */ 1666 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1667 typedef union { 1668 struct { // DITH4 mode 1669 uint32_t CCBUF:4; /*!< bit: 0.. 3 Channel Compare/Capture Buffer Value */ 1670 uint32_t DITHERBUF:20; /*!< bit: 4..23 Dithering Buffer Cycle Number */ 1671 uint32_t :8; /*!< bit: 24..31 Reserved */ 1672 } DITH4; /*!< Structure used for DITH4 */ 1673 struct { // DITH5 mode 1674 uint32_t DITHERBUF:5; /*!< bit: 0.. 4 Dithering Buffer Cycle Number */ 1675 uint32_t CCBUF:19; /*!< bit: 5..23 Channel Compare/Capture Buffer Value */ 1676 uint32_t :8; /*!< bit: 24..31 Reserved */ 1677 } DITH5; /*!< Structure used for DITH5 */ 1678 struct { // DITH6 mode 1679 uint32_t DITHERBUF:6; /*!< bit: 0.. 5 Dithering Buffer Cycle Number */ 1680 uint32_t CCBUF:18; /*!< bit: 6..23 Channel Compare/Capture Buffer Value */ 1681 uint32_t :8; /*!< bit: 24..31 Reserved */ 1682 } DITH6; /*!< Structure used for DITH6 */ 1683 struct { 1684 uint32_t CCBUF:24; /*!< bit: 0..23 Channel Compare/Capture Buffer Value */ 1685 uint32_t :8; /*!< bit: 24..31 Reserved */ 1686 } bit; /*!< Structure used for bit access */ 1687 uint32_t reg; /*!< Type used for register access */ 1688 } TCC_CCBUF_Type; 1689 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1690 1691 #define TCC_CCBUF_OFFSET 0x70 /**< \brief (TCC_CCBUF offset) Compare and Capture Buffer */ 1692 #define TCC_CCBUF_RESETVALUE _U_(0x00000000) /**< \brief (TCC_CCBUF reset_value) Compare and Capture Buffer */ 1693 1694 // DITH4 mode 1695 #define TCC_CCBUF_DITH4_CCBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH4) Channel Compare/Capture Buffer Value */ 1696 #define TCC_CCBUF_DITH4_CCBUF_Msk (_U_(0xF) << TCC_CCBUF_DITH4_CCBUF_Pos) 1697 #define TCC_CCBUF_DITH4_CCBUF(value) (TCC_CCBUF_DITH4_CCBUF_Msk & ((value) << TCC_CCBUF_DITH4_CCBUF_Pos)) 1698 #define TCC_CCBUF_DITH4_DITHERBUF_Pos 4 /**< \brief (TCC_CCBUF_DITH4) Dithering Buffer Cycle Number */ 1699 #define TCC_CCBUF_DITH4_DITHERBUF_Msk (_U_(0xFFFFF) << TCC_CCBUF_DITH4_DITHERBUF_Pos) 1700 #define TCC_CCBUF_DITH4_DITHERBUF(value) (TCC_CCBUF_DITH4_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH4_DITHERBUF_Pos)) 1701 #define TCC_CCBUF_DITH4_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH4) MASK Register */ 1702 1703 // DITH5 mode 1704 #define TCC_CCBUF_DITH5_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH5) Dithering Buffer Cycle Number */ 1705 #define TCC_CCBUF_DITH5_DITHERBUF_Msk (_U_(0x1F) << TCC_CCBUF_DITH5_DITHERBUF_Pos) 1706 #define TCC_CCBUF_DITH5_DITHERBUF(value) (TCC_CCBUF_DITH5_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH5_DITHERBUF_Pos)) 1707 #define TCC_CCBUF_DITH5_CCBUF_Pos 5 /**< \brief (TCC_CCBUF_DITH5) Channel Compare/Capture Buffer Value */ 1708 #define TCC_CCBUF_DITH5_CCBUF_Msk (_U_(0x7FFFF) << TCC_CCBUF_DITH5_CCBUF_Pos) 1709 #define TCC_CCBUF_DITH5_CCBUF(value) (TCC_CCBUF_DITH5_CCBUF_Msk & ((value) << TCC_CCBUF_DITH5_CCBUF_Pos)) 1710 #define TCC_CCBUF_DITH5_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH5) MASK Register */ 1711 1712 // DITH6 mode 1713 #define TCC_CCBUF_DITH6_DITHERBUF_Pos 0 /**< \brief (TCC_CCBUF_DITH6) Dithering Buffer Cycle Number */ 1714 #define TCC_CCBUF_DITH6_DITHERBUF_Msk (_U_(0x3F) << TCC_CCBUF_DITH6_DITHERBUF_Pos) 1715 #define TCC_CCBUF_DITH6_DITHERBUF(value) (TCC_CCBUF_DITH6_DITHERBUF_Msk & ((value) << TCC_CCBUF_DITH6_DITHERBUF_Pos)) 1716 #define TCC_CCBUF_DITH6_CCBUF_Pos 6 /**< \brief (TCC_CCBUF_DITH6) Channel Compare/Capture Buffer Value */ 1717 #define TCC_CCBUF_DITH6_CCBUF_Msk (_U_(0x3FFFF) << TCC_CCBUF_DITH6_CCBUF_Pos) 1718 #define TCC_CCBUF_DITH6_CCBUF(value) (TCC_CCBUF_DITH6_CCBUF_Msk & ((value) << TCC_CCBUF_DITH6_CCBUF_Pos)) 1719 #define TCC_CCBUF_DITH6_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF_DITH6) MASK Register */ 1720 1721 #define TCC_CCBUF_CCBUF_Pos 0 /**< \brief (TCC_CCBUF) Channel Compare/Capture Buffer Value */ 1722 #define TCC_CCBUF_CCBUF_Msk (_U_(0xFFFFFF) << TCC_CCBUF_CCBUF_Pos) 1723 #define TCC_CCBUF_CCBUF(value) (TCC_CCBUF_CCBUF_Msk & ((value) << TCC_CCBUF_CCBUF_Pos)) 1724 #define TCC_CCBUF_MASK _U_(0x00FFFFFF) /**< \brief (TCC_CCBUF) MASK Register */ 1725 1726 /** \brief TCC hardware registers */ 1727 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1728 typedef struct { 1729 __IO TCC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 1730 __IO TCC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 1731 __IO TCC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 1732 RoReg8 Reserved1[0x2]; 1733 __I TCC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ 1734 __IO TCC_FCTRLA_Type FCTRLA; /**< \brief Offset: 0x0C (R/W 32) Recoverable Fault A Configuration */ 1735 __IO TCC_FCTRLB_Type FCTRLB; /**< \brief Offset: 0x10 (R/W 32) Recoverable Fault B Configuration */ 1736 __IO TCC_WEXCTRL_Type WEXCTRL; /**< \brief Offset: 0x14 (R/W 32) Waveform Extension Configuration */ 1737 __IO TCC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x18 (R/W 32) Driver Control */ 1738 RoReg8 Reserved2[0x2]; 1739 __IO TCC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x1E (R/W 8) Debug Control */ 1740 RoReg8 Reserved3[0x1]; 1741 __IO TCC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x20 (R/W 32) Event Control */ 1742 __IO TCC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x24 (R/W 32) Interrupt Enable Clear */ 1743 __IO TCC_INTENSET_Type INTENSET; /**< \brief Offset: 0x28 (R/W 32) Interrupt Enable Set */ 1744 __IO TCC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear */ 1745 __IO TCC_STATUS_Type STATUS; /**< \brief Offset: 0x30 (R/W 32) Status */ 1746 __IO TCC_COUNT_Type COUNT; /**< \brief Offset: 0x34 (R/W 32) Count */ 1747 __IO TCC_PATT_Type PATT; /**< \brief Offset: 0x38 (R/W 16) Pattern */ 1748 RoReg8 Reserved4[0x2]; 1749 __IO TCC_WAVE_Type WAVE; /**< \brief Offset: 0x3C (R/W 32) Waveform Control */ 1750 __IO TCC_PER_Type PER; /**< \brief Offset: 0x40 (R/W 32) Period */ 1751 __IO TCC_CC_Type CC[6]; /**< \brief Offset: 0x44 (R/W 32) Compare and Capture */ 1752 RoReg8 Reserved5[0x8]; 1753 __IO TCC_PATTBUF_Type PATTBUF; /**< \brief Offset: 0x64 (R/W 16) Pattern Buffer */ 1754 RoReg8 Reserved6[0x6]; 1755 __IO TCC_PERBUF_Type PERBUF; /**< \brief Offset: 0x6C (R/W 32) Period Buffer */ 1756 __IO TCC_CCBUF_Type CCBUF[6]; /**< \brief Offset: 0x70 (R/W 32) Compare and Capture Buffer */ 1757 } Tcc; 1758 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1759 1760 /*@}*/ 1761 1762 #endif /* _SAME53_TCC_COMPONENT_ */ 1763
