1 /** 2 * \file 3 * 4 * \brief Component description for OSCCTRL 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD51_OSCCTRL_COMPONENT_ 31 #define _SAMD51_OSCCTRL_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR OSCCTRL */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMD51_OSCCTRL Oscillators Control */ 37 /*@{*/ 38 39 #define OSCCTRL_U2401 40 #define REV_OSCCTRL 0x100 41 42 /* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t CFDEO0:1; /*!< bit: 0 Clock 0 Failure Detector Event Output Enable */ 47 uint8_t CFDEO1:1; /*!< bit: 1 Clock 1 Failure Detector Event Output Enable */ 48 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 struct { 51 uint8_t CFDEO:2; /*!< bit: 0.. 1 Clock x Failure Detector Event Output Enable */ 52 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 53 } vec; /*!< Structure used for vec access */ 54 uint8_t reg; /*!< Type used for register access */ 55 } OSCCTRL_EVCTRL_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 #define OSCCTRL_EVCTRL_OFFSET 0x00 /**< \brief (OSCCTRL_EVCTRL offset) Event Control */ 59 #define OSCCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_EVCTRL reset_value) Event Control */ 60 61 #define OSCCTRL_EVCTRL_CFDEO0_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock 0 Failure Detector Event Output Enable */ 62 #define OSCCTRL_EVCTRL_CFDEO0 (_U_(1) << OSCCTRL_EVCTRL_CFDEO0_Pos) 63 #define OSCCTRL_EVCTRL_CFDEO1_Pos 1 /**< \brief (OSCCTRL_EVCTRL) Clock 1 Failure Detector Event Output Enable */ 64 #define OSCCTRL_EVCTRL_CFDEO1 (_U_(1) << OSCCTRL_EVCTRL_CFDEO1_Pos) 65 #define OSCCTRL_EVCTRL_CFDEO_Pos 0 /**< \brief (OSCCTRL_EVCTRL) Clock x Failure Detector Event Output Enable */ 66 #define OSCCTRL_EVCTRL_CFDEO_Msk (_U_(0x3) << OSCCTRL_EVCTRL_CFDEO_Pos) 67 #define OSCCTRL_EVCTRL_CFDEO(value) (OSCCTRL_EVCTRL_CFDEO_Msk & ((value) << OSCCTRL_EVCTRL_CFDEO_Pos)) 68 #define OSCCTRL_EVCTRL_MASK _U_(0x03) /**< \brief (OSCCTRL_EVCTRL) MASK Register */ 69 70 /* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */ 71 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 72 typedef union { 73 struct { 74 uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */ 75 uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */ 76 uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */ 77 uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */ 78 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 79 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ 80 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ 81 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ 82 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ 83 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ 84 uint32_t :3; /*!< bit: 13..15 Reserved */ 85 uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */ 86 uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */ 87 uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */ 88 uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */ 89 uint32_t :4; /*!< bit: 20..23 Reserved */ 90 uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */ 91 uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */ 92 uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */ 93 uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */ 94 uint32_t :4; /*!< bit: 28..31 Reserved */ 95 } bit; /*!< Structure used for bit access */ 96 struct { 97 uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */ 98 uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */ 99 uint32_t :28; /*!< bit: 4..31 Reserved */ 100 } vec; /*!< Structure used for vec access */ 101 uint32_t reg; /*!< Type used for register access */ 102 } OSCCTRL_INTENCLR_Type; 103 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #define OSCCTRL_INTENCLR_OFFSET 0x04 /**< \brief (OSCCTRL_INTENCLR offset) Interrupt Enable Clear */ 106 #define OSCCTRL_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENCLR reset_value) Interrupt Enable Clear */ 107 108 #define OSCCTRL_INTENCLR_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Ready Interrupt Enable */ 109 #define OSCCTRL_INTENCLR_XOSCRDY0 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY0_Pos) 110 #define OSCCTRL_INTENCLR_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Ready Interrupt Enable */ 111 #define OSCCTRL_INTENCLR_XOSCRDY1 (_U_(1) << OSCCTRL_INTENCLR_XOSCRDY1_Pos) 112 #define OSCCTRL_INTENCLR_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENCLR) XOSC x Ready Interrupt Enable */ 113 #define OSCCTRL_INTENCLR_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCRDY_Pos) 114 #define OSCCTRL_INTENCLR_XOSCRDY(value) (OSCCTRL_INTENCLR_XOSCRDY_Msk & ((value) << OSCCTRL_INTENCLR_XOSCRDY_Pos)) 115 #define OSCCTRL_INTENCLR_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC 0 Clock Failure Detector Interrupt Enable */ 116 #define OSCCTRL_INTENCLR_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL0_Pos) 117 #define OSCCTRL_INTENCLR_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENCLR) XOSC 1 Clock Failure Detector Interrupt Enable */ 118 #define OSCCTRL_INTENCLR_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENCLR_XOSCFAIL1_Pos) 119 #define OSCCTRL_INTENCLR_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENCLR) XOSC x Clock Failure Detector Interrupt Enable */ 120 #define OSCCTRL_INTENCLR_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENCLR_XOSCFAIL_Pos) 121 #define OSCCTRL_INTENCLR_XOSCFAIL(value) (OSCCTRL_INTENCLR_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENCLR_XOSCFAIL_Pos)) 122 #define OSCCTRL_INTENCLR_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENCLR) DFLL Ready Interrupt Enable */ 123 #define OSCCTRL_INTENCLR_DFLLRDY (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRDY_Pos) 124 #define OSCCTRL_INTENCLR_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENCLR) DFLL Out Of Bounds Interrupt Enable */ 125 #define OSCCTRL_INTENCLR_DFLLOOB (_U_(0x1) << OSCCTRL_INTENCLR_DFLLOOB_Pos) 126 #define OSCCTRL_INTENCLR_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Fine Interrupt Enable */ 127 #define OSCCTRL_INTENCLR_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKF_Pos) 128 #define OSCCTRL_INTENCLR_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENCLR) DFLL Lock Coarse Interrupt Enable */ 129 #define OSCCTRL_INTENCLR_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENCLR_DFLLLCKC_Pos) 130 #define OSCCTRL_INTENCLR_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENCLR) DFLL Reference Clock Stopped Interrupt Enable */ 131 #define OSCCTRL_INTENCLR_DFLLRCS (_U_(0x1) << OSCCTRL_INTENCLR_DFLLRCS_Pos) 132 #define OSCCTRL_INTENCLR_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Rise Interrupt Enable */ 133 #define OSCCTRL_INTENCLR_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKR_Pos) 134 #define OSCCTRL_INTENCLR_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Fall Interrupt Enable */ 135 #define OSCCTRL_INTENCLR_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LCKF_Pos) 136 #define OSCCTRL_INTENCLR_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Lock Timeout Interrupt Enable */ 137 #define OSCCTRL_INTENCLR_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LTO_Pos) 138 #define OSCCTRL_INTENCLR_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENCLR) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */ 139 #define OSCCTRL_INTENCLR_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL0LDRTO_Pos) 140 #define OSCCTRL_INTENCLR_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Rise Interrupt Enable */ 141 #define OSCCTRL_INTENCLR_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKR_Pos) 142 #define OSCCTRL_INTENCLR_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Fall Interrupt Enable */ 143 #define OSCCTRL_INTENCLR_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LCKF_Pos) 144 #define OSCCTRL_INTENCLR_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Lock Timeout Interrupt Enable */ 145 #define OSCCTRL_INTENCLR_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LTO_Pos) 146 #define OSCCTRL_INTENCLR_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENCLR) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */ 147 #define OSCCTRL_INTENCLR_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENCLR_DPLL1LDRTO_Pos) 148 #define OSCCTRL_INTENCLR_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENCLR) MASK Register */ 149 150 /* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */ 151 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 152 typedef union { 153 struct { 154 uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */ 155 uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */ 156 uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */ 157 uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */ 158 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 159 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ 160 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ 161 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ 162 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ 163 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ 164 uint32_t :3; /*!< bit: 13..15 Reserved */ 165 uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */ 166 uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */ 167 uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */ 168 uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */ 169 uint32_t :4; /*!< bit: 20..23 Reserved */ 170 uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */ 171 uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */ 172 uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */ 173 uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */ 174 uint32_t :4; /*!< bit: 28..31 Reserved */ 175 } bit; /*!< Structure used for bit access */ 176 struct { 177 uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */ 178 uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */ 179 uint32_t :28; /*!< bit: 4..31 Reserved */ 180 } vec; /*!< Structure used for vec access */ 181 uint32_t reg; /*!< Type used for register access */ 182 } OSCCTRL_INTENSET_Type; 183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 184 185 #define OSCCTRL_INTENSET_OFFSET 0x08 /**< \brief (OSCCTRL_INTENSET offset) Interrupt Enable Set */ 186 #define OSCCTRL_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTENSET reset_value) Interrupt Enable Set */ 187 188 #define OSCCTRL_INTENSET_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Ready Interrupt Enable */ 189 #define OSCCTRL_INTENSET_XOSCRDY0 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY0_Pos) 190 #define OSCCTRL_INTENSET_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Ready Interrupt Enable */ 191 #define OSCCTRL_INTENSET_XOSCRDY1 (_U_(1) << OSCCTRL_INTENSET_XOSCRDY1_Pos) 192 #define OSCCTRL_INTENSET_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTENSET) XOSC x Ready Interrupt Enable */ 193 #define OSCCTRL_INTENSET_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCRDY_Pos) 194 #define OSCCTRL_INTENSET_XOSCRDY(value) (OSCCTRL_INTENSET_XOSCRDY_Msk & ((value) << OSCCTRL_INTENSET_XOSCRDY_Pos)) 195 #define OSCCTRL_INTENSET_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC 0 Clock Failure Detector Interrupt Enable */ 196 #define OSCCTRL_INTENSET_XOSCFAIL0 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL0_Pos) 197 #define OSCCTRL_INTENSET_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTENSET) XOSC 1 Clock Failure Detector Interrupt Enable */ 198 #define OSCCTRL_INTENSET_XOSCFAIL1 (_U_(1) << OSCCTRL_INTENSET_XOSCFAIL1_Pos) 199 #define OSCCTRL_INTENSET_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTENSET) XOSC x Clock Failure Detector Interrupt Enable */ 200 #define OSCCTRL_INTENSET_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTENSET_XOSCFAIL_Pos) 201 #define OSCCTRL_INTENSET_XOSCFAIL(value) (OSCCTRL_INTENSET_XOSCFAIL_Msk & ((value) << OSCCTRL_INTENSET_XOSCFAIL_Pos)) 202 #define OSCCTRL_INTENSET_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTENSET) DFLL Ready Interrupt Enable */ 203 #define OSCCTRL_INTENSET_DFLLRDY (_U_(0x1) << OSCCTRL_INTENSET_DFLLRDY_Pos) 204 #define OSCCTRL_INTENSET_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTENSET) DFLL Out Of Bounds Interrupt Enable */ 205 #define OSCCTRL_INTENSET_DFLLOOB (_U_(0x1) << OSCCTRL_INTENSET_DFLLOOB_Pos) 206 #define OSCCTRL_INTENSET_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Fine Interrupt Enable */ 207 #define OSCCTRL_INTENSET_DFLLLCKF (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKF_Pos) 208 #define OSCCTRL_INTENSET_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTENSET) DFLL Lock Coarse Interrupt Enable */ 209 #define OSCCTRL_INTENSET_DFLLLCKC (_U_(0x1) << OSCCTRL_INTENSET_DFLLLCKC_Pos) 210 #define OSCCTRL_INTENSET_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTENSET) DFLL Reference Clock Stopped Interrupt Enable */ 211 #define OSCCTRL_INTENSET_DFLLRCS (_U_(0x1) << OSCCTRL_INTENSET_DFLLRCS_Pos) 212 #define OSCCTRL_INTENSET_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Rise Interrupt Enable */ 213 #define OSCCTRL_INTENSET_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKR_Pos) 214 #define OSCCTRL_INTENSET_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Fall Interrupt Enable */ 215 #define OSCCTRL_INTENSET_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LCKF_Pos) 216 #define OSCCTRL_INTENSET_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTENSET) DPLL0 Lock Timeout Interrupt Enable */ 217 #define OSCCTRL_INTENSET_DPLL0LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LTO_Pos) 218 #define OSCCTRL_INTENSET_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTENSET) DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */ 219 #define OSCCTRL_INTENSET_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL0LDRTO_Pos) 220 #define OSCCTRL_INTENSET_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Rise Interrupt Enable */ 221 #define OSCCTRL_INTENSET_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKR_Pos) 222 #define OSCCTRL_INTENSET_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Fall Interrupt Enable */ 223 #define OSCCTRL_INTENSET_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LCKF_Pos) 224 #define OSCCTRL_INTENSET_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTENSET) DPLL1 Lock Timeout Interrupt Enable */ 225 #define OSCCTRL_INTENSET_DPLL1LTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LTO_Pos) 226 #define OSCCTRL_INTENSET_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTENSET) DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */ 227 #define OSCCTRL_INTENSET_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTENSET_DPLL1LDRTO_Pos) 228 #define OSCCTRL_INTENSET_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTENSET) MASK Register */ 229 230 /* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */ 231 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 232 typedef union { // __I to avoid read-modify-write on write-to-clear register 233 struct { 234 __I uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */ 235 __I uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */ 236 __I uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */ 237 __I uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */ 238 __I uint32_t :4; /*!< bit: 4.. 7 Reserved */ 239 __I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ 240 __I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ 241 __I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ 242 __I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ 243 __I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ 244 __I uint32_t :3; /*!< bit: 13..15 Reserved */ 245 __I uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */ 246 __I uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */ 247 __I uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout */ 248 __I uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */ 249 __I uint32_t :4; /*!< bit: 20..23 Reserved */ 250 __I uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */ 251 __I uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */ 252 __I uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout */ 253 __I uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */ 254 __I uint32_t :4; /*!< bit: 28..31 Reserved */ 255 } bit; /*!< Structure used for bit access */ 256 struct { 257 __I uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */ 258 __I uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */ 259 __I uint32_t :28; /*!< bit: 4..31 Reserved */ 260 } vec; /*!< Structure used for vec access */ 261 uint32_t reg; /*!< Type used for register access */ 262 } OSCCTRL_INTFLAG_Type; 263 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 264 265 #define OSCCTRL_INTFLAG_OFFSET 0x0C /**< \brief (OSCCTRL_INTFLAG offset) Interrupt Flag Status and Clear */ 266 #define OSCCTRL_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_INTFLAG reset_value) Interrupt Flag Status and Clear */ 267 268 #define OSCCTRL_INTFLAG_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Ready */ 269 #define OSCCTRL_INTFLAG_XOSCRDY0 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY0_Pos) 270 #define OSCCTRL_INTFLAG_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Ready */ 271 #define OSCCTRL_INTFLAG_XOSCRDY1 (_U_(1) << OSCCTRL_INTFLAG_XOSCRDY1_Pos) 272 #define OSCCTRL_INTFLAG_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_INTFLAG) XOSC x Ready */ 273 #define OSCCTRL_INTFLAG_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCRDY_Pos) 274 #define OSCCTRL_INTFLAG_XOSCRDY(value) (OSCCTRL_INTFLAG_XOSCRDY_Msk & ((value) << OSCCTRL_INTFLAG_XOSCRDY_Pos)) 275 #define OSCCTRL_INTFLAG_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC 0 Clock Failure Detector */ 276 #define OSCCTRL_INTFLAG_XOSCFAIL0 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL0_Pos) 277 #define OSCCTRL_INTFLAG_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_INTFLAG) XOSC 1 Clock Failure Detector */ 278 #define OSCCTRL_INTFLAG_XOSCFAIL1 (_U_(1) << OSCCTRL_INTFLAG_XOSCFAIL1_Pos) 279 #define OSCCTRL_INTFLAG_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_INTFLAG) XOSC x Clock Failure Detector */ 280 #define OSCCTRL_INTFLAG_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_INTFLAG_XOSCFAIL_Pos) 281 #define OSCCTRL_INTFLAG_XOSCFAIL(value) (OSCCTRL_INTFLAG_XOSCFAIL_Msk & ((value) << OSCCTRL_INTFLAG_XOSCFAIL_Pos)) 282 #define OSCCTRL_INTFLAG_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_INTFLAG) DFLL Ready */ 283 #define OSCCTRL_INTFLAG_DFLLRDY (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRDY_Pos) 284 #define OSCCTRL_INTFLAG_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_INTFLAG) DFLL Out Of Bounds */ 285 #define OSCCTRL_INTFLAG_DFLLOOB (_U_(0x1) << OSCCTRL_INTFLAG_DFLLOOB_Pos) 286 #define OSCCTRL_INTFLAG_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Fine */ 287 #define OSCCTRL_INTFLAG_DFLLLCKF (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKF_Pos) 288 #define OSCCTRL_INTFLAG_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_INTFLAG) DFLL Lock Coarse */ 289 #define OSCCTRL_INTFLAG_DFLLLCKC (_U_(0x1) << OSCCTRL_INTFLAG_DFLLLCKC_Pos) 290 #define OSCCTRL_INTFLAG_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_INTFLAG) DFLL Reference Clock Stopped */ 291 #define OSCCTRL_INTFLAG_DFLLRCS (_U_(0x1) << OSCCTRL_INTFLAG_DFLLRCS_Pos) 292 #define OSCCTRL_INTFLAG_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Rise */ 293 #define OSCCTRL_INTFLAG_DPLL0LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKR_Pos) 294 #define OSCCTRL_INTFLAG_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Fall */ 295 #define OSCCTRL_INTFLAG_DPLL0LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LCKF_Pos) 296 #define OSCCTRL_INTFLAG_DPLL0LTO_Pos 18 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Lock Timeout */ 297 #define OSCCTRL_INTFLAG_DPLL0LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LTO_Pos) 298 #define OSCCTRL_INTFLAG_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_INTFLAG) DPLL0 Loop Divider Ratio Update Complete */ 299 #define OSCCTRL_INTFLAG_DPLL0LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL0LDRTO_Pos) 300 #define OSCCTRL_INTFLAG_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Rise */ 301 #define OSCCTRL_INTFLAG_DPLL1LCKR (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKR_Pos) 302 #define OSCCTRL_INTFLAG_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Fall */ 303 #define OSCCTRL_INTFLAG_DPLL1LCKF (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LCKF_Pos) 304 #define OSCCTRL_INTFLAG_DPLL1LTO_Pos 26 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Lock Timeout */ 305 #define OSCCTRL_INTFLAG_DPLL1LTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LTO_Pos) 306 #define OSCCTRL_INTFLAG_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_INTFLAG) DPLL1 Loop Divider Ratio Update Complete */ 307 #define OSCCTRL_INTFLAG_DPLL1LDRTO (_U_(0x1) << OSCCTRL_INTFLAG_DPLL1LDRTO_Pos) 308 #define OSCCTRL_INTFLAG_MASK _U_(0x0F0F1F0F) /**< \brief (OSCCTRL_INTFLAG) MASK Register */ 309 310 /* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) (R/ 32) Status -------- */ 311 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 312 typedef union { 313 struct { 314 uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */ 315 uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */ 316 uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */ 317 uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */ 318 uint32_t XOSCCKSW0:1; /*!< bit: 4 XOSC 0 Clock Switch */ 319 uint32_t XOSCCKSW1:1; /*!< bit: 5 XOSC 1 Clock Switch */ 320 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 321 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ 322 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ 323 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ 324 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ 325 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ 326 uint32_t :3; /*!< bit: 13..15 Reserved */ 327 uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */ 328 uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */ 329 uint32_t DPLL0TO:1; /*!< bit: 18 DPLL0 Timeout */ 330 uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */ 331 uint32_t :4; /*!< bit: 20..23 Reserved */ 332 uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */ 333 uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */ 334 uint32_t DPLL1TO:1; /*!< bit: 26 DPLL1 Timeout */ 335 uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */ 336 uint32_t :4; /*!< bit: 28..31 Reserved */ 337 } bit; /*!< Structure used for bit access */ 338 struct { 339 uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */ 340 uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */ 341 uint32_t XOSCCKSW:2; /*!< bit: 4.. 5 XOSC x Clock Switch */ 342 uint32_t :26; /*!< bit: 6..31 Reserved */ 343 } vec; /*!< Structure used for vec access */ 344 uint32_t reg; /*!< Type used for register access */ 345 } OSCCTRL_STATUS_Type; 346 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 347 348 #define OSCCTRL_STATUS_OFFSET 0x10 /**< \brief (OSCCTRL_STATUS offset) Status */ 349 #define OSCCTRL_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_STATUS reset_value) Status */ 350 351 #define OSCCTRL_STATUS_XOSCRDY0_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC 0 Ready */ 352 #define OSCCTRL_STATUS_XOSCRDY0 (_U_(1) << OSCCTRL_STATUS_XOSCRDY0_Pos) 353 #define OSCCTRL_STATUS_XOSCRDY1_Pos 1 /**< \brief (OSCCTRL_STATUS) XOSC 1 Ready */ 354 #define OSCCTRL_STATUS_XOSCRDY1 (_U_(1) << OSCCTRL_STATUS_XOSCRDY1_Pos) 355 #define OSCCTRL_STATUS_XOSCRDY_Pos 0 /**< \brief (OSCCTRL_STATUS) XOSC x Ready */ 356 #define OSCCTRL_STATUS_XOSCRDY_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCRDY_Pos) 357 #define OSCCTRL_STATUS_XOSCRDY(value) (OSCCTRL_STATUS_XOSCRDY_Msk & ((value) << OSCCTRL_STATUS_XOSCRDY_Pos)) 358 #define OSCCTRL_STATUS_XOSCFAIL0_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Failure Detector */ 359 #define OSCCTRL_STATUS_XOSCFAIL0 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL0_Pos) 360 #define OSCCTRL_STATUS_XOSCFAIL1_Pos 3 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Failure Detector */ 361 #define OSCCTRL_STATUS_XOSCFAIL1 (_U_(1) << OSCCTRL_STATUS_XOSCFAIL1_Pos) 362 #define OSCCTRL_STATUS_XOSCFAIL_Pos 2 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Failure Detector */ 363 #define OSCCTRL_STATUS_XOSCFAIL_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCFAIL_Pos) 364 #define OSCCTRL_STATUS_XOSCFAIL(value) (OSCCTRL_STATUS_XOSCFAIL_Msk & ((value) << OSCCTRL_STATUS_XOSCFAIL_Pos)) 365 #define OSCCTRL_STATUS_XOSCCKSW0_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC 0 Clock Switch */ 366 #define OSCCTRL_STATUS_XOSCCKSW0 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW0_Pos) 367 #define OSCCTRL_STATUS_XOSCCKSW1_Pos 5 /**< \brief (OSCCTRL_STATUS) XOSC 1 Clock Switch */ 368 #define OSCCTRL_STATUS_XOSCCKSW1 (_U_(1) << OSCCTRL_STATUS_XOSCCKSW1_Pos) 369 #define OSCCTRL_STATUS_XOSCCKSW_Pos 4 /**< \brief (OSCCTRL_STATUS) XOSC x Clock Switch */ 370 #define OSCCTRL_STATUS_XOSCCKSW_Msk (_U_(0x3) << OSCCTRL_STATUS_XOSCCKSW_Pos) 371 #define OSCCTRL_STATUS_XOSCCKSW(value) (OSCCTRL_STATUS_XOSCCKSW_Msk & ((value) << OSCCTRL_STATUS_XOSCCKSW_Pos)) 372 #define OSCCTRL_STATUS_DFLLRDY_Pos 8 /**< \brief (OSCCTRL_STATUS) DFLL Ready */ 373 #define OSCCTRL_STATUS_DFLLRDY (_U_(0x1) << OSCCTRL_STATUS_DFLLRDY_Pos) 374 #define OSCCTRL_STATUS_DFLLOOB_Pos 9 /**< \brief (OSCCTRL_STATUS) DFLL Out Of Bounds */ 375 #define OSCCTRL_STATUS_DFLLOOB (_U_(0x1) << OSCCTRL_STATUS_DFLLOOB_Pos) 376 #define OSCCTRL_STATUS_DFLLLCKF_Pos 10 /**< \brief (OSCCTRL_STATUS) DFLL Lock Fine */ 377 #define OSCCTRL_STATUS_DFLLLCKF (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKF_Pos) 378 #define OSCCTRL_STATUS_DFLLLCKC_Pos 11 /**< \brief (OSCCTRL_STATUS) DFLL Lock Coarse */ 379 #define OSCCTRL_STATUS_DFLLLCKC (_U_(0x1) << OSCCTRL_STATUS_DFLLLCKC_Pos) 380 #define OSCCTRL_STATUS_DFLLRCS_Pos 12 /**< \brief (OSCCTRL_STATUS) DFLL Reference Clock Stopped */ 381 #define OSCCTRL_STATUS_DFLLRCS (_U_(0x1) << OSCCTRL_STATUS_DFLLRCS_Pos) 382 #define OSCCTRL_STATUS_DPLL0LCKR_Pos 16 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Rise */ 383 #define OSCCTRL_STATUS_DPLL0LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKR_Pos) 384 #define OSCCTRL_STATUS_DPLL0LCKF_Pos 17 /**< \brief (OSCCTRL_STATUS) DPLL0 Lock Fall */ 385 #define OSCCTRL_STATUS_DPLL0LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL0LCKF_Pos) 386 #define OSCCTRL_STATUS_DPLL0TO_Pos 18 /**< \brief (OSCCTRL_STATUS) DPLL0 Timeout */ 387 #define OSCCTRL_STATUS_DPLL0TO (_U_(0x1) << OSCCTRL_STATUS_DPLL0TO_Pos) 388 #define OSCCTRL_STATUS_DPLL0LDRTO_Pos 19 /**< \brief (OSCCTRL_STATUS) DPLL0 Loop Divider Ratio Update Complete */ 389 #define OSCCTRL_STATUS_DPLL0LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL0LDRTO_Pos) 390 #define OSCCTRL_STATUS_DPLL1LCKR_Pos 24 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Rise */ 391 #define OSCCTRL_STATUS_DPLL1LCKR (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKR_Pos) 392 #define OSCCTRL_STATUS_DPLL1LCKF_Pos 25 /**< \brief (OSCCTRL_STATUS) DPLL1 Lock Fall */ 393 #define OSCCTRL_STATUS_DPLL1LCKF (_U_(0x1) << OSCCTRL_STATUS_DPLL1LCKF_Pos) 394 #define OSCCTRL_STATUS_DPLL1TO_Pos 26 /**< \brief (OSCCTRL_STATUS) DPLL1 Timeout */ 395 #define OSCCTRL_STATUS_DPLL1TO (_U_(0x1) << OSCCTRL_STATUS_DPLL1TO_Pos) 396 #define OSCCTRL_STATUS_DPLL1LDRTO_Pos 27 /**< \brief (OSCCTRL_STATUS) DPLL1 Loop Divider Ratio Update Complete */ 397 #define OSCCTRL_STATUS_DPLL1LDRTO (_U_(0x1) << OSCCTRL_STATUS_DPLL1LDRTO_Pos) 398 #define OSCCTRL_STATUS_MASK _U_(0x0F0F1F3F) /**< \brief (OSCCTRL_STATUS) MASK Register */ 399 400 /* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */ 401 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 402 typedef union { 403 struct { 404 uint32_t :1; /*!< bit: 0 Reserved */ 405 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 406 uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ 407 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 408 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 409 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 410 uint32_t LOWBUFGAIN:1; /*!< bit: 8 Low Buffer Gain Enable */ 411 uint32_t IPTAT:2; /*!< bit: 9..10 Oscillator Current Reference */ 412 uint32_t IMULT:4; /*!< bit: 11..14 Oscillator Current Multiplier */ 413 uint32_t ENALC:1; /*!< bit: 15 Automatic Loop Control Enable */ 414 uint32_t CFDEN:1; /*!< bit: 16 Clock Failure Detector Enable */ 415 uint32_t SWBEN:1; /*!< bit: 17 Xosc Clock Switch Enable */ 416 uint32_t :2; /*!< bit: 18..19 Reserved */ 417 uint32_t STARTUP:4; /*!< bit: 20..23 Start-Up Time */ 418 uint32_t CFDPRESC:4; /*!< bit: 24..27 Clock Failure Detector Prescaler */ 419 uint32_t :4; /*!< bit: 28..31 Reserved */ 420 } bit; /*!< Structure used for bit access */ 421 uint32_t reg; /*!< Type used for register access */ 422 } OSCCTRL_XOSCCTRL_Type; 423 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 424 425 #define OSCCTRL_XOSCCTRL_OFFSET 0x14 /**< \brief (OSCCTRL_XOSCCTRL offset) External Multipurpose Crystal Oscillator Control */ 426 #define OSCCTRL_XOSCCTRL_RESETVALUE _U_(0x00000080) /**< \brief (OSCCTRL_XOSCCTRL reset_value) External Multipurpose Crystal Oscillator Control */ 427 428 #define OSCCTRL_XOSCCTRL_ENABLE_Pos 1 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Enable */ 429 #define OSCCTRL_XOSCCTRL_ENABLE (_U_(0x1) << OSCCTRL_XOSCCTRL_ENABLE_Pos) 430 #define OSCCTRL_XOSCCTRL_XTALEN_Pos 2 /**< \brief (OSCCTRL_XOSCCTRL) Crystal Oscillator Enable */ 431 #define OSCCTRL_XOSCCTRL_XTALEN (_U_(0x1) << OSCCTRL_XOSCCTRL_XTALEN_Pos) 432 #define OSCCTRL_XOSCCTRL_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_XOSCCTRL) Run in Standby */ 433 #define OSCCTRL_XOSCCTRL_RUNSTDBY (_U_(0x1) << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) 434 #define OSCCTRL_XOSCCTRL_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_XOSCCTRL) On Demand Control */ 435 #define OSCCTRL_XOSCCTRL_ONDEMAND (_U_(0x1) << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) 436 #define OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos 8 /**< \brief (OSCCTRL_XOSCCTRL) Low Buffer Gain Enable */ 437 #define OSCCTRL_XOSCCTRL_LOWBUFGAIN (_U_(0x1) << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) 438 #define OSCCTRL_XOSCCTRL_IPTAT_Pos 9 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Reference */ 439 #define OSCCTRL_XOSCCTRL_IPTAT_Msk (_U_(0x3) << OSCCTRL_XOSCCTRL_IPTAT_Pos) 440 #define OSCCTRL_XOSCCTRL_IPTAT(value) (OSCCTRL_XOSCCTRL_IPTAT_Msk & ((value) << OSCCTRL_XOSCCTRL_IPTAT_Pos)) 441 #define OSCCTRL_XOSCCTRL_IMULT_Pos 11 /**< \brief (OSCCTRL_XOSCCTRL) Oscillator Current Multiplier */ 442 #define OSCCTRL_XOSCCTRL_IMULT_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_IMULT_Pos) 443 #define OSCCTRL_XOSCCTRL_IMULT(value) (OSCCTRL_XOSCCTRL_IMULT_Msk & ((value) << OSCCTRL_XOSCCTRL_IMULT_Pos)) 444 #define OSCCTRL_XOSCCTRL_ENALC_Pos 15 /**< \brief (OSCCTRL_XOSCCTRL) Automatic Loop Control Enable */ 445 #define OSCCTRL_XOSCCTRL_ENALC (_U_(0x1) << OSCCTRL_XOSCCTRL_ENALC_Pos) 446 #define OSCCTRL_XOSCCTRL_CFDEN_Pos 16 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Enable */ 447 #define OSCCTRL_XOSCCTRL_CFDEN (_U_(0x1) << OSCCTRL_XOSCCTRL_CFDEN_Pos) 448 #define OSCCTRL_XOSCCTRL_SWBEN_Pos 17 /**< \brief (OSCCTRL_XOSCCTRL) Xosc Clock Switch Enable */ 449 #define OSCCTRL_XOSCCTRL_SWBEN (_U_(0x1) << OSCCTRL_XOSCCTRL_SWBEN_Pos) 450 #define OSCCTRL_XOSCCTRL_STARTUP_Pos 20 /**< \brief (OSCCTRL_XOSCCTRL) Start-Up Time */ 451 #define OSCCTRL_XOSCCTRL_STARTUP_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_STARTUP_Pos) 452 #define OSCCTRL_XOSCCTRL_STARTUP(value) (OSCCTRL_XOSCCTRL_STARTUP_Msk & ((value) << OSCCTRL_XOSCCTRL_STARTUP_Pos)) 453 #define OSCCTRL_XOSCCTRL_CFDPRESC_Pos 24 /**< \brief (OSCCTRL_XOSCCTRL) Clock Failure Detector Prescaler */ 454 #define OSCCTRL_XOSCCTRL_CFDPRESC_Msk (_U_(0xF) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos) 455 #define OSCCTRL_XOSCCTRL_CFDPRESC(value) (OSCCTRL_XOSCCTRL_CFDPRESC_Msk & ((value) << OSCCTRL_XOSCCTRL_CFDPRESC_Pos)) 456 #define OSCCTRL_XOSCCTRL_MASK _U_(0x0FF3FFC6) /**< \brief (OSCCTRL_XOSCCTRL) MASK Register */ 457 458 /* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */ 459 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 460 typedef union { 461 struct { 462 uint8_t :1; /*!< bit: 0 Reserved */ 463 uint8_t ENABLE:1; /*!< bit: 1 DFLL Enable */ 464 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 465 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 466 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 467 } bit; /*!< Structure used for bit access */ 468 uint8_t reg; /*!< Type used for register access */ 469 } OSCCTRL_DFLLCTRLA_Type; 470 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 471 472 #define OSCCTRL_DFLLCTRLA_OFFSET 0x1C /**< \brief (OSCCTRL_DFLLCTRLA offset) DFLL48M Control A */ 473 #define OSCCTRL_DFLLCTRLA_RESETVALUE _U_(0x82) /**< \brief (OSCCTRL_DFLLCTRLA reset_value) DFLL48M Control A */ 474 475 #define OSCCTRL_DFLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLA) DFLL Enable */ 476 #define OSCCTRL_DFLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DFLLCTRLA_ENABLE_Pos) 477 #define OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLA) Run in Standby */ 478 #define OSCCTRL_DFLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) 479 #define OSCCTRL_DFLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLA) On Demand Control */ 480 #define OSCCTRL_DFLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos) 481 #define OSCCTRL_DFLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DFLLCTRLA) MASK Register */ 482 483 /* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */ 484 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 485 typedef union { 486 struct { 487 uint8_t MODE:1; /*!< bit: 0 Operating Mode Selection */ 488 uint8_t STABLE:1; /*!< bit: 1 Stable DFLL Frequency */ 489 uint8_t LLAW:1; /*!< bit: 2 Lose Lock After Wake */ 490 uint8_t USBCRM:1; /*!< bit: 3 USB Clock Recovery Mode */ 491 uint8_t CCDIS:1; /*!< bit: 4 Chill Cycle Disable */ 492 uint8_t QLDIS:1; /*!< bit: 5 Quick Lock Disable */ 493 uint8_t BPLCKC:1; /*!< bit: 6 Bypass Coarse Lock */ 494 uint8_t WAITLOCK:1; /*!< bit: 7 Wait Lock */ 495 } bit; /*!< Structure used for bit access */ 496 uint8_t reg; /*!< Type used for register access */ 497 } OSCCTRL_DFLLCTRLB_Type; 498 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 499 500 #define OSCCTRL_DFLLCTRLB_OFFSET 0x20 /**< \brief (OSCCTRL_DFLLCTRLB offset) DFLL48M Control B */ 501 #define OSCCTRL_DFLLCTRLB_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLCTRLB reset_value) DFLL48M Control B */ 502 503 #define OSCCTRL_DFLLCTRLB_MODE_Pos 0 /**< \brief (OSCCTRL_DFLLCTRLB) Operating Mode Selection */ 504 #define OSCCTRL_DFLLCTRLB_MODE (_U_(0x1) << OSCCTRL_DFLLCTRLB_MODE_Pos) 505 #define OSCCTRL_DFLLCTRLB_STABLE_Pos 1 /**< \brief (OSCCTRL_DFLLCTRLB) Stable DFLL Frequency */ 506 #define OSCCTRL_DFLLCTRLB_STABLE (_U_(0x1) << OSCCTRL_DFLLCTRLB_STABLE_Pos) 507 #define OSCCTRL_DFLLCTRLB_LLAW_Pos 2 /**< \brief (OSCCTRL_DFLLCTRLB) Lose Lock After Wake */ 508 #define OSCCTRL_DFLLCTRLB_LLAW (_U_(0x1) << OSCCTRL_DFLLCTRLB_LLAW_Pos) 509 #define OSCCTRL_DFLLCTRLB_USBCRM_Pos 3 /**< \brief (OSCCTRL_DFLLCTRLB) USB Clock Recovery Mode */ 510 #define OSCCTRL_DFLLCTRLB_USBCRM (_U_(0x1) << OSCCTRL_DFLLCTRLB_USBCRM_Pos) 511 #define OSCCTRL_DFLLCTRLB_CCDIS_Pos 4 /**< \brief (OSCCTRL_DFLLCTRLB) Chill Cycle Disable */ 512 #define OSCCTRL_DFLLCTRLB_CCDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_CCDIS_Pos) 513 #define OSCCTRL_DFLLCTRLB_QLDIS_Pos 5 /**< \brief (OSCCTRL_DFLLCTRLB) Quick Lock Disable */ 514 #define OSCCTRL_DFLLCTRLB_QLDIS (_U_(0x1) << OSCCTRL_DFLLCTRLB_QLDIS_Pos) 515 #define OSCCTRL_DFLLCTRLB_BPLCKC_Pos 6 /**< \brief (OSCCTRL_DFLLCTRLB) Bypass Coarse Lock */ 516 #define OSCCTRL_DFLLCTRLB_BPLCKC (_U_(0x1) << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) 517 #define OSCCTRL_DFLLCTRLB_WAITLOCK_Pos 7 /**< \brief (OSCCTRL_DFLLCTRLB) Wait Lock */ 518 #define OSCCTRL_DFLLCTRLB_WAITLOCK (_U_(0x1) << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) 519 #define OSCCTRL_DFLLCTRLB_MASK _U_(0xFF) /**< \brief (OSCCTRL_DFLLCTRLB) MASK Register */ 520 521 /* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */ 522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 523 typedef union { 524 struct { 525 uint32_t FINE:8; /*!< bit: 0.. 7 Fine Value */ 526 uint32_t :2; /*!< bit: 8.. 9 Reserved */ 527 uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ 528 uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ 529 } bit; /*!< Structure used for bit access */ 530 uint32_t reg; /*!< Type used for register access */ 531 } OSCCTRL_DFLLVAL_Type; 532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 533 534 #define OSCCTRL_DFLLVAL_OFFSET 0x24 /**< \brief (OSCCTRL_DFLLVAL offset) DFLL48M Value */ 535 #define OSCCTRL_DFLLVAL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLVAL reset_value) DFLL48M Value */ 536 537 #define OSCCTRL_DFLLVAL_FINE_Pos 0 /**< \brief (OSCCTRL_DFLLVAL) Fine Value */ 538 #define OSCCTRL_DFLLVAL_FINE_Msk (_U_(0xFF) << OSCCTRL_DFLLVAL_FINE_Pos) 539 #define OSCCTRL_DFLLVAL_FINE(value) (OSCCTRL_DFLLVAL_FINE_Msk & ((value) << OSCCTRL_DFLLVAL_FINE_Pos)) 540 #define OSCCTRL_DFLLVAL_COARSE_Pos 10 /**< \brief (OSCCTRL_DFLLVAL) Coarse Value */ 541 #define OSCCTRL_DFLLVAL_COARSE_Msk (_U_(0x3F) << OSCCTRL_DFLLVAL_COARSE_Pos) 542 #define OSCCTRL_DFLLVAL_COARSE(value) (OSCCTRL_DFLLVAL_COARSE_Msk & ((value) << OSCCTRL_DFLLVAL_COARSE_Pos)) 543 #define OSCCTRL_DFLLVAL_DIFF_Pos 16 /**< \brief (OSCCTRL_DFLLVAL) Multiplication Ratio Difference */ 544 #define OSCCTRL_DFLLVAL_DIFF_Msk (_U_(0xFFFF) << OSCCTRL_DFLLVAL_DIFF_Pos) 545 #define OSCCTRL_DFLLVAL_DIFF(value) (OSCCTRL_DFLLVAL_DIFF_Msk & ((value) << OSCCTRL_DFLLVAL_DIFF_Pos)) 546 #define OSCCTRL_DFLLVAL_MASK _U_(0xFFFFFCFF) /**< \brief (OSCCTRL_DFLLVAL) MASK Register */ 547 548 /* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */ 549 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 550 typedef union { 551 struct { 552 uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ 553 uint32_t FSTEP:8; /*!< bit: 16..23 Fine Maximum Step */ 554 uint32_t :2; /*!< bit: 24..25 Reserved */ 555 uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ 556 } bit; /*!< Structure used for bit access */ 557 uint32_t reg; /*!< Type used for register access */ 558 } OSCCTRL_DFLLMUL_Type; 559 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 560 561 #define OSCCTRL_DFLLMUL_OFFSET 0x28 /**< \brief (OSCCTRL_DFLLMUL offset) DFLL48M Multiplier */ 562 #define OSCCTRL_DFLLMUL_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DFLLMUL reset_value) DFLL48M Multiplier */ 563 564 #define OSCCTRL_DFLLMUL_MUL_Pos 0 /**< \brief (OSCCTRL_DFLLMUL) DFLL Multiply Factor */ 565 #define OSCCTRL_DFLLMUL_MUL_Msk (_U_(0xFFFF) << OSCCTRL_DFLLMUL_MUL_Pos) 566 #define OSCCTRL_DFLLMUL_MUL(value) (OSCCTRL_DFLLMUL_MUL_Msk & ((value) << OSCCTRL_DFLLMUL_MUL_Pos)) 567 #define OSCCTRL_DFLLMUL_FSTEP_Pos 16 /**< \brief (OSCCTRL_DFLLMUL) Fine Maximum Step */ 568 #define OSCCTRL_DFLLMUL_FSTEP_Msk (_U_(0xFF) << OSCCTRL_DFLLMUL_FSTEP_Pos) 569 #define OSCCTRL_DFLLMUL_FSTEP(value) (OSCCTRL_DFLLMUL_FSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_FSTEP_Pos)) 570 #define OSCCTRL_DFLLMUL_CSTEP_Pos 26 /**< \brief (OSCCTRL_DFLLMUL) Coarse Maximum Step */ 571 #define OSCCTRL_DFLLMUL_CSTEP_Msk (_U_(0x3F) << OSCCTRL_DFLLMUL_CSTEP_Pos) 572 #define OSCCTRL_DFLLMUL_CSTEP(value) (OSCCTRL_DFLLMUL_CSTEP_Msk & ((value) << OSCCTRL_DFLLMUL_CSTEP_Pos)) 573 #define OSCCTRL_DFLLMUL_MASK _U_(0xFCFFFFFF) /**< \brief (OSCCTRL_DFLLMUL) MASK Register */ 574 575 /* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */ 576 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 577 typedef union { 578 struct { 579 uint8_t :1; /*!< bit: 0 Reserved */ 580 uint8_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ 581 uint8_t DFLLCTRLB:1; /*!< bit: 2 DFLLCTRLB Synchronization Busy */ 582 uint8_t DFLLVAL:1; /*!< bit: 3 DFLLVAL Synchronization Busy */ 583 uint8_t DFLLMUL:1; /*!< bit: 4 DFLLMUL Synchronization Busy */ 584 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 585 } bit; /*!< Structure used for bit access */ 586 uint8_t reg; /*!< Type used for register access */ 587 } OSCCTRL_DFLLSYNC_Type; 588 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 589 590 #define OSCCTRL_DFLLSYNC_OFFSET 0x2C /**< \brief (OSCCTRL_DFLLSYNC offset) DFLL48M Synchronization */ 591 #define OSCCTRL_DFLLSYNC_RESETVALUE _U_(0x00) /**< \brief (OSCCTRL_DFLLSYNC reset_value) DFLL48M Synchronization */ 592 593 #define OSCCTRL_DFLLSYNC_ENABLE_Pos 1 /**< \brief (OSCCTRL_DFLLSYNC) ENABLE Synchronization Busy */ 594 #define OSCCTRL_DFLLSYNC_ENABLE (_U_(0x1) << OSCCTRL_DFLLSYNC_ENABLE_Pos) 595 #define OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos 2 /**< \brief (OSCCTRL_DFLLSYNC) DFLLCTRLB Synchronization Busy */ 596 #define OSCCTRL_DFLLSYNC_DFLLCTRLB (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos) 597 #define OSCCTRL_DFLLSYNC_DFLLVAL_Pos 3 /**< \brief (OSCCTRL_DFLLSYNC) DFLLVAL Synchronization Busy */ 598 #define OSCCTRL_DFLLSYNC_DFLLVAL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLVAL_Pos) 599 #define OSCCTRL_DFLLSYNC_DFLLMUL_Pos 4 /**< \brief (OSCCTRL_DFLLSYNC) DFLLMUL Synchronization Busy */ 600 #define OSCCTRL_DFLLSYNC_DFLLMUL (_U_(0x1) << OSCCTRL_DFLLSYNC_DFLLMUL_Pos) 601 #define OSCCTRL_DFLLSYNC_MASK _U_(0x1E) /**< \brief (OSCCTRL_DFLLSYNC) MASK Register */ 602 603 /* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x30) (R/W 8) DPLL DPLL Control A -------- */ 604 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 605 typedef union { 606 struct { 607 uint8_t :1; /*!< bit: 0 Reserved */ 608 uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ 609 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 610 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 611 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 612 } bit; /*!< Structure used for bit access */ 613 uint8_t reg; /*!< Type used for register access */ 614 } OSCCTRL_DPLLCTRLA_Type; 615 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 616 617 #define OSCCTRL_DPLLCTRLA_OFFSET 0x30 /**< \brief (OSCCTRL_DPLLCTRLA offset) DPLL Control A */ 618 #define OSCCTRL_DPLLCTRLA_RESETVALUE _U_(0x80) /**< \brief (OSCCTRL_DPLLCTRLA reset_value) DPLL Control A */ 619 620 #define OSCCTRL_DPLLCTRLA_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLCTRLA) DPLL Enable */ 621 #define OSCCTRL_DPLLCTRLA_ENABLE (_U_(0x1) << OSCCTRL_DPLLCTRLA_ENABLE_Pos) 622 #define OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos 6 /**< \brief (OSCCTRL_DPLLCTRLA) Run in Standby */ 623 #define OSCCTRL_DPLLCTRLA_RUNSTDBY (_U_(0x1) << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) 624 #define OSCCTRL_DPLLCTRLA_ONDEMAND_Pos 7 /**< \brief (OSCCTRL_DPLLCTRLA) On Demand Control */ 625 #define OSCCTRL_DPLLCTRLA_ONDEMAND (_U_(0x1) << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos) 626 #define OSCCTRL_DPLLCTRLA_MASK _U_(0xC2) /**< \brief (OSCCTRL_DPLLCTRLA) MASK Register */ 627 628 /* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x34) (R/W 32) DPLL DPLL Ratio Control -------- */ 629 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 630 typedef union { 631 struct { 632 uint32_t LDR:13; /*!< bit: 0..12 Loop Divider Ratio */ 633 uint32_t :3; /*!< bit: 13..15 Reserved */ 634 uint32_t LDRFRAC:5; /*!< bit: 16..20 Loop Divider Ratio Fractional Part */ 635 uint32_t :11; /*!< bit: 21..31 Reserved */ 636 } bit; /*!< Structure used for bit access */ 637 uint32_t reg; /*!< Type used for register access */ 638 } OSCCTRL_DPLLRATIO_Type; 639 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 640 641 #define OSCCTRL_DPLLRATIO_OFFSET 0x34 /**< \brief (OSCCTRL_DPLLRATIO offset) DPLL Ratio Control */ 642 #define OSCCTRL_DPLLRATIO_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLRATIO reset_value) DPLL Ratio Control */ 643 644 #define OSCCTRL_DPLLRATIO_LDR_Pos 0 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio */ 645 #define OSCCTRL_DPLLRATIO_LDR_Msk (_U_(0x1FFF) << OSCCTRL_DPLLRATIO_LDR_Pos) 646 #define OSCCTRL_DPLLRATIO_LDR(value) (OSCCTRL_DPLLRATIO_LDR_Msk & ((value) << OSCCTRL_DPLLRATIO_LDR_Pos)) 647 #define OSCCTRL_DPLLRATIO_LDRFRAC_Pos 16 /**< \brief (OSCCTRL_DPLLRATIO) Loop Divider Ratio Fractional Part */ 648 #define OSCCTRL_DPLLRATIO_LDRFRAC_Msk (_U_(0x1F) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos) 649 #define OSCCTRL_DPLLRATIO_LDRFRAC(value) (OSCCTRL_DPLLRATIO_LDRFRAC_Msk & ((value) << OSCCTRL_DPLLRATIO_LDRFRAC_Pos)) 650 #define OSCCTRL_DPLLRATIO_MASK _U_(0x001F1FFF) /**< \brief (OSCCTRL_DPLLRATIO) MASK Register */ 651 652 /* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x38) (R/W 32) DPLL DPLL Control B -------- */ 653 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 654 typedef union { 655 struct { 656 uint32_t FILTER:4; /*!< bit: 0.. 3 Proportional Integral Filter Selection */ 657 uint32_t WUF:1; /*!< bit: 4 Wake Up Fast */ 658 uint32_t REFCLK:3; /*!< bit: 5.. 7 Reference Clock Selection */ 659 uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ 660 uint32_t LBYPASS:1; /*!< bit: 11 Lock Bypass */ 661 uint32_t DCOFILTER:3; /*!< bit: 12..14 Sigma-Delta DCO Filter Selection */ 662 uint32_t DCOEN:1; /*!< bit: 15 DCO Filter Enable */ 663 uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ 664 uint32_t :5; /*!< bit: 27..31 Reserved */ 665 } bit; /*!< Structure used for bit access */ 666 uint32_t reg; /*!< Type used for register access */ 667 } OSCCTRL_DPLLCTRLB_Type; 668 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 669 670 #define OSCCTRL_DPLLCTRLB_OFFSET 0x38 /**< \brief (OSCCTRL_DPLLCTRLB offset) DPLL Control B */ 671 #define OSCCTRL_DPLLCTRLB_RESETVALUE _U_(0x00000020) /**< \brief (OSCCTRL_DPLLCTRLB reset_value) DPLL Control B */ 672 673 #define OSCCTRL_DPLLCTRLB_FILTER_Pos 0 /**< \brief (OSCCTRL_DPLLCTRLB) Proportional Integral Filter Selection */ 674 #define OSCCTRL_DPLLCTRLB_FILTER_Msk (_U_(0xF) << OSCCTRL_DPLLCTRLB_FILTER_Pos) 675 #define OSCCTRL_DPLLCTRLB_FILTER(value) (OSCCTRL_DPLLCTRLB_FILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_FILTER_Pos)) 676 #define OSCCTRL_DPLLCTRLB_WUF_Pos 4 /**< \brief (OSCCTRL_DPLLCTRLB) Wake Up Fast */ 677 #define OSCCTRL_DPLLCTRLB_WUF (_U_(0x1) << OSCCTRL_DPLLCTRLB_WUF_Pos) 678 #define OSCCTRL_DPLLCTRLB_REFCLK_Pos 5 /**< \brief (OSCCTRL_DPLLCTRLB) Reference Clock Selection */ 679 #define OSCCTRL_DPLLCTRLB_REFCLK_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_REFCLK_Pos) 680 #define OSCCTRL_DPLLCTRLB_REFCLK(value) (OSCCTRL_DPLLCTRLB_REFCLK_Msk & ((value) << OSCCTRL_DPLLCTRLB_REFCLK_Pos)) 681 #define OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) Dedicated GCLK clock reference */ 682 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val _U_(0x1) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC32K clock reference */ 683 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val _U_(0x2) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC0 clock reference */ 684 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val _U_(0x3) /**< \brief (OSCCTRL_DPLLCTRLB) XOSC1 clock reference */ 685 #define OSCCTRL_DPLLCTRLB_REFCLK_GCLK (OSCCTRL_DPLLCTRLB_REFCLK_GCLK_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) 686 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC32 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC32_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) 687 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC0 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC0_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) 688 #define OSCCTRL_DPLLCTRLB_REFCLK_XOSC1 (OSCCTRL_DPLLCTRLB_REFCLK_XOSC1_Val << OSCCTRL_DPLLCTRLB_REFCLK_Pos) 689 #define OSCCTRL_DPLLCTRLB_LTIME_Pos 8 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Time */ 690 #define OSCCTRL_DPLLCTRLB_LTIME_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_LTIME_Pos) 691 #define OSCCTRL_DPLLCTRLB_LTIME(value) (OSCCTRL_DPLLCTRLB_LTIME_Msk & ((value) << OSCCTRL_DPLLCTRLB_LTIME_Pos)) 692 #define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val _U_(0x0) /**< \brief (OSCCTRL_DPLLCTRLB) No time-out. Automatic lock */ 693 #define OSCCTRL_DPLLCTRLB_LTIME_800US_Val _U_(0x4) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 800us */ 694 #define OSCCTRL_DPLLCTRLB_LTIME_900US_Val _U_(0x5) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 900us */ 695 #define OSCCTRL_DPLLCTRLB_LTIME_1MS_Val _U_(0x6) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1ms */ 696 #define OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val _U_(0x7) /**< \brief (OSCCTRL_DPLLCTRLB) Time-out if no lock within 1.1ms */ 697 #define OSCCTRL_DPLLCTRLB_LTIME_DEFAULT (OSCCTRL_DPLLCTRLB_LTIME_DEFAULT_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) 698 #define OSCCTRL_DPLLCTRLB_LTIME_800US (OSCCTRL_DPLLCTRLB_LTIME_800US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) 699 #define OSCCTRL_DPLLCTRLB_LTIME_900US (OSCCTRL_DPLLCTRLB_LTIME_900US_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) 700 #define OSCCTRL_DPLLCTRLB_LTIME_1MS (OSCCTRL_DPLLCTRLB_LTIME_1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) 701 #define OSCCTRL_DPLLCTRLB_LTIME_1P1MS (OSCCTRL_DPLLCTRLB_LTIME_1P1MS_Val << OSCCTRL_DPLLCTRLB_LTIME_Pos) 702 #define OSCCTRL_DPLLCTRLB_LBYPASS_Pos 11 /**< \brief (OSCCTRL_DPLLCTRLB) Lock Bypass */ 703 #define OSCCTRL_DPLLCTRLB_LBYPASS (_U_(0x1) << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) 704 #define OSCCTRL_DPLLCTRLB_DCOFILTER_Pos 12 /**< \brief (OSCCTRL_DPLLCTRLB) Sigma-Delta DCO Filter Selection */ 705 #define OSCCTRL_DPLLCTRLB_DCOFILTER_Msk (_U_(0x7) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos) 706 #define OSCCTRL_DPLLCTRLB_DCOFILTER(value) (OSCCTRL_DPLLCTRLB_DCOFILTER_Msk & ((value) << OSCCTRL_DPLLCTRLB_DCOFILTER_Pos)) 707 #define OSCCTRL_DPLLCTRLB_DCOEN_Pos 15 /**< \brief (OSCCTRL_DPLLCTRLB) DCO Filter Enable */ 708 #define OSCCTRL_DPLLCTRLB_DCOEN (_U_(0x1) << OSCCTRL_DPLLCTRLB_DCOEN_Pos) 709 #define OSCCTRL_DPLLCTRLB_DIV_Pos 16 /**< \brief (OSCCTRL_DPLLCTRLB) Clock Divider */ 710 #define OSCCTRL_DPLLCTRLB_DIV_Msk (_U_(0x7FF) << OSCCTRL_DPLLCTRLB_DIV_Pos) 711 #define OSCCTRL_DPLLCTRLB_DIV(value) (OSCCTRL_DPLLCTRLB_DIV_Msk & ((value) << OSCCTRL_DPLLCTRLB_DIV_Pos)) 712 #define OSCCTRL_DPLLCTRLB_MASK _U_(0x07FFFFFF) /**< \brief (OSCCTRL_DPLLCTRLB) MASK Register */ 713 714 /* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x3C) (R/ 32) DPLL DPLL Synchronization Busy -------- */ 715 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 716 typedef union { 717 struct { 718 uint32_t :1; /*!< bit: 0 Reserved */ 719 uint32_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */ 720 uint32_t DPLLRATIO:1; /*!< bit: 2 DPLL Loop Divider Ratio Synchronization Status */ 721 uint32_t :29; /*!< bit: 3..31 Reserved */ 722 } bit; /*!< Structure used for bit access */ 723 uint32_t reg; /*!< Type used for register access */ 724 } OSCCTRL_DPLLSYNCBUSY_Type; 725 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 726 727 #define OSCCTRL_DPLLSYNCBUSY_OFFSET 0x3C /**< \brief (OSCCTRL_DPLLSYNCBUSY offset) DPLL Synchronization Busy */ 728 #define OSCCTRL_DPLLSYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSYNCBUSY reset_value) DPLL Synchronization Busy */ 729 730 #define OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos 1 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Enable Synchronization Status */ 731 #define OSCCTRL_DPLLSYNCBUSY_ENABLE (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos) 732 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos 2 /**< \brief (OSCCTRL_DPLLSYNCBUSY) DPLL Loop Divider Ratio Synchronization Status */ 733 #define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (_U_(0x1) << OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos) 734 #define OSCCTRL_DPLLSYNCBUSY_MASK _U_(0x00000006) /**< \brief (OSCCTRL_DPLLSYNCBUSY) MASK Register */ 735 736 /* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x40) (R/ 32) DPLL DPLL Status -------- */ 737 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 738 typedef union { 739 struct { 740 uint32_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ 741 uint32_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */ 742 uint32_t :30; /*!< bit: 2..31 Reserved */ 743 } bit; /*!< Structure used for bit access */ 744 uint32_t reg; /*!< Type used for register access */ 745 } OSCCTRL_DPLLSTATUS_Type; 746 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 747 748 #define OSCCTRL_DPLLSTATUS_OFFSET 0x40 /**< \brief (OSCCTRL_DPLLSTATUS offset) DPLL Status */ 749 #define OSCCTRL_DPLLSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (OSCCTRL_DPLLSTATUS reset_value) DPLL Status */ 750 751 #define OSCCTRL_DPLLSTATUS_LOCK_Pos 0 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Lock Status */ 752 #define OSCCTRL_DPLLSTATUS_LOCK (_U_(0x1) << OSCCTRL_DPLLSTATUS_LOCK_Pos) 753 #define OSCCTRL_DPLLSTATUS_CLKRDY_Pos 1 /**< \brief (OSCCTRL_DPLLSTATUS) DPLL Clock Ready */ 754 #define OSCCTRL_DPLLSTATUS_CLKRDY (_U_(0x1) << OSCCTRL_DPLLSTATUS_CLKRDY_Pos) 755 #define OSCCTRL_DPLLSTATUS_MASK _U_(0x00000003) /**< \brief (OSCCTRL_DPLLSTATUS) MASK Register */ 756 757 /** \brief OscctrlDpll hardware registers */ 758 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 759 typedef struct { 760 __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x00 (R/W 8) DPLL Control A */ 761 RoReg8 Reserved1[0x3]; 762 __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x04 (R/W 32) DPLL Ratio Control */ 763 __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x08 (R/W 32) DPLL Control B */ 764 __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) DPLL Synchronization Busy */ 765 __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x10 (R/ 32) DPLL Status */ 766 } OscctrlDpll; 767 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 768 769 /** \brief OSCCTRL hardware registers */ 770 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 771 typedef struct { 772 __IO OSCCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x00 (R/W 8) Event Control */ 773 RoReg8 Reserved1[0x3]; 774 __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Clear */ 775 __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Set */ 776 __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */ 777 __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/ 32) Status */ 778 __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL[2]; /**< \brief Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */ 779 __IO OSCCTRL_DFLLCTRLA_Type DFLLCTRLA; /**< \brief Offset: 0x1C (R/W 8) DFLL48M Control A */ 780 RoReg8 Reserved2[0x3]; 781 __IO OSCCTRL_DFLLCTRLB_Type DFLLCTRLB; /**< \brief Offset: 0x20 (R/W 8) DFLL48M Control B */ 782 RoReg8 Reserved3[0x3]; 783 __IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x24 (R/W 32) DFLL48M Value */ 784 __IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Multiplier */ 785 __IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x2C (R/W 8) DFLL48M Synchronization */ 786 RoReg8 Reserved4[0x3]; 787 OscctrlDpll Dpll[2]; /**< \brief Offset: 0x30 OscctrlDpll groups [DPLLS_NUM] */ 788 } Oscctrl; 789 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 790 791 /*@}*/ 792 793 #endif /* _SAMD51_OSCCTRL_COMPONENT_ */ 794
