1 /** 2 * \file 3 * 4 * \brief Component description for ICM 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD51_ICM_COMPONENT_ 31 #define _SAMD51_ICM_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR ICM */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMD51_ICM Integrity Check Monitor */ 37 /*@{*/ 38 39 #define ICM_U2010 40 #define REV_ICM 0x120 41 42 /* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t WBDIS:1; /*!< bit: 0 Write Back Disable */ 47 uint32_t EOMDIS:1; /*!< bit: 1 End of Monitoring Disable */ 48 uint32_t SLBDIS:1; /*!< bit: 2 Secondary List Branching Disable */ 49 uint32_t :1; /*!< bit: 3 Reserved */ 50 uint32_t BBC:4; /*!< bit: 4.. 7 Bus Burden Control */ 51 uint32_t ASCD:1; /*!< bit: 8 Automatic Switch To Compare Digest */ 52 uint32_t DUALBUFF:1; /*!< bit: 9 Dual Input Buffer */ 53 uint32_t :2; /*!< bit: 10..11 Reserved */ 54 uint32_t UIHASH:1; /*!< bit: 12 User Initial Hash Value */ 55 uint32_t UALGO:3; /*!< bit: 13..15 User SHA Algorithm */ 56 uint32_t HAPROT:6; /*!< bit: 16..21 Region Hash Area Protection */ 57 uint32_t :2; /*!< bit: 22..23 Reserved */ 58 uint32_t DAPROT:6; /*!< bit: 24..29 Region Descriptor Area Protection */ 59 uint32_t :2; /*!< bit: 30..31 Reserved */ 60 } bit; /*!< Structure used for bit access */ 61 uint32_t reg; /*!< Type used for register access */ 62 } ICM_CFG_Type; 63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 #define ICM_CFG_OFFSET 0x00 /**< \brief (ICM_CFG offset) Configuration */ 66 #define ICM_CFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_CFG reset_value) Configuration */ 67 68 #define ICM_CFG_WBDIS_Pos 0 /**< \brief (ICM_CFG) Write Back Disable */ 69 #define ICM_CFG_WBDIS (_U_(0x1) << ICM_CFG_WBDIS_Pos) 70 #define ICM_CFG_EOMDIS_Pos 1 /**< \brief (ICM_CFG) End of Monitoring Disable */ 71 #define ICM_CFG_EOMDIS (_U_(0x1) << ICM_CFG_EOMDIS_Pos) 72 #define ICM_CFG_SLBDIS_Pos 2 /**< \brief (ICM_CFG) Secondary List Branching Disable */ 73 #define ICM_CFG_SLBDIS (_U_(0x1) << ICM_CFG_SLBDIS_Pos) 74 #define ICM_CFG_BBC_Pos 4 /**< \brief (ICM_CFG) Bus Burden Control */ 75 #define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos) 76 #define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)) 77 #define ICM_CFG_ASCD_Pos 8 /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ 78 #define ICM_CFG_ASCD (_U_(0x1) << ICM_CFG_ASCD_Pos) 79 #define ICM_CFG_DUALBUFF_Pos 9 /**< \brief (ICM_CFG) Dual Input Buffer */ 80 #define ICM_CFG_DUALBUFF (_U_(0x1) << ICM_CFG_DUALBUFF_Pos) 81 #define ICM_CFG_UIHASH_Pos 12 /**< \brief (ICM_CFG) User Initial Hash Value */ 82 #define ICM_CFG_UIHASH (_U_(0x1) << ICM_CFG_UIHASH_Pos) 83 #define ICM_CFG_UALGO_Pos 13 /**< \brief (ICM_CFG) User SHA Algorithm */ 84 #define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos) 85 #define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)) 86 #define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< \brief (ICM_CFG) SHA1 Algorithm */ 87 #define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< \brief (ICM_CFG) SHA256 Algorithm */ 88 #define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< \brief (ICM_CFG) SHA224 Algorithm */ 89 #define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos) 90 #define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos) 91 #define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos) 92 #define ICM_CFG_HAPROT_Pos 16 /**< \brief (ICM_CFG) Region Hash Area Protection */ 93 #define ICM_CFG_HAPROT_Msk (_U_(0x3F) << ICM_CFG_HAPROT_Pos) 94 #define ICM_CFG_HAPROT(value) (ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos)) 95 #define ICM_CFG_DAPROT_Pos 24 /**< \brief (ICM_CFG) Region Descriptor Area Protection */ 96 #define ICM_CFG_DAPROT_Msk (_U_(0x3F) << ICM_CFG_DAPROT_Pos) 97 #define ICM_CFG_DAPROT(value) (ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos)) 98 #define ICM_CFG_MASK _U_(0x3F3FF3F7) /**< \brief (ICM_CFG) MASK Register */ 99 100 /* -------- ICM_CTRL : (ICM Offset: 0x04) ( /W 32) Control -------- */ 101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 102 typedef union { 103 struct { 104 uint32_t ENABLE:1; /*!< bit: 0 ICM Enable */ 105 uint32_t DISABLE:1; /*!< bit: 1 ICM Disable Register */ 106 uint32_t SWRST:1; /*!< bit: 2 Software Reset */ 107 uint32_t :1; /*!< bit: 3 Reserved */ 108 uint32_t REHASH:4; /*!< bit: 4.. 7 Recompute Internal Hash */ 109 uint32_t RMDIS:4; /*!< bit: 8..11 Region Monitoring Disable */ 110 uint32_t RMEN:4; /*!< bit: 12..15 Region Monitoring Enable */ 111 uint32_t :16; /*!< bit: 16..31 Reserved */ 112 } bit; /*!< Structure used for bit access */ 113 uint32_t reg; /*!< Type used for register access */ 114 } ICM_CTRL_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 #define ICM_CTRL_OFFSET 0x04 /**< \brief (ICM_CTRL offset) Control */ 118 119 #define ICM_CTRL_ENABLE_Pos 0 /**< \brief (ICM_CTRL) ICM Enable */ 120 #define ICM_CTRL_ENABLE (_U_(0x1) << ICM_CTRL_ENABLE_Pos) 121 #define ICM_CTRL_DISABLE_Pos 1 /**< \brief (ICM_CTRL) ICM Disable Register */ 122 #define ICM_CTRL_DISABLE (_U_(0x1) << ICM_CTRL_DISABLE_Pos) 123 #define ICM_CTRL_SWRST_Pos 2 /**< \brief (ICM_CTRL) Software Reset */ 124 #define ICM_CTRL_SWRST (_U_(0x1) << ICM_CTRL_SWRST_Pos) 125 #define ICM_CTRL_REHASH_Pos 4 /**< \brief (ICM_CTRL) Recompute Internal Hash */ 126 #define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos) 127 #define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)) 128 #define ICM_CTRL_RMDIS_Pos 8 /**< \brief (ICM_CTRL) Region Monitoring Disable */ 129 #define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos) 130 #define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)) 131 #define ICM_CTRL_RMEN_Pos 12 /**< \brief (ICM_CTRL) Region Monitoring Enable */ 132 #define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos) 133 #define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)) 134 #define ICM_CTRL_MASK _U_(0x0000FFF7) /**< \brief (ICM_CTRL) MASK Register */ 135 136 /* -------- ICM_SR : (ICM Offset: 0x08) (R/ 32) Status -------- */ 137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 138 typedef union { 139 struct { 140 uint32_t ENABLE:1; /*!< bit: 0 ICM Controller Enable Register */ 141 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 142 uint32_t RAWRMDIS:4; /*!< bit: 8..11 RAW Region Monitoring Disabled Status */ 143 uint32_t RMDIS:4; /*!< bit: 12..15 Region Monitoring Disabled Status */ 144 uint32_t :16; /*!< bit: 16..31 Reserved */ 145 } bit; /*!< Structure used for bit access */ 146 uint32_t reg; /*!< Type used for register access */ 147 } ICM_SR_Type; 148 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 149 150 #define ICM_SR_OFFSET 0x08 /**< \brief (ICM_SR offset) Status */ 151 #define ICM_SR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_SR reset_value) Status */ 152 153 #define ICM_SR_ENABLE_Pos 0 /**< \brief (ICM_SR) ICM Controller Enable Register */ 154 #define ICM_SR_ENABLE (_U_(0x1) << ICM_SR_ENABLE_Pos) 155 #define ICM_SR_RAWRMDIS_Pos 8 /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */ 156 #define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos) 157 #define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)) 158 #define ICM_SR_RMDIS_Pos 12 /**< \brief (ICM_SR) Region Monitoring Disabled Status */ 159 #define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos) 160 #define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)) 161 #define ICM_SR_MASK _U_(0x0000FF01) /**< \brief (ICM_SR) MASK Register */ 162 163 /* -------- ICM_IER : (ICM Offset: 0x10) ( /W 32) Interrupt Enable -------- */ 164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 165 typedef union { 166 struct { 167 uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Enable */ 168 uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Enable */ 169 uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Enable */ 170 uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition detected Interrupt Enable */ 171 uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Enable */ 172 uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */ 173 uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Enable */ 174 uint32_t :7; /*!< bit: 25..31 Reserved */ 175 } bit; /*!< Structure used for bit access */ 176 uint32_t reg; /*!< Type used for register access */ 177 } ICM_IER_Type; 178 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 179 180 #define ICM_IER_OFFSET 0x10 /**< \brief (ICM_IER offset) Interrupt Enable */ 181 182 #define ICM_IER_RHC_Pos 0 /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ 183 #define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos) 184 #define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)) 185 #define ICM_IER_RDM_Pos 4 /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ 186 #define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos) 187 #define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)) 188 #define ICM_IER_RBE_Pos 8 /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ 189 #define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos) 190 #define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)) 191 #define ICM_IER_RWC_Pos 12 /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ 192 #define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos) 193 #define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)) 194 #define ICM_IER_REC_Pos 16 /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ 195 #define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos) 196 #define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)) 197 #define ICM_IER_RSU_Pos 20 /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ 198 #define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos) 199 #define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)) 200 #define ICM_IER_URAD_Pos 24 /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ 201 #define ICM_IER_URAD (_U_(0x1) << ICM_IER_URAD_Pos) 202 #define ICM_IER_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IER) MASK Register */ 203 204 /* -------- ICM_IDR : (ICM Offset: 0x14) ( /W 32) Interrupt Disable -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 struct { 208 uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Disable */ 209 uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Disable */ 210 uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Disable */ 211 uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Disable */ 212 uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition detected Interrupt Disable */ 213 uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Disable */ 214 uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Disable */ 215 uint32_t :7; /*!< bit: 25..31 Reserved */ 216 } bit; /*!< Structure used for bit access */ 217 uint32_t reg; /*!< Type used for register access */ 218 } ICM_IDR_Type; 219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 220 221 #define ICM_IDR_OFFSET 0x14 /**< \brief (ICM_IDR offset) Interrupt Disable */ 222 #define ICM_IDR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IDR reset_value) Interrupt Disable */ 223 224 #define ICM_IDR_RHC_Pos 0 /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ 225 #define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos) 226 #define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)) 227 #define ICM_IDR_RDM_Pos 4 /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ 228 #define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos) 229 #define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)) 230 #define ICM_IDR_RBE_Pos 8 /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ 231 #define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos) 232 #define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)) 233 #define ICM_IDR_RWC_Pos 12 /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ 234 #define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos) 235 #define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)) 236 #define ICM_IDR_REC_Pos 16 /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ 237 #define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos) 238 #define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)) 239 #define ICM_IDR_RSU_Pos 20 /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ 240 #define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos) 241 #define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)) 242 #define ICM_IDR_URAD_Pos 24 /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ 243 #define ICM_IDR_URAD (_U_(0x1) << ICM_IDR_URAD_Pos) 244 #define ICM_IDR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IDR) MASK Register */ 245 246 /* -------- ICM_IMR : (ICM Offset: 0x18) (R/ 32) Interrupt Mask -------- */ 247 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 248 typedef union { 249 struct { 250 uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed Interrupt Mask */ 251 uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch Interrupt Mask */ 252 uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error Interrupt Mask */ 253 uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected Interrupt Mask */ 254 uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected Interrupt Mask */ 255 uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Interrupt Mask */ 256 uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Interrupt Mask */ 257 uint32_t :7; /*!< bit: 25..31 Reserved */ 258 } bit; /*!< Structure used for bit access */ 259 uint32_t reg; /*!< Type used for register access */ 260 } ICM_IMR_Type; 261 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 262 263 #define ICM_IMR_OFFSET 0x18 /**< \brief (ICM_IMR offset) Interrupt Mask */ 264 #define ICM_IMR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_IMR reset_value) Interrupt Mask */ 265 266 #define ICM_IMR_RHC_Pos 0 /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ 267 #define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos) 268 #define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos)) 269 #define ICM_IMR_RDM_Pos 4 /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ 270 #define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos) 271 #define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos)) 272 #define ICM_IMR_RBE_Pos 8 /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ 273 #define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos) 274 #define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos)) 275 #define ICM_IMR_RWC_Pos 12 /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ 276 #define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos) 277 #define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos)) 278 #define ICM_IMR_REC_Pos 16 /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ 279 #define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos) 280 #define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos)) 281 #define ICM_IMR_RSU_Pos 20 /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ 282 #define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos) 283 #define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos)) 284 #define ICM_IMR_URAD_Pos 24 /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ 285 #define ICM_IMR_URAD (_U_(0x1) << ICM_IMR_URAD_Pos) 286 #define ICM_IMR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_IMR) MASK Register */ 287 288 /* -------- ICM_ISR : (ICM Offset: 0x1C) (R/ 32) Interrupt Status -------- */ 289 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 290 typedef union { 291 struct { 292 uint32_t RHC:4; /*!< bit: 0.. 3 Region Hash Completed */ 293 uint32_t RDM:4; /*!< bit: 4.. 7 Region Digest Mismatch */ 294 uint32_t RBE:4; /*!< bit: 8..11 Region Bus Error */ 295 uint32_t RWC:4; /*!< bit: 12..15 Region Wrap Condition Detected */ 296 uint32_t REC:4; /*!< bit: 16..19 Region End bit Condition Detected */ 297 uint32_t RSU:4; /*!< bit: 20..23 Region Status Updated Detected */ 298 uint32_t URAD:1; /*!< bit: 24 Undefined Register Access Detection Status */ 299 uint32_t :7; /*!< bit: 25..31 Reserved */ 300 } bit; /*!< Structure used for bit access */ 301 uint32_t reg; /*!< Type used for register access */ 302 } ICM_ISR_Type; 303 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 304 305 #define ICM_ISR_OFFSET 0x1C /**< \brief (ICM_ISR offset) Interrupt Status */ 306 #define ICM_ISR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_ISR reset_value) Interrupt Status */ 307 308 #define ICM_ISR_RHC_Pos 0 /**< \brief (ICM_ISR) Region Hash Completed */ 309 #define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos) 310 #define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos)) 311 #define ICM_ISR_RDM_Pos 4 /**< \brief (ICM_ISR) Region Digest Mismatch */ 312 #define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos) 313 #define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos)) 314 #define ICM_ISR_RBE_Pos 8 /**< \brief (ICM_ISR) Region Bus Error */ 315 #define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos) 316 #define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos)) 317 #define ICM_ISR_RWC_Pos 12 /**< \brief (ICM_ISR) Region Wrap Condition Detected */ 318 #define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos) 319 #define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos)) 320 #define ICM_ISR_REC_Pos 16 /**< \brief (ICM_ISR) Region End bit Condition Detected */ 321 #define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos) 322 #define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos)) 323 #define ICM_ISR_RSU_Pos 20 /**< \brief (ICM_ISR) Region Status Updated Detected */ 324 #define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos) 325 #define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos)) 326 #define ICM_ISR_URAD_Pos 24 /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ 327 #define ICM_ISR_URAD (_U_(0x1) << ICM_ISR_URAD_Pos) 328 #define ICM_ISR_MASK _U_(0x01FFFFFF) /**< \brief (ICM_ISR) MASK Register */ 329 330 /* -------- ICM_UASR : (ICM Offset: 0x20) (R/ 32) Undefined Access Status -------- */ 331 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 332 typedef union { 333 struct { 334 uint32_t URAT:3; /*!< bit: 0.. 2 Undefined Register Access Trace */ 335 uint32_t :29; /*!< bit: 3..31 Reserved */ 336 } bit; /*!< Structure used for bit access */ 337 uint32_t reg; /*!< Type used for register access */ 338 } ICM_UASR_Type; 339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 340 341 #define ICM_UASR_OFFSET 0x20 /**< \brief (ICM_UASR offset) Undefined Access Status */ 342 #define ICM_UASR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UASR reset_value) Undefined Access Status */ 343 344 #define ICM_UASR_URAT_Pos 0 /**< \brief (ICM_UASR) Undefined Register Access Trace */ 345 #define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos) 346 #define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos)) 347 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded */ 348 #define ICM_UASR_URAT_CFG_MODIFIED_Val _U_(0x1) /**< \brief (ICM_UASR) CFG modified during active monitoring */ 349 #define ICM_UASR_URAT_DSCR_MODIFIED_Val _U_(0x2) /**< \brief (ICM_UASR) DSCR modified during active monitoring */ 350 #define ICM_UASR_URAT_HASH_MODIFIED_Val _U_(0x3) /**< \brief (ICM_UASR) HASH modified during active monitoring */ 351 #define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< \brief (ICM_UASR) Write-only register read access */ 352 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos) 353 #define ICM_UASR_URAT_CFG_MODIFIED (ICM_UASR_URAT_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos) 354 #define ICM_UASR_URAT_DSCR_MODIFIED (ICM_UASR_URAT_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos) 355 #define ICM_UASR_URAT_HASH_MODIFIED (ICM_UASR_URAT_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos) 356 #define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos) 357 #define ICM_UASR_MASK _U_(0x00000007) /**< \brief (ICM_UASR) MASK Register */ 358 359 /* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address -------- */ 360 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 361 typedef union { 362 struct { 363 uint32_t :6; /*!< bit: 0.. 5 Reserved */ 364 uint32_t DASA:26; /*!< bit: 6..31 Descriptor Area Start Address */ 365 } bit; /*!< Structure used for bit access */ 366 uint32_t reg; /*!< Type used for register access */ 367 } ICM_DSCR_Type; 368 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 369 370 #define ICM_DSCR_OFFSET 0x30 /**< \brief (ICM_DSCR offset) Region Descriptor Area Start Address */ 371 #define ICM_DSCR_RESETVALUE _U_(0x00000000) /**< \brief (ICM_DSCR reset_value) Region Descriptor Area Start Address */ 372 373 #define ICM_DSCR_DASA_Pos 6 /**< \brief (ICM_DSCR) Descriptor Area Start Address */ 374 #define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos) 375 #define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)) 376 #define ICM_DSCR_MASK _U_(0xFFFFFFC0) /**< \brief (ICM_DSCR) MASK Register */ 377 378 /* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address -------- */ 379 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 380 typedef union { 381 struct { 382 uint32_t :7; /*!< bit: 0.. 6 Reserved */ 383 uint32_t HASA:25; /*!< bit: 7..31 Hash Area Start Address */ 384 } bit; /*!< Structure used for bit access */ 385 uint32_t reg; /*!< Type used for register access */ 386 } ICM_HASH_Type; 387 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 388 389 #define ICM_HASH_OFFSET 0x34 /**< \brief (ICM_HASH offset) Region Hash Area Start Address */ 390 #define ICM_HASH_RESETVALUE _U_(0x00000000) /**< \brief (ICM_HASH reset_value) Region Hash Area Start Address */ 391 392 #define ICM_HASH_HASA_Pos 7 /**< \brief (ICM_HASH) Hash Area Start Address */ 393 #define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos) 394 #define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)) 395 #define ICM_HASH_MASK _U_(0xFFFFFF80) /**< \brief (ICM_HASH) MASK Register */ 396 397 /* -------- ICM_UIHVAL : (ICM Offset: 0x38) ( /W 32) User Initial Hash Value n -------- */ 398 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 399 typedef union { 400 struct { 401 uint32_t VAL:32; /*!< bit: 0..31 Initial Hash Value */ 402 } bit; /*!< Structure used for bit access */ 403 uint32_t reg; /*!< Type used for register access */ 404 } ICM_UIHVAL_Type; 405 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 406 407 #define ICM_UIHVAL_OFFSET 0x38 /**< \brief (ICM_UIHVAL offset) User Initial Hash Value n */ 408 #define ICM_UIHVAL_RESETVALUE _U_(0x00000000) /**< \brief (ICM_UIHVAL reset_value) User Initial Hash Value n */ 409 410 #define ICM_UIHVAL_VAL_Pos 0 /**< \brief (ICM_UIHVAL) Initial Hash Value */ 411 #define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos) 412 #define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)) 413 #define ICM_UIHVAL_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_UIHVAL) MASK Register */ 414 415 /* -------- ICM_RADDR : (ICM Offset: 0x00) (R/W 32) Region Start Address -------- */ 416 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 417 typedef union { 418 uint32_t reg; /*!< Type used for register access */ 419 } ICM_RADDR_Type; 420 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 421 422 #define ICM_RADDR_OFFSET 0x00 /**< \brief (ICM_RADDR offset) Region Start Address */ 423 #define ICM_RADDR_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RADDR) MASK Register */ 424 425 /* -------- ICM_RCFG : (ICM Offset: 0x04) (R/W 32) Region Configuration -------- */ 426 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 427 typedef union { 428 struct { 429 uint32_t CDWBN:1; /*!< bit: 0 Compare Digest Write Back */ 430 uint32_t WRAP:1; /*!< bit: 1 Region Wrap */ 431 uint32_t EOM:1; /*!< bit: 2 End of Monitoring */ 432 uint32_t :1; /*!< bit: 3 Reserved */ 433 uint32_t RHIEN:1; /*!< bit: 4 Region Hash Interrupt Enable */ 434 uint32_t DMIEN:1; /*!< bit: 5 Region Digest Mismatch Interrupt Enable */ 435 uint32_t BEIEN:1; /*!< bit: 6 Region Bus Error Interrupt Enable */ 436 uint32_t WCIEN:1; /*!< bit: 7 Region Wrap Condition Detected Interrupt Enable */ 437 uint32_t ECIEN:1; /*!< bit: 8 Region End bit Condition detected Interrupt Enable */ 438 uint32_t SUIEN:1; /*!< bit: 9 Region Status Updated Interrupt Enable */ 439 uint32_t PROCDLY:1; /*!< bit: 10 SHA Processing Delay */ 440 uint32_t :1; /*!< bit: 11 Reserved */ 441 uint32_t ALGO:3; /*!< bit: 12..14 SHA Algorithm */ 442 uint32_t :9; /*!< bit: 15..23 Reserved */ 443 uint32_t MRPROT:6; /*!< bit: 24..29 Memory Region AHB Protection */ 444 uint32_t :2; /*!< bit: 30..31 Reserved */ 445 } bit; /*!< Structure used for bit access */ 446 uint32_t reg; /*!< Type used for register access */ 447 } ICM_RCFG_Type; 448 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 449 450 #define ICM_RCFG_OFFSET 0x04 /**< \brief (ICM_RCFG offset) Region Configuration */ 451 #define ICM_RCFG_RESETVALUE _U_(0x00000000) /**< \brief (ICM_RCFG reset_value) Region Configuration */ 452 453 #define ICM_RCFG_CDWBN_Pos 0 /**< \brief (ICM_RCFG) Compare Digest Write Back */ 454 #define ICM_RCFG_CDWBN (_U_(0x1) << ICM_RCFG_CDWBN_Pos) 455 #define ICM_RCFG_CDWBN_WRBA_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 456 #define ICM_RCFG_CDWBN_COMP_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 457 #define ICM_RCFG_CDWBN_WRBA (ICM_RCFG_CDWBN_WRBA_Val << ICM_RCFG_CDWBN_Pos) 458 #define ICM_RCFG_CDWBN_COMP (ICM_RCFG_CDWBN_COMP_Val << ICM_RCFG_CDWBN_Pos) 459 #define ICM_RCFG_WRAP_Pos 1 /**< \brief (ICM_RCFG) Region Wrap */ 460 #define ICM_RCFG_WRAP (_U_(0x1) << ICM_RCFG_WRAP_Pos) 461 #define ICM_RCFG_WRAP_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 462 #define ICM_RCFG_WRAP_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 463 #define ICM_RCFG_WRAP_NO (ICM_RCFG_WRAP_NO_Val << ICM_RCFG_WRAP_Pos) 464 #define ICM_RCFG_WRAP_YES (ICM_RCFG_WRAP_YES_Val << ICM_RCFG_WRAP_Pos) 465 #define ICM_RCFG_EOM_Pos 2 /**< \brief (ICM_RCFG) End of Monitoring */ 466 #define ICM_RCFG_EOM (_U_(0x1) << ICM_RCFG_EOM_Pos) 467 #define ICM_RCFG_EOM_NO_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 468 #define ICM_RCFG_EOM_YES_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 469 #define ICM_RCFG_EOM_NO (ICM_RCFG_EOM_NO_Val << ICM_RCFG_EOM_Pos) 470 #define ICM_RCFG_EOM_YES (ICM_RCFG_EOM_YES_Val << ICM_RCFG_EOM_Pos) 471 #define ICM_RCFG_RHIEN_Pos 4 /**< \brief (ICM_RCFG) Region Hash Interrupt Enable */ 472 #define ICM_RCFG_RHIEN (_U_(0x1) << ICM_RCFG_RHIEN_Pos) 473 #define ICM_RCFG_RHIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 474 #define ICM_RCFG_RHIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 475 #define ICM_RCFG_RHIEN_EN (ICM_RCFG_RHIEN_EN_Val << ICM_RCFG_RHIEN_Pos) 476 #define ICM_RCFG_RHIEN_DIS (ICM_RCFG_RHIEN_DIS_Val << ICM_RCFG_RHIEN_Pos) 477 #define ICM_RCFG_DMIEN_Pos 5 /**< \brief (ICM_RCFG) Region Digest Mismatch Interrupt Enable */ 478 #define ICM_RCFG_DMIEN (_U_(0x1) << ICM_RCFG_DMIEN_Pos) 479 #define ICM_RCFG_DMIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 480 #define ICM_RCFG_DMIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 481 #define ICM_RCFG_DMIEN_EN (ICM_RCFG_DMIEN_EN_Val << ICM_RCFG_DMIEN_Pos) 482 #define ICM_RCFG_DMIEN_DIS (ICM_RCFG_DMIEN_DIS_Val << ICM_RCFG_DMIEN_Pos) 483 #define ICM_RCFG_BEIEN_Pos 6 /**< \brief (ICM_RCFG) Region Bus Error Interrupt Enable */ 484 #define ICM_RCFG_BEIEN (_U_(0x1) << ICM_RCFG_BEIEN_Pos) 485 #define ICM_RCFG_BEIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 486 #define ICM_RCFG_BEIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 487 #define ICM_RCFG_BEIEN_EN (ICM_RCFG_BEIEN_EN_Val << ICM_RCFG_BEIEN_Pos) 488 #define ICM_RCFG_BEIEN_DIS (ICM_RCFG_BEIEN_DIS_Val << ICM_RCFG_BEIEN_Pos) 489 #define ICM_RCFG_WCIEN_Pos 7 /**< \brief (ICM_RCFG) Region Wrap Condition Detected Interrupt Enable */ 490 #define ICM_RCFG_WCIEN (_U_(0x1) << ICM_RCFG_WCIEN_Pos) 491 #define ICM_RCFG_WCIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 492 #define ICM_RCFG_WCIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 493 #define ICM_RCFG_WCIEN_EN (ICM_RCFG_WCIEN_EN_Val << ICM_RCFG_WCIEN_Pos) 494 #define ICM_RCFG_WCIEN_DIS (ICM_RCFG_WCIEN_DIS_Val << ICM_RCFG_WCIEN_Pos) 495 #define ICM_RCFG_ECIEN_Pos 8 /**< \brief (ICM_RCFG) Region End bit Condition detected Interrupt Enable */ 496 #define ICM_RCFG_ECIEN (_U_(0x1) << ICM_RCFG_ECIEN_Pos) 497 #define ICM_RCFG_ECIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 498 #define ICM_RCFG_ECIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 499 #define ICM_RCFG_ECIEN_EN (ICM_RCFG_ECIEN_EN_Val << ICM_RCFG_ECIEN_Pos) 500 #define ICM_RCFG_ECIEN_DIS (ICM_RCFG_ECIEN_DIS_Val << ICM_RCFG_ECIEN_Pos) 501 #define ICM_RCFG_SUIEN_Pos 9 /**< \brief (ICM_RCFG) Region Status Updated Interrupt Enable */ 502 #define ICM_RCFG_SUIEN (_U_(0x1) << ICM_RCFG_SUIEN_Pos) 503 #define ICM_RCFG_SUIEN_EN_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 504 #define ICM_RCFG_SUIEN_DIS_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 505 #define ICM_RCFG_SUIEN_EN (ICM_RCFG_SUIEN_EN_Val << ICM_RCFG_SUIEN_Pos) 506 #define ICM_RCFG_SUIEN_DIS (ICM_RCFG_SUIEN_DIS_Val << ICM_RCFG_SUIEN_Pos) 507 #define ICM_RCFG_PROCDLY_Pos 10 /**< \brief (ICM_RCFG) SHA Processing Delay */ 508 #define ICM_RCFG_PROCDLY (_U_(0x1) << ICM_RCFG_PROCDLY_Pos) 509 #define ICM_RCFG_PROCDLY_SHORT_Val _U_(0x0) /**< \brief (ICM_RCFG) */ 510 #define ICM_RCFG_PROCDLY_LONG_Val _U_(0x1) /**< \brief (ICM_RCFG) */ 511 #define ICM_RCFG_PROCDLY_SHORT (ICM_RCFG_PROCDLY_SHORT_Val << ICM_RCFG_PROCDLY_Pos) 512 #define ICM_RCFG_PROCDLY_LONG (ICM_RCFG_PROCDLY_LONG_Val << ICM_RCFG_PROCDLY_Pos) 513 #define ICM_RCFG_ALGO_Pos 12 /**< \brief (ICM_RCFG) SHA Algorithm */ 514 #define ICM_RCFG_ALGO_Msk (_U_(0x7) << ICM_RCFG_ALGO_Pos) 515 #define ICM_RCFG_ALGO(value) (ICM_RCFG_ALGO_Msk & ((value) << ICM_RCFG_ALGO_Pos)) 516 #define ICM_RCFG_MRPROT_Pos 24 /**< \brief (ICM_RCFG) Memory Region AHB Protection */ 517 #define ICM_RCFG_MRPROT_Msk (_U_(0x3F) << ICM_RCFG_MRPROT_Pos) 518 #define ICM_RCFG_MRPROT(value) (ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos)) 519 #define ICM_RCFG_MASK _U_(0x3F0077F7) /**< \brief (ICM_RCFG) MASK Register */ 520 521 /* -------- ICM_RCTRL : (ICM Offset: 0x08) (R/W 32) Region Control -------- */ 522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 523 typedef union { 524 struct { 525 uint32_t TRSIZE:16; /*!< bit: 0..15 Transfer Size */ 526 uint32_t :16; /*!< bit: 16..31 Reserved */ 527 } bit; /*!< Structure used for bit access */ 528 uint32_t reg; /*!< Type used for register access */ 529 } ICM_RCTRL_Type; 530 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 531 532 #define ICM_RCTRL_OFFSET 0x08 /**< \brief (ICM_RCTRL offset) Region Control */ 533 534 #define ICM_RCTRL_TRSIZE_Pos 0 /**< \brief (ICM_RCTRL) Transfer Size */ 535 #define ICM_RCTRL_TRSIZE_Msk (_U_(0xFFFF) << ICM_RCTRL_TRSIZE_Pos) 536 #define ICM_RCTRL_TRSIZE(value) (ICM_RCTRL_TRSIZE_Msk & ((value) << ICM_RCTRL_TRSIZE_Pos)) 537 #define ICM_RCTRL_MASK _U_(0x0000FFFF) /**< \brief (ICM_RCTRL) MASK Register */ 538 539 /* -------- ICM_RNEXT : (ICM Offset: 0x0C) (R/W 32) Region Next Address -------- */ 540 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 541 typedef union { 542 uint32_t reg; /*!< Type used for register access */ 543 } ICM_RNEXT_Type; 544 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 545 546 #define ICM_RNEXT_OFFSET 0x0C /**< \brief (ICM_RNEXT offset) Region Next Address */ 547 #define ICM_RNEXT_MASK _U_(0xFFFFFFFF) /**< \brief (ICM_RNEXT) MASK Register */ 548 549 /** \brief ICM APB hardware registers */ 550 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 551 typedef struct { 552 __IO ICM_CFG_Type CFG; /**< \brief Offset: 0x00 (R/W 32) Configuration */ 553 __O ICM_CTRL_Type CTRL; /**< \brief Offset: 0x04 ( /W 32) Control */ 554 __I ICM_SR_Type SR; /**< \brief Offset: 0x08 (R/ 32) Status */ 555 RoReg8 Reserved1[0x4]; 556 __O ICM_IER_Type IER; /**< \brief Offset: 0x10 ( /W 32) Interrupt Enable */ 557 __O ICM_IDR_Type IDR; /**< \brief Offset: 0x14 ( /W 32) Interrupt Disable */ 558 __I ICM_IMR_Type IMR; /**< \brief Offset: 0x18 (R/ 32) Interrupt Mask */ 559 __I ICM_ISR_Type ISR; /**< \brief Offset: 0x1C (R/ 32) Interrupt Status */ 560 __I ICM_UASR_Type UASR; /**< \brief Offset: 0x20 (R/ 32) Undefined Access Status */ 561 RoReg8 Reserved2[0xC]; 562 __IO ICM_DSCR_Type DSCR; /**< \brief Offset: 0x30 (R/W 32) Region Descriptor Area Start Address */ 563 __IO ICM_HASH_Type HASH; /**< \brief Offset: 0x34 (R/W 32) Region Hash Area Start Address */ 564 __O ICM_UIHVAL_Type UIHVAL[8]; /**< \brief Offset: 0x38 ( /W 32) User Initial Hash Value n */ 565 } Icm; 566 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 567 568 /** \brief ICM Descriptor SRAM registers */ 569 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 570 typedef struct { 571 __IO ICM_RADDR_Type RADDR; /**< \brief Offset: 0x00 (R/W 32) Region Start Address */ 572 __IO ICM_RCFG_Type RCFG; /**< \brief Offset: 0x04 (R/W 32) Region Configuration */ 573 __IO ICM_RCTRL_Type RCTRL; /**< \brief Offset: 0x08 (R/W 32) Region Control */ 574 __IO ICM_RNEXT_Type RNEXT; /**< \brief Offset: 0x0C (R/W 32) Region Next Address */ 575 } IcmDescriptor; 576 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 577 578 #define SECTION_ICM_DESCRIPTOR 579 580 /*@}*/ 581 582 #endif /* _SAMD51_ICM_COMPONENT_ */ 583
