1 /** 2 * \file 3 * 4 * \brief Component description for AC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAMD21_AC_COMPONENT_ 30 #define _SAMD21_AC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR AC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAMD21_AC Analog Comparators */ 36 /*@{*/ 37 38 #define AC_U2205 39 #define REV_AC 0x111 40 41 /* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ 48 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 49 uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } AC_CTRLA_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ 56 #define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ 57 58 #define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ 59 #define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) 60 #define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ 61 #define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) 62 #define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ 63 #define AC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << AC_CTRLA_RUNSTDBY_Pos) 64 #define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) 65 #define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ 66 #define AC_CTRLA_LPMUX (_U_(0x1) << AC_CTRLA_LPMUX_Pos) 67 #define AC_CTRLA_MASK _U_(0x87) /**< \brief (AC_CTRLA) MASK Register */ 68 69 /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ 70 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 71 typedef union { 72 struct { 73 uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ 74 uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ 75 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 76 } bit; /*!< Structure used for bit access */ 77 struct { 78 uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ 79 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 80 } vec; /*!< Structure used for vec access */ 81 uint8_t reg; /*!< Type used for register access */ 82 } AC_CTRLB_Type; 83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 84 85 #define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ 86 #define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ 87 88 #define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ 89 #define AC_CTRLB_START0 (1 << AC_CTRLB_START0_Pos) 90 #define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ 91 #define AC_CTRLB_START1 (1 << AC_CTRLB_START1_Pos) 92 #define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ 93 #define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) 94 #define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) 95 #define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ 96 97 /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ 98 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 99 typedef union { 100 struct { 101 uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ 102 uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ 103 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 104 uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ 105 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 106 uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ 107 uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ 108 uint16_t :6; /*!< bit: 10..15 Reserved */ 109 } bit; /*!< Structure used for bit access */ 110 struct { 111 uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ 112 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 113 uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ 114 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 115 uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ 116 uint16_t :6; /*!< bit: 10..15 Reserved */ 117 } vec; /*!< Structure used for vec access */ 118 uint16_t reg; /*!< Type used for register access */ 119 } AC_EVCTRL_Type; 120 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 121 122 #define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ 123 #define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ 124 125 #define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ 126 #define AC_EVCTRL_COMPEO0 (1 << AC_EVCTRL_COMPEO0_Pos) 127 #define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ 128 #define AC_EVCTRL_COMPEO1 (1 << AC_EVCTRL_COMPEO1_Pos) 129 #define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ 130 #define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) 131 #define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) 132 #define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ 133 #define AC_EVCTRL_WINEO0 (1 << AC_EVCTRL_WINEO0_Pos) 134 #define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ 135 #define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) 136 #define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) 137 #define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ 138 #define AC_EVCTRL_COMPEI0 (1 << AC_EVCTRL_COMPEI0_Pos) 139 #define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ 140 #define AC_EVCTRL_COMPEI1 (1 << AC_EVCTRL_COMPEI1_Pos) 141 #define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ 142 #define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) 143 #define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) 144 #define AC_EVCTRL_MASK _U_(0x0313) /**< \brief (AC_EVCTRL) MASK Register */ 145 146 /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 147 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 148 typedef union { 149 struct { 150 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ 151 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ 152 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 153 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ 154 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 155 } bit; /*!< Structure used for bit access */ 156 struct { 157 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ 158 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 159 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ 160 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 161 } vec; /*!< Structure used for vec access */ 162 uint8_t reg; /*!< Type used for register access */ 163 } AC_INTENCLR_Type; 164 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 165 166 #define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ 167 #define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ 168 169 #define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ 170 #define AC_INTENCLR_COMP0 (1 << AC_INTENCLR_COMP0_Pos) 171 #define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ 172 #define AC_INTENCLR_COMP1 (1 << AC_INTENCLR_COMP1_Pos) 173 #define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ 174 #define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) 175 #define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) 176 #define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ 177 #define AC_INTENCLR_WIN0 (1 << AC_INTENCLR_WIN0_Pos) 178 #define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ 179 #define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) 180 #define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) 181 #define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ 182 183 /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 184 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 185 typedef union { 186 struct { 187 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ 188 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ 189 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 190 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ 191 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 192 } bit; /*!< Structure used for bit access */ 193 struct { 194 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ 195 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 196 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ 197 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 198 } vec; /*!< Structure used for vec access */ 199 uint8_t reg; /*!< Type used for register access */ 200 } AC_INTENSET_Type; 201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 202 203 #define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ 204 #define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ 205 206 #define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ 207 #define AC_INTENSET_COMP0 (1 << AC_INTENSET_COMP0_Pos) 208 #define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ 209 #define AC_INTENSET_COMP1 (1 << AC_INTENSET_COMP1_Pos) 210 #define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ 211 #define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) 212 #define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) 213 #define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ 214 #define AC_INTENSET_WIN0 (1 << AC_INTENSET_WIN0_Pos) 215 #define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ 216 #define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) 217 #define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) 218 #define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ 219 220 /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 221 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 222 typedef union { // __I to avoid read-modify-write on write-to-clear register 223 struct { 224 __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ 225 __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ 226 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 227 __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ 228 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ 229 } bit; /*!< Structure used for bit access */ 230 struct { 231 __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ 232 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 233 __I uint8_t WIN:1; /*!< bit: 4 Window x */ 234 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ 235 } vec; /*!< Structure used for vec access */ 236 uint8_t reg; /*!< Type used for register access */ 237 } AC_INTFLAG_Type; 238 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 239 240 #define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ 241 #define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 242 243 #define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ 244 #define AC_INTFLAG_COMP0 (1 << AC_INTFLAG_COMP0_Pos) 245 #define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ 246 #define AC_INTFLAG_COMP1 (1 << AC_INTFLAG_COMP1_Pos) 247 #define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ 248 #define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) 249 #define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) 250 #define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ 251 #define AC_INTFLAG_WIN0 (1 << AC_INTFLAG_WIN0_Pos) 252 #define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ 253 #define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) 254 #define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) 255 #define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ 256 257 /* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ 258 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 259 typedef union { 260 struct { 261 uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ 262 uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ 263 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 264 uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ 265 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 266 } bit; /*!< Structure used for bit access */ 267 struct { 268 uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ 269 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 270 } vec; /*!< Structure used for vec access */ 271 uint8_t reg; /*!< Type used for register access */ 272 } AC_STATUSA_Type; 273 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 274 275 #define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ 276 #define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ 277 278 #define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ 279 #define AC_STATUSA_STATE0 (1 << AC_STATUSA_STATE0_Pos) 280 #define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ 281 #define AC_STATUSA_STATE1 (1 << AC_STATUSA_STATE1_Pos) 282 #define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ 283 #define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) 284 #define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) 285 #define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ 286 #define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) 287 #define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) 288 #define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ 289 #define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ 290 #define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ 291 #define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) 292 #define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) 293 #define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) 294 #define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ 295 296 /* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ 297 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 298 typedef union { 299 struct { 300 uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ 301 uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ 302 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 303 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ 304 } bit; /*!< Structure used for bit access */ 305 struct { 306 uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ 307 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 308 } vec; /*!< Structure used for vec access */ 309 uint8_t reg; /*!< Type used for register access */ 310 } AC_STATUSB_Type; 311 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 312 313 #define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ 314 #define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ 315 316 #define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ 317 #define AC_STATUSB_READY0 (1 << AC_STATUSB_READY0_Pos) 318 #define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ 319 #define AC_STATUSB_READY1 (1 << AC_STATUSB_READY1_Pos) 320 #define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ 321 #define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) 322 #define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) 323 #define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ 324 #define AC_STATUSB_SYNCBUSY (_U_(0x1) << AC_STATUSB_SYNCBUSY_Pos) 325 #define AC_STATUSB_MASK _U_(0x83) /**< \brief (AC_STATUSB) MASK Register */ 326 327 /* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ 328 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 329 typedef union { 330 struct { 331 uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ 332 uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ 333 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 334 uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ 335 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 336 } bit; /*!< Structure used for bit access */ 337 struct { 338 uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ 339 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 340 } vec; /*!< Structure used for vec access */ 341 uint8_t reg; /*!< Type used for register access */ 342 } AC_STATUSC_Type; 343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 344 345 #define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ 346 #define AC_STATUSC_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSC reset_value) Status C */ 347 348 #define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ 349 #define AC_STATUSC_STATE0 (1 << AC_STATUSC_STATE0_Pos) 350 #define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ 351 #define AC_STATUSC_STATE1 (1 << AC_STATUSC_STATE1_Pos) 352 #define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ 353 #define AC_STATUSC_STATE_Msk (_U_(0x3) << AC_STATUSC_STATE_Pos) 354 #define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) 355 #define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ 356 #define AC_STATUSC_WSTATE0_Msk (_U_(0x3) << AC_STATUSC_WSTATE0_Pos) 357 #define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) 358 #define AC_STATUSC_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSC) Signal is above window */ 359 #define AC_STATUSC_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSC) Signal is inside window */ 360 #define AC_STATUSC_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSC) Signal is below window */ 361 #define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) 362 #define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) 363 #define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) 364 #define AC_STATUSC_MASK _U_(0x33) /**< \brief (AC_STATUSC) MASK Register */ 365 366 /* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ 367 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 368 typedef union { 369 struct { 370 uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ 371 uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ 372 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 373 } bit; /*!< Structure used for bit access */ 374 uint8_t reg; /*!< Type used for register access */ 375 } AC_WINCTRL_Type; 376 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 377 378 #define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ 379 #define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ 380 381 #define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ 382 #define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) 383 #define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ 384 #define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) 385 #define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) 386 #define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ 387 #define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ 388 #define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ 389 #define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ 390 #define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) 391 #define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) 392 #define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) 393 #define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) 394 #define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ 395 396 /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ 397 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 398 typedef union { 399 struct { 400 uint32_t ENABLE:1; /*!< bit: 0 Enable */ 401 uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ 402 uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ 403 uint32_t :1; /*!< bit: 4 Reserved */ 404 uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ 405 uint32_t :1; /*!< bit: 7 Reserved */ 406 uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ 407 uint32_t :1; /*!< bit: 11 Reserved */ 408 uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ 409 uint32_t :1; /*!< bit: 14 Reserved */ 410 uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ 411 uint32_t OUT:2; /*!< bit: 16..17 Output */ 412 uint32_t :1; /*!< bit: 18 Reserved */ 413 uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ 414 uint32_t :4; /*!< bit: 20..23 Reserved */ 415 uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ 416 uint32_t :5; /*!< bit: 27..31 Reserved */ 417 } bit; /*!< Structure used for bit access */ 418 uint32_t reg; /*!< Type used for register access */ 419 } AC_COMPCTRL_Type; 420 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 421 422 #define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ 423 #define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ 424 425 #define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ 426 #define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) 427 #define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ 428 #define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) 429 #define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ 430 #define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) 431 #define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) 432 #define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */ 433 #define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x1) /**< \brief (AC_COMPCTRL) High speed */ 434 #define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) 435 #define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) 436 #define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ 437 #define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) 438 #define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) 439 #define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ 440 #define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ 441 #define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ 442 #define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ 443 #define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) 444 #define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) 445 #define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) 446 #define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) 447 #define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ 448 #define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) 449 #define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) 450 #define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ 451 #define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ 452 #define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ 453 #define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ 454 #define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ 455 #define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ 456 #define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ 457 #define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ 458 #define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) 459 #define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) 460 #define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) 461 #define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) 462 #define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) 463 #define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) 464 #define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) 465 #define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) 466 #define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ 467 #define AC_COMPCTRL_MUXPOS_Msk (_U_(0x3) << AC_COMPCTRL_MUXPOS_Pos) 468 #define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) 469 #define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ 470 #define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ 471 #define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ 472 #define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ 473 #define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) 474 #define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) 475 #define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) 476 #define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) 477 #define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ 478 #define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) 479 #define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ 480 #define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) 481 #define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) 482 #define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ 483 #define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ 484 #define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ 485 #define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) 486 #define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) 487 #define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) 488 #define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ 489 #define AC_COMPCTRL_HYST (_U_(0x1) << AC_COMPCTRL_HYST_Pos) 490 #define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ 491 #define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) 492 #define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) 493 #define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ 494 #define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ 495 #define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ 496 #define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) 497 #define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) 498 #define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) 499 #define AC_COMPCTRL_MASK _U_(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */ 500 501 /* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ 502 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 503 typedef union { 504 struct { 505 uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ 506 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 507 } bit; /*!< Structure used for bit access */ 508 uint8_t reg; /*!< Type used for register access */ 509 } AC_SCALER_Type; 510 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 511 512 #define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ 513 #define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ 514 515 #define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ 516 #define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) 517 #define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) 518 #define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ 519 520 /** \brief AC hardware registers */ 521 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 522 typedef struct { 523 __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 524 __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ 525 __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ 526 __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 527 __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 528 __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 529 RoReg8 Reserved1[0x1]; 530 __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ 531 __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ 532 __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ 533 RoReg8 Reserved2[0x1]; 534 __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ 535 RoReg8 Reserved3[0x3]; 536 __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ 537 RoReg8 Reserved4[0x8]; 538 __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ 539 } Ac; 540 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 541 542 /*@}*/ 543 544 #endif /* _SAMD21_AC_COMPONENT_ */ 545
