1 /** 2 * \file 3 * 4 * \brief Component description for RTC 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_RTC_COMPONENT_ 31 #define _SAMD20_RTC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR RTC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMD20_RTC Real-Time Counter */ 37 /*@{*/ 38 39 #define RTC_U2202 40 #define REV_RTC 0x101 41 42 /* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 49 uint16_t :3; /*!< bit: 4.. 6 Reserved */ 50 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ 51 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 52 uint16_t :4; /*!< bit: 12..15 Reserved */ 53 } bit; /*!< Structure used for bit access */ 54 uint16_t reg; /*!< Type used for register access */ 55 } RTC_MODE0_CTRL_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 #define RTC_MODE0_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE0_CTRL offset) MODE0 Control */ 59 #define RTC_MODE0_CTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_CTRL reset_value) MODE0 Control */ 60 61 #define RTC_MODE0_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE0_CTRL) Software Reset */ 62 #define RTC_MODE0_CTRL_SWRST (_U_(0x1) << RTC_MODE0_CTRL_SWRST_Pos) 63 #define RTC_MODE0_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE0_CTRL) Enable */ 64 #define RTC_MODE0_CTRL_ENABLE (_U_(0x1) << RTC_MODE0_CTRL_ENABLE_Pos) 65 #define RTC_MODE0_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE0_CTRL) Operating Mode */ 66 #define RTC_MODE0_CTRL_MODE_Msk (_U_(0x3) << RTC_MODE0_CTRL_MODE_Pos) 67 #define RTC_MODE0_CTRL_MODE(value) (RTC_MODE0_CTRL_MODE_Msk & ((value) << RTC_MODE0_CTRL_MODE_Pos)) 68 #define RTC_MODE0_CTRL_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRL) Mode 0: 32-bit Counter */ 69 #define RTC_MODE0_CTRL_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRL) Mode 1: 16-bit Counter */ 70 #define RTC_MODE0_CTRL_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRL) Mode 2: Clock/Calendar */ 71 #define RTC_MODE0_CTRL_MODE_COUNT32 (RTC_MODE0_CTRL_MODE_COUNT32_Val << RTC_MODE0_CTRL_MODE_Pos) 72 #define RTC_MODE0_CTRL_MODE_COUNT16 (RTC_MODE0_CTRL_MODE_COUNT16_Val << RTC_MODE0_CTRL_MODE_Pos) 73 #define RTC_MODE0_CTRL_MODE_CLOCK (RTC_MODE0_CTRL_MODE_CLOCK_Val << RTC_MODE0_CTRL_MODE_Pos) 74 #define RTC_MODE0_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE0_CTRL) Clear on Match */ 75 #define RTC_MODE0_CTRL_MATCHCLR (_U_(0x1) << RTC_MODE0_CTRL_MATCHCLR_Pos) 76 #define RTC_MODE0_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE0_CTRL) Prescaler */ 77 #define RTC_MODE0_CTRL_PRESCALER_Msk (_U_(0xF) << RTC_MODE0_CTRL_PRESCALER_Pos) 78 #define RTC_MODE0_CTRL_PRESCALER(value) (RTC_MODE0_CTRL_PRESCALER_Msk & ((value) << RTC_MODE0_CTRL_PRESCALER_Pos)) 79 #define RTC_MODE0_CTRL_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ 80 #define RTC_MODE0_CTRL_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ 81 #define RTC_MODE0_CTRL_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ 82 #define RTC_MODE0_CTRL_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ 83 #define RTC_MODE0_CTRL_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ 84 #define RTC_MODE0_CTRL_PRESCALER_DIV32_Val _U_(0x5) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ 85 #define RTC_MODE0_CTRL_PRESCALER_DIV64_Val _U_(0x6) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ 86 #define RTC_MODE0_CTRL_PRESCALER_DIV128_Val _U_(0x7) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ 87 #define RTC_MODE0_CTRL_PRESCALER_DIV256_Val _U_(0x8) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ 88 #define RTC_MODE0_CTRL_PRESCALER_DIV512_Val _U_(0x9) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ 89 #define RTC_MODE0_CTRL_PRESCALER_DIV1024_Val _U_(0xA) /**< \brief (RTC_MODE0_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ 90 #define RTC_MODE0_CTRL_PRESCALER_DIV1 (RTC_MODE0_CTRL_PRESCALER_DIV1_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 91 #define RTC_MODE0_CTRL_PRESCALER_DIV2 (RTC_MODE0_CTRL_PRESCALER_DIV2_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 92 #define RTC_MODE0_CTRL_PRESCALER_DIV4 (RTC_MODE0_CTRL_PRESCALER_DIV4_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 93 #define RTC_MODE0_CTRL_PRESCALER_DIV8 (RTC_MODE0_CTRL_PRESCALER_DIV8_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 94 #define RTC_MODE0_CTRL_PRESCALER_DIV16 (RTC_MODE0_CTRL_PRESCALER_DIV16_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 95 #define RTC_MODE0_CTRL_PRESCALER_DIV32 (RTC_MODE0_CTRL_PRESCALER_DIV32_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 96 #define RTC_MODE0_CTRL_PRESCALER_DIV64 (RTC_MODE0_CTRL_PRESCALER_DIV64_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 97 #define RTC_MODE0_CTRL_PRESCALER_DIV128 (RTC_MODE0_CTRL_PRESCALER_DIV128_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 98 #define RTC_MODE0_CTRL_PRESCALER_DIV256 (RTC_MODE0_CTRL_PRESCALER_DIV256_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 99 #define RTC_MODE0_CTRL_PRESCALER_DIV512 (RTC_MODE0_CTRL_PRESCALER_DIV512_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 100 #define RTC_MODE0_CTRL_PRESCALER_DIV1024 (RTC_MODE0_CTRL_PRESCALER_DIV1024_Val << RTC_MODE0_CTRL_PRESCALER_Pos) 101 #define RTC_MODE0_CTRL_MASK _U_(0x0F8F) /**< \brief (RTC_MODE0_CTRL) MASK Register */ 102 103 /* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */ 104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 105 typedef union { 106 struct { 107 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 108 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 109 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 110 uint16_t :4; /*!< bit: 4.. 7 Reserved */ 111 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 112 uint16_t :4; /*!< bit: 12..15 Reserved */ 113 } bit; /*!< Structure used for bit access */ 114 uint16_t reg; /*!< Type used for register access */ 115 } RTC_MODE1_CTRL_Type; 116 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 117 118 #define RTC_MODE1_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE1_CTRL offset) MODE1 Control */ 119 #define RTC_MODE1_CTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_CTRL reset_value) MODE1 Control */ 120 121 #define RTC_MODE1_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE1_CTRL) Software Reset */ 122 #define RTC_MODE1_CTRL_SWRST (_U_(0x1) << RTC_MODE1_CTRL_SWRST_Pos) 123 #define RTC_MODE1_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE1_CTRL) Enable */ 124 #define RTC_MODE1_CTRL_ENABLE (_U_(0x1) << RTC_MODE1_CTRL_ENABLE_Pos) 125 #define RTC_MODE1_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE1_CTRL) Operating Mode */ 126 #define RTC_MODE1_CTRL_MODE_Msk (_U_(0x3) << RTC_MODE1_CTRL_MODE_Pos) 127 #define RTC_MODE1_CTRL_MODE(value) (RTC_MODE1_CTRL_MODE_Msk & ((value) << RTC_MODE1_CTRL_MODE_Pos)) 128 #define RTC_MODE1_CTRL_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRL) Mode 0: 32-bit Counter */ 129 #define RTC_MODE1_CTRL_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRL) Mode 1: 16-bit Counter */ 130 #define RTC_MODE1_CTRL_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRL) Mode 2: Clock/Calendar */ 131 #define RTC_MODE1_CTRL_MODE_COUNT32 (RTC_MODE1_CTRL_MODE_COUNT32_Val << RTC_MODE1_CTRL_MODE_Pos) 132 #define RTC_MODE1_CTRL_MODE_COUNT16 (RTC_MODE1_CTRL_MODE_COUNT16_Val << RTC_MODE1_CTRL_MODE_Pos) 133 #define RTC_MODE1_CTRL_MODE_CLOCK (RTC_MODE1_CTRL_MODE_CLOCK_Val << RTC_MODE1_CTRL_MODE_Pos) 134 #define RTC_MODE1_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE1_CTRL) Prescaler */ 135 #define RTC_MODE1_CTRL_PRESCALER_Msk (_U_(0xF) << RTC_MODE1_CTRL_PRESCALER_Pos) 136 #define RTC_MODE1_CTRL_PRESCALER(value) (RTC_MODE1_CTRL_PRESCALER_Msk & ((value) << RTC_MODE1_CTRL_PRESCALER_Pos)) 137 #define RTC_MODE1_CTRL_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ 138 #define RTC_MODE1_CTRL_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ 139 #define RTC_MODE1_CTRL_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ 140 #define RTC_MODE1_CTRL_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ 141 #define RTC_MODE1_CTRL_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ 142 #define RTC_MODE1_CTRL_PRESCALER_DIV32_Val _U_(0x5) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ 143 #define RTC_MODE1_CTRL_PRESCALER_DIV64_Val _U_(0x6) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ 144 #define RTC_MODE1_CTRL_PRESCALER_DIV128_Val _U_(0x7) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ 145 #define RTC_MODE1_CTRL_PRESCALER_DIV256_Val _U_(0x8) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ 146 #define RTC_MODE1_CTRL_PRESCALER_DIV512_Val _U_(0x9) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ 147 #define RTC_MODE1_CTRL_PRESCALER_DIV1024_Val _U_(0xA) /**< \brief (RTC_MODE1_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ 148 #define RTC_MODE1_CTRL_PRESCALER_DIV1 (RTC_MODE1_CTRL_PRESCALER_DIV1_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 149 #define RTC_MODE1_CTRL_PRESCALER_DIV2 (RTC_MODE1_CTRL_PRESCALER_DIV2_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 150 #define RTC_MODE1_CTRL_PRESCALER_DIV4 (RTC_MODE1_CTRL_PRESCALER_DIV4_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 151 #define RTC_MODE1_CTRL_PRESCALER_DIV8 (RTC_MODE1_CTRL_PRESCALER_DIV8_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 152 #define RTC_MODE1_CTRL_PRESCALER_DIV16 (RTC_MODE1_CTRL_PRESCALER_DIV16_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 153 #define RTC_MODE1_CTRL_PRESCALER_DIV32 (RTC_MODE1_CTRL_PRESCALER_DIV32_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 154 #define RTC_MODE1_CTRL_PRESCALER_DIV64 (RTC_MODE1_CTRL_PRESCALER_DIV64_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 155 #define RTC_MODE1_CTRL_PRESCALER_DIV128 (RTC_MODE1_CTRL_PRESCALER_DIV128_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 156 #define RTC_MODE1_CTRL_PRESCALER_DIV256 (RTC_MODE1_CTRL_PRESCALER_DIV256_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 157 #define RTC_MODE1_CTRL_PRESCALER_DIV512 (RTC_MODE1_CTRL_PRESCALER_DIV512_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 158 #define RTC_MODE1_CTRL_PRESCALER_DIV1024 (RTC_MODE1_CTRL_PRESCALER_DIV1024_Val << RTC_MODE1_CTRL_PRESCALER_Pos) 159 #define RTC_MODE1_CTRL_MASK _U_(0x0F0F) /**< \brief (RTC_MODE1_CTRL) MASK Register */ 160 161 /* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */ 162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 163 typedef union { 164 struct { 165 uint16_t SWRST:1; /*!< bit: 0 Software Reset */ 166 uint16_t ENABLE:1; /*!< bit: 1 Enable */ 167 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */ 168 uint16_t :2; /*!< bit: 4.. 5 Reserved */ 169 uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */ 170 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */ 171 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */ 172 uint16_t :4; /*!< bit: 12..15 Reserved */ 173 } bit; /*!< Structure used for bit access */ 174 uint16_t reg; /*!< Type used for register access */ 175 } RTC_MODE2_CTRL_Type; 176 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 177 178 #define RTC_MODE2_CTRL_OFFSET 0x00 /**< \brief (RTC_MODE2_CTRL offset) MODE2 Control */ 179 #define RTC_MODE2_CTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_CTRL reset_value) MODE2 Control */ 180 181 #define RTC_MODE2_CTRL_SWRST_Pos 0 /**< \brief (RTC_MODE2_CTRL) Software Reset */ 182 #define RTC_MODE2_CTRL_SWRST (_U_(0x1) << RTC_MODE2_CTRL_SWRST_Pos) 183 #define RTC_MODE2_CTRL_ENABLE_Pos 1 /**< \brief (RTC_MODE2_CTRL) Enable */ 184 #define RTC_MODE2_CTRL_ENABLE (_U_(0x1) << RTC_MODE2_CTRL_ENABLE_Pos) 185 #define RTC_MODE2_CTRL_MODE_Pos 2 /**< \brief (RTC_MODE2_CTRL) Operating Mode */ 186 #define RTC_MODE2_CTRL_MODE_Msk (_U_(0x3) << RTC_MODE2_CTRL_MODE_Pos) 187 #define RTC_MODE2_CTRL_MODE(value) (RTC_MODE2_CTRL_MODE_Msk & ((value) << RTC_MODE2_CTRL_MODE_Pos)) 188 #define RTC_MODE2_CTRL_MODE_COUNT32_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRL) Mode 0: 32-bit Counter */ 189 #define RTC_MODE2_CTRL_MODE_COUNT16_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRL) Mode 1: 16-bit Counter */ 190 #define RTC_MODE2_CTRL_MODE_CLOCK_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRL) Mode 2: Clock/Calendar */ 191 #define RTC_MODE2_CTRL_MODE_COUNT32 (RTC_MODE2_CTRL_MODE_COUNT32_Val << RTC_MODE2_CTRL_MODE_Pos) 192 #define RTC_MODE2_CTRL_MODE_COUNT16 (RTC_MODE2_CTRL_MODE_COUNT16_Val << RTC_MODE2_CTRL_MODE_Pos) 193 #define RTC_MODE2_CTRL_MODE_CLOCK (RTC_MODE2_CTRL_MODE_CLOCK_Val << RTC_MODE2_CTRL_MODE_Pos) 194 #define RTC_MODE2_CTRL_CLKREP_Pos 6 /**< \brief (RTC_MODE2_CTRL) Clock Representation */ 195 #define RTC_MODE2_CTRL_CLKREP (_U_(0x1) << RTC_MODE2_CTRL_CLKREP_Pos) 196 #define RTC_MODE2_CTRL_MATCHCLR_Pos 7 /**< \brief (RTC_MODE2_CTRL) Clear on Match */ 197 #define RTC_MODE2_CTRL_MATCHCLR (_U_(0x1) << RTC_MODE2_CTRL_MATCHCLR_Pos) 198 #define RTC_MODE2_CTRL_PRESCALER_Pos 8 /**< \brief (RTC_MODE2_CTRL) Prescaler */ 199 #define RTC_MODE2_CTRL_PRESCALER_Msk (_U_(0xF) << RTC_MODE2_CTRL_PRESCALER_Pos) 200 #define RTC_MODE2_CTRL_PRESCALER(value) (RTC_MODE2_CTRL_PRESCALER_Msk & ((value) << RTC_MODE2_CTRL_PRESCALER_Pos)) 201 #define RTC_MODE2_CTRL_PRESCALER_DIV1_Val _U_(0x0) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1 */ 202 #define RTC_MODE2_CTRL_PRESCALER_DIV2_Val _U_(0x1) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/2 */ 203 #define RTC_MODE2_CTRL_PRESCALER_DIV4_Val _U_(0x2) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/4 */ 204 #define RTC_MODE2_CTRL_PRESCALER_DIV8_Val _U_(0x3) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/8 */ 205 #define RTC_MODE2_CTRL_PRESCALER_DIV16_Val _U_(0x4) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/16 */ 206 #define RTC_MODE2_CTRL_PRESCALER_DIV32_Val _U_(0x5) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/32 */ 207 #define RTC_MODE2_CTRL_PRESCALER_DIV64_Val _U_(0x6) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/64 */ 208 #define RTC_MODE2_CTRL_PRESCALER_DIV128_Val _U_(0x7) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/128 */ 209 #define RTC_MODE2_CTRL_PRESCALER_DIV256_Val _U_(0x8) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/256 */ 210 #define RTC_MODE2_CTRL_PRESCALER_DIV512_Val _U_(0x9) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/512 */ 211 #define RTC_MODE2_CTRL_PRESCALER_DIV1024_Val _U_(0xA) /**< \brief (RTC_MODE2_CTRL) CLK_RTC_CNT = GCLK_RTC/1024 */ 212 #define RTC_MODE2_CTRL_PRESCALER_DIV1 (RTC_MODE2_CTRL_PRESCALER_DIV1_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 213 #define RTC_MODE2_CTRL_PRESCALER_DIV2 (RTC_MODE2_CTRL_PRESCALER_DIV2_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 214 #define RTC_MODE2_CTRL_PRESCALER_DIV4 (RTC_MODE2_CTRL_PRESCALER_DIV4_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 215 #define RTC_MODE2_CTRL_PRESCALER_DIV8 (RTC_MODE2_CTRL_PRESCALER_DIV8_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 216 #define RTC_MODE2_CTRL_PRESCALER_DIV16 (RTC_MODE2_CTRL_PRESCALER_DIV16_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 217 #define RTC_MODE2_CTRL_PRESCALER_DIV32 (RTC_MODE2_CTRL_PRESCALER_DIV32_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 218 #define RTC_MODE2_CTRL_PRESCALER_DIV64 (RTC_MODE2_CTRL_PRESCALER_DIV64_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 219 #define RTC_MODE2_CTRL_PRESCALER_DIV128 (RTC_MODE2_CTRL_PRESCALER_DIV128_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 220 #define RTC_MODE2_CTRL_PRESCALER_DIV256 (RTC_MODE2_CTRL_PRESCALER_DIV256_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 221 #define RTC_MODE2_CTRL_PRESCALER_DIV512 (RTC_MODE2_CTRL_PRESCALER_DIV512_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 222 #define RTC_MODE2_CTRL_PRESCALER_DIV1024 (RTC_MODE2_CTRL_PRESCALER_DIV1024_Val << RTC_MODE2_CTRL_PRESCALER_Pos) 223 #define RTC_MODE2_CTRL_MASK _U_(0x0FCF) /**< \brief (RTC_MODE2_CTRL) MASK Register */ 224 225 /* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */ 226 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 227 typedef union { 228 struct { 229 uint16_t ADDR:6; /*!< bit: 0.. 5 Address */ 230 uint16_t :8; /*!< bit: 6..13 Reserved */ 231 uint16_t RCONT:1; /*!< bit: 14 Read Continuously */ 232 uint16_t RREQ:1; /*!< bit: 15 Read Request */ 233 } bit; /*!< Structure used for bit access */ 234 uint16_t reg; /*!< Type used for register access */ 235 } RTC_READREQ_Type; 236 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 237 238 #define RTC_READREQ_OFFSET 0x02 /**< \brief (RTC_READREQ offset) Read Request */ 239 #define RTC_READREQ_RESETVALUE _U_(0x0010) /**< \brief (RTC_READREQ reset_value) Read Request */ 240 241 #define RTC_READREQ_ADDR_Pos 0 /**< \brief (RTC_READREQ) Address */ 242 #define RTC_READREQ_ADDR_Msk (_U_(0x3F) << RTC_READREQ_ADDR_Pos) 243 #define RTC_READREQ_ADDR(value) (RTC_READREQ_ADDR_Msk & ((value) << RTC_READREQ_ADDR_Pos)) 244 #define RTC_READREQ_RCONT_Pos 14 /**< \brief (RTC_READREQ) Read Continuously */ 245 #define RTC_READREQ_RCONT (_U_(0x1) << RTC_READREQ_RCONT_Pos) 246 #define RTC_READREQ_RREQ_Pos 15 /**< \brief (RTC_READREQ) Read Request */ 247 #define RTC_READREQ_RREQ (_U_(0x1) << RTC_READREQ_RREQ_Pos) 248 #define RTC_READREQ_MASK _U_(0xC03F) /**< \brief (RTC_READREQ) MASK Register */ 249 250 /* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */ 251 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 252 typedef union { 253 struct { 254 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 255 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 256 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 257 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 258 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 259 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 260 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 261 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 262 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ 263 uint16_t :6; /*!< bit: 9..14 Reserved */ 264 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 265 } bit; /*!< Structure used for bit access */ 266 struct { 267 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 268 uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */ 269 uint16_t :7; /*!< bit: 9..15 Reserved */ 270 } vec; /*!< Structure used for vec access */ 271 uint16_t reg; /*!< Type used for register access */ 272 } RTC_MODE0_EVCTRL_Type; 273 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 274 275 #define RTC_MODE0_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE0_EVCTRL offset) MODE0 Event Control */ 276 #define RTC_MODE0_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE0_EVCTRL reset_value) MODE0 Event Control */ 277 278 #define RTC_MODE0_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 0 Event Output Enable */ 279 #define RTC_MODE0_EVCTRL_PEREO0 (_U_(1) << RTC_MODE0_EVCTRL_PEREO0_Pos) 280 #define RTC_MODE0_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 1 Event Output Enable */ 281 #define RTC_MODE0_EVCTRL_PEREO1 (_U_(1) << RTC_MODE0_EVCTRL_PEREO1_Pos) 282 #define RTC_MODE0_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 2 Event Output Enable */ 283 #define RTC_MODE0_EVCTRL_PEREO2 (_U_(1) << RTC_MODE0_EVCTRL_PEREO2_Pos) 284 #define RTC_MODE0_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 3 Event Output Enable */ 285 #define RTC_MODE0_EVCTRL_PEREO3 (_U_(1) << RTC_MODE0_EVCTRL_PEREO3_Pos) 286 #define RTC_MODE0_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 4 Event Output Enable */ 287 #define RTC_MODE0_EVCTRL_PEREO4 (_U_(1) << RTC_MODE0_EVCTRL_PEREO4_Pos) 288 #define RTC_MODE0_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 5 Event Output Enable */ 289 #define RTC_MODE0_EVCTRL_PEREO5 (_U_(1) << RTC_MODE0_EVCTRL_PEREO5_Pos) 290 #define RTC_MODE0_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 6 Event Output Enable */ 291 #define RTC_MODE0_EVCTRL_PEREO6 (_U_(1) << RTC_MODE0_EVCTRL_PEREO6_Pos) 292 #define RTC_MODE0_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval 7 Event Output Enable */ 293 #define RTC_MODE0_EVCTRL_PEREO7 (_U_(1) << RTC_MODE0_EVCTRL_PEREO7_Pos) 294 #define RTC_MODE0_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE0_EVCTRL) Periodic Interval x Event Output Enable */ 295 #define RTC_MODE0_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE0_EVCTRL_PEREO_Pos) 296 #define RTC_MODE0_EVCTRL_PEREO(value) (RTC_MODE0_EVCTRL_PEREO_Msk & ((value) << RTC_MODE0_EVCTRL_PEREO_Pos)) 297 #define RTC_MODE0_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare 0 Event Output Enable */ 298 #define RTC_MODE0_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE0_EVCTRL_CMPEO0_Pos) 299 #define RTC_MODE0_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE0_EVCTRL) Compare x Event Output Enable */ 300 #define RTC_MODE0_EVCTRL_CMPEO_Msk (_U_(0x1) << RTC_MODE0_EVCTRL_CMPEO_Pos) 301 #define RTC_MODE0_EVCTRL_CMPEO(value) (RTC_MODE0_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE0_EVCTRL_CMPEO_Pos)) 302 #define RTC_MODE0_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE0_EVCTRL) Overflow Event Output Enable */ 303 #define RTC_MODE0_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE0_EVCTRL_OVFEO_Pos) 304 #define RTC_MODE0_EVCTRL_MASK _U_(0x81FF) /**< \brief (RTC_MODE0_EVCTRL) MASK Register */ 305 306 /* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */ 307 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 308 typedef union { 309 struct { 310 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 311 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 312 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 313 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 314 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 315 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 316 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 317 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 318 uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */ 319 uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */ 320 uint16_t :5; /*!< bit: 10..14 Reserved */ 321 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 322 } bit; /*!< Structure used for bit access */ 323 struct { 324 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 325 uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */ 326 uint16_t :6; /*!< bit: 10..15 Reserved */ 327 } vec; /*!< Structure used for vec access */ 328 uint16_t reg; /*!< Type used for register access */ 329 } RTC_MODE1_EVCTRL_Type; 330 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 331 332 #define RTC_MODE1_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE1_EVCTRL offset) MODE1 Event Control */ 333 #define RTC_MODE1_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_EVCTRL reset_value) MODE1 Event Control */ 334 335 #define RTC_MODE1_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 0 Event Output Enable */ 336 #define RTC_MODE1_EVCTRL_PEREO0 (_U_(1) << RTC_MODE1_EVCTRL_PEREO0_Pos) 337 #define RTC_MODE1_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 1 Event Output Enable */ 338 #define RTC_MODE1_EVCTRL_PEREO1 (_U_(1) << RTC_MODE1_EVCTRL_PEREO1_Pos) 339 #define RTC_MODE1_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 2 Event Output Enable */ 340 #define RTC_MODE1_EVCTRL_PEREO2 (_U_(1) << RTC_MODE1_EVCTRL_PEREO2_Pos) 341 #define RTC_MODE1_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 3 Event Output Enable */ 342 #define RTC_MODE1_EVCTRL_PEREO3 (_U_(1) << RTC_MODE1_EVCTRL_PEREO3_Pos) 343 #define RTC_MODE1_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 4 Event Output Enable */ 344 #define RTC_MODE1_EVCTRL_PEREO4 (_U_(1) << RTC_MODE1_EVCTRL_PEREO4_Pos) 345 #define RTC_MODE1_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 5 Event Output Enable */ 346 #define RTC_MODE1_EVCTRL_PEREO5 (_U_(1) << RTC_MODE1_EVCTRL_PEREO5_Pos) 347 #define RTC_MODE1_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 6 Event Output Enable */ 348 #define RTC_MODE1_EVCTRL_PEREO6 (_U_(1) << RTC_MODE1_EVCTRL_PEREO6_Pos) 349 #define RTC_MODE1_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval 7 Event Output Enable */ 350 #define RTC_MODE1_EVCTRL_PEREO7 (_U_(1) << RTC_MODE1_EVCTRL_PEREO7_Pos) 351 #define RTC_MODE1_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE1_EVCTRL) Periodic Interval x Event Output Enable */ 352 #define RTC_MODE1_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE1_EVCTRL_PEREO_Pos) 353 #define RTC_MODE1_EVCTRL_PEREO(value) (RTC_MODE1_EVCTRL_PEREO_Msk & ((value) << RTC_MODE1_EVCTRL_PEREO_Pos)) 354 #define RTC_MODE1_EVCTRL_CMPEO0_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare 0 Event Output Enable */ 355 #define RTC_MODE1_EVCTRL_CMPEO0 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO0_Pos) 356 #define RTC_MODE1_EVCTRL_CMPEO1_Pos 9 /**< \brief (RTC_MODE1_EVCTRL) Compare 1 Event Output Enable */ 357 #define RTC_MODE1_EVCTRL_CMPEO1 (_U_(1) << RTC_MODE1_EVCTRL_CMPEO1_Pos) 358 #define RTC_MODE1_EVCTRL_CMPEO_Pos 8 /**< \brief (RTC_MODE1_EVCTRL) Compare x Event Output Enable */ 359 #define RTC_MODE1_EVCTRL_CMPEO_Msk (_U_(0x3) << RTC_MODE1_EVCTRL_CMPEO_Pos) 360 #define RTC_MODE1_EVCTRL_CMPEO(value) (RTC_MODE1_EVCTRL_CMPEO_Msk & ((value) << RTC_MODE1_EVCTRL_CMPEO_Pos)) 361 #define RTC_MODE1_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE1_EVCTRL) Overflow Event Output Enable */ 362 #define RTC_MODE1_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE1_EVCTRL_OVFEO_Pos) 363 #define RTC_MODE1_EVCTRL_MASK _U_(0x83FF) /**< \brief (RTC_MODE1_EVCTRL) MASK Register */ 364 365 /* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */ 366 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 367 typedef union { 368 struct { 369 uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */ 370 uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */ 371 uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */ 372 uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */ 373 uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */ 374 uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */ 375 uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */ 376 uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */ 377 uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */ 378 uint16_t :6; /*!< bit: 9..14 Reserved */ 379 uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */ 380 } bit; /*!< Structure used for bit access */ 381 struct { 382 uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */ 383 uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */ 384 uint16_t :7; /*!< bit: 9..15 Reserved */ 385 } vec; /*!< Structure used for vec access */ 386 uint16_t reg; /*!< Type used for register access */ 387 } RTC_MODE2_EVCTRL_Type; 388 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 389 390 #define RTC_MODE2_EVCTRL_OFFSET 0x04 /**< \brief (RTC_MODE2_EVCTRL offset) MODE2 Event Control */ 391 #define RTC_MODE2_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE2_EVCTRL reset_value) MODE2 Event Control */ 392 393 #define RTC_MODE2_EVCTRL_PEREO0_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 0 Event Output Enable */ 394 #define RTC_MODE2_EVCTRL_PEREO0 (_U_(1) << RTC_MODE2_EVCTRL_PEREO0_Pos) 395 #define RTC_MODE2_EVCTRL_PEREO1_Pos 1 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 1 Event Output Enable */ 396 #define RTC_MODE2_EVCTRL_PEREO1 (_U_(1) << RTC_MODE2_EVCTRL_PEREO1_Pos) 397 #define RTC_MODE2_EVCTRL_PEREO2_Pos 2 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 2 Event Output Enable */ 398 #define RTC_MODE2_EVCTRL_PEREO2 (_U_(1) << RTC_MODE2_EVCTRL_PEREO2_Pos) 399 #define RTC_MODE2_EVCTRL_PEREO3_Pos 3 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 3 Event Output Enable */ 400 #define RTC_MODE2_EVCTRL_PEREO3 (_U_(1) << RTC_MODE2_EVCTRL_PEREO3_Pos) 401 #define RTC_MODE2_EVCTRL_PEREO4_Pos 4 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 4 Event Output Enable */ 402 #define RTC_MODE2_EVCTRL_PEREO4 (_U_(1) << RTC_MODE2_EVCTRL_PEREO4_Pos) 403 #define RTC_MODE2_EVCTRL_PEREO5_Pos 5 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 5 Event Output Enable */ 404 #define RTC_MODE2_EVCTRL_PEREO5 (_U_(1) << RTC_MODE2_EVCTRL_PEREO5_Pos) 405 #define RTC_MODE2_EVCTRL_PEREO6_Pos 6 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 6 Event Output Enable */ 406 #define RTC_MODE2_EVCTRL_PEREO6 (_U_(1) << RTC_MODE2_EVCTRL_PEREO6_Pos) 407 #define RTC_MODE2_EVCTRL_PEREO7_Pos 7 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval 7 Event Output Enable */ 408 #define RTC_MODE2_EVCTRL_PEREO7 (_U_(1) << RTC_MODE2_EVCTRL_PEREO7_Pos) 409 #define RTC_MODE2_EVCTRL_PEREO_Pos 0 /**< \brief (RTC_MODE2_EVCTRL) Periodic Interval x Event Output Enable */ 410 #define RTC_MODE2_EVCTRL_PEREO_Msk (_U_(0xFF) << RTC_MODE2_EVCTRL_PEREO_Pos) 411 #define RTC_MODE2_EVCTRL_PEREO(value) (RTC_MODE2_EVCTRL_PEREO_Msk & ((value) << RTC_MODE2_EVCTRL_PEREO_Pos)) 412 #define RTC_MODE2_EVCTRL_ALARMEO0_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm 0 Event Output Enable */ 413 #define RTC_MODE2_EVCTRL_ALARMEO0 (_U_(1) << RTC_MODE2_EVCTRL_ALARMEO0_Pos) 414 #define RTC_MODE2_EVCTRL_ALARMEO_Pos 8 /**< \brief (RTC_MODE2_EVCTRL) Alarm x Event Output Enable */ 415 #define RTC_MODE2_EVCTRL_ALARMEO_Msk (_U_(0x1) << RTC_MODE2_EVCTRL_ALARMEO_Pos) 416 #define RTC_MODE2_EVCTRL_ALARMEO(value) (RTC_MODE2_EVCTRL_ALARMEO_Msk & ((value) << RTC_MODE2_EVCTRL_ALARMEO_Pos)) 417 #define RTC_MODE2_EVCTRL_OVFEO_Pos 15 /**< \brief (RTC_MODE2_EVCTRL) Overflow Event Output Enable */ 418 #define RTC_MODE2_EVCTRL_OVFEO (_U_(0x1) << RTC_MODE2_EVCTRL_OVFEO_Pos) 419 #define RTC_MODE2_EVCTRL_MASK _U_(0x81FF) /**< \brief (RTC_MODE2_EVCTRL) MASK Register */ 420 421 /* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */ 422 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 423 typedef union { 424 struct { 425 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ 426 uint8_t :5; /*!< bit: 1.. 5 Reserved */ 427 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 428 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 429 } bit; /*!< Structure used for bit access */ 430 struct { 431 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ 432 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 433 } vec; /*!< Structure used for vec access */ 434 uint8_t reg; /*!< Type used for register access */ 435 } RTC_MODE0_INTENCLR_Type; 436 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 437 438 #define RTC_MODE0_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE0_INTENCLR offset) MODE0 Interrupt Enable Clear */ 439 #define RTC_MODE0_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE0_INTENCLR reset_value) MODE0 Interrupt Enable Clear */ 440 441 #define RTC_MODE0_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare 0 Interrupt Enable */ 442 #define RTC_MODE0_INTENCLR_CMP0 (_U_(1) << RTC_MODE0_INTENCLR_CMP0_Pos) 443 #define RTC_MODE0_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENCLR) Compare x Interrupt Enable */ 444 #define RTC_MODE0_INTENCLR_CMP_Msk (_U_(0x1) << RTC_MODE0_INTENCLR_CMP_Pos) 445 #define RTC_MODE0_INTENCLR_CMP(value) (RTC_MODE0_INTENCLR_CMP_Msk & ((value) << RTC_MODE0_INTENCLR_CMP_Pos)) 446 #define RTC_MODE0_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENCLR) Synchronization Ready Interrupt Enable */ 447 #define RTC_MODE0_INTENCLR_SYNCRDY (_U_(0x1) << RTC_MODE0_INTENCLR_SYNCRDY_Pos) 448 #define RTC_MODE0_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENCLR) Overflow Interrupt Enable */ 449 #define RTC_MODE0_INTENCLR_OVF (_U_(0x1) << RTC_MODE0_INTENCLR_OVF_Pos) 450 #define RTC_MODE0_INTENCLR_MASK _U_(0xC1) /**< \brief (RTC_MODE0_INTENCLR) MASK Register */ 451 452 /* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */ 453 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 454 typedef union { 455 struct { 456 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ 457 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ 458 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 459 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 460 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 461 } bit; /*!< Structure used for bit access */ 462 struct { 463 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ 464 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 465 } vec; /*!< Structure used for vec access */ 466 uint8_t reg; /*!< Type used for register access */ 467 } RTC_MODE1_INTENCLR_Type; 468 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 469 470 #define RTC_MODE1_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE1_INTENCLR offset) MODE1 Interrupt Enable Clear */ 471 #define RTC_MODE1_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE1_INTENCLR reset_value) MODE1 Interrupt Enable Clear */ 472 473 #define RTC_MODE1_INTENCLR_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare 0 Interrupt Enable */ 474 #define RTC_MODE1_INTENCLR_CMP0 (_U_(1) << RTC_MODE1_INTENCLR_CMP0_Pos) 475 #define RTC_MODE1_INTENCLR_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENCLR) Compare 1 Interrupt Enable */ 476 #define RTC_MODE1_INTENCLR_CMP1 (_U_(1) << RTC_MODE1_INTENCLR_CMP1_Pos) 477 #define RTC_MODE1_INTENCLR_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENCLR) Compare x Interrupt Enable */ 478 #define RTC_MODE1_INTENCLR_CMP_Msk (_U_(0x3) << RTC_MODE1_INTENCLR_CMP_Pos) 479 #define RTC_MODE1_INTENCLR_CMP(value) (RTC_MODE1_INTENCLR_CMP_Msk & ((value) << RTC_MODE1_INTENCLR_CMP_Pos)) 480 #define RTC_MODE1_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENCLR) Synchronization Ready Interrupt Enable */ 481 #define RTC_MODE1_INTENCLR_SYNCRDY (_U_(0x1) << RTC_MODE1_INTENCLR_SYNCRDY_Pos) 482 #define RTC_MODE1_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENCLR) Overflow Interrupt Enable */ 483 #define RTC_MODE1_INTENCLR_OVF (_U_(0x1) << RTC_MODE1_INTENCLR_OVF_Pos) 484 #define RTC_MODE1_INTENCLR_MASK _U_(0xC3) /**< \brief (RTC_MODE1_INTENCLR) MASK Register */ 485 486 /* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */ 487 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 488 typedef union { 489 struct { 490 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ 491 uint8_t :5; /*!< bit: 1.. 5 Reserved */ 492 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 493 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 494 } bit; /*!< Structure used for bit access */ 495 struct { 496 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ 497 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 498 } vec; /*!< Structure used for vec access */ 499 uint8_t reg; /*!< Type used for register access */ 500 } RTC_MODE2_INTENCLR_Type; 501 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 502 503 #define RTC_MODE2_INTENCLR_OFFSET 0x06 /**< \brief (RTC_MODE2_INTENCLR offset) MODE2 Interrupt Enable Clear */ 504 #define RTC_MODE2_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_INTENCLR reset_value) MODE2 Interrupt Enable Clear */ 505 506 #define RTC_MODE2_INTENCLR_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm 0 Interrupt Enable */ 507 #define RTC_MODE2_INTENCLR_ALARM0 (_U_(1) << RTC_MODE2_INTENCLR_ALARM0_Pos) 508 #define RTC_MODE2_INTENCLR_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENCLR) Alarm x Interrupt Enable */ 509 #define RTC_MODE2_INTENCLR_ALARM_Msk (_U_(0x1) << RTC_MODE2_INTENCLR_ALARM_Pos) 510 #define RTC_MODE2_INTENCLR_ALARM(value) (RTC_MODE2_INTENCLR_ALARM_Msk & ((value) << RTC_MODE2_INTENCLR_ALARM_Pos)) 511 #define RTC_MODE2_INTENCLR_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENCLR) Synchronization Ready Interrupt Enable */ 512 #define RTC_MODE2_INTENCLR_SYNCRDY (_U_(0x1) << RTC_MODE2_INTENCLR_SYNCRDY_Pos) 513 #define RTC_MODE2_INTENCLR_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENCLR) Overflow Interrupt Enable */ 514 #define RTC_MODE2_INTENCLR_OVF (_U_(0x1) << RTC_MODE2_INTENCLR_OVF_Pos) 515 #define RTC_MODE2_INTENCLR_MASK _U_(0xC1) /**< \brief (RTC_MODE2_INTENCLR) MASK Register */ 516 517 /* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */ 518 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 519 typedef union { 520 struct { 521 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ 522 uint8_t :5; /*!< bit: 1.. 5 Reserved */ 523 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 524 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 525 } bit; /*!< Structure used for bit access */ 526 struct { 527 uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */ 528 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 529 } vec; /*!< Structure used for vec access */ 530 uint8_t reg; /*!< Type used for register access */ 531 } RTC_MODE0_INTENSET_Type; 532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 533 534 #define RTC_MODE0_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE0_INTENSET offset) MODE0 Interrupt Enable Set */ 535 #define RTC_MODE0_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE0_INTENSET reset_value) MODE0 Interrupt Enable Set */ 536 537 #define RTC_MODE0_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare 0 Interrupt Enable */ 538 #define RTC_MODE0_INTENSET_CMP0 (_U_(1) << RTC_MODE0_INTENSET_CMP0_Pos) 539 #define RTC_MODE0_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE0_INTENSET) Compare x Interrupt Enable */ 540 #define RTC_MODE0_INTENSET_CMP_Msk (_U_(0x1) << RTC_MODE0_INTENSET_CMP_Pos) 541 #define RTC_MODE0_INTENSET_CMP(value) (RTC_MODE0_INTENSET_CMP_Msk & ((value) << RTC_MODE0_INTENSET_CMP_Pos)) 542 #define RTC_MODE0_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTENSET) Synchronization Ready Interrupt Enable */ 543 #define RTC_MODE0_INTENSET_SYNCRDY (_U_(0x1) << RTC_MODE0_INTENSET_SYNCRDY_Pos) 544 #define RTC_MODE0_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE0_INTENSET) Overflow Interrupt Enable */ 545 #define RTC_MODE0_INTENSET_OVF (_U_(0x1) << RTC_MODE0_INTENSET_OVF_Pos) 546 #define RTC_MODE0_INTENSET_MASK _U_(0xC1) /**< \brief (RTC_MODE0_INTENSET) MASK Register */ 547 548 /* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */ 549 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 550 typedef union { 551 struct { 552 uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */ 553 uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */ 554 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 555 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 556 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 557 } bit; /*!< Structure used for bit access */ 558 struct { 559 uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */ 560 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 561 } vec; /*!< Structure used for vec access */ 562 uint8_t reg; /*!< Type used for register access */ 563 } RTC_MODE1_INTENSET_Type; 564 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 565 566 #define RTC_MODE1_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE1_INTENSET offset) MODE1 Interrupt Enable Set */ 567 #define RTC_MODE1_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE1_INTENSET reset_value) MODE1 Interrupt Enable Set */ 568 569 #define RTC_MODE1_INTENSET_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare 0 Interrupt Enable */ 570 #define RTC_MODE1_INTENSET_CMP0 (_U_(1) << RTC_MODE1_INTENSET_CMP0_Pos) 571 #define RTC_MODE1_INTENSET_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTENSET) Compare 1 Interrupt Enable */ 572 #define RTC_MODE1_INTENSET_CMP1 (_U_(1) << RTC_MODE1_INTENSET_CMP1_Pos) 573 #define RTC_MODE1_INTENSET_CMP_Pos 0 /**< \brief (RTC_MODE1_INTENSET) Compare x Interrupt Enable */ 574 #define RTC_MODE1_INTENSET_CMP_Msk (_U_(0x3) << RTC_MODE1_INTENSET_CMP_Pos) 575 #define RTC_MODE1_INTENSET_CMP(value) (RTC_MODE1_INTENSET_CMP_Msk & ((value) << RTC_MODE1_INTENSET_CMP_Pos)) 576 #define RTC_MODE1_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTENSET) Synchronization Ready Interrupt Enable */ 577 #define RTC_MODE1_INTENSET_SYNCRDY (_U_(0x1) << RTC_MODE1_INTENSET_SYNCRDY_Pos) 578 #define RTC_MODE1_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE1_INTENSET) Overflow Interrupt Enable */ 579 #define RTC_MODE1_INTENSET_OVF (_U_(0x1) << RTC_MODE1_INTENSET_OVF_Pos) 580 #define RTC_MODE1_INTENSET_MASK _U_(0xC3) /**< \brief (RTC_MODE1_INTENSET) MASK Register */ 581 582 /* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */ 583 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 584 typedef union { 585 struct { 586 uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */ 587 uint8_t :5; /*!< bit: 1.. 5 Reserved */ 588 uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */ 589 uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */ 590 } bit; /*!< Structure used for bit access */ 591 struct { 592 uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */ 593 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 594 } vec; /*!< Structure used for vec access */ 595 uint8_t reg; /*!< Type used for register access */ 596 } RTC_MODE2_INTENSET_Type; 597 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 598 599 #define RTC_MODE2_INTENSET_OFFSET 0x07 /**< \brief (RTC_MODE2_INTENSET offset) MODE2 Interrupt Enable Set */ 600 #define RTC_MODE2_INTENSET_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_INTENSET reset_value) MODE2 Interrupt Enable Set */ 601 602 #define RTC_MODE2_INTENSET_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm 0 Interrupt Enable */ 603 #define RTC_MODE2_INTENSET_ALARM0 (_U_(1) << RTC_MODE2_INTENSET_ALARM0_Pos) 604 #define RTC_MODE2_INTENSET_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTENSET) Alarm x Interrupt Enable */ 605 #define RTC_MODE2_INTENSET_ALARM_Msk (_U_(0x1) << RTC_MODE2_INTENSET_ALARM_Pos) 606 #define RTC_MODE2_INTENSET_ALARM(value) (RTC_MODE2_INTENSET_ALARM_Msk & ((value) << RTC_MODE2_INTENSET_ALARM_Pos)) 607 #define RTC_MODE2_INTENSET_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTENSET) Synchronization Ready Interrupt Enable */ 608 #define RTC_MODE2_INTENSET_SYNCRDY (_U_(0x1) << RTC_MODE2_INTENSET_SYNCRDY_Pos) 609 #define RTC_MODE2_INTENSET_OVF_Pos 7 /**< \brief (RTC_MODE2_INTENSET) Overflow Interrupt Enable */ 610 #define RTC_MODE2_INTENSET_OVF (_U_(0x1) << RTC_MODE2_INTENSET_OVF_Pos) 611 #define RTC_MODE2_INTENSET_MASK _U_(0xC1) /**< \brief (RTC_MODE2_INTENSET) MASK Register */ 612 613 /* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */ 614 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 615 typedef union { // __I to avoid read-modify-write on write-to-clear register 616 struct { 617 __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ 618 __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ 619 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ 620 __I uint8_t OVF:1; /*!< bit: 7 Overflow */ 621 } bit; /*!< Structure used for bit access */ 622 struct { 623 __I uint8_t CMP:1; /*!< bit: 0 Compare x */ 624 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 625 } vec; /*!< Structure used for vec access */ 626 uint8_t reg; /*!< Type used for register access */ 627 } RTC_MODE0_INTFLAG_Type; 628 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 629 630 #define RTC_MODE0_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE0_INTFLAG offset) MODE0 Interrupt Flag Status and Clear */ 631 #define RTC_MODE0_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE0_INTFLAG reset_value) MODE0 Interrupt Flag Status and Clear */ 632 633 #define RTC_MODE0_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare 0 */ 634 #define RTC_MODE0_INTFLAG_CMP0 (_U_(1) << RTC_MODE0_INTFLAG_CMP0_Pos) 635 #define RTC_MODE0_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE0_INTFLAG) Compare x */ 636 #define RTC_MODE0_INTFLAG_CMP_Msk (_U_(0x1) << RTC_MODE0_INTFLAG_CMP_Pos) 637 #define RTC_MODE0_INTFLAG_CMP(value) (RTC_MODE0_INTFLAG_CMP_Msk & ((value) << RTC_MODE0_INTFLAG_CMP_Pos)) 638 #define RTC_MODE0_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE0_INTFLAG) Synchronization Ready */ 639 #define RTC_MODE0_INTFLAG_SYNCRDY (_U_(0x1) << RTC_MODE0_INTFLAG_SYNCRDY_Pos) 640 #define RTC_MODE0_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE0_INTFLAG) Overflow */ 641 #define RTC_MODE0_INTFLAG_OVF (_U_(0x1) << RTC_MODE0_INTFLAG_OVF_Pos) 642 #define RTC_MODE0_INTFLAG_MASK _U_(0xC1) /**< \brief (RTC_MODE0_INTFLAG) MASK Register */ 643 644 /* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */ 645 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 646 typedef union { // __I to avoid read-modify-write on write-to-clear register 647 struct { 648 __I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */ 649 __I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */ 650 __I uint8_t :4; /*!< bit: 2.. 5 Reserved */ 651 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ 652 __I uint8_t OVF:1; /*!< bit: 7 Overflow */ 653 } bit; /*!< Structure used for bit access */ 654 struct { 655 __I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */ 656 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ 657 } vec; /*!< Structure used for vec access */ 658 uint8_t reg; /*!< Type used for register access */ 659 } RTC_MODE1_INTFLAG_Type; 660 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 661 662 #define RTC_MODE1_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE1_INTFLAG offset) MODE1 Interrupt Flag Status and Clear */ 663 #define RTC_MODE1_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE1_INTFLAG reset_value) MODE1 Interrupt Flag Status and Clear */ 664 665 #define RTC_MODE1_INTFLAG_CMP0_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare 0 */ 666 #define RTC_MODE1_INTFLAG_CMP0 (_U_(1) << RTC_MODE1_INTFLAG_CMP0_Pos) 667 #define RTC_MODE1_INTFLAG_CMP1_Pos 1 /**< \brief (RTC_MODE1_INTFLAG) Compare 1 */ 668 #define RTC_MODE1_INTFLAG_CMP1 (_U_(1) << RTC_MODE1_INTFLAG_CMP1_Pos) 669 #define RTC_MODE1_INTFLAG_CMP_Pos 0 /**< \brief (RTC_MODE1_INTFLAG) Compare x */ 670 #define RTC_MODE1_INTFLAG_CMP_Msk (_U_(0x3) << RTC_MODE1_INTFLAG_CMP_Pos) 671 #define RTC_MODE1_INTFLAG_CMP(value) (RTC_MODE1_INTFLAG_CMP_Msk & ((value) << RTC_MODE1_INTFLAG_CMP_Pos)) 672 #define RTC_MODE1_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE1_INTFLAG) Synchronization Ready */ 673 #define RTC_MODE1_INTFLAG_SYNCRDY (_U_(0x1) << RTC_MODE1_INTFLAG_SYNCRDY_Pos) 674 #define RTC_MODE1_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE1_INTFLAG) Overflow */ 675 #define RTC_MODE1_INTFLAG_OVF (_U_(0x1) << RTC_MODE1_INTFLAG_OVF_Pos) 676 #define RTC_MODE1_INTFLAG_MASK _U_(0xC3) /**< \brief (RTC_MODE1_INTFLAG) MASK Register */ 677 678 /* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */ 679 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 680 typedef union { // __I to avoid read-modify-write on write-to-clear register 681 struct { 682 __I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */ 683 __I uint8_t :5; /*!< bit: 1.. 5 Reserved */ 684 __I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */ 685 __I uint8_t OVF:1; /*!< bit: 7 Overflow */ 686 } bit; /*!< Structure used for bit access */ 687 struct { 688 __I uint8_t ALARM:1; /*!< bit: 0 Alarm x */ 689 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 690 } vec; /*!< Structure used for vec access */ 691 uint8_t reg; /*!< Type used for register access */ 692 } RTC_MODE2_INTFLAG_Type; 693 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 694 695 #define RTC_MODE2_INTFLAG_OFFSET 0x08 /**< \brief (RTC_MODE2_INTFLAG offset) MODE2 Interrupt Flag Status and Clear */ 696 #define RTC_MODE2_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_INTFLAG reset_value) MODE2 Interrupt Flag Status and Clear */ 697 698 #define RTC_MODE2_INTFLAG_ALARM0_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm 0 */ 699 #define RTC_MODE2_INTFLAG_ALARM0 (_U_(1) << RTC_MODE2_INTFLAG_ALARM0_Pos) 700 #define RTC_MODE2_INTFLAG_ALARM_Pos 0 /**< \brief (RTC_MODE2_INTFLAG) Alarm x */ 701 #define RTC_MODE2_INTFLAG_ALARM_Msk (_U_(0x1) << RTC_MODE2_INTFLAG_ALARM_Pos) 702 #define RTC_MODE2_INTFLAG_ALARM(value) (RTC_MODE2_INTFLAG_ALARM_Msk & ((value) << RTC_MODE2_INTFLAG_ALARM_Pos)) 703 #define RTC_MODE2_INTFLAG_SYNCRDY_Pos 6 /**< \brief (RTC_MODE2_INTFLAG) Synchronization Ready */ 704 #define RTC_MODE2_INTFLAG_SYNCRDY (_U_(0x1) << RTC_MODE2_INTFLAG_SYNCRDY_Pos) 705 #define RTC_MODE2_INTFLAG_OVF_Pos 7 /**< \brief (RTC_MODE2_INTFLAG) Overflow */ 706 #define RTC_MODE2_INTFLAG_OVF (_U_(0x1) << RTC_MODE2_INTFLAG_OVF_Pos) 707 #define RTC_MODE2_INTFLAG_MASK _U_(0xC1) /**< \brief (RTC_MODE2_INTFLAG) MASK Register */ 708 709 /* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */ 710 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 711 typedef union { 712 struct { 713 uint8_t :7; /*!< bit: 0.. 6 Reserved */ 714 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ 715 } bit; /*!< Structure used for bit access */ 716 uint8_t reg; /*!< Type used for register access */ 717 } RTC_STATUS_Type; 718 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 719 720 #define RTC_STATUS_OFFSET 0x0A /**< \brief (RTC_STATUS offset) Status */ 721 #define RTC_STATUS_RESETVALUE _U_(0x00) /**< \brief (RTC_STATUS reset_value) Status */ 722 723 #define RTC_STATUS_SYNCBUSY_Pos 7 /**< \brief (RTC_STATUS) Synchronization Busy */ 724 #define RTC_STATUS_SYNCBUSY (_U_(0x1) << RTC_STATUS_SYNCBUSY_Pos) 725 #define RTC_STATUS_MASK _U_(0x80) /**< \brief (RTC_STATUS) MASK Register */ 726 727 /* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */ 728 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 729 typedef union { 730 struct { 731 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ 732 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 733 } bit; /*!< Structure used for bit access */ 734 uint8_t reg; /*!< Type used for register access */ 735 } RTC_DBGCTRL_Type; 736 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 737 738 #define RTC_DBGCTRL_OFFSET 0x0B /**< \brief (RTC_DBGCTRL offset) Debug Control */ 739 #define RTC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (RTC_DBGCTRL reset_value) Debug Control */ 740 741 #define RTC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (RTC_DBGCTRL) Run During Debug */ 742 #define RTC_DBGCTRL_DBGRUN (_U_(0x1) << RTC_DBGCTRL_DBGRUN_Pos) 743 #define RTC_DBGCTRL_MASK _U_(0x01) /**< \brief (RTC_DBGCTRL) MASK Register */ 744 745 /* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */ 746 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 747 typedef union { 748 struct { 749 uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */ 750 uint8_t SIGN:1; /*!< bit: 7 Correction Sign */ 751 } bit; /*!< Structure used for bit access */ 752 uint8_t reg; /*!< Type used for register access */ 753 } RTC_FREQCORR_Type; 754 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 755 756 #define RTC_FREQCORR_OFFSET 0x0C /**< \brief (RTC_FREQCORR offset) Frequency Correction */ 757 #define RTC_FREQCORR_RESETVALUE _U_(0x00) /**< \brief (RTC_FREQCORR reset_value) Frequency Correction */ 758 759 #define RTC_FREQCORR_VALUE_Pos 0 /**< \brief (RTC_FREQCORR) Correction Value */ 760 #define RTC_FREQCORR_VALUE_Msk (_U_(0x7F) << RTC_FREQCORR_VALUE_Pos) 761 #define RTC_FREQCORR_VALUE(value) (RTC_FREQCORR_VALUE_Msk & ((value) << RTC_FREQCORR_VALUE_Pos)) 762 #define RTC_FREQCORR_SIGN_Pos 7 /**< \brief (RTC_FREQCORR) Correction Sign */ 763 #define RTC_FREQCORR_SIGN (_U_(0x1) << RTC_FREQCORR_SIGN_Pos) 764 #define RTC_FREQCORR_MASK _U_(0xFF) /**< \brief (RTC_FREQCORR) MASK Register */ 765 766 /* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */ 767 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 768 typedef union { 769 struct { 770 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ 771 } bit; /*!< Structure used for bit access */ 772 uint32_t reg; /*!< Type used for register access */ 773 } RTC_MODE0_COUNT_Type; 774 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 775 776 #define RTC_MODE0_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE0_COUNT offset) MODE0 Counter Value */ 777 #define RTC_MODE0_COUNT_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COUNT reset_value) MODE0 Counter Value */ 778 779 #define RTC_MODE0_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE0_COUNT) Counter Value */ 780 #define RTC_MODE0_COUNT_COUNT_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COUNT_COUNT_Pos) 781 #define RTC_MODE0_COUNT_COUNT(value) (RTC_MODE0_COUNT_COUNT_Msk & ((value) << RTC_MODE0_COUNT_COUNT_Pos)) 782 #define RTC_MODE0_COUNT_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COUNT) MASK Register */ 783 784 /* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */ 785 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 786 typedef union { 787 struct { 788 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ 789 } bit; /*!< Structure used for bit access */ 790 uint16_t reg; /*!< Type used for register access */ 791 } RTC_MODE1_COUNT_Type; 792 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 793 794 #define RTC_MODE1_COUNT_OFFSET 0x10 /**< \brief (RTC_MODE1_COUNT offset) MODE1 Counter Value */ 795 #define RTC_MODE1_COUNT_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COUNT reset_value) MODE1 Counter Value */ 796 797 #define RTC_MODE1_COUNT_COUNT_Pos 0 /**< \brief (RTC_MODE1_COUNT) Counter Value */ 798 #define RTC_MODE1_COUNT_COUNT_Msk (_U_(0xFFFF) << RTC_MODE1_COUNT_COUNT_Pos) 799 #define RTC_MODE1_COUNT_COUNT(value) (RTC_MODE1_COUNT_COUNT_Msk & ((value) << RTC_MODE1_COUNT_COUNT_Pos)) 800 #define RTC_MODE1_COUNT_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COUNT) MASK Register */ 801 802 /* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */ 803 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 804 typedef union { 805 struct { 806 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ 807 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ 808 uint32_t HOUR:5; /*!< bit: 12..16 Hour */ 809 uint32_t DAY:5; /*!< bit: 17..21 Day */ 810 uint32_t MONTH:4; /*!< bit: 22..25 Month */ 811 uint32_t YEAR:6; /*!< bit: 26..31 Year */ 812 } bit; /*!< Structure used for bit access */ 813 uint32_t reg; /*!< Type used for register access */ 814 } RTC_MODE2_CLOCK_Type; 815 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 816 817 #define RTC_MODE2_CLOCK_OFFSET 0x10 /**< \brief (RTC_MODE2_CLOCK offset) MODE2 Clock Value */ 818 #define RTC_MODE2_CLOCK_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_CLOCK reset_value) MODE2 Clock Value */ 819 820 #define RTC_MODE2_CLOCK_SECOND_Pos 0 /**< \brief (RTC_MODE2_CLOCK) Second */ 821 #define RTC_MODE2_CLOCK_SECOND_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_SECOND_Pos) 822 #define RTC_MODE2_CLOCK_SECOND(value) (RTC_MODE2_CLOCK_SECOND_Msk & ((value) << RTC_MODE2_CLOCK_SECOND_Pos)) 823 #define RTC_MODE2_CLOCK_MINUTE_Pos 6 /**< \brief (RTC_MODE2_CLOCK) Minute */ 824 #define RTC_MODE2_CLOCK_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_MINUTE_Pos) 825 #define RTC_MODE2_CLOCK_MINUTE(value) (RTC_MODE2_CLOCK_MINUTE_Msk & ((value) << RTC_MODE2_CLOCK_MINUTE_Pos)) 826 #define RTC_MODE2_CLOCK_HOUR_Pos 12 /**< \brief (RTC_MODE2_CLOCK) Hour */ 827 #define RTC_MODE2_CLOCK_HOUR_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_HOUR_Pos) 828 #define RTC_MODE2_CLOCK_HOUR(value) (RTC_MODE2_CLOCK_HOUR_Msk & ((value) << RTC_MODE2_CLOCK_HOUR_Pos)) 829 #define RTC_MODE2_CLOCK_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_CLOCK) AM when CLKREP in 12-hour */ 830 #define RTC_MODE2_CLOCK_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_CLOCK) Afternoon Hour */ 831 #define RTC_MODE2_CLOCK_HOUR_AM (RTC_MODE2_CLOCK_HOUR_AM_Val << RTC_MODE2_CLOCK_HOUR_Pos) 832 #define RTC_MODE2_CLOCK_HOUR_PM (RTC_MODE2_CLOCK_HOUR_PM_Val << RTC_MODE2_CLOCK_HOUR_Pos) 833 #define RTC_MODE2_CLOCK_DAY_Pos 17 /**< \brief (RTC_MODE2_CLOCK) Day */ 834 #define RTC_MODE2_CLOCK_DAY_Msk (_U_(0x1F) << RTC_MODE2_CLOCK_DAY_Pos) 835 #define RTC_MODE2_CLOCK_DAY(value) (RTC_MODE2_CLOCK_DAY_Msk & ((value) << RTC_MODE2_CLOCK_DAY_Pos)) 836 #define RTC_MODE2_CLOCK_MONTH_Pos 22 /**< \brief (RTC_MODE2_CLOCK) Month */ 837 #define RTC_MODE2_CLOCK_MONTH_Msk (_U_(0xF) << RTC_MODE2_CLOCK_MONTH_Pos) 838 #define RTC_MODE2_CLOCK_MONTH(value) (RTC_MODE2_CLOCK_MONTH_Msk & ((value) << RTC_MODE2_CLOCK_MONTH_Pos)) 839 #define RTC_MODE2_CLOCK_YEAR_Pos 26 /**< \brief (RTC_MODE2_CLOCK) Year */ 840 #define RTC_MODE2_CLOCK_YEAR_Msk (_U_(0x3F) << RTC_MODE2_CLOCK_YEAR_Pos) 841 #define RTC_MODE2_CLOCK_YEAR(value) (RTC_MODE2_CLOCK_YEAR_Msk & ((value) << RTC_MODE2_CLOCK_YEAR_Pos)) 842 #define RTC_MODE2_CLOCK_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_CLOCK) MASK Register */ 843 844 /* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */ 845 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 846 typedef union { 847 struct { 848 uint16_t PER:16; /*!< bit: 0..15 Counter Period */ 849 } bit; /*!< Structure used for bit access */ 850 uint16_t reg; /*!< Type used for register access */ 851 } RTC_MODE1_PER_Type; 852 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 853 854 #define RTC_MODE1_PER_OFFSET 0x14 /**< \brief (RTC_MODE1_PER offset) MODE1 Counter Period */ 855 #define RTC_MODE1_PER_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_PER reset_value) MODE1 Counter Period */ 856 857 #define RTC_MODE1_PER_PER_Pos 0 /**< \brief (RTC_MODE1_PER) Counter Period */ 858 #define RTC_MODE1_PER_PER_Msk (_U_(0xFFFF) << RTC_MODE1_PER_PER_Pos) 859 #define RTC_MODE1_PER_PER(value) (RTC_MODE1_PER_PER_Msk & ((value) << RTC_MODE1_PER_PER_Pos)) 860 #define RTC_MODE1_PER_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_PER) MASK Register */ 861 862 /* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */ 863 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 864 typedef union { 865 struct { 866 uint32_t COMP:32; /*!< bit: 0..31 Compare Value */ 867 } bit; /*!< Structure used for bit access */ 868 uint32_t reg; /*!< Type used for register access */ 869 } RTC_MODE0_COMP_Type; 870 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 871 872 #define RTC_MODE0_COMP_OFFSET 0x18 /**< \brief (RTC_MODE0_COMP offset) MODE0 Compare n Value */ 873 #define RTC_MODE0_COMP_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE0_COMP reset_value) MODE0 Compare n Value */ 874 875 #define RTC_MODE0_COMP_COMP_Pos 0 /**< \brief (RTC_MODE0_COMP) Compare Value */ 876 #define RTC_MODE0_COMP_COMP_Msk (_U_(0xFFFFFFFF) << RTC_MODE0_COMP_COMP_Pos) 877 #define RTC_MODE0_COMP_COMP(value) (RTC_MODE0_COMP_COMP_Msk & ((value) << RTC_MODE0_COMP_COMP_Pos)) 878 #define RTC_MODE0_COMP_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE0_COMP) MASK Register */ 879 880 /* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */ 881 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 882 typedef union { 883 struct { 884 uint16_t COMP:16; /*!< bit: 0..15 Compare Value */ 885 } bit; /*!< Structure used for bit access */ 886 uint16_t reg; /*!< Type used for register access */ 887 } RTC_MODE1_COMP_Type; 888 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 889 890 #define RTC_MODE1_COMP_OFFSET 0x18 /**< \brief (RTC_MODE1_COMP offset) MODE1 Compare n Value */ 891 #define RTC_MODE1_COMP_RESETVALUE _U_(0x0000) /**< \brief (RTC_MODE1_COMP reset_value) MODE1 Compare n Value */ 892 893 #define RTC_MODE1_COMP_COMP_Pos 0 /**< \brief (RTC_MODE1_COMP) Compare Value */ 894 #define RTC_MODE1_COMP_COMP_Msk (_U_(0xFFFF) << RTC_MODE1_COMP_COMP_Pos) 895 #define RTC_MODE1_COMP_COMP(value) (RTC_MODE1_COMP_COMP_Msk & ((value) << RTC_MODE1_COMP_COMP_Pos)) 896 #define RTC_MODE1_COMP_MASK _U_(0xFFFF) /**< \brief (RTC_MODE1_COMP) MASK Register */ 897 898 /* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */ 899 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 900 typedef union { 901 struct { 902 uint32_t SECOND:6; /*!< bit: 0.. 5 Second */ 903 uint32_t MINUTE:6; /*!< bit: 6..11 Minute */ 904 uint32_t HOUR:5; /*!< bit: 12..16 Hour */ 905 uint32_t DAY:5; /*!< bit: 17..21 Day */ 906 uint32_t MONTH:4; /*!< bit: 22..25 Month */ 907 uint32_t YEAR:6; /*!< bit: 26..31 Year */ 908 } bit; /*!< Structure used for bit access */ 909 uint32_t reg; /*!< Type used for register access */ 910 } RTC_MODE2_ALARM_Type; 911 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 912 913 #define RTC_MODE2_ALARM_OFFSET 0x18 /**< \brief (RTC_MODE2_ALARM offset) MODE2_ALARM Alarm n Value */ 914 #define RTC_MODE2_ALARM_RESETVALUE _U_(0x00000000) /**< \brief (RTC_MODE2_ALARM reset_value) MODE2_ALARM Alarm n Value */ 915 916 #define RTC_MODE2_ALARM_SECOND_Pos 0 /**< \brief (RTC_MODE2_ALARM) Second */ 917 #define RTC_MODE2_ALARM_SECOND_Msk (_U_(0x3F) << RTC_MODE2_ALARM_SECOND_Pos) 918 #define RTC_MODE2_ALARM_SECOND(value) (RTC_MODE2_ALARM_SECOND_Msk & ((value) << RTC_MODE2_ALARM_SECOND_Pos)) 919 #define RTC_MODE2_ALARM_MINUTE_Pos 6 /**< \brief (RTC_MODE2_ALARM) Minute */ 920 #define RTC_MODE2_ALARM_MINUTE_Msk (_U_(0x3F) << RTC_MODE2_ALARM_MINUTE_Pos) 921 #define RTC_MODE2_ALARM_MINUTE(value) (RTC_MODE2_ALARM_MINUTE_Msk & ((value) << RTC_MODE2_ALARM_MINUTE_Pos)) 922 #define RTC_MODE2_ALARM_HOUR_Pos 12 /**< \brief (RTC_MODE2_ALARM) Hour */ 923 #define RTC_MODE2_ALARM_HOUR_Msk (_U_(0x1F) << RTC_MODE2_ALARM_HOUR_Pos) 924 #define RTC_MODE2_ALARM_HOUR(value) (RTC_MODE2_ALARM_HOUR_Msk & ((value) << RTC_MODE2_ALARM_HOUR_Pos)) 925 #define RTC_MODE2_ALARM_HOUR_AM_Val _U_(0x0) /**< \brief (RTC_MODE2_ALARM) Morning hour */ 926 #define RTC_MODE2_ALARM_HOUR_PM_Val _U_(0x10) /**< \brief (RTC_MODE2_ALARM) Afternoon hour */ 927 #define RTC_MODE2_ALARM_HOUR_AM (RTC_MODE2_ALARM_HOUR_AM_Val << RTC_MODE2_ALARM_HOUR_Pos) 928 #define RTC_MODE2_ALARM_HOUR_PM (RTC_MODE2_ALARM_HOUR_PM_Val << RTC_MODE2_ALARM_HOUR_Pos) 929 #define RTC_MODE2_ALARM_DAY_Pos 17 /**< \brief (RTC_MODE2_ALARM) Day */ 930 #define RTC_MODE2_ALARM_DAY_Msk (_U_(0x1F) << RTC_MODE2_ALARM_DAY_Pos) 931 #define RTC_MODE2_ALARM_DAY(value) (RTC_MODE2_ALARM_DAY_Msk & ((value) << RTC_MODE2_ALARM_DAY_Pos)) 932 #define RTC_MODE2_ALARM_MONTH_Pos 22 /**< \brief (RTC_MODE2_ALARM) Month */ 933 #define RTC_MODE2_ALARM_MONTH_Msk (_U_(0xF) << RTC_MODE2_ALARM_MONTH_Pos) 934 #define RTC_MODE2_ALARM_MONTH(value) (RTC_MODE2_ALARM_MONTH_Msk & ((value) << RTC_MODE2_ALARM_MONTH_Pos)) 935 #define RTC_MODE2_ALARM_YEAR_Pos 26 /**< \brief (RTC_MODE2_ALARM) Year */ 936 #define RTC_MODE2_ALARM_YEAR_Msk (_U_(0x3F) << RTC_MODE2_ALARM_YEAR_Pos) 937 #define RTC_MODE2_ALARM_YEAR(value) (RTC_MODE2_ALARM_YEAR_Msk & ((value) << RTC_MODE2_ALARM_YEAR_Pos)) 938 #define RTC_MODE2_ALARM_MASK _U_(0xFFFFFFFF) /**< \brief (RTC_MODE2_ALARM) MASK Register */ 939 940 /* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */ 941 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 942 typedef union { 943 struct { 944 uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */ 945 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 946 } bit; /*!< Structure used for bit access */ 947 uint8_t reg; /*!< Type used for register access */ 948 } RTC_MODE2_MASK_Type; 949 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 950 951 #define RTC_MODE2_MASK_OFFSET 0x1C /**< \brief (RTC_MODE2_MASK offset) MODE2_ALARM Alarm n Mask */ 952 #define RTC_MODE2_MASK_RESETVALUE _U_(0x00) /**< \brief (RTC_MODE2_MASK reset_value) MODE2_ALARM Alarm n Mask */ 953 954 #define RTC_MODE2_MASK_SEL_Pos 0 /**< \brief (RTC_MODE2_MASK) Alarm Mask Selection */ 955 #define RTC_MODE2_MASK_SEL_Msk (_U_(0x7) << RTC_MODE2_MASK_SEL_Pos) 956 #define RTC_MODE2_MASK_SEL(value) (RTC_MODE2_MASK_SEL_Msk & ((value) << RTC_MODE2_MASK_SEL_Pos)) 957 #define RTC_MODE2_MASK_SEL_OFF_Val _U_(0x0) /**< \brief (RTC_MODE2_MASK) Alarm Disabled */ 958 #define RTC_MODE2_MASK_SEL_SS_Val _U_(0x1) /**< \brief (RTC_MODE2_MASK) Match seconds only */ 959 #define RTC_MODE2_MASK_SEL_MMSS_Val _U_(0x2) /**< \brief (RTC_MODE2_MASK) Match seconds and minutes only */ 960 #define RTC_MODE2_MASK_SEL_HHMMSS_Val _U_(0x3) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, and hours only */ 961 #define RTC_MODE2_MASK_SEL_DDHHMMSS_Val _U_(0x4) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, and days only */ 962 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val _U_(0x5) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, and months only */ 963 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val _U_(0x6) /**< \brief (RTC_MODE2_MASK) Match seconds, minutes, hours, days, months, and years */ 964 #define RTC_MODE2_MASK_SEL_OFF (RTC_MODE2_MASK_SEL_OFF_Val << RTC_MODE2_MASK_SEL_Pos) 965 #define RTC_MODE2_MASK_SEL_SS (RTC_MODE2_MASK_SEL_SS_Val << RTC_MODE2_MASK_SEL_Pos) 966 #define RTC_MODE2_MASK_SEL_MMSS (RTC_MODE2_MASK_SEL_MMSS_Val << RTC_MODE2_MASK_SEL_Pos) 967 #define RTC_MODE2_MASK_SEL_HHMMSS (RTC_MODE2_MASK_SEL_HHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 968 #define RTC_MODE2_MASK_SEL_DDHHMMSS (RTC_MODE2_MASK_SEL_DDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 969 #define RTC_MODE2_MASK_SEL_MMDDHHMMSS (RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 970 #define RTC_MODE2_MASK_SEL_YYMMDDHHMMSS (RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val << RTC_MODE2_MASK_SEL_Pos) 971 #define RTC_MODE2_MASK_MASK _U_(0x07) /**< \brief (RTC_MODE2_MASK) MASK Register */ 972 973 /** \brief RtcMode2Alarm hardware registers */ 974 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 975 typedef struct { 976 __IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */ 977 __IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */ 978 RoReg8 Reserved1[0x3]; 979 } RtcMode2Alarm; 980 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 981 982 /** \brief RTC_MODE0 hardware registers */ 983 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 984 typedef struct { /* 32-bit Counter with Single 32-bit Compare */ 985 __IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */ 986 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 987 __IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */ 988 __IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */ 989 __IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */ 990 __IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */ 991 RoReg8 Reserved1[0x1]; 992 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ 993 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ 994 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ 995 RoReg8 Reserved2[0x3]; 996 __IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */ 997 RoReg8 Reserved3[0x4]; 998 __IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */ 999 } RtcMode0; 1000 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1001 1002 /** \brief RTC_MODE1 hardware registers */ 1003 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1004 typedef struct { /* 16-bit Counter with Two 16-bit Compares */ 1005 __IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */ 1006 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 1007 __IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */ 1008 __IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */ 1009 __IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */ 1010 __IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */ 1011 RoReg8 Reserved1[0x1]; 1012 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ 1013 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ 1014 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ 1015 RoReg8 Reserved2[0x3]; 1016 __IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */ 1017 RoReg8 Reserved3[0x2]; 1018 __IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */ 1019 RoReg8 Reserved4[0x2]; 1020 __IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */ 1021 } RtcMode1; 1022 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1023 1024 /** \brief RTC_MODE2 hardware registers */ 1025 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1026 typedef struct { /* Clock/Calendar with Alarm */ 1027 __IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */ 1028 __IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */ 1029 __IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */ 1030 __IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */ 1031 __IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */ 1032 __IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */ 1033 RoReg8 Reserved1[0x1]; 1034 __IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */ 1035 __IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */ 1036 __IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */ 1037 RoReg8 Reserved2[0x3]; 1038 __IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */ 1039 RoReg8 Reserved3[0x4]; 1040 RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */ 1041 } RtcMode2; 1042 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1043 1044 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1045 typedef union { 1046 RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */ 1047 RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */ 1048 RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */ 1049 } Rtc; 1050 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1051 1052 /*@}*/ 1053 1054 #endif /* _SAMD20_RTC_COMPONENT_ */ 1055
