1 /** 2 * \file 3 * 4 * \brief Component description for AC 5 * 6 * Copyright (c) 2017 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMD20_AC_COMPONENT_ 31 #define _SAMD20_AC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR AC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMD20_AC Analog Comparators */ 37 /*@{*/ 38 39 #define AC_U2205 40 #define REV_AC 0x111 41 42 /* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ 49 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 50 uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ 51 } bit; /*!< Structure used for bit access */ 52 uint8_t reg; /*!< Type used for register access */ 53 } AC_CTRLA_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 #define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ 57 #define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ 58 59 #define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ 60 #define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) 61 #define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ 62 #define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) 63 #define AC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (AC_CTRLA) Run in Standby */ 64 #define AC_CTRLA_RUNSTDBY_Msk (_U_(0x1) << AC_CTRLA_RUNSTDBY_Pos) 65 #define AC_CTRLA_RUNSTDBY(value) (AC_CTRLA_RUNSTDBY_Msk & ((value) << AC_CTRLA_RUNSTDBY_Pos)) 66 #define AC_CTRLA_LPMUX_Pos 7 /**< \brief (AC_CTRLA) Low-Power Mux */ 67 #define AC_CTRLA_LPMUX (_U_(0x1) << AC_CTRLA_LPMUX_Pos) 68 #define AC_CTRLA_MASK _U_(0x87) /**< \brief (AC_CTRLA) MASK Register */ 69 70 /* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ 71 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 72 typedef union { 73 struct { 74 uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ 75 uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ 76 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 77 } bit; /*!< Structure used for bit access */ 78 struct { 79 uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ 80 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 81 } vec; /*!< Structure used for vec access */ 82 uint8_t reg; /*!< Type used for register access */ 83 } AC_CTRLB_Type; 84 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 85 86 #define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ 87 #define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ 88 89 #define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ 90 #define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) 91 #define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ 92 #define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) 93 #define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ 94 #define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) 95 #define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) 96 #define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ 97 98 /* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ 99 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 100 typedef union { 101 struct { 102 uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ 103 uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ 104 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 105 uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ 106 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 107 uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */ 108 uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */ 109 uint16_t :6; /*!< bit: 10..15 Reserved */ 110 } bit; /*!< Structure used for bit access */ 111 struct { 112 uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ 113 uint16_t :2; /*!< bit: 2.. 3 Reserved */ 114 uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ 115 uint16_t :3; /*!< bit: 5.. 7 Reserved */ 116 uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */ 117 uint16_t :6; /*!< bit: 10..15 Reserved */ 118 } vec; /*!< Structure used for vec access */ 119 uint16_t reg; /*!< Type used for register access */ 120 } AC_EVCTRL_Type; 121 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 122 123 #define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ 124 #define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ 125 126 #define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ 127 #define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) 128 #define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ 129 #define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) 130 #define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ 131 #define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) 132 #define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) 133 #define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ 134 #define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) 135 #define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ 136 #define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) 137 #define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) 138 #define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input */ 139 #define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) 140 #define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input */ 141 #define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) 142 #define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input */ 143 #define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) 144 #define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) 145 #define AC_EVCTRL_MASK _U_(0x0313) /**< \brief (AC_EVCTRL) MASK Register */ 146 147 /* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 148 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 149 typedef union { 150 struct { 151 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ 152 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ 153 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 154 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ 155 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 156 } bit; /*!< Structure used for bit access */ 157 struct { 158 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ 159 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 160 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ 161 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 162 } vec; /*!< Structure used for vec access */ 163 uint8_t reg; /*!< Type used for register access */ 164 } AC_INTENCLR_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 #define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ 168 #define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ 169 170 #define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ 171 #define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) 172 #define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ 173 #define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) 174 #define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ 175 #define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) 176 #define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) 177 #define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ 178 #define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) 179 #define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ 180 #define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) 181 #define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) 182 #define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ 183 184 /* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 185 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 186 typedef union { 187 struct { 188 uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ 189 uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ 190 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 191 uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ 192 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 193 } bit; /*!< Structure used for bit access */ 194 struct { 195 uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ 196 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 197 uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ 198 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 199 } vec; /*!< Structure used for vec access */ 200 uint8_t reg; /*!< Type used for register access */ 201 } AC_INTENSET_Type; 202 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 203 204 #define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ 205 #define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ 206 207 #define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ 208 #define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) 209 #define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ 210 #define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) 211 #define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ 212 #define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) 213 #define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) 214 #define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ 215 #define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) 216 #define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ 217 #define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) 218 #define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) 219 #define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ 220 221 /* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 222 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 223 typedef union { // __I to avoid read-modify-write on write-to-clear register 224 struct { 225 __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ 226 __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ 227 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 228 __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ 229 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ 230 } bit; /*!< Structure used for bit access */ 231 struct { 232 __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ 233 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 234 __I uint8_t WIN:1; /*!< bit: 4 Window x */ 235 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ 236 } vec; /*!< Structure used for vec access */ 237 uint8_t reg; /*!< Type used for register access */ 238 } AC_INTFLAG_Type; 239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 240 241 #define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ 242 #define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 243 244 #define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ 245 #define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) 246 #define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ 247 #define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) 248 #define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ 249 #define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) 250 #define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) 251 #define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ 252 #define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) 253 #define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ 254 #define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) 255 #define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) 256 #define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ 257 258 /* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */ 259 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 260 typedef union { 261 struct { 262 uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ 263 uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ 264 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 265 uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ 266 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 267 } bit; /*!< Structure used for bit access */ 268 struct { 269 uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ 270 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 271 } vec; /*!< Structure used for vec access */ 272 uint8_t reg; /*!< Type used for register access */ 273 } AC_STATUSA_Type; 274 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 275 276 #define AC_STATUSA_OFFSET 0x08 /**< \brief (AC_STATUSA offset) Status A */ 277 #define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ 278 279 #define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ 280 #define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) 281 #define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ 282 #define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) 283 #define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ 284 #define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) 285 #define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) 286 #define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ 287 #define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) 288 #define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) 289 #define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ 290 #define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ 291 #define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ 292 #define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) 293 #define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) 294 #define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) 295 #define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ 296 297 /* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */ 298 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 299 typedef union { 300 struct { 301 uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ 302 uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ 303 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 304 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */ 305 } bit; /*!< Structure used for bit access */ 306 struct { 307 uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ 308 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 309 } vec; /*!< Structure used for vec access */ 310 uint8_t reg; /*!< Type used for register access */ 311 } AC_STATUSB_Type; 312 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 313 314 #define AC_STATUSB_OFFSET 0x09 /**< \brief (AC_STATUSB offset) Status B */ 315 #define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ 316 317 #define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ 318 #define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) 319 #define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ 320 #define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) 321 #define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ 322 #define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) 323 #define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) 324 #define AC_STATUSB_SYNCBUSY_Pos 7 /**< \brief (AC_STATUSB) Synchronization Busy */ 325 #define AC_STATUSB_SYNCBUSY (_U_(0x1) << AC_STATUSB_SYNCBUSY_Pos) 326 #define AC_STATUSB_MASK _U_(0x83) /**< \brief (AC_STATUSB) MASK Register */ 327 328 /* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */ 329 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 330 typedef union { 331 struct { 332 uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ 333 uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ 334 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 335 uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ 336 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 337 } bit; /*!< Structure used for bit access */ 338 struct { 339 uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ 340 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 341 } vec; /*!< Structure used for vec access */ 342 uint8_t reg; /*!< Type used for register access */ 343 } AC_STATUSC_Type; 344 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 345 346 #define AC_STATUSC_OFFSET 0x0A /**< \brief (AC_STATUSC offset) Status C */ 347 #define AC_STATUSC_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSC reset_value) Status C */ 348 349 #define AC_STATUSC_STATE0_Pos 0 /**< \brief (AC_STATUSC) Comparator 0 Current State */ 350 #define AC_STATUSC_STATE0 (_U_(1) << AC_STATUSC_STATE0_Pos) 351 #define AC_STATUSC_STATE1_Pos 1 /**< \brief (AC_STATUSC) Comparator 1 Current State */ 352 #define AC_STATUSC_STATE1 (_U_(1) << AC_STATUSC_STATE1_Pos) 353 #define AC_STATUSC_STATE_Pos 0 /**< \brief (AC_STATUSC) Comparator x Current State */ 354 #define AC_STATUSC_STATE_Msk (_U_(0x3) << AC_STATUSC_STATE_Pos) 355 #define AC_STATUSC_STATE(value) (AC_STATUSC_STATE_Msk & ((value) << AC_STATUSC_STATE_Pos)) 356 #define AC_STATUSC_WSTATE0_Pos 4 /**< \brief (AC_STATUSC) Window 0 Current State */ 357 #define AC_STATUSC_WSTATE0_Msk (_U_(0x3) << AC_STATUSC_WSTATE0_Pos) 358 #define AC_STATUSC_WSTATE0(value) (AC_STATUSC_WSTATE0_Msk & ((value) << AC_STATUSC_WSTATE0_Pos)) 359 #define AC_STATUSC_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSC) Signal is above window */ 360 #define AC_STATUSC_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSC) Signal is inside window */ 361 #define AC_STATUSC_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSC) Signal is below window */ 362 #define AC_STATUSC_WSTATE0_ABOVE (AC_STATUSC_WSTATE0_ABOVE_Val << AC_STATUSC_WSTATE0_Pos) 363 #define AC_STATUSC_WSTATE0_INSIDE (AC_STATUSC_WSTATE0_INSIDE_Val << AC_STATUSC_WSTATE0_Pos) 364 #define AC_STATUSC_WSTATE0_BELOW (AC_STATUSC_WSTATE0_BELOW_Val << AC_STATUSC_WSTATE0_Pos) 365 #define AC_STATUSC_MASK _U_(0x33) /**< \brief (AC_STATUSC) MASK Register */ 366 367 /* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */ 368 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 369 typedef union { 370 struct { 371 uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ 372 uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ 373 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 374 } bit; /*!< Structure used for bit access */ 375 uint8_t reg; /*!< Type used for register access */ 376 } AC_WINCTRL_Type; 377 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 378 379 #define AC_WINCTRL_OFFSET 0x0C /**< \brief (AC_WINCTRL offset) Window Control */ 380 #define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ 381 382 #define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ 383 #define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) 384 #define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ 385 #define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) 386 #define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) 387 #define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ 388 #define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ 389 #define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ 390 #define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ 391 #define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) 392 #define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) 393 #define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) 394 #define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) 395 #define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ 396 397 /* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ 398 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 399 typedef union { 400 struct { 401 uint32_t ENABLE:1; /*!< bit: 0 Enable */ 402 uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */ 403 uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */ 404 uint32_t :1; /*!< bit: 4 Reserved */ 405 uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */ 406 uint32_t :1; /*!< bit: 7 Reserved */ 407 uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ 408 uint32_t :1; /*!< bit: 11 Reserved */ 409 uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */ 410 uint32_t :1; /*!< bit: 14 Reserved */ 411 uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ 412 uint32_t OUT:2; /*!< bit: 16..17 Output */ 413 uint32_t :1; /*!< bit: 18 Reserved */ 414 uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */ 415 uint32_t :4; /*!< bit: 20..23 Reserved */ 416 uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ 417 uint32_t :5; /*!< bit: 27..31 Reserved */ 418 } bit; /*!< Structure used for bit access */ 419 uint32_t reg; /*!< Type used for register access */ 420 } AC_COMPCTRL_Type; 421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 422 423 #define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ 424 #define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ 425 426 #define AC_COMPCTRL_ENABLE_Pos 0 /**< \brief (AC_COMPCTRL) Enable */ 427 #define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) 428 #define AC_COMPCTRL_SINGLE_Pos 1 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ 429 #define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) 430 #define AC_COMPCTRL_SPEED_Pos 2 /**< \brief (AC_COMPCTRL) Speed Selection */ 431 #define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) 432 #define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) 433 #define AC_COMPCTRL_SPEED_LOW_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Low speed */ 434 #define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x1) /**< \brief (AC_COMPCTRL) High speed */ 435 #define AC_COMPCTRL_SPEED_LOW (AC_COMPCTRL_SPEED_LOW_Val << AC_COMPCTRL_SPEED_Pos) 436 #define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) 437 #define AC_COMPCTRL_INTSEL_Pos 5 /**< \brief (AC_COMPCTRL) Interrupt Selection */ 438 #define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) 439 #define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) 440 #define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ 441 #define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ 442 #define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ 443 #define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ 444 #define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) 445 #define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) 446 #define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) 447 #define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) 448 #define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ 449 #define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) 450 #define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) 451 #define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ 452 #define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ 453 #define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ 454 #define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ 455 #define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ 456 #define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ 457 #define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ 458 #define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ 459 #define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) 460 #define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) 461 #define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) 462 #define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) 463 #define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) 464 #define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) 465 #define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) 466 #define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) 467 #define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ 468 #define AC_COMPCTRL_MUXPOS_Msk (_U_(0x3) << AC_COMPCTRL_MUXPOS_Pos) 469 #define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) 470 #define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ 471 #define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ 472 #define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ 473 #define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ 474 #define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) 475 #define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) 476 #define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) 477 #define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) 478 #define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ 479 #define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) 480 #define AC_COMPCTRL_OUT_Pos 16 /**< \brief (AC_COMPCTRL) Output */ 481 #define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) 482 #define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) 483 #define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ 484 #define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ 485 #define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ 486 #define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) 487 #define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) 488 #define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) 489 #define AC_COMPCTRL_HYST_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ 490 #define AC_COMPCTRL_HYST (_U_(0x1) << AC_COMPCTRL_HYST_Pos) 491 #define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ 492 #define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) 493 #define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) 494 #define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ 495 #define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ 496 #define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ 497 #define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) 498 #define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) 499 #define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) 500 #define AC_COMPCTRL_MASK _U_(0x070BB76F) /**< \brief (AC_COMPCTRL) MASK Register */ 501 502 /* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */ 503 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 504 typedef union { 505 struct { 506 uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ 507 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 508 } bit; /*!< Structure used for bit access */ 509 uint8_t reg; /*!< Type used for register access */ 510 } AC_SCALER_Type; 511 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 512 513 #define AC_SCALER_OFFSET 0x20 /**< \brief (AC_SCALER offset) Scaler n */ 514 #define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ 515 516 #define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ 517 #define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) 518 #define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) 519 #define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ 520 521 /** \brief AC hardware registers */ 522 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 523 typedef struct { 524 __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 525 __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ 526 __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ 527 __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 528 __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 529 __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 530 RoReg8 Reserved1[0x1]; 531 __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */ 532 __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */ 533 __I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */ 534 RoReg8 Reserved2[0x1]; 535 __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */ 536 RoReg8 Reserved3[0x3]; 537 __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ 538 RoReg8 Reserved4[0x8]; 539 __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */ 540 } Ac; 541 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 542 543 /*@}*/ 544 545 #endif /* _SAMD20_AC_COMPONENT_ */ 546
