1 /** 2 * \file 3 * 4 * \brief Header file for SAMC21N17A 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21N17A_ 31 #define _SAMC21N17A_ 32 33 /** 34 * \ingroup SAMC21_definitions 35 * \addtogroup SAMC21N17A_definitions SAMC21N17A definitions 36 * This file defines all structures and symbols for SAMC21N17A: 37 * - registers and bitfields 38 * - peripheral base address 39 * - peripheral ID 40 * - PIO definitions 41 */ 42 /*@{*/ 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 #include <stdint.h> 50 #ifndef __cplusplus 51 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 52 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 53 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 54 #else 55 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 56 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 57 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 58 #endif 59 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 60 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 61 typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 62 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 63 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 64 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 65 #endif 66 67 #if !defined(SKIP_INTEGER_LITERALS) 68 #if defined(_U_) || defined(_L_) || defined(_UL_) 69 #error "Integer Literals macros already defined elsewhere" 70 #endif 71 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */ 74 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 75 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 76 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 77 #else /* Assembler */ 78 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 79 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 80 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 #endif /* SKIP_INTEGER_LITERALS */ 83 84 /* ************************************************************************** */ 85 /** CMSIS DEFINITIONS FOR SAMC21N17A */ 86 /* ************************************************************************** */ 87 /** \defgroup SAMC21N17A_cmsis CMSIS Definitions */ 88 /*@{*/ 89 90 /** Interrupt Number Definition */ 91 typedef enum IRQn 92 { 93 /****** Cortex-M0+ Processor Exceptions Numbers *******************/ 94 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 95 HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ 96 SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ 97 PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ 98 SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ 99 /****** SAMC21N17A-specific Interrupt Numbers *********************/ 100 SYSTEM_IRQn = 0, /**< 0 SAMC21N17A System Interrupts */ 101 WDT_IRQn = 1, /**< 1 SAMC21N17A Watchdog Timer (WDT) */ 102 RTC_IRQn = 2, /**< 2 SAMC21N17A Real-Time Counter (RTC) */ 103 EIC_IRQn = 3, /**< 3 SAMC21N17A External Interrupt Controller (EIC) */ 104 FREQM_IRQn = 4, /**< 4 SAMC21N17A Frequency Meter (FREQM) */ 105 TSENS_IRQn = 5, /**< 5 SAMC21N17A Temperature Sensor (TSENS) */ 106 NVMCTRL_IRQn = 6, /**< 6 SAMC21N17A Non-Volatile Memory Controller (NVMCTRL) */ 107 DMAC_IRQn = 7, /**< 7 SAMC21N17A Direct Memory Access Controller (DMAC) */ 108 EVSYS_IRQn = 8, /**< 8 SAMC21N17A Event System Interface (EVSYS) */ 109 SERCOM0_IRQn = 9, /**< 9 SAMC21N17A Serial Communication Interface 0 (SERCOM0) */ 110 SERCOM6_IRQn = 9, /**< 9 SAMC21N17A Serial Communication Interface 6 (SERCOM6) */ 111 SERCOM1_IRQn = 10, /**< 10 SAMC21N17A Serial Communication Interface 1 (SERCOM1) */ 112 SERCOM7_IRQn = 10, /**< 10 SAMC21N17A Serial Communication Interface 7 (SERCOM7) */ 113 SERCOM2_IRQn = 11, /**< 11 SAMC21N17A Serial Communication Interface 2 (SERCOM2) */ 114 SERCOM3_IRQn = 12, /**< 12 SAMC21N17A Serial Communication Interface 3 (SERCOM3) */ 115 SERCOM4_IRQn = 13, /**< 13 SAMC21N17A Serial Communication Interface 4 (SERCOM4) */ 116 SERCOM5_IRQn = 14, /**< 14 SAMC21N17A Serial Communication Interface 5 (SERCOM5) */ 117 CAN0_IRQn = 15, /**< 15 SAMC21N17A Control Area Network 0 (CAN0) */ 118 CAN1_IRQn = 16, /**< 16 SAMC21N17A Control Area Network 1 (CAN1) */ 119 TCC0_IRQn = 17, /**< 17 SAMC21N17A Timer Counter Control 0 (TCC0) */ 120 TCC1_IRQn = 18, /**< 18 SAMC21N17A Timer Counter Control 1 (TCC1) */ 121 TCC2_IRQn = 19, /**< 19 SAMC21N17A Timer Counter Control 2 (TCC2) */ 122 TC0_IRQn = 20, /**< 20 SAMC21N17A Basic Timer Counter 0 (TC0) */ 123 TC5_IRQn = 20, /**< 20 SAMC21N17A Basic Timer Counter 5 (TC5) */ 124 TC1_IRQn = 21, /**< 21 SAMC21N17A Basic Timer Counter 1 (TC1) */ 125 TC6_IRQn = 21, /**< 21 SAMC21N17A Basic Timer Counter 6 (TC6) */ 126 TC2_IRQn = 22, /**< 22 SAMC21N17A Basic Timer Counter 2 (TC2) */ 127 TC7_IRQn = 22, /**< 22 SAMC21N17A Basic Timer Counter 7 (TC7) */ 128 TC3_IRQn = 23, /**< 23 SAMC21N17A Basic Timer Counter 3 (TC3) */ 129 TC4_IRQn = 24, /**< 24 SAMC21N17A Basic Timer Counter 4 (TC4) */ 130 ADC0_IRQn = 25, /**< 25 SAMC21N17A Analog Digital Converter 0 (ADC0) */ 131 ADC1_IRQn = 26, /**< 26 SAMC21N17A Analog Digital Converter 1 (ADC1) */ 132 AC_IRQn = 27, /**< 27 SAMC21N17A Analog Comparators (AC) */ 133 DAC_IRQn = 28, /**< 28 SAMC21N17A Digital Analog Converter (DAC) */ 134 SDADC_IRQn = 29, /**< 29 SAMC21N17A Sigma-Delta Analog Digital Converter (SDADC) */ 135 PTC_IRQn = 30, /**< 30 SAMC21N17A Peripheral Touch Controller (PTC) */ 136 137 PERIPH_COUNT_IRQn = 31 /**< Number of peripheral IDs */ 138 } IRQn_Type; 139 140 typedef struct _DeviceVectors 141 { 142 /* Stack pointer */ 143 void* pvStack; 144 145 /* Cortex-M handlers */ 146 void* pfnReset_Handler; 147 void* pfnNonMaskableInt_Handler; 148 void* pfnHardFault_Handler; 149 void* pvReservedM12; 150 void* pvReservedM11; 151 void* pvReservedM10; 152 void* pvReservedM9; 153 void* pvReservedM8; 154 void* pvReservedM7; 155 void* pvReservedM6; 156 void* pfnSVCall_Handler; 157 void* pvReservedM4; 158 void* pvReservedM3; 159 void* pfnPendSV_Handler; 160 void* pfnSysTick_Handler; 161 162 /* Peripheral handlers */ 163 void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ 164 void* pfnWDT_Handler; /* 1 Watchdog Timer */ 165 void* pfnRTC_Handler; /* 2 Real-Time Counter */ 166 void* pfnEIC_Handler; /* 3 External Interrupt Controller */ 167 void* pfnFREQM_Handler; /* 4 Frequency Meter */ 168 void* pfnTSENS_Handler; /* 5 Temperature Sensor */ 169 void* pfnNVMCTRL_Handler; /* 6 Non-Volatile Memory Controller */ 170 void* pfnDMAC_Handler; /* 7 Direct Memory Access Controller */ 171 void* pfnEVSYS_Handler; /* 8 Event System Interface */ 172 void* pfnINT9_Handler; /* 9 Serial Communication Interface 0, Serial Communication Interface 6 */ 173 void* pfnINT10_Handler; /* 10 Serial Communication Interface 1, Serial Communication Interface 7 */ 174 void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ 175 void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ 176 void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ 177 void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ 178 void* pfnCAN0_Handler; /* 15 Control Area Network 0 */ 179 void* pfnCAN1_Handler; /* 16 Control Area Network 1 */ 180 void* pfnTCC0_Handler; /* 17 Timer Counter Control 0 */ 181 void* pfnTCC1_Handler; /* 18 Timer Counter Control 1 */ 182 void* pfnTCC2_Handler; /* 19 Timer Counter Control 2 */ 183 void* pfnINT20_Handler; /* 20 Basic Timer Counter 0, Basic Timer Counter 5 */ 184 void* pfnINT21_Handler; /* 21 Basic Timer Counter 1, Basic Timer Counter 6 */ 185 void* pfnINT22_Handler; /* 22 Basic Timer Counter 2, Basic Timer Counter 7 */ 186 void* pfnTC3_Handler; /* 23 Basic Timer Counter 3 */ 187 void* pfnTC4_Handler; /* 24 Basic Timer Counter 4 */ 188 void* pfnADC0_Handler; /* 25 Analog Digital Converter 0 */ 189 void* pfnADC1_Handler; /* 26 Analog Digital Converter 1 */ 190 void* pfnAC_Handler; /* 27 Analog Comparators */ 191 void* pfnDAC_Handler; /* 28 Digital Analog Converter */ 192 void* pfnSDADC_Handler; /* 29 Sigma-Delta Analog Digital Converter */ 193 void* pfnPTC_Handler; /* 30 Peripheral Touch Controller */ 194 } DeviceVectors; 195 196 /* Cortex-M0+ processor handlers */ 197 void Reset_Handler ( void ); 198 void NonMaskableInt_Handler ( void ); 199 void HardFault_Handler ( void ); 200 void SVCall_Handler ( void ); 201 void PendSV_Handler ( void ); 202 void SysTick_Handler ( void ); 203 204 /* Peripherals handlers */ 205 void SYSTEM_Handler ( void ); 206 void WDT_Handler ( void ); 207 void RTC_Handler ( void ); 208 void EIC_Handler ( void ); 209 void FREQM_Handler ( void ); 210 void TSENS_Handler ( void ); 211 void NVMCTRL_Handler ( void ); 212 void DMAC_Handler ( void ); 213 void EVSYS_Handler ( void ); 214 void INT9_Handler ( void ); 215 #define SERCOM0_Handler INT9_Handler 216 #define SERCOM6_Handler INT9_Handler 217 void INT10_Handler ( void ); 218 #define SERCOM1_Handler INT10_Handler 219 #define SERCOM7_Handler INT10_Handler 220 void SERCOM2_Handler ( void ); 221 void SERCOM3_Handler ( void ); 222 void SERCOM4_Handler ( void ); 223 void SERCOM5_Handler ( void ); 224 void CAN0_Handler ( void ); 225 void CAN1_Handler ( void ); 226 void TCC0_Handler ( void ); 227 void TCC1_Handler ( void ); 228 void TCC2_Handler ( void ); 229 void INT20_Handler ( void ); 230 #define TC0_Handler INT20_Handler 231 #define TC5_Handler INT20_Handler 232 void INT21_Handler ( void ); 233 #define TC1_Handler INT21_Handler 234 #define TC6_Handler INT21_Handler 235 void INT22_Handler ( void ); 236 #define TC2_Handler INT22_Handler 237 #define TC7_Handler INT22_Handler 238 void TC3_Handler ( void ); 239 void TC4_Handler ( void ); 240 void ADC0_Handler ( void ); 241 void ADC1_Handler ( void ); 242 void AC_Handler ( void ); 243 void DAC_Handler ( void ); 244 void SDADC_Handler ( void ); 245 void PTC_Handler ( void ); 246 247 /* 248 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 249 */ 250 251 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 252 #define __MPU_PRESENT 1 /*!< MPU present or not */ 253 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 254 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 255 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 256 257 /** 258 * \brief CMSIS includes 259 */ 260 261 #include <core_cm0plus.h> 262 #if !defined DONT_USE_CMSIS_INIT 263 #include "system_samc21.h" 264 #endif /* DONT_USE_CMSIS_INIT */ 265 266 /*@}*/ 267 268 /* ************************************************************************** */ 269 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMC21N17A */ 270 /* ************************************************************************** */ 271 /** \defgroup SAMC21N17A_api Peripheral Software API */ 272 /*@{*/ 273 274 #include "component/ac.h" 275 #include "component/adc.h" 276 #include "component/can.h" 277 #include "component/ccl.h" 278 #include "component/dac.h" 279 #include "component/divas.h" 280 #include "component/dmac.h" 281 #include "component/dsu.h" 282 #include "component/eic.h" 283 #include "component/evsys.h" 284 #include "component/freqm.h" 285 #include "component/gclk.h" 286 #include "component/hmatrixb.h" 287 #include "component/mclk.h" 288 #include "component/mtb.h" 289 #include "component/nvmctrl.h" 290 #include "component/oscctrl.h" 291 #include "component/osc32kctrl.h" 292 #include "component/pac.h" 293 #include "component/pm.h" 294 #include "component/port.h" 295 #include "component/rstc.h" 296 #include "component/rtc.h" 297 #include "component/sdadc.h" 298 #include "component/sercom.h" 299 #include "component/supc.h" 300 #include "component/tc.h" 301 #include "component/tcc.h" 302 #include "component/tsens.h" 303 #include "component/wdt.h" 304 /*@}*/ 305 306 /* ************************************************************************** */ 307 /** REGISTERS ACCESS DEFINITIONS FOR SAMC21N17A */ 308 /* ************************************************************************** */ 309 /** \defgroup SAMC21N17A_reg Registers Access Definitions */ 310 /*@{*/ 311 312 #include "instance/ac.h" 313 #include "instance/adc0.h" 314 #include "instance/adc1.h" 315 #include "instance/can0.h" 316 #include "instance/can1.h" 317 #include "instance/ccl.h" 318 #include "instance/dac.h" 319 #include "instance/divas.h" 320 #include "instance/dmac.h" 321 #include "instance/dsu.h" 322 #include "instance/eic.h" 323 #include "instance/evsys.h" 324 #include "instance/freqm.h" 325 #include "instance/gclk.h" 326 #include "instance/hmatrixhs.h" 327 #include "instance/mclk.h" 328 #include "instance/mtb.h" 329 #include "instance/nvmctrl.h" 330 #include "instance/oscctrl.h" 331 #include "instance/osc32kctrl.h" 332 #include "instance/pac.h" 333 #include "instance/pm.h" 334 #include "instance/port.h" 335 #include "instance/ptc.h" 336 #include "instance/rstc.h" 337 #include "instance/rtc.h" 338 #include "instance/sdadc.h" 339 #include "instance/sercom0.h" 340 #include "instance/sercom1.h" 341 #include "instance/sercom2.h" 342 #include "instance/sercom3.h" 343 #include "instance/sercom4.h" 344 #include "instance/sercom5.h" 345 #include "instance/sercom6.h" 346 #include "instance/sercom7.h" 347 #include "instance/supc.h" 348 #include "instance/tc0.h" 349 #include "instance/tc1.h" 350 #include "instance/tc2.h" 351 #include "instance/tc3.h" 352 #include "instance/tc4.h" 353 #include "instance/tc5.h" 354 #include "instance/tc6.h" 355 #include "instance/tc7.h" 356 #include "instance/tcc0.h" 357 #include "instance/tcc1.h" 358 #include "instance/tcc2.h" 359 #include "instance/tsens.h" 360 #include "instance/wdt.h" 361 /*@}*/ 362 363 /* ************************************************************************** */ 364 /** PERIPHERAL ID DEFINITIONS FOR SAMC21N17A */ 365 /* ************************************************************************** */ 366 /** \defgroup SAMC21N17A_id Peripheral Ids Definitions */ 367 /*@{*/ 368 369 // Peripheral instances on HPB0 bridge 370 #define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ 371 #define ID_PM 1 /**< \brief Power Manager (PM) */ 372 #define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ 373 #define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ 374 #define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ 375 #define ID_OSC32KCTRL 5 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ 376 #define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ 377 #define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ 378 #define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ 379 #define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ 380 #define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ 381 #define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ 382 #define ID_TSENS 12 /**< \brief Temperature Sensor (TSENS) */ 383 384 // Peripheral instances on HPB1 bridge 385 #define ID_PORT 32 /**< \brief Port Module (PORT) */ 386 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 387 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 388 #define ID_DMAC 35 /**< \brief Direct Memory Access Controller (DMAC) */ 389 #define ID_MTB 36 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ 390 #define ID_HMATRIXHS 37 /**< \brief HSB Matrix (HMATRIXHS) */ 391 392 // Peripheral instances on HPB2 bridge 393 #define ID_EVSYS 64 /**< \brief Event System Interface (EVSYS) */ 394 #define ID_SERCOM0 65 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 395 #define ID_SERCOM1 66 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 396 #define ID_SERCOM2 67 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 397 #define ID_SERCOM3 68 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 398 #define ID_SERCOM4 69 /**< \brief Serial Communication Interface 4 (SERCOM4) */ 399 #define ID_SERCOM5 70 /**< \brief Serial Communication Interface 5 (SERCOM5) */ 400 #define ID_CAN0 71 /**< \brief Control Area Network 0 (CAN0) */ 401 #define ID_CAN1 72 /**< \brief Control Area Network 1 (CAN1) */ 402 #define ID_TCC0 73 /**< \brief Timer Counter Control 0 (TCC0) */ 403 #define ID_TCC1 74 /**< \brief Timer Counter Control 1 (TCC1) */ 404 #define ID_TCC2 75 /**< \brief Timer Counter Control 2 (TCC2) */ 405 #define ID_TC0 76 /**< \brief Basic Timer Counter 0 (TC0) */ 406 #define ID_TC1 77 /**< \brief Basic Timer Counter 1 (TC1) */ 407 #define ID_TC2 78 /**< \brief Basic Timer Counter 2 (TC2) */ 408 #define ID_TC3 79 /**< \brief Basic Timer Counter 3 (TC3) */ 409 #define ID_TC4 80 /**< \brief Basic Timer Counter 4 (TC4) */ 410 #define ID_ADC0 81 /**< \brief Analog Digital Converter 0 (ADC0) */ 411 #define ID_ADC1 82 /**< \brief Analog Digital Converter 1 (ADC1) */ 412 #define ID_SDADC 83 /**< \brief Sigma-Delta Analog Digital Converter (SDADC) */ 413 #define ID_AC 84 /**< \brief Analog Comparators (AC) */ 414 #define ID_DAC 85 /**< \brief Digital Analog Converter (DAC) */ 415 #define ID_PTC 86 /**< \brief Peripheral Touch Controller (PTC) */ 416 #define ID_CCL 87 /**< \brief Configurable Custom Logic (CCL) */ 417 418 // Peripheral instances on HPB3 bridge 419 #define ID_SERCOM6 96 /**< \brief Serial Communication Interface 6 (SERCOM6) */ 420 #define ID_SERCOM7 97 /**< \brief Serial Communication Interface 7 (SERCOM7) */ 421 #define ID_TC5 98 /**< \brief Basic Timer Counter 5 (TC5) */ 422 #define ID_TC6 99 /**< \brief Basic Timer Counter 6 (TC6) */ 423 #define ID_TC7 100 /**< \brief Basic Timer Counter 7 (TC7) */ 424 425 // Peripheral instances on AHB (as if on bridge 4) 426 #define ID_DIVAS 128 /**< \brief Divide and Square Root Accelerator (DIVAS) */ 427 428 #define ID_PERIPH_COUNT 129 /**< \brief Max number of peripheral IDs */ 429 /*@}*/ 430 431 /* ************************************************************************** */ 432 /** BASE ADDRESS DEFINITIONS FOR SAMC21N17A */ 433 /* ************************************************************************** */ 434 /** \defgroup SAMC21N17A_base Peripheral Base Address Definitions */ 435 /*@{*/ 436 437 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 438 #define AC (0x42005000) /**< \brief (AC) APB Base Address */ 439 #define ADC0 (0x42004400) /**< \brief (ADC0) APB Base Address */ 440 #define ADC1 (0x42004800) /**< \brief (ADC1) APB Base Address */ 441 #define CAN0 (0x42001C00) /**< \brief (CAN0) APB Base Address */ 442 #define CAN1 (0x42002000) /**< \brief (CAN1) APB Base Address */ 443 #define CCL (0x42005C00) /**< \brief (CCL) APB Base Address */ 444 #define DAC (0x42005400) /**< \brief (DAC) APB Base Address */ 445 #define DIVAS (0x48000000) /**< \brief (DIVAS) AHB Base Address */ 446 #define DIVAS_IOBUS (0x60000200) /**< \brief (DIVAS) IOBUS Base Address */ 447 #define DMAC (0x41006000) /**< \brief (DMAC) APB Base Address */ 448 #define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ 449 #define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ 450 #define EVSYS (0x42000000) /**< \brief (EVSYS) APB Base Address */ 451 #define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ 452 #define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ 453 #define HMATRIXHS (0x4100A000) /**< \brief (HMATRIXHS) APB Base Address */ 454 #define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ 455 #define MTB (0x41008000) /**< \brief (MTB) APB Base Address */ 456 #define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ 457 #define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ 458 #define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 459 #define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ 460 #define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ 461 #define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ 462 #define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ 463 #define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ 464 #define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 465 #define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ 466 #define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ 467 #define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ 468 #define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ 469 #define PM (0x40000400) /**< \brief (PM) APB Base Address */ 470 #define PORT (0x41000000) /**< \brief (PORT) APB Base Address */ 471 #define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ 472 #define PTC (0x42005800) /**< \brief (PTC) APB Base Address */ 473 #define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ 474 #define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ 475 #define SDADC (0x42004C00) /**< \brief (SDADC) APB Base Address */ 476 #define SERCOM0 (0x42000400) /**< \brief (SERCOM0) APB Base Address */ 477 #define SERCOM1 (0x42000800) /**< \brief (SERCOM1) APB Base Address */ 478 #define SERCOM2 (0x42000C00) /**< \brief (SERCOM2) APB Base Address */ 479 #define SERCOM3 (0x42001000) /**< \brief (SERCOM3) APB Base Address */ 480 #define SERCOM4 (0x42001400) /**< \brief (SERCOM4) APB Base Address */ 481 #define SERCOM5 (0x42001800) /**< \brief (SERCOM5) APB Base Address */ 482 #define SERCOM6 (0x43000000) /**< \brief (SERCOM6) APB Base Address */ 483 #define SERCOM7 (0x43000400) /**< \brief (SERCOM7) APB Base Address */ 484 #define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ 485 #define TC0 (0x42003000) /**< \brief (TC0) APB Base Address */ 486 #define TC1 (0x42003400) /**< \brief (TC1) APB Base Address */ 487 #define TC2 (0x42003800) /**< \brief (TC2) APB Base Address */ 488 #define TC3 (0x42003C00) /**< \brief (TC3) APB Base Address */ 489 #define TC4 (0x42004000) /**< \brief (TC4) APB Base Address */ 490 #define TC5 (0x43000800) /**< \brief (TC5) APB Base Address */ 491 #define TC6 (0x43000C00) /**< \brief (TC6) APB Base Address */ 492 #define TC7 (0x43001000) /**< \brief (TC7) APB Base Address */ 493 #define TCC0 (0x42002400) /**< \brief (TCC0) APB Base Address */ 494 #define TCC1 (0x42002800) /**< \brief (TCC1) APB Base Address */ 495 #define TCC2 (0x42002C00) /**< \brief (TCC2) APB Base Address */ 496 #define TSENS (0x40003000) /**< \brief (TSENS) APB Base Address */ 497 #define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ 498 #else 499 #define AC ((Ac *)0x42005000UL) /**< \brief (AC) APB Base Address */ 500 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 501 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 502 503 #define ADC0 ((Adc *)0x42004400UL) /**< \brief (ADC0) APB Base Address */ 504 #define ADC1 ((Adc *)0x42004800UL) /**< \brief (ADC1) APB Base Address */ 505 #define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ 506 #define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ 507 508 #define CAN0 ((Can *)0x42001C00UL) /**< \brief (CAN0) APB Base Address */ 509 #define CAN1 ((Can *)0x42002000UL) /**< \brief (CAN1) APB Base Address */ 510 #define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ 511 #define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ 512 513 #define CCL ((Ccl *)0x42005C00UL) /**< \brief (CCL) APB Base Address */ 514 #define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ 515 #define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ 516 517 #define DAC ((Dac *)0x42005400UL) /**< \brief (DAC) APB Base Address */ 518 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 519 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 520 521 #define DIVAS ((Divas *)0x48000000UL) /**< \brief (DIVAS) AHB Base Address */ 522 #define DIVAS_IOBUS ((Divas *)0x60000200UL) /**< \brief (DIVAS) IOBUS Base Address */ 523 #define DIVAS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ 524 #define DIVAS_INSTS { DIVAS } /**< \brief (DIVAS) Instances List */ 525 #define DIVAS_IOBUS_INST_NUM 1 /**< \brief (DIVAS) Number of instances */ 526 #define DIVAS_IOBUS_INSTS { DIVAS_IOBUS } /**< \brief (DIVAS) Instances List */ 527 528 #define DMAC ((Dmac *)0x41006000UL) /**< \brief (DMAC) APB Base Address */ 529 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ 530 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ 531 532 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 533 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 534 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 535 536 #define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ 537 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 538 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 539 540 #define EVSYS ((Evsys *)0x42000000UL) /**< \brief (EVSYS) APB Base Address */ 541 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 542 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 543 544 #define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ 545 #define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ 546 #define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ 547 548 #define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ 549 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 550 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 551 552 #define HMATRIXHS ((Hmatrixb *)0x4100A000UL) /**< \brief (HMATRIXHS) APB Base Address */ 553 #define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ 554 #define HMATRIXB_INSTS { HMATRIXHS } /**< \brief (HMATRIXB) Instances List */ 555 556 #define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ 557 #define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ 558 #define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ 559 560 #define MTB ((Mtb *)0x41008000UL) /**< \brief (MTB) APB Base Address */ 561 #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ 562 #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ 563 564 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 565 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 566 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 567 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 568 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 569 #define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ 570 #define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 571 #define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ 572 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 573 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 574 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 575 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 576 577 #define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ 578 #define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ 579 #define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ 580 581 #define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ 582 #define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ 583 #define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ 584 585 #define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ 586 #define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ 587 #define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ 588 589 #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ 590 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 591 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 592 593 #define PORT ((Port *)0x41000000UL) /**< \brief (PORT) APB Base Address */ 594 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 595 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 596 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 597 #define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ 598 #define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ 599 600 #define PTC ((void *)0x42005800UL) /**< \brief (PTC) APB Base Address */ 601 #define PTC_GCLK_ID 37 602 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 603 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 604 605 #define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ 606 #define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ 607 #define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ 608 609 #define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ 610 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 611 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 612 613 #define SDADC ((Sdadc *)0x42004C00UL) /**< \brief (SDADC) APB Base Address */ 614 #define SDADC_INST_NUM 1 /**< \brief (SDADC) Number of instances */ 615 #define SDADC_INSTS { SDADC } /**< \brief (SDADC) Instances List */ 616 617 #define SERCOM0 ((Sercom *)0x42000400UL) /**< \brief (SERCOM0) APB Base Address */ 618 #define SERCOM1 ((Sercom *)0x42000800UL) /**< \brief (SERCOM1) APB Base Address */ 619 #define SERCOM2 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM2) APB Base Address */ 620 #define SERCOM3 ((Sercom *)0x42001000UL) /**< \brief (SERCOM3) APB Base Address */ 621 #define SERCOM4 ((Sercom *)0x42001400UL) /**< \brief (SERCOM4) APB Base Address */ 622 #define SERCOM5 ((Sercom *)0x42001800UL) /**< \brief (SERCOM5) APB Base Address */ 623 #define SERCOM6 ((Sercom *)0x43000000UL) /**< \brief (SERCOM6) APB Base Address */ 624 #define SERCOM7 ((Sercom *)0x43000400UL) /**< \brief (SERCOM7) APB Base Address */ 625 #define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ 626 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ 627 628 #define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ 629 #define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ 630 #define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ 631 632 #define TC0 ((Tc *)0x42003000UL) /**< \brief (TC0) APB Base Address */ 633 #define TC1 ((Tc *)0x42003400UL) /**< \brief (TC1) APB Base Address */ 634 #define TC2 ((Tc *)0x42003800UL) /**< \brief (TC2) APB Base Address */ 635 #define TC3 ((Tc *)0x42003C00UL) /**< \brief (TC3) APB Base Address */ 636 #define TC4 ((Tc *)0x42004000UL) /**< \brief (TC4) APB Base Address */ 637 #define TC5 ((Tc *)0x43000800UL) /**< \brief (TC5) APB Base Address */ 638 #define TC6 ((Tc *)0x43000C00UL) /**< \brief (TC6) APB Base Address */ 639 #define TC7 ((Tc *)0x43001000UL) /**< \brief (TC7) APB Base Address */ 640 #define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ 641 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ 642 643 #define TCC0 ((Tcc *)0x42002400UL) /**< \brief (TCC0) APB Base Address */ 644 #define TCC1 ((Tcc *)0x42002800UL) /**< \brief (TCC1) APB Base Address */ 645 #define TCC2 ((Tcc *)0x42002C00UL) /**< \brief (TCC2) APB Base Address */ 646 #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ 647 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ 648 649 #define TSENS ((Tsens *)0x40003000UL) /**< \brief (TSENS) APB Base Address */ 650 #define TSENS_INST_NUM 1 /**< \brief (TSENS) Number of instances */ 651 #define TSENS_INSTS { TSENS } /**< \brief (TSENS) Instances List */ 652 653 #define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ 654 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 655 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 656 657 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 658 /*@}*/ 659 660 /* ************************************************************************** */ 661 /** PORT DEFINITIONS FOR SAMC21N17A */ 662 /* ************************************************************************** */ 663 /** \defgroup SAMC21N17A_port PORT Definitions */ 664 /*@{*/ 665 666 #include "pio/samc21n17a.h" 667 /*@}*/ 668 669 /* ************************************************************************** */ 670 /** MEMORY MAPPING DEFINITIONS FOR SAMC21N17A */ 671 /* ************************************************************************** */ 672 673 #define FLASH_SIZE _UL_(0x00020000) /* 128 kB */ 674 #define FLASH_PAGE_SIZE 64 675 #define FLASH_NB_OF_PAGES 2048 676 #define FLASH_USER_PAGE_SIZE 64 677 #define HSRAM_SIZE _UL_(0x00004000) /* 16 kB */ 678 679 #define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ 680 #define FLASH_USER_PAGE_ADDR _UL_(0x00800000) /**< FLASH_USER_PAGE base address */ 681 #define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ 682 #define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ 683 #define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ 684 #define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ 685 #define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ 686 #define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ 687 688 #define DSU_DID_RESETVALUE _UL_(0x11011421) 689 #define AC_PAIRS 2 690 #define DMAC_CH_NUM 12 691 #define EVSYS_CHANNELS 12 692 #define NVMCTRL_RWW_EEPROM_SIZE _UL_(0x00001000) /* 4 kB */ 693 #define PORT_GROUPS 3 694 695 /* ************************************************************************** */ 696 /** ELECTRICAL DEFINITIONS FOR SAMC21N17A */ 697 /* ************************************************************************** */ 698 699 700 #ifdef __cplusplus 701 } 702 #endif 703 704 /*@}*/ 705 706 #endif /* SAMC21N17A_H */ 707
