1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAMC21J17A 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21J17A_PIO_ 31 #define _SAMC21J17A_PIO_ 32 33 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 34 #define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ 35 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 36 #define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ 37 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 38 #define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ 39 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 40 #define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ 41 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 42 #define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ 43 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 44 #define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ 45 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 46 #define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ 47 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 48 #define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ 49 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 50 #define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ 51 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 52 #define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ 53 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 54 #define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ 55 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 56 #define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ 57 #define PIN_PA12 12 /**< \brief Pin Number for PA12 */ 58 #define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ 59 #define PIN_PA13 13 /**< \brief Pin Number for PA13 */ 60 #define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ 61 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 62 #define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ 63 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 64 #define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ 65 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 66 #define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ 67 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 68 #define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ 69 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 70 #define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ 71 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 72 #define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ 73 #define PIN_PA20 20 /**< \brief Pin Number for PA20 */ 74 #define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ 75 #define PIN_PA21 21 /**< \brief Pin Number for PA21 */ 76 #define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ 77 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 78 #define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ 79 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 80 #define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ 81 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 82 #define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ 83 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 84 #define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ 85 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 86 #define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ 87 #define PIN_PA28 28 /**< \brief Pin Number for PA28 */ 88 #define PORT_PA28 (_UL_(1) << 28) /**< \brief PORT Mask for PA28 */ 89 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 90 #define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ 91 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 92 #define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ 93 #define PIN_PB00 32 /**< \brief Pin Number for PB00 */ 94 #define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ 95 #define PIN_PB01 33 /**< \brief Pin Number for PB01 */ 96 #define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ 97 #define PIN_PB02 34 /**< \brief Pin Number for PB02 */ 98 #define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ 99 #define PIN_PB03 35 /**< \brief Pin Number for PB03 */ 100 #define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ 101 #define PIN_PB04 36 /**< \brief Pin Number for PB04 */ 102 #define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ 103 #define PIN_PB05 37 /**< \brief Pin Number for PB05 */ 104 #define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ 105 #define PIN_PB06 38 /**< \brief Pin Number for PB06 */ 106 #define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ 107 #define PIN_PB07 39 /**< \brief Pin Number for PB07 */ 108 #define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ 109 #define PIN_PB08 40 /**< \brief Pin Number for PB08 */ 110 #define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ 111 #define PIN_PB09 41 /**< \brief Pin Number for PB09 */ 112 #define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ 113 #define PIN_PB10 42 /**< \brief Pin Number for PB10 */ 114 #define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ 115 #define PIN_PB11 43 /**< \brief Pin Number for PB11 */ 116 #define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ 117 #define PIN_PB12 44 /**< \brief Pin Number for PB12 */ 118 #define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ 119 #define PIN_PB13 45 /**< \brief Pin Number for PB13 */ 120 #define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ 121 #define PIN_PB14 46 /**< \brief Pin Number for PB14 */ 122 #define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ 123 #define PIN_PB15 47 /**< \brief Pin Number for PB15 */ 124 #define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ 125 #define PIN_PB16 48 /**< \brief Pin Number for PB16 */ 126 #define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ 127 #define PIN_PB17 49 /**< \brief Pin Number for PB17 */ 128 #define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ 129 #define PIN_PB22 54 /**< \brief Pin Number for PB22 */ 130 #define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ 131 #define PIN_PB23 55 /**< \brief Pin Number for PB23 */ 132 #define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ 133 #define PIN_PB30 62 /**< \brief Pin Number for PB30 */ 134 #define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ 135 #define PIN_PB31 63 /**< \brief Pin Number for PB31 */ 136 #define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ 137 /* ========== PORT definition for RSTC peripheral ========== */ 138 #define PIN_PA00A_RSTC_EXTWAKE0 _L_(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ 139 #define MUX_PA00A_RSTC_EXTWAKE0 _L_(0) 140 #define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) 141 #define PORT_PA00A_RSTC_EXTWAKE0 (_UL_(1) << 0) 142 #define PIN_PA01A_RSTC_EXTWAKE1 _L_(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ 143 #define MUX_PA01A_RSTC_EXTWAKE1 _L_(0) 144 #define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) 145 #define PORT_PA01A_RSTC_EXTWAKE1 (_UL_(1) << 1) 146 #define PIN_PA02A_RSTC_EXTWAKE2 _L_(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ 147 #define MUX_PA02A_RSTC_EXTWAKE2 _L_(0) 148 #define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) 149 #define PORT_PA02A_RSTC_EXTWAKE2 (_UL_(1) << 2) 150 #define PIN_PA03A_RSTC_EXTWAKE3 _L_(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ 151 #define MUX_PA03A_RSTC_EXTWAKE3 _L_(0) 152 #define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) 153 #define PORT_PA03A_RSTC_EXTWAKE3 (_UL_(1) << 3) 154 #define PIN_PA04A_RSTC_EXTWAKE4 _L_(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ 155 #define MUX_PA04A_RSTC_EXTWAKE4 _L_(0) 156 #define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) 157 #define PORT_PA04A_RSTC_EXTWAKE4 (_UL_(1) << 4) 158 #define PIN_PA05A_RSTC_EXTWAKE5 _L_(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ 159 #define MUX_PA05A_RSTC_EXTWAKE5 _L_(0) 160 #define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) 161 #define PORT_PA05A_RSTC_EXTWAKE5 (_UL_(1) << 5) 162 #define PIN_PA06A_RSTC_EXTWAKE6 _L_(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ 163 #define MUX_PA06A_RSTC_EXTWAKE6 _L_(0) 164 #define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) 165 #define PORT_PA06A_RSTC_EXTWAKE6 (_UL_(1) << 6) 166 #define PIN_PA07A_RSTC_EXTWAKE7 _L_(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ 167 #define MUX_PA07A_RSTC_EXTWAKE7 _L_(0) 168 #define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) 169 #define PORT_PA07A_RSTC_EXTWAKE7 (_UL_(1) << 7) 170 #define PIN_PA08A_RSTC_EXTWAKE8 _L_(8) /**< \brief RSTC signal: EXTWAKE8 on PA08 mux A */ 171 #define MUX_PA08A_RSTC_EXTWAKE8 _L_(0) 172 #define PINMUX_PA08A_RSTC_EXTWAKE8 ((PIN_PA08A_RSTC_EXTWAKE8 << 16) | MUX_PA08A_RSTC_EXTWAKE8) 173 #define PORT_PA08A_RSTC_EXTWAKE8 (_UL_(1) << 8) 174 #define PIN_PA09A_RSTC_EXTWAKE9 _L_(9) /**< \brief RSTC signal: EXTWAKE9 on PA09 mux A */ 175 #define MUX_PA09A_RSTC_EXTWAKE9 _L_(0) 176 #define PINMUX_PA09A_RSTC_EXTWAKE9 ((PIN_PA09A_RSTC_EXTWAKE9 << 16) | MUX_PA09A_RSTC_EXTWAKE9) 177 #define PORT_PA09A_RSTC_EXTWAKE9 (_UL_(1) << 9) 178 #define PIN_PA10A_RSTC_EXTWAKE10 _L_(10) /**< \brief RSTC signal: EXTWAKE10 on PA10 mux A */ 179 #define MUX_PA10A_RSTC_EXTWAKE10 _L_(0) 180 #define PINMUX_PA10A_RSTC_EXTWAKE10 ((PIN_PA10A_RSTC_EXTWAKE10 << 16) | MUX_PA10A_RSTC_EXTWAKE10) 181 #define PORT_PA10A_RSTC_EXTWAKE10 (_UL_(1) << 10) 182 #define PIN_PA11A_RSTC_EXTWAKE11 _L_(11) /**< \brief RSTC signal: EXTWAKE11 on PA11 mux A */ 183 #define MUX_PA11A_RSTC_EXTWAKE11 _L_(0) 184 #define PINMUX_PA11A_RSTC_EXTWAKE11 ((PIN_PA11A_RSTC_EXTWAKE11 << 16) | MUX_PA11A_RSTC_EXTWAKE11) 185 #define PORT_PA11A_RSTC_EXTWAKE11 (_UL_(1) << 11) 186 #define PIN_PA12A_RSTC_EXTWAKE12 _L_(12) /**< \brief RSTC signal: EXTWAKE12 on PA12 mux A */ 187 #define MUX_PA12A_RSTC_EXTWAKE12 _L_(0) 188 #define PINMUX_PA12A_RSTC_EXTWAKE12 ((PIN_PA12A_RSTC_EXTWAKE12 << 16) | MUX_PA12A_RSTC_EXTWAKE12) 189 #define PORT_PA12A_RSTC_EXTWAKE12 (_UL_(1) << 12) 190 #define PIN_PA13A_RSTC_EXTWAKE13 _L_(13) /**< \brief RSTC signal: EXTWAKE13 on PA13 mux A */ 191 #define MUX_PA13A_RSTC_EXTWAKE13 _L_(0) 192 #define PINMUX_PA13A_RSTC_EXTWAKE13 ((PIN_PA13A_RSTC_EXTWAKE13 << 16) | MUX_PA13A_RSTC_EXTWAKE13) 193 #define PORT_PA13A_RSTC_EXTWAKE13 (_UL_(1) << 13) 194 #define PIN_PA14A_RSTC_EXTWAKE14 _L_(14) /**< \brief RSTC signal: EXTWAKE14 on PA14 mux A */ 195 #define MUX_PA14A_RSTC_EXTWAKE14 _L_(0) 196 #define PINMUX_PA14A_RSTC_EXTWAKE14 ((PIN_PA14A_RSTC_EXTWAKE14 << 16) | MUX_PA14A_RSTC_EXTWAKE14) 197 #define PORT_PA14A_RSTC_EXTWAKE14 (_UL_(1) << 14) 198 #define PIN_PA15A_RSTC_EXTWAKE15 _L_(15) /**< \brief RSTC signal: EXTWAKE15 on PA15 mux A */ 199 #define MUX_PA15A_RSTC_EXTWAKE15 _L_(0) 200 #define PINMUX_PA15A_RSTC_EXTWAKE15 ((PIN_PA15A_RSTC_EXTWAKE15 << 16) | MUX_PA15A_RSTC_EXTWAKE15) 201 #define PORT_PA15A_RSTC_EXTWAKE15 (_UL_(1) << 15) 202 /* ========== PORT definition for GCLK peripheral ========== */ 203 #define PIN_PB14H_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux H */ 204 #define MUX_PB14H_GCLK_IO0 _L_(7) 205 #define PINMUX_PB14H_GCLK_IO0 ((PIN_PB14H_GCLK_IO0 << 16) | MUX_PB14H_GCLK_IO0) 206 #define PORT_PB14H_GCLK_IO0 (_UL_(1) << 14) 207 #define PIN_PB22H_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux H */ 208 #define MUX_PB22H_GCLK_IO0 _L_(7) 209 #define PINMUX_PB22H_GCLK_IO0 ((PIN_PB22H_GCLK_IO0 << 16) | MUX_PB22H_GCLK_IO0) 210 #define PORT_PB22H_GCLK_IO0 (_UL_(1) << 22) 211 #define PIN_PA14H_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 212 #define MUX_PA14H_GCLK_IO0 _L_(7) 213 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 214 #define PORT_PA14H_GCLK_IO0 (_UL_(1) << 14) 215 #define PIN_PA27H_GCLK_IO0 _L_(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 216 #define MUX_PA27H_GCLK_IO0 _L_(7) 217 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 218 #define PORT_PA27H_GCLK_IO0 (_UL_(1) << 27) 219 #define PIN_PA30H_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 220 #define MUX_PA30H_GCLK_IO0 _L_(7) 221 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 222 #define PORT_PA30H_GCLK_IO0 (_UL_(1) << 30) 223 #define PIN_PA28H_GCLK_IO0 _L_(28) /**< \brief GCLK signal: IO0 on PA28 mux H */ 224 #define MUX_PA28H_GCLK_IO0 _L_(7) 225 #define PINMUX_PA28H_GCLK_IO0 ((PIN_PA28H_GCLK_IO0 << 16) | MUX_PA28H_GCLK_IO0) 226 #define PORT_PA28H_GCLK_IO0 (_UL_(1) << 28) 227 #define PIN_PB15H_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux H */ 228 #define MUX_PB15H_GCLK_IO1 _L_(7) 229 #define PINMUX_PB15H_GCLK_IO1 ((PIN_PB15H_GCLK_IO1 << 16) | MUX_PB15H_GCLK_IO1) 230 #define PORT_PB15H_GCLK_IO1 (_UL_(1) << 15) 231 #define PIN_PB23H_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux H */ 232 #define MUX_PB23H_GCLK_IO1 _L_(7) 233 #define PINMUX_PB23H_GCLK_IO1 ((PIN_PB23H_GCLK_IO1 << 16) | MUX_PB23H_GCLK_IO1) 234 #define PORT_PB23H_GCLK_IO1 (_UL_(1) << 23) 235 #define PIN_PA15H_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 236 #define MUX_PA15H_GCLK_IO1 _L_(7) 237 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 238 #define PORT_PA15H_GCLK_IO1 (_UL_(1) << 15) 239 #define PIN_PB16H_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux H */ 240 #define MUX_PB16H_GCLK_IO2 _L_(7) 241 #define PINMUX_PB16H_GCLK_IO2 ((PIN_PB16H_GCLK_IO2 << 16) | MUX_PB16H_GCLK_IO2) 242 #define PORT_PB16H_GCLK_IO2 (_UL_(1) << 16) 243 #define PIN_PA16H_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 244 #define MUX_PA16H_GCLK_IO2 _L_(7) 245 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 246 #define PORT_PA16H_GCLK_IO2 (_UL_(1) << 16) 247 #define PIN_PA17H_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 248 #define MUX_PA17H_GCLK_IO3 _L_(7) 249 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 250 #define PORT_PA17H_GCLK_IO3 (_UL_(1) << 17) 251 #define PIN_PB17H_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux H */ 252 #define MUX_PB17H_GCLK_IO3 _L_(7) 253 #define PINMUX_PB17H_GCLK_IO3 ((PIN_PB17H_GCLK_IO3 << 16) | MUX_PB17H_GCLK_IO3) 254 #define PORT_PB17H_GCLK_IO3 (_UL_(1) << 17) 255 #define PIN_PA10H_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 256 #define MUX_PA10H_GCLK_IO4 _L_(7) 257 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 258 #define PORT_PA10H_GCLK_IO4 (_UL_(1) << 10) 259 #define PIN_PA20H_GCLK_IO4 _L_(20) /**< \brief GCLK signal: IO4 on PA20 mux H */ 260 #define MUX_PA20H_GCLK_IO4 _L_(7) 261 #define PINMUX_PA20H_GCLK_IO4 ((PIN_PA20H_GCLK_IO4 << 16) | MUX_PA20H_GCLK_IO4) 262 #define PORT_PA20H_GCLK_IO4 (_UL_(1) << 20) 263 #define PIN_PB10H_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux H */ 264 #define MUX_PB10H_GCLK_IO4 _L_(7) 265 #define PINMUX_PB10H_GCLK_IO4 ((PIN_PB10H_GCLK_IO4 << 16) | MUX_PB10H_GCLK_IO4) 266 #define PORT_PB10H_GCLK_IO4 (_UL_(1) << 10) 267 #define PIN_PA11H_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 268 #define MUX_PA11H_GCLK_IO5 _L_(7) 269 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 270 #define PORT_PA11H_GCLK_IO5 (_UL_(1) << 11) 271 #define PIN_PA21H_GCLK_IO5 _L_(21) /**< \brief GCLK signal: IO5 on PA21 mux H */ 272 #define MUX_PA21H_GCLK_IO5 _L_(7) 273 #define PINMUX_PA21H_GCLK_IO5 ((PIN_PA21H_GCLK_IO5 << 16) | MUX_PA21H_GCLK_IO5) 274 #define PORT_PA21H_GCLK_IO5 (_UL_(1) << 21) 275 #define PIN_PB11H_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux H */ 276 #define MUX_PB11H_GCLK_IO5 _L_(7) 277 #define PINMUX_PB11H_GCLK_IO5 ((PIN_PB11H_GCLK_IO5 << 16) | MUX_PB11H_GCLK_IO5) 278 #define PORT_PB11H_GCLK_IO5 (_UL_(1) << 11) 279 #define PIN_PA22H_GCLK_IO6 _L_(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 280 #define MUX_PA22H_GCLK_IO6 _L_(7) 281 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 282 #define PORT_PA22H_GCLK_IO6 (_UL_(1) << 22) 283 #define PIN_PB12H_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux H */ 284 #define MUX_PB12H_GCLK_IO6 _L_(7) 285 #define PINMUX_PB12H_GCLK_IO6 ((PIN_PB12H_GCLK_IO6 << 16) | MUX_PB12H_GCLK_IO6) 286 #define PORT_PB12H_GCLK_IO6 (_UL_(1) << 12) 287 #define PIN_PA23H_GCLK_IO7 _L_(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 288 #define MUX_PA23H_GCLK_IO7 _L_(7) 289 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 290 #define PORT_PA23H_GCLK_IO7 (_UL_(1) << 23) 291 #define PIN_PB13H_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux H */ 292 #define MUX_PB13H_GCLK_IO7 _L_(7) 293 #define PINMUX_PB13H_GCLK_IO7 ((PIN_PB13H_GCLK_IO7 << 16) | MUX_PB13H_GCLK_IO7) 294 #define PORT_PB13H_GCLK_IO7 (_UL_(1) << 13) 295 /* ========== PORT definition for EIC peripheral ========== */ 296 #define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 297 #define MUX_PA16A_EIC_EXTINT0 _L_(0) 298 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 299 #define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) 300 #define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 301 #define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ 302 #define MUX_PB00A_EIC_EXTINT0 _L_(0) 303 #define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) 304 #define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) 305 #define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ 306 #define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ 307 #define MUX_PB16A_EIC_EXTINT0 _L_(0) 308 #define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) 309 #define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) 310 #define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ 311 #define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 312 #define MUX_PA00A_EIC_EXTINT0 _L_(0) 313 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 314 #define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) 315 #define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 316 #define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 317 #define MUX_PA17A_EIC_EXTINT1 _L_(0) 318 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 319 #define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) 320 #define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 321 #define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ 322 #define MUX_PB01A_EIC_EXTINT1 _L_(0) 323 #define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) 324 #define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) 325 #define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ 326 #define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ 327 #define MUX_PB17A_EIC_EXTINT1 _L_(0) 328 #define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) 329 #define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) 330 #define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ 331 #define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 332 #define MUX_PA01A_EIC_EXTINT1 _L_(0) 333 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 334 #define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) 335 #define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 336 #define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 337 #define MUX_PA02A_EIC_EXTINT2 _L_(0) 338 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 339 #define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) 340 #define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 341 #define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 342 #define MUX_PA18A_EIC_EXTINT2 _L_(0) 343 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 344 #define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) 345 #define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 346 #define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ 347 #define MUX_PB02A_EIC_EXTINT2 _L_(0) 348 #define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) 349 #define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) 350 #define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ 351 #define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 352 #define MUX_PA03A_EIC_EXTINT3 _L_(0) 353 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 354 #define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) 355 #define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 356 #define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 357 #define MUX_PA19A_EIC_EXTINT3 _L_(0) 358 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 359 #define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) 360 #define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 361 #define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ 362 #define MUX_PB03A_EIC_EXTINT3 _L_(0) 363 #define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) 364 #define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) 365 #define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ 366 #define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 367 #define MUX_PA04A_EIC_EXTINT4 _L_(0) 368 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 369 #define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) 370 #define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 371 #define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ 372 #define MUX_PA20A_EIC_EXTINT4 _L_(0) 373 #define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) 374 #define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) 375 #define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ 376 #define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ 377 #define MUX_PB04A_EIC_EXTINT4 _L_(0) 378 #define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) 379 #define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) 380 #define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ 381 #define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 382 #define MUX_PA05A_EIC_EXTINT5 _L_(0) 383 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 384 #define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) 385 #define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 386 #define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ 387 #define MUX_PA21A_EIC_EXTINT5 _L_(0) 388 #define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) 389 #define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) 390 #define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ 391 #define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ 392 #define MUX_PB05A_EIC_EXTINT5 _L_(0) 393 #define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) 394 #define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) 395 #define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ 396 #define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 397 #define MUX_PA06A_EIC_EXTINT6 _L_(0) 398 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 399 #define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) 400 #define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 401 #define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 402 #define MUX_PA22A_EIC_EXTINT6 _L_(0) 403 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 404 #define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) 405 #define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 406 #define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ 407 #define MUX_PB06A_EIC_EXTINT6 _L_(0) 408 #define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) 409 #define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) 410 #define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ 411 #define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ 412 #define MUX_PB22A_EIC_EXTINT6 _L_(0) 413 #define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) 414 #define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) 415 #define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ 416 #define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 417 #define MUX_PA07A_EIC_EXTINT7 _L_(0) 418 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 419 #define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) 420 #define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 421 #define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 422 #define MUX_PA23A_EIC_EXTINT7 _L_(0) 423 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 424 #define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) 425 #define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 426 #define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ 427 #define MUX_PB07A_EIC_EXTINT7 _L_(0) 428 #define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) 429 #define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) 430 #define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ 431 #define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ 432 #define MUX_PB23A_EIC_EXTINT7 _L_(0) 433 #define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) 434 #define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) 435 #define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ 436 #define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ 437 #define MUX_PB08A_EIC_EXTINT8 _L_(0) 438 #define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) 439 #define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) 440 #define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ 441 #define PIN_PA28A_EIC_EXTINT8 _L_(28) /**< \brief EIC signal: EXTINT8 on PA28 mux A */ 442 #define MUX_PA28A_EIC_EXTINT8 _L_(0) 443 #define PINMUX_PA28A_EIC_EXTINT8 ((PIN_PA28A_EIC_EXTINT8 << 16) | MUX_PA28A_EIC_EXTINT8) 444 #define PORT_PA28A_EIC_EXTINT8 (_UL_(1) << 28) 445 #define PIN_PA28A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA28 External Interrupt Line */ 446 #define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 447 #define MUX_PA09A_EIC_EXTINT9 _L_(0) 448 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 449 #define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) 450 #define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 451 #define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ 452 #define MUX_PB09A_EIC_EXTINT9 _L_(0) 453 #define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) 454 #define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) 455 #define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ 456 #define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 457 #define MUX_PA10A_EIC_EXTINT10 _L_(0) 458 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 459 #define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) 460 #define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 461 #define PIN_PA30A_EIC_EXTINT10 _L_(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 462 #define MUX_PA30A_EIC_EXTINT10 _L_(0) 463 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 464 #define PORT_PA30A_EIC_EXTINT10 (_UL_(1) << 30) 465 #define PIN_PA30A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 466 #define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ 467 #define MUX_PB10A_EIC_EXTINT10 _L_(0) 468 #define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) 469 #define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) 470 #define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ 471 #define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 472 #define MUX_PA11A_EIC_EXTINT11 _L_(0) 473 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 474 #define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) 475 #define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 476 #define PIN_PA31A_EIC_EXTINT11 _L_(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 477 #define MUX_PA31A_EIC_EXTINT11 _L_(0) 478 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 479 #define PORT_PA31A_EIC_EXTINT11 (_UL_(1) << 31) 480 #define PIN_PA31A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 481 #define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ 482 #define MUX_PB11A_EIC_EXTINT11 _L_(0) 483 #define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) 484 #define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) 485 #define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ 486 #define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ 487 #define MUX_PA12A_EIC_EXTINT12 _L_(0) 488 #define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) 489 #define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) 490 #define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ 491 #define PIN_PA24A_EIC_EXTINT12 _L_(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 492 #define MUX_PA24A_EIC_EXTINT12 _L_(0) 493 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 494 #define PORT_PA24A_EIC_EXTINT12 (_UL_(1) << 24) 495 #define PIN_PA24A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 496 #define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ 497 #define MUX_PB12A_EIC_EXTINT12 _L_(0) 498 #define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) 499 #define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) 500 #define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ 501 #define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ 502 #define MUX_PA13A_EIC_EXTINT13 _L_(0) 503 #define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) 504 #define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) 505 #define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ 506 #define PIN_PA25A_EIC_EXTINT13 _L_(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 507 #define MUX_PA25A_EIC_EXTINT13 _L_(0) 508 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 509 #define PORT_PA25A_EIC_EXTINT13 (_UL_(1) << 25) 510 #define PIN_PA25A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 511 #define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ 512 #define MUX_PB13A_EIC_EXTINT13 _L_(0) 513 #define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) 514 #define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) 515 #define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ 516 #define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ 517 #define MUX_PB14A_EIC_EXTINT14 _L_(0) 518 #define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) 519 #define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) 520 #define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ 521 #define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ 522 #define MUX_PB30A_EIC_EXTINT14 _L_(0) 523 #define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) 524 #define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) 525 #define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ 526 #define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 527 #define MUX_PA14A_EIC_EXTINT14 _L_(0) 528 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 529 #define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) 530 #define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 531 #define PIN_PA27A_EIC_EXTINT15 _L_(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 532 #define MUX_PA27A_EIC_EXTINT15 _L_(0) 533 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 534 #define PORT_PA27A_EIC_EXTINT15 (_UL_(1) << 27) 535 #define PIN_PA27A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 536 #define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ 537 #define MUX_PB15A_EIC_EXTINT15 _L_(0) 538 #define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) 539 #define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) 540 #define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ 541 #define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ 542 #define MUX_PB31A_EIC_EXTINT15 _L_(0) 543 #define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) 544 #define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) 545 #define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ 546 #define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 547 #define MUX_PA15A_EIC_EXTINT15 _L_(0) 548 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 549 #define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) 550 #define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 551 #define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ 552 #define MUX_PA08A_EIC_NMI _L_(0) 553 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 554 #define PORT_PA08A_EIC_NMI (_UL_(1) << 8) 555 /* ========== PORT definition for SERCOM0 peripheral ========== */ 556 #define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 557 #define MUX_PA04D_SERCOM0_PAD0 _L_(3) 558 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 559 #define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) 560 #define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 561 #define MUX_PA08C_SERCOM0_PAD0 _L_(2) 562 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 563 #define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) 564 #define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 565 #define MUX_PA05D_SERCOM0_PAD1 _L_(3) 566 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 567 #define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) 568 #define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 569 #define MUX_PA09C_SERCOM0_PAD1 _L_(2) 570 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 571 #define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) 572 #define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 573 #define MUX_PA06D_SERCOM0_PAD2 _L_(3) 574 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 575 #define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) 576 #define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 577 #define MUX_PA10C_SERCOM0_PAD2 _L_(2) 578 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 579 #define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) 580 #define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 581 #define MUX_PA07D_SERCOM0_PAD3 _L_(3) 582 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 583 #define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) 584 #define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 585 #define MUX_PA11C_SERCOM0_PAD3 _L_(2) 586 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 587 #define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) 588 /* ========== PORT definition for SERCOM1 peripheral ========== */ 589 #define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 590 #define MUX_PA16C_SERCOM1_PAD0 _L_(2) 591 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 592 #define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) 593 #define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 594 #define MUX_PA00D_SERCOM1_PAD0 _L_(3) 595 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 596 #define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) 597 #define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 598 #define MUX_PA17C_SERCOM1_PAD1 _L_(2) 599 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 600 #define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) 601 #define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 602 #define MUX_PA01D_SERCOM1_PAD1 _L_(3) 603 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 604 #define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) 605 #define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 606 #define MUX_PA30D_SERCOM1_PAD2 _L_(3) 607 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 608 #define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) 609 #define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 610 #define MUX_PA18C_SERCOM1_PAD2 _L_(2) 611 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 612 #define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) 613 #define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 614 #define MUX_PA31D_SERCOM1_PAD3 _L_(3) 615 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 616 #define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) 617 #define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 618 #define MUX_PA19C_SERCOM1_PAD3 _L_(2) 619 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 620 #define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) 621 /* ========== PORT definition for SERCOM2 peripheral ========== */ 622 #define PIN_PA08D_SERCOM2_PAD0 _L_(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 623 #define MUX_PA08D_SERCOM2_PAD0 _L_(3) 624 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 625 #define PORT_PA08D_SERCOM2_PAD0 (_UL_(1) << 8) 626 #define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ 627 #define MUX_PA12C_SERCOM2_PAD0 _L_(2) 628 #define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) 629 #define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) 630 #define PIN_PA09D_SERCOM2_PAD1 _L_(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 631 #define MUX_PA09D_SERCOM2_PAD1 _L_(3) 632 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 633 #define PORT_PA09D_SERCOM2_PAD1 (_UL_(1) << 9) 634 #define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ 635 #define MUX_PA13C_SERCOM2_PAD1 _L_(2) 636 #define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) 637 #define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) 638 #define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 639 #define MUX_PA10D_SERCOM2_PAD2 _L_(3) 640 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 641 #define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) 642 #define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 643 #define MUX_PA14C_SERCOM2_PAD2 _L_(2) 644 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 645 #define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) 646 #define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 647 #define MUX_PA11D_SERCOM2_PAD3 _L_(3) 648 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 649 #define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) 650 #define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 651 #define MUX_PA15C_SERCOM2_PAD3 _L_(2) 652 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 653 #define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) 654 /* ========== PORT definition for SERCOM3 peripheral ========== */ 655 #define PIN_PA16D_SERCOM3_PAD0 _L_(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 656 #define MUX_PA16D_SERCOM3_PAD0 _L_(3) 657 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 658 #define PORT_PA16D_SERCOM3_PAD0 (_UL_(1) << 16) 659 #define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 660 #define MUX_PA22C_SERCOM3_PAD0 _L_(2) 661 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 662 #define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) 663 #define PIN_PA17D_SERCOM3_PAD1 _L_(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 664 #define MUX_PA17D_SERCOM3_PAD1 _L_(3) 665 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 666 #define PORT_PA17D_SERCOM3_PAD1 (_UL_(1) << 17) 667 #define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 668 #define MUX_PA23C_SERCOM3_PAD1 _L_(2) 669 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 670 #define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) 671 #define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 672 #define MUX_PA18D_SERCOM3_PAD2 _L_(3) 673 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 674 #define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) 675 #define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ 676 #define MUX_PA20D_SERCOM3_PAD2 _L_(3) 677 #define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) 678 #define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) 679 #define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 680 #define MUX_PA24C_SERCOM3_PAD2 _L_(2) 681 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 682 #define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) 683 #define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 684 #define MUX_PA19D_SERCOM3_PAD3 _L_(3) 685 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 686 #define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) 687 #define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ 688 #define MUX_PA21D_SERCOM3_PAD3 _L_(3) 689 #define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) 690 #define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) 691 #define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 692 #define MUX_PA25C_SERCOM3_PAD3 _L_(2) 693 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 694 #define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) 695 /* ========== PORT definition for SERCOM4 peripheral ========== */ 696 #define PIN_PA12D_SERCOM4_PAD0 _L_(12) /**< \brief SERCOM4 signal: PAD0 on PA12 mux D */ 697 #define MUX_PA12D_SERCOM4_PAD0 _L_(3) 698 #define PINMUX_PA12D_SERCOM4_PAD0 ((PIN_PA12D_SERCOM4_PAD0 << 16) | MUX_PA12D_SERCOM4_PAD0) 699 #define PORT_PA12D_SERCOM4_PAD0 (_UL_(1) << 12) 700 #define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ 701 #define MUX_PB08D_SERCOM4_PAD0 _L_(3) 702 #define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) 703 #define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) 704 #define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ 705 #define MUX_PB12C_SERCOM4_PAD0 _L_(2) 706 #define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) 707 #define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) 708 #define PIN_PA13D_SERCOM4_PAD1 _L_(13) /**< \brief SERCOM4 signal: PAD1 on PA13 mux D */ 709 #define MUX_PA13D_SERCOM4_PAD1 _L_(3) 710 #define PINMUX_PA13D_SERCOM4_PAD1 ((PIN_PA13D_SERCOM4_PAD1 << 16) | MUX_PA13D_SERCOM4_PAD1) 711 #define PORT_PA13D_SERCOM4_PAD1 (_UL_(1) << 13) 712 #define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ 713 #define MUX_PB09D_SERCOM4_PAD1 _L_(3) 714 #define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) 715 #define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) 716 #define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ 717 #define MUX_PB13C_SERCOM4_PAD1 _L_(2) 718 #define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) 719 #define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) 720 #define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 721 #define MUX_PA14D_SERCOM4_PAD2 _L_(3) 722 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 723 #define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) 724 #define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ 725 #define MUX_PB10D_SERCOM4_PAD2 _L_(3) 726 #define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) 727 #define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) 728 #define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ 729 #define MUX_PB14C_SERCOM4_PAD2 _L_(2) 730 #define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) 731 #define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) 732 #define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 733 #define MUX_PA15D_SERCOM4_PAD3 _L_(3) 734 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 735 #define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) 736 #define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ 737 #define MUX_PB11D_SERCOM4_PAD3 _L_(3) 738 #define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) 739 #define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) 740 #define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ 741 #define MUX_PB15C_SERCOM4_PAD3 _L_(2) 742 #define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) 743 #define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) 744 /* ========== PORT definition for SERCOM5 peripheral ========== */ 745 #define PIN_PA22D_SERCOM5_PAD0 _L_(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 746 #define MUX_PA22D_SERCOM5_PAD0 _L_(3) 747 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 748 #define PORT_PA22D_SERCOM5_PAD0 (_UL_(1) << 22) 749 #define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ 750 #define MUX_PB02D_SERCOM5_PAD0 _L_(3) 751 #define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) 752 #define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) 753 #define PIN_PB30D_SERCOM5_PAD0 _L_(62) /**< \brief SERCOM5 signal: PAD0 on PB30 mux D */ 754 #define MUX_PB30D_SERCOM5_PAD0 _L_(3) 755 #define PINMUX_PB30D_SERCOM5_PAD0 ((PIN_PB30D_SERCOM5_PAD0 << 16) | MUX_PB30D_SERCOM5_PAD0) 756 #define PORT_PB30D_SERCOM5_PAD0 (_UL_(1) << 30) 757 #define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ 758 #define MUX_PB16C_SERCOM5_PAD0 _L_(2) 759 #define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) 760 #define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) 761 #define PIN_PA23D_SERCOM5_PAD1 _L_(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 762 #define MUX_PA23D_SERCOM5_PAD1 _L_(3) 763 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 764 #define PORT_PA23D_SERCOM5_PAD1 (_UL_(1) << 23) 765 #define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ 766 #define MUX_PB03D_SERCOM5_PAD1 _L_(3) 767 #define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) 768 #define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) 769 #define PIN_PB31D_SERCOM5_PAD1 _L_(63) /**< \brief SERCOM5 signal: PAD1 on PB31 mux D */ 770 #define MUX_PB31D_SERCOM5_PAD1 _L_(3) 771 #define PINMUX_PB31D_SERCOM5_PAD1 ((PIN_PB31D_SERCOM5_PAD1 << 16) | MUX_PB31D_SERCOM5_PAD1) 772 #define PORT_PB31D_SERCOM5_PAD1 (_UL_(1) << 31) 773 #define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ 774 #define MUX_PB17C_SERCOM5_PAD1 _L_(2) 775 #define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) 776 #define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) 777 #define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 778 #define MUX_PA24D_SERCOM5_PAD2 _L_(3) 779 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 780 #define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) 781 #define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ 782 #define MUX_PB00D_SERCOM5_PAD2 _L_(3) 783 #define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) 784 #define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) 785 #define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ 786 #define MUX_PB22D_SERCOM5_PAD2 _L_(3) 787 #define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) 788 #define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) 789 #define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ 790 #define MUX_PA20C_SERCOM5_PAD2 _L_(2) 791 #define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) 792 #define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) 793 #define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 794 #define MUX_PA25D_SERCOM5_PAD3 _L_(3) 795 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 796 #define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) 797 #define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ 798 #define MUX_PB01D_SERCOM5_PAD3 _L_(3) 799 #define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) 800 #define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) 801 #define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ 802 #define MUX_PB23D_SERCOM5_PAD3 _L_(3) 803 #define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) 804 #define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) 805 #define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ 806 #define MUX_PA21C_SERCOM5_PAD3 _L_(2) 807 #define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) 808 #define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) 809 /* ========== PORT definition for CAN0 peripheral ========== */ 810 #define PIN_PA25G_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux G */ 811 #define MUX_PA25G_CAN0_RX _L_(6) 812 #define PINMUX_PA25G_CAN0_RX ((PIN_PA25G_CAN0_RX << 16) | MUX_PA25G_CAN0_RX) 813 #define PORT_PA25G_CAN0_RX (_UL_(1) << 25) 814 #define PIN_PB23G_CAN0_RX _L_(55) /**< \brief CAN0 signal: RX on PB23 mux G */ 815 #define MUX_PB23G_CAN0_RX _L_(6) 816 #define PINMUX_PB23G_CAN0_RX ((PIN_PB23G_CAN0_RX << 16) | MUX_PB23G_CAN0_RX) 817 #define PORT_PB23G_CAN0_RX (_UL_(1) << 23) 818 #define PIN_PA24G_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux G */ 819 #define MUX_PA24G_CAN0_TX _L_(6) 820 #define PINMUX_PA24G_CAN0_TX ((PIN_PA24G_CAN0_TX << 16) | MUX_PA24G_CAN0_TX) 821 #define PORT_PA24G_CAN0_TX (_UL_(1) << 24) 822 #define PIN_PB22G_CAN0_TX _L_(54) /**< \brief CAN0 signal: TX on PB22 mux G */ 823 #define MUX_PB22G_CAN0_TX _L_(6) 824 #define PINMUX_PB22G_CAN0_TX ((PIN_PB22G_CAN0_TX << 16) | MUX_PB22G_CAN0_TX) 825 #define PORT_PB22G_CAN0_TX (_UL_(1) << 22) 826 /* ========== PORT definition for CAN1 peripheral ========== */ 827 #define PIN_PB11G_CAN1_RX _L_(43) /**< \brief CAN1 signal: RX on PB11 mux G */ 828 #define MUX_PB11G_CAN1_RX _L_(6) 829 #define PINMUX_PB11G_CAN1_RX ((PIN_PB11G_CAN1_RX << 16) | MUX_PB11G_CAN1_RX) 830 #define PORT_PB11G_CAN1_RX (_UL_(1) << 11) 831 #define PIN_PB15G_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux G */ 832 #define MUX_PB15G_CAN1_RX _L_(6) 833 #define PINMUX_PB15G_CAN1_RX ((PIN_PB15G_CAN1_RX << 16) | MUX_PB15G_CAN1_RX) 834 #define PORT_PB15G_CAN1_RX (_UL_(1) << 15) 835 #define PIN_PB10G_CAN1_TX _L_(42) /**< \brief CAN1 signal: TX on PB10 mux G */ 836 #define MUX_PB10G_CAN1_TX _L_(6) 837 #define PINMUX_PB10G_CAN1_TX ((PIN_PB10G_CAN1_TX << 16) | MUX_PB10G_CAN1_TX) 838 #define PORT_PB10G_CAN1_TX (_UL_(1) << 10) 839 #define PIN_PB14G_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux G */ 840 #define MUX_PB14G_CAN1_TX _L_(6) 841 #define PINMUX_PB14G_CAN1_TX ((PIN_PB14G_CAN1_TX << 16) | MUX_PB14G_CAN1_TX) 842 #define PORT_PB14G_CAN1_TX (_UL_(1) << 14) 843 /* ========== PORT definition for TCC0 peripheral ========== */ 844 #define PIN_PA04E_TCC0_WO0 _L_(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 845 #define MUX_PA04E_TCC0_WO0 _L_(4) 846 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 847 #define PORT_PA04E_TCC0_WO0 (_UL_(1) << 4) 848 #define PIN_PA08E_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 849 #define MUX_PA08E_TCC0_WO0 _L_(4) 850 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 851 #define PORT_PA08E_TCC0_WO0 (_UL_(1) << 8) 852 #define PIN_PB30E_TCC0_WO0 _L_(62) /**< \brief TCC0 signal: WO0 on PB30 mux E */ 853 #define MUX_PB30E_TCC0_WO0 _L_(4) 854 #define PINMUX_PB30E_TCC0_WO0 ((PIN_PB30E_TCC0_WO0 << 16) | MUX_PB30E_TCC0_WO0) 855 #define PORT_PB30E_TCC0_WO0 (_UL_(1) << 30) 856 #define PIN_PA05E_TCC0_WO1 _L_(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 857 #define MUX_PA05E_TCC0_WO1 _L_(4) 858 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 859 #define PORT_PA05E_TCC0_WO1 (_UL_(1) << 5) 860 #define PIN_PA09E_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 861 #define MUX_PA09E_TCC0_WO1 _L_(4) 862 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 863 #define PORT_PA09E_TCC0_WO1 (_UL_(1) << 9) 864 #define PIN_PB31E_TCC0_WO1 _L_(63) /**< \brief TCC0 signal: WO1 on PB31 mux E */ 865 #define MUX_PB31E_TCC0_WO1 _L_(4) 866 #define PINMUX_PB31E_TCC0_WO1 ((PIN_PB31E_TCC0_WO1 << 16) | MUX_PB31E_TCC0_WO1) 867 #define PORT_PB31E_TCC0_WO1 (_UL_(1) << 31) 868 #define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 869 #define MUX_PA10F_TCC0_WO2 _L_(5) 870 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 871 #define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) 872 #define PIN_PA18F_TCC0_WO2 _L_(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 873 #define MUX_PA18F_TCC0_WO2 _L_(5) 874 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 875 #define PORT_PA18F_TCC0_WO2 (_UL_(1) << 18) 876 #define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 877 #define MUX_PA11F_TCC0_WO3 _L_(5) 878 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 879 #define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) 880 #define PIN_PA19F_TCC0_WO3 _L_(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 881 #define MUX_PA19F_TCC0_WO3 _L_(5) 882 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 883 #define PORT_PA19F_TCC0_WO3 (_UL_(1) << 19) 884 #define PIN_PA22F_TCC0_WO4 _L_(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 885 #define MUX_PA22F_TCC0_WO4 _L_(5) 886 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 887 #define PORT_PA22F_TCC0_WO4 (_UL_(1) << 22) 888 #define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ 889 #define MUX_PB10F_TCC0_WO4 _L_(5) 890 #define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) 891 #define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) 892 #define PIN_PB16F_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux F */ 893 #define MUX_PB16F_TCC0_WO4 _L_(5) 894 #define PINMUX_PB16F_TCC0_WO4 ((PIN_PB16F_TCC0_WO4 << 16) | MUX_PB16F_TCC0_WO4) 895 #define PORT_PB16F_TCC0_WO4 (_UL_(1) << 16) 896 #define PIN_PA14F_TCC0_WO4 _L_(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ 897 #define MUX_PA14F_TCC0_WO4 _L_(5) 898 #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) 899 #define PORT_PA14F_TCC0_WO4 (_UL_(1) << 14) 900 #define PIN_PA15F_TCC0_WO5 _L_(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ 901 #define MUX_PA15F_TCC0_WO5 _L_(5) 902 #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) 903 #define PORT_PA15F_TCC0_WO5 (_UL_(1) << 15) 904 #define PIN_PA23F_TCC0_WO5 _L_(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 905 #define MUX_PA23F_TCC0_WO5 _L_(5) 906 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 907 #define PORT_PA23F_TCC0_WO5 (_UL_(1) << 23) 908 #define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ 909 #define MUX_PB11F_TCC0_WO5 _L_(5) 910 #define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) 911 #define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) 912 #define PIN_PB17F_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux F */ 913 #define MUX_PB17F_TCC0_WO5 _L_(5) 914 #define PINMUX_PB17F_TCC0_WO5 ((PIN_PB17F_TCC0_WO5 << 16) | MUX_PB17F_TCC0_WO5) 915 #define PORT_PB17F_TCC0_WO5 (_UL_(1) << 17) 916 #define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ 917 #define MUX_PA12F_TCC0_WO6 _L_(5) 918 #define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) 919 #define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) 920 #define PIN_PA16F_TCC0_WO6 _L_(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ 921 #define MUX_PA16F_TCC0_WO6 _L_(5) 922 #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) 923 #define PORT_PA16F_TCC0_WO6 (_UL_(1) << 16) 924 #define PIN_PA20F_TCC0_WO6 _L_(20) /**< \brief TCC0 signal: WO6 on PA20 mux F */ 925 #define MUX_PA20F_TCC0_WO6 _L_(5) 926 #define PINMUX_PA20F_TCC0_WO6 ((PIN_PA20F_TCC0_WO6 << 16) | MUX_PA20F_TCC0_WO6) 927 #define PORT_PA20F_TCC0_WO6 (_UL_(1) << 20) 928 #define PIN_PB12F_TCC0_WO6 _L_(44) /**< \brief TCC0 signal: WO6 on PB12 mux F */ 929 #define MUX_PB12F_TCC0_WO6 _L_(5) 930 #define PINMUX_PB12F_TCC0_WO6 ((PIN_PB12F_TCC0_WO6 << 16) | MUX_PB12F_TCC0_WO6) 931 #define PORT_PB12F_TCC0_WO6 (_UL_(1) << 12) 932 #define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ 933 #define MUX_PA13F_TCC0_WO7 _L_(5) 934 #define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) 935 #define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) 936 #define PIN_PA17F_TCC0_WO7 _L_(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ 937 #define MUX_PA17F_TCC0_WO7 _L_(5) 938 #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) 939 #define PORT_PA17F_TCC0_WO7 (_UL_(1) << 17) 940 #define PIN_PA21F_TCC0_WO7 _L_(21) /**< \brief TCC0 signal: WO7 on PA21 mux F */ 941 #define MUX_PA21F_TCC0_WO7 _L_(5) 942 #define PINMUX_PA21F_TCC0_WO7 ((PIN_PA21F_TCC0_WO7 << 16) | MUX_PA21F_TCC0_WO7) 943 #define PORT_PA21F_TCC0_WO7 (_UL_(1) << 21) 944 #define PIN_PB13F_TCC0_WO7 _L_(45) /**< \brief TCC0 signal: WO7 on PB13 mux F */ 945 #define MUX_PB13F_TCC0_WO7 _L_(5) 946 #define PINMUX_PB13F_TCC0_WO7 ((PIN_PB13F_TCC0_WO7 << 16) | MUX_PB13F_TCC0_WO7) 947 #define PORT_PB13F_TCC0_WO7 (_UL_(1) << 13) 948 /* ========== PORT definition for TCC1 peripheral ========== */ 949 #define PIN_PA06E_TCC1_WO0 _L_(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 950 #define MUX_PA06E_TCC1_WO0 _L_(4) 951 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 952 #define PORT_PA06E_TCC1_WO0 (_UL_(1) << 6) 953 #define PIN_PA10E_TCC1_WO0 _L_(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 954 #define MUX_PA10E_TCC1_WO0 _L_(4) 955 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 956 #define PORT_PA10E_TCC1_WO0 (_UL_(1) << 10) 957 #define PIN_PA30E_TCC1_WO0 _L_(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 958 #define MUX_PA30E_TCC1_WO0 _L_(4) 959 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 960 #define PORT_PA30E_TCC1_WO0 (_UL_(1) << 30) 961 #define PIN_PA07E_TCC1_WO1 _L_(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 962 #define MUX_PA07E_TCC1_WO1 _L_(4) 963 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 964 #define PORT_PA07E_TCC1_WO1 (_UL_(1) << 7) 965 #define PIN_PA11E_TCC1_WO1 _L_(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 966 #define MUX_PA11E_TCC1_WO1 _L_(4) 967 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 968 #define PORT_PA11E_TCC1_WO1 (_UL_(1) << 11) 969 #define PIN_PA31E_TCC1_WO1 _L_(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 970 #define MUX_PA31E_TCC1_WO1 _L_(4) 971 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 972 #define PORT_PA31E_TCC1_WO1 (_UL_(1) << 31) 973 #define PIN_PA08F_TCC1_WO2 _L_(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */ 974 #define MUX_PA08F_TCC1_WO2 _L_(5) 975 #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) 976 #define PORT_PA08F_TCC1_WO2 (_UL_(1) << 8) 977 #define PIN_PA24F_TCC1_WO2 _L_(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 978 #define MUX_PA24F_TCC1_WO2 _L_(5) 979 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 980 #define PORT_PA24F_TCC1_WO2 (_UL_(1) << 24) 981 #define PIN_PB30F_TCC1_WO2 _L_(62) /**< \brief TCC1 signal: WO2 on PB30 mux F */ 982 #define MUX_PB30F_TCC1_WO2 _L_(5) 983 #define PINMUX_PB30F_TCC1_WO2 ((PIN_PB30F_TCC1_WO2 << 16) | MUX_PB30F_TCC1_WO2) 984 #define PORT_PB30F_TCC1_WO2 (_UL_(1) << 30) 985 #define PIN_PA09F_TCC1_WO3 _L_(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */ 986 #define MUX_PA09F_TCC1_WO3 _L_(5) 987 #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) 988 #define PORT_PA09F_TCC1_WO3 (_UL_(1) << 9) 989 #define PIN_PA25F_TCC1_WO3 _L_(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 990 #define MUX_PA25F_TCC1_WO3 _L_(5) 991 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 992 #define PORT_PA25F_TCC1_WO3 (_UL_(1) << 25) 993 #define PIN_PB31F_TCC1_WO3 _L_(63) /**< \brief TCC1 signal: WO3 on PB31 mux F */ 994 #define MUX_PB31F_TCC1_WO3 _L_(5) 995 #define PINMUX_PB31F_TCC1_WO3 ((PIN_PB31F_TCC1_WO3 << 16) | MUX_PB31F_TCC1_WO3) 996 #define PORT_PB31F_TCC1_WO3 (_UL_(1) << 31) 997 /* ========== PORT definition for TCC2 peripheral ========== */ 998 #define PIN_PA12E_TCC2_WO0 _L_(12) /**< \brief TCC2 signal: WO0 on PA12 mux E */ 999 #define MUX_PA12E_TCC2_WO0 _L_(4) 1000 #define PINMUX_PA12E_TCC2_WO0 ((PIN_PA12E_TCC2_WO0 << 16) | MUX_PA12E_TCC2_WO0) 1001 #define PORT_PA12E_TCC2_WO0 (_UL_(1) << 12) 1002 #define PIN_PA16E_TCC2_WO0 _L_(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 1003 #define MUX_PA16E_TCC2_WO0 _L_(4) 1004 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 1005 #define PORT_PA16E_TCC2_WO0 (_UL_(1) << 16) 1006 #define PIN_PA00E_TCC2_WO0 _L_(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 1007 #define MUX_PA00E_TCC2_WO0 _L_(4) 1008 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 1009 #define PORT_PA00E_TCC2_WO0 (_UL_(1) << 0) 1010 #define PIN_PA13E_TCC2_WO1 _L_(13) /**< \brief TCC2 signal: WO1 on PA13 mux E */ 1011 #define MUX_PA13E_TCC2_WO1 _L_(4) 1012 #define PINMUX_PA13E_TCC2_WO1 ((PIN_PA13E_TCC2_WO1 << 16) | MUX_PA13E_TCC2_WO1) 1013 #define PORT_PA13E_TCC2_WO1 (_UL_(1) << 13) 1014 #define PIN_PA17E_TCC2_WO1 _L_(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 1015 #define MUX_PA17E_TCC2_WO1 _L_(4) 1016 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 1017 #define PORT_PA17E_TCC2_WO1 (_UL_(1) << 17) 1018 #define PIN_PA01E_TCC2_WO1 _L_(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 1019 #define MUX_PA01E_TCC2_WO1 _L_(4) 1020 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 1021 #define PORT_PA01E_TCC2_WO1 (_UL_(1) << 1) 1022 /* ========== PORT definition for TC0 peripheral ========== */ 1023 #define PIN_PA22E_TC0_WO0 _L_(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ 1024 #define MUX_PA22E_TC0_WO0 _L_(4) 1025 #define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) 1026 #define PORT_PA22E_TC0_WO0 (_UL_(1) << 22) 1027 #define PIN_PB08E_TC0_WO0 _L_(40) /**< \brief TC0 signal: WO0 on PB08 mux E */ 1028 #define MUX_PB08E_TC0_WO0 _L_(4) 1029 #define PINMUX_PB08E_TC0_WO0 ((PIN_PB08E_TC0_WO0 << 16) | MUX_PB08E_TC0_WO0) 1030 #define PORT_PB08E_TC0_WO0 (_UL_(1) << 8) 1031 #define PIN_PB12E_TC0_WO0 _L_(44) /**< \brief TC0 signal: WO0 on PB12 mux E */ 1032 #define MUX_PB12E_TC0_WO0 _L_(4) 1033 #define PINMUX_PB12E_TC0_WO0 ((PIN_PB12E_TC0_WO0 << 16) | MUX_PB12E_TC0_WO0) 1034 #define PORT_PB12E_TC0_WO0 (_UL_(1) << 12) 1035 #define PIN_PA23E_TC0_WO1 _L_(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ 1036 #define MUX_PA23E_TC0_WO1 _L_(4) 1037 #define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) 1038 #define PORT_PA23E_TC0_WO1 (_UL_(1) << 23) 1039 #define PIN_PB09E_TC0_WO1 _L_(41) /**< \brief TC0 signal: WO1 on PB09 mux E */ 1040 #define MUX_PB09E_TC0_WO1 _L_(4) 1041 #define PINMUX_PB09E_TC0_WO1 ((PIN_PB09E_TC0_WO1 << 16) | MUX_PB09E_TC0_WO1) 1042 #define PORT_PB09E_TC0_WO1 (_UL_(1) << 9) 1043 #define PIN_PB13E_TC0_WO1 _L_(45) /**< \brief TC0 signal: WO1 on PB13 mux E */ 1044 #define MUX_PB13E_TC0_WO1 _L_(4) 1045 #define PINMUX_PB13E_TC0_WO1 ((PIN_PB13E_TC0_WO1 << 16) | MUX_PB13E_TC0_WO1) 1046 #define PORT_PB13E_TC0_WO1 (_UL_(1) << 13) 1047 /* ========== PORT definition for TC1 peripheral ========== */ 1048 #define PIN_PA24E_TC1_WO0 _L_(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ 1049 #define MUX_PA24E_TC1_WO0 _L_(4) 1050 #define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) 1051 #define PORT_PA24E_TC1_WO0 (_UL_(1) << 24) 1052 #define PIN_PB10E_TC1_WO0 _L_(42) /**< \brief TC1 signal: WO0 on PB10 mux E */ 1053 #define MUX_PB10E_TC1_WO0 _L_(4) 1054 #define PINMUX_PB10E_TC1_WO0 ((PIN_PB10E_TC1_WO0 << 16) | MUX_PB10E_TC1_WO0) 1055 #define PORT_PB10E_TC1_WO0 (_UL_(1) << 10) 1056 #define PIN_PB14E_TC1_WO0 _L_(46) /**< \brief TC1 signal: WO0 on PB14 mux E */ 1057 #define MUX_PB14E_TC1_WO0 _L_(4) 1058 #define PINMUX_PB14E_TC1_WO0 ((PIN_PB14E_TC1_WO0 << 16) | MUX_PB14E_TC1_WO0) 1059 #define PORT_PB14E_TC1_WO0 (_UL_(1) << 14) 1060 #define PIN_PA25E_TC1_WO1 _L_(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ 1061 #define MUX_PA25E_TC1_WO1 _L_(4) 1062 #define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) 1063 #define PORT_PA25E_TC1_WO1 (_UL_(1) << 25) 1064 #define PIN_PB11E_TC1_WO1 _L_(43) /**< \brief TC1 signal: WO1 on PB11 mux E */ 1065 #define MUX_PB11E_TC1_WO1 _L_(4) 1066 #define PINMUX_PB11E_TC1_WO1 ((PIN_PB11E_TC1_WO1 << 16) | MUX_PB11E_TC1_WO1) 1067 #define PORT_PB11E_TC1_WO1 (_UL_(1) << 11) 1068 #define PIN_PB15E_TC1_WO1 _L_(47) /**< \brief TC1 signal: WO1 on PB15 mux E */ 1069 #define MUX_PB15E_TC1_WO1 _L_(4) 1070 #define PINMUX_PB15E_TC1_WO1 ((PIN_PB15E_TC1_WO1 << 16) | MUX_PB15E_TC1_WO1) 1071 #define PORT_PB15E_TC1_WO1 (_UL_(1) << 15) 1072 /* ========== PORT definition for TC2 peripheral ========== */ 1073 #define PIN_PB02E_TC2_WO0 _L_(34) /**< \brief TC2 signal: WO0 on PB02 mux E */ 1074 #define MUX_PB02E_TC2_WO0 _L_(4) 1075 #define PINMUX_PB02E_TC2_WO0 ((PIN_PB02E_TC2_WO0 << 16) | MUX_PB02E_TC2_WO0) 1076 #define PORT_PB02E_TC2_WO0 (_UL_(1) << 2) 1077 #define PIN_PB16E_TC2_WO0 _L_(48) /**< \brief TC2 signal: WO0 on PB16 mux E */ 1078 #define MUX_PB16E_TC2_WO0 _L_(4) 1079 #define PINMUX_PB16E_TC2_WO0 ((PIN_PB16E_TC2_WO0 << 16) | MUX_PB16E_TC2_WO0) 1080 #define PORT_PB16E_TC2_WO0 (_UL_(1) << 16) 1081 #define PIN_PB03E_TC2_WO1 _L_(35) /**< \brief TC2 signal: WO1 on PB03 mux E */ 1082 #define MUX_PB03E_TC2_WO1 _L_(4) 1083 #define PINMUX_PB03E_TC2_WO1 ((PIN_PB03E_TC2_WO1 << 16) | MUX_PB03E_TC2_WO1) 1084 #define PORT_PB03E_TC2_WO1 (_UL_(1) << 3) 1085 #define PIN_PB17E_TC2_WO1 _L_(49) /**< \brief TC2 signal: WO1 on PB17 mux E */ 1086 #define MUX_PB17E_TC2_WO1 _L_(4) 1087 #define PINMUX_PB17E_TC2_WO1 ((PIN_PB17E_TC2_WO1 << 16) | MUX_PB17E_TC2_WO1) 1088 #define PORT_PB17E_TC2_WO1 (_UL_(1) << 17) 1089 /* ========== PORT definition for TC3 peripheral ========== */ 1090 #define PIN_PA20E_TC3_WO0 _L_(20) /**< \brief TC3 signal: WO0 on PA20 mux E */ 1091 #define MUX_PA20E_TC3_WO0 _L_(4) 1092 #define PINMUX_PA20E_TC3_WO0 ((PIN_PA20E_TC3_WO0 << 16) | MUX_PA20E_TC3_WO0) 1093 #define PORT_PA20E_TC3_WO0 (_UL_(1) << 20) 1094 #define PIN_PB00E_TC3_WO0 _L_(32) /**< \brief TC3 signal: WO0 on PB00 mux E */ 1095 #define MUX_PB00E_TC3_WO0 _L_(4) 1096 #define PINMUX_PB00E_TC3_WO0 ((PIN_PB00E_TC3_WO0 << 16) | MUX_PB00E_TC3_WO0) 1097 #define PORT_PB00E_TC3_WO0 (_UL_(1) << 0) 1098 #define PIN_PB22E_TC3_WO0 _L_(54) /**< \brief TC3 signal: WO0 on PB22 mux E */ 1099 #define MUX_PB22E_TC3_WO0 _L_(4) 1100 #define PINMUX_PB22E_TC3_WO0 ((PIN_PB22E_TC3_WO0 << 16) | MUX_PB22E_TC3_WO0) 1101 #define PORT_PB22E_TC3_WO0 (_UL_(1) << 22) 1102 #define PIN_PA21E_TC3_WO1 _L_(21) /**< \brief TC3 signal: WO1 on PA21 mux E */ 1103 #define MUX_PA21E_TC3_WO1 _L_(4) 1104 #define PINMUX_PA21E_TC3_WO1 ((PIN_PA21E_TC3_WO1 << 16) | MUX_PA21E_TC3_WO1) 1105 #define PORT_PA21E_TC3_WO1 (_UL_(1) << 21) 1106 #define PIN_PB01E_TC3_WO1 _L_(33) /**< \brief TC3 signal: WO1 on PB01 mux E */ 1107 #define MUX_PB01E_TC3_WO1 _L_(4) 1108 #define PINMUX_PB01E_TC3_WO1 ((PIN_PB01E_TC3_WO1 << 16) | MUX_PB01E_TC3_WO1) 1109 #define PORT_PB01E_TC3_WO1 (_UL_(1) << 1) 1110 #define PIN_PB23E_TC3_WO1 _L_(55) /**< \brief TC3 signal: WO1 on PB23 mux E */ 1111 #define MUX_PB23E_TC3_WO1 _L_(4) 1112 #define PINMUX_PB23E_TC3_WO1 ((PIN_PB23E_TC3_WO1 << 16) | MUX_PB23E_TC3_WO1) 1113 #define PORT_PB23E_TC3_WO1 (_UL_(1) << 23) 1114 /* ========== PORT definition for TC4 peripheral ========== */ 1115 #define PIN_PA18E_TC4_WO0 _L_(18) /**< \brief TC4 signal: WO0 on PA18 mux E */ 1116 #define MUX_PA18E_TC4_WO0 _L_(4) 1117 #define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) 1118 #define PORT_PA18E_TC4_WO0 (_UL_(1) << 18) 1119 #define PIN_PA14E_TC4_WO0 _L_(14) /**< \brief TC4 signal: WO0 on PA14 mux E */ 1120 #define MUX_PA14E_TC4_WO0 _L_(4) 1121 #define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) 1122 #define PORT_PA14E_TC4_WO0 (_UL_(1) << 14) 1123 #define PIN_PA19E_TC4_WO1 _L_(19) /**< \brief TC4 signal: WO1 on PA19 mux E */ 1124 #define MUX_PA19E_TC4_WO1 _L_(4) 1125 #define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) 1126 #define PORT_PA19E_TC4_WO1 (_UL_(1) << 19) 1127 #define PIN_PA15E_TC4_WO1 _L_(15) /**< \brief TC4 signal: WO1 on PA15 mux E */ 1128 #define MUX_PA15E_TC4_WO1 _L_(4) 1129 #define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) 1130 #define PORT_PA15E_TC4_WO1 (_UL_(1) << 15) 1131 /* ========== PORT definition for ADC0 peripheral ========== */ 1132 #define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ 1133 #define MUX_PA02B_ADC0_AIN0 _L_(1) 1134 #define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) 1135 #define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) 1136 #define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ 1137 #define MUX_PA03B_ADC0_AIN1 _L_(1) 1138 #define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) 1139 #define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) 1140 #define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ 1141 #define MUX_PB08B_ADC0_AIN2 _L_(1) 1142 #define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) 1143 #define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) 1144 #define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ 1145 #define MUX_PB09B_ADC0_AIN3 _L_(1) 1146 #define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) 1147 #define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) 1148 #define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ 1149 #define MUX_PA04B_ADC0_AIN4 _L_(1) 1150 #define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) 1151 #define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) 1152 #define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ 1153 #define MUX_PA05B_ADC0_AIN5 _L_(1) 1154 #define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) 1155 #define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) 1156 #define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ 1157 #define MUX_PA06B_ADC0_AIN6 _L_(1) 1158 #define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) 1159 #define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) 1160 #define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ 1161 #define MUX_PA07B_ADC0_AIN7 _L_(1) 1162 #define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) 1163 #define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) 1164 #define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ 1165 #define MUX_PA08B_ADC0_AIN8 _L_(1) 1166 #define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) 1167 #define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) 1168 #define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ 1169 #define MUX_PA09B_ADC0_AIN9 _L_(1) 1170 #define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) 1171 #define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) 1172 #define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ 1173 #define MUX_PA10B_ADC0_AIN10 _L_(1) 1174 #define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) 1175 #define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) 1176 #define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ 1177 #define MUX_PA11B_ADC0_AIN11 _L_(1) 1178 #define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) 1179 #define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) 1180 #define PIN_PA03B_ADC0_VREFP _L_(3) /**< \brief ADC0 signal: VREFP on PA03 mux B */ 1181 #define MUX_PA03B_ADC0_VREFP _L_(1) 1182 #define PINMUX_PA03B_ADC0_VREFP ((PIN_PA03B_ADC0_VREFP << 16) | MUX_PA03B_ADC0_VREFP) 1183 #define PORT_PA03B_ADC0_VREFP (_UL_(1) << 3) 1184 /* ========== PORT definition for ADC1 peripheral ========== */ 1185 #define PIN_PB00B_ADC1_AIN0 _L_(32) /**< \brief ADC1 signal: AIN0 on PB00 mux B */ 1186 #define MUX_PB00B_ADC1_AIN0 _L_(1) 1187 #define PINMUX_PB00B_ADC1_AIN0 ((PIN_PB00B_ADC1_AIN0 << 16) | MUX_PB00B_ADC1_AIN0) 1188 #define PORT_PB00B_ADC1_AIN0 (_UL_(1) << 0) 1189 #define PIN_PB01B_ADC1_AIN1 _L_(33) /**< \brief ADC1 signal: AIN1 on PB01 mux B */ 1190 #define MUX_PB01B_ADC1_AIN1 _L_(1) 1191 #define PINMUX_PB01B_ADC1_AIN1 ((PIN_PB01B_ADC1_AIN1 << 16) | MUX_PB01B_ADC1_AIN1) 1192 #define PORT_PB01B_ADC1_AIN1 (_UL_(1) << 1) 1193 #define PIN_PB02B_ADC1_AIN2 _L_(34) /**< \brief ADC1 signal: AIN2 on PB02 mux B */ 1194 #define MUX_PB02B_ADC1_AIN2 _L_(1) 1195 #define PINMUX_PB02B_ADC1_AIN2 ((PIN_PB02B_ADC1_AIN2 << 16) | MUX_PB02B_ADC1_AIN2) 1196 #define PORT_PB02B_ADC1_AIN2 (_UL_(1) << 2) 1197 #define PIN_PB03B_ADC1_AIN3 _L_(35) /**< \brief ADC1 signal: AIN3 on PB03 mux B */ 1198 #define MUX_PB03B_ADC1_AIN3 _L_(1) 1199 #define PINMUX_PB03B_ADC1_AIN3 ((PIN_PB03B_ADC1_AIN3 << 16) | MUX_PB03B_ADC1_AIN3) 1200 #define PORT_PB03B_ADC1_AIN3 (_UL_(1) << 3) 1201 #define PIN_PB08B_ADC1_AIN4 _L_(40) /**< \brief ADC1 signal: AIN4 on PB08 mux B */ 1202 #define MUX_PB08B_ADC1_AIN4 _L_(1) 1203 #define PINMUX_PB08B_ADC1_AIN4 ((PIN_PB08B_ADC1_AIN4 << 16) | MUX_PB08B_ADC1_AIN4) 1204 #define PORT_PB08B_ADC1_AIN4 (_UL_(1) << 8) 1205 #define PIN_PB09B_ADC1_AIN5 _L_(41) /**< \brief ADC1 signal: AIN5 on PB09 mux B */ 1206 #define MUX_PB09B_ADC1_AIN5 _L_(1) 1207 #define PINMUX_PB09B_ADC1_AIN5 ((PIN_PB09B_ADC1_AIN5 << 16) | MUX_PB09B_ADC1_AIN5) 1208 #define PORT_PB09B_ADC1_AIN5 (_UL_(1) << 9) 1209 #define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ 1210 #define MUX_PB04B_ADC1_AIN6 _L_(1) 1211 #define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) 1212 #define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) 1213 #define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ 1214 #define MUX_PB05B_ADC1_AIN7 _L_(1) 1215 #define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) 1216 #define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) 1217 #define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ 1218 #define MUX_PB06B_ADC1_AIN8 _L_(1) 1219 #define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) 1220 #define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) 1221 #define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ 1222 #define MUX_PB07B_ADC1_AIN9 _L_(1) 1223 #define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) 1224 #define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) 1225 #define PIN_PA08B_ADC1_AIN10 _L_(8) /**< \brief ADC1 signal: AIN10 on PA08 mux B */ 1226 #define MUX_PA08B_ADC1_AIN10 _L_(1) 1227 #define PINMUX_PA08B_ADC1_AIN10 ((PIN_PA08B_ADC1_AIN10 << 16) | MUX_PA08B_ADC1_AIN10) 1228 #define PORT_PA08B_ADC1_AIN10 (_UL_(1) << 8) 1229 #define PIN_PA09B_ADC1_AIN11 _L_(9) /**< \brief ADC1 signal: AIN11 on PA09 mux B */ 1230 #define MUX_PA09B_ADC1_AIN11 _L_(1) 1231 #define PINMUX_PA09B_ADC1_AIN11 ((PIN_PA09B_ADC1_AIN11 << 16) | MUX_PA09B_ADC1_AIN11) 1232 #define PORT_PA09B_ADC1_AIN11 (_UL_(1) << 9) 1233 /* ========== PORT definition for SDADC peripheral ========== */ 1234 #define PIN_PA06B_SDADC_INN0 _L_(6) /**< \brief SDADC signal: INN0 on PA06 mux B */ 1235 #define MUX_PA06B_SDADC_INN0 _L_(1) 1236 #define PINMUX_PA06B_SDADC_INN0 ((PIN_PA06B_SDADC_INN0 << 16) | MUX_PA06B_SDADC_INN0) 1237 #define PORT_PA06B_SDADC_INN0 (_UL_(1) << 6) 1238 #define PIN_PB08B_SDADC_INN1 _L_(40) /**< \brief SDADC signal: INN1 on PB08 mux B */ 1239 #define MUX_PB08B_SDADC_INN1 _L_(1) 1240 #define PINMUX_PB08B_SDADC_INN1 ((PIN_PB08B_SDADC_INN1 << 16) | MUX_PB08B_SDADC_INN1) 1241 #define PORT_PB08B_SDADC_INN1 (_UL_(1) << 8) 1242 #define PIN_PB06B_SDADC_INN2 _L_(38) /**< \brief SDADC signal: INN2 on PB06 mux B */ 1243 #define MUX_PB06B_SDADC_INN2 _L_(1) 1244 #define PINMUX_PB06B_SDADC_INN2 ((PIN_PB06B_SDADC_INN2 << 16) | MUX_PB06B_SDADC_INN2) 1245 #define PORT_PB06B_SDADC_INN2 (_UL_(1) << 6) 1246 #define PIN_PA07B_SDADC_INP0 _L_(7) /**< \brief SDADC signal: INP0 on PA07 mux B */ 1247 #define MUX_PA07B_SDADC_INP0 _L_(1) 1248 #define PINMUX_PA07B_SDADC_INP0 ((PIN_PA07B_SDADC_INP0 << 16) | MUX_PA07B_SDADC_INP0) 1249 #define PORT_PA07B_SDADC_INP0 (_UL_(1) << 7) 1250 #define PIN_PB09B_SDADC_INP1 _L_(41) /**< \brief SDADC signal: INP1 on PB09 mux B */ 1251 #define MUX_PB09B_SDADC_INP1 _L_(1) 1252 #define PINMUX_PB09B_SDADC_INP1 ((PIN_PB09B_SDADC_INP1 << 16) | MUX_PB09B_SDADC_INP1) 1253 #define PORT_PB09B_SDADC_INP1 (_UL_(1) << 9) 1254 #define PIN_PB07B_SDADC_INP2 _L_(39) /**< \brief SDADC signal: INP2 on PB07 mux B */ 1255 #define MUX_PB07B_SDADC_INP2 _L_(1) 1256 #define PINMUX_PB07B_SDADC_INP2 ((PIN_PB07B_SDADC_INP2 << 16) | MUX_PB07B_SDADC_INP2) 1257 #define PORT_PB07B_SDADC_INP2 (_UL_(1) << 7) 1258 #define PIN_PA04B_SDADC_VREFP _L_(4) /**< \brief SDADC signal: VREFP on PA04 mux B */ 1259 #define MUX_PA04B_SDADC_VREFP _L_(1) 1260 #define PINMUX_PA04B_SDADC_VREFP ((PIN_PA04B_SDADC_VREFP << 16) | MUX_PA04B_SDADC_VREFP) 1261 #define PORT_PA04B_SDADC_VREFP (_UL_(1) << 4) 1262 /* ========== PORT definition for AC peripheral ========== */ 1263 #define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 1264 #define MUX_PA04B_AC_AIN0 _L_(1) 1265 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 1266 #define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) 1267 #define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 1268 #define MUX_PA05B_AC_AIN1 _L_(1) 1269 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 1270 #define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) 1271 #define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 1272 #define MUX_PA06B_AC_AIN2 _L_(1) 1273 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 1274 #define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) 1275 #define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 1276 #define MUX_PA07B_AC_AIN3 _L_(1) 1277 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 1278 #define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) 1279 #define PIN_PA02B_AC_AIN4 _L_(2) /**< \brief AC signal: AIN4 on PA02 mux B */ 1280 #define MUX_PA02B_AC_AIN4 _L_(1) 1281 #define PINMUX_PA02B_AC_AIN4 ((PIN_PA02B_AC_AIN4 << 16) | MUX_PA02B_AC_AIN4) 1282 #define PORT_PA02B_AC_AIN4 (_UL_(1) << 2) 1283 #define PIN_PA03B_AC_AIN5 _L_(3) /**< \brief AC signal: AIN5 on PA03 mux B */ 1284 #define MUX_PA03B_AC_AIN5 _L_(1) 1285 #define PINMUX_PA03B_AC_AIN5 ((PIN_PA03B_AC_AIN5 << 16) | MUX_PA03B_AC_AIN5) 1286 #define PORT_PA03B_AC_AIN5 (_UL_(1) << 3) 1287 #define PIN_PB05B_AC_AIN6 _L_(37) /**< \brief AC signal: AIN6 on PB05 mux B */ 1288 #define MUX_PB05B_AC_AIN6 _L_(1) 1289 #define PINMUX_PB05B_AC_AIN6 ((PIN_PB05B_AC_AIN6 << 16) | MUX_PB05B_AC_AIN6) 1290 #define PORT_PB05B_AC_AIN6 (_UL_(1) << 5) 1291 #define PIN_PB06B_AC_AIN7 _L_(38) /**< \brief AC signal: AIN7 on PB06 mux B */ 1292 #define MUX_PB06B_AC_AIN7 _L_(1) 1293 #define PINMUX_PB06B_AC_AIN7 ((PIN_PB06B_AC_AIN7 << 16) | MUX_PB06B_AC_AIN7) 1294 #define PORT_PB06B_AC_AIN7 (_UL_(1) << 6) 1295 #define PIN_PA12H_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux H */ 1296 #define MUX_PA12H_AC_CMP0 _L_(7) 1297 #define PINMUX_PA12H_AC_CMP0 ((PIN_PA12H_AC_CMP0 << 16) | MUX_PA12H_AC_CMP0) 1298 #define PORT_PA12H_AC_CMP0 (_UL_(1) << 12) 1299 #define PIN_PA18H_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 1300 #define MUX_PA18H_AC_CMP0 _L_(7) 1301 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 1302 #define PORT_PA18H_AC_CMP0 (_UL_(1) << 18) 1303 #define PIN_PA13H_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux H */ 1304 #define MUX_PA13H_AC_CMP1 _L_(7) 1305 #define PINMUX_PA13H_AC_CMP1 ((PIN_PA13H_AC_CMP1 << 16) | MUX_PA13H_AC_CMP1) 1306 #define PORT_PA13H_AC_CMP1 (_UL_(1) << 13) 1307 #define PIN_PA19H_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 1308 #define MUX_PA19H_AC_CMP1 _L_(7) 1309 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 1310 #define PORT_PA19H_AC_CMP1 (_UL_(1) << 19) 1311 #define PIN_PA00H_AC_CMP2 _L_(0) /**< \brief AC signal: CMP2 on PA00 mux H */ 1312 #define MUX_PA00H_AC_CMP2 _L_(7) 1313 #define PINMUX_PA00H_AC_CMP2 ((PIN_PA00H_AC_CMP2 << 16) | MUX_PA00H_AC_CMP2) 1314 #define PORT_PA00H_AC_CMP2 (_UL_(1) << 0) 1315 #define PIN_PA24H_AC_CMP2 _L_(24) /**< \brief AC signal: CMP2 on PA24 mux H */ 1316 #define MUX_PA24H_AC_CMP2 _L_(7) 1317 #define PINMUX_PA24H_AC_CMP2 ((PIN_PA24H_AC_CMP2 << 16) | MUX_PA24H_AC_CMP2) 1318 #define PORT_PA24H_AC_CMP2 (_UL_(1) << 24) 1319 #define PIN_PB30H_AC_CMP2 _L_(62) /**< \brief AC signal: CMP2 on PB30 mux H */ 1320 #define MUX_PB30H_AC_CMP2 _L_(7) 1321 #define PINMUX_PB30H_AC_CMP2 ((PIN_PB30H_AC_CMP2 << 16) | MUX_PB30H_AC_CMP2) 1322 #define PORT_PB30H_AC_CMP2 (_UL_(1) << 30) 1323 #define PIN_PA01H_AC_CMP3 _L_(1) /**< \brief AC signal: CMP3 on PA01 mux H */ 1324 #define MUX_PA01H_AC_CMP3 _L_(7) 1325 #define PINMUX_PA01H_AC_CMP3 ((PIN_PA01H_AC_CMP3 << 16) | MUX_PA01H_AC_CMP3) 1326 #define PORT_PA01H_AC_CMP3 (_UL_(1) << 1) 1327 #define PIN_PA25H_AC_CMP3 _L_(25) /**< \brief AC signal: CMP3 on PA25 mux H */ 1328 #define MUX_PA25H_AC_CMP3 _L_(7) 1329 #define PINMUX_PA25H_AC_CMP3 ((PIN_PA25H_AC_CMP3 << 16) | MUX_PA25H_AC_CMP3) 1330 #define PORT_PA25H_AC_CMP3 (_UL_(1) << 25) 1331 #define PIN_PB31H_AC_CMP3 _L_(63) /**< \brief AC signal: CMP3 on PB31 mux H */ 1332 #define MUX_PB31H_AC_CMP3 _L_(7) 1333 #define PINMUX_PB31H_AC_CMP3 ((PIN_PB31H_AC_CMP3 << 16) | MUX_PB31H_AC_CMP3) 1334 #define PORT_PB31H_AC_CMP3 (_UL_(1) << 31) 1335 /* ========== PORT definition for DAC peripheral ========== */ 1336 #define PIN_PA02B_DAC_VOUT _L_(2) /**< \brief DAC signal: VOUT on PA02 mux B */ 1337 #define MUX_PA02B_DAC_VOUT _L_(1) 1338 #define PINMUX_PA02B_DAC_VOUT ((PIN_PA02B_DAC_VOUT << 16) | MUX_PA02B_DAC_VOUT) 1339 #define PORT_PA02B_DAC_VOUT (_UL_(1) << 2) 1340 #define PIN_PA03B_DAC_VREFP _L_(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 1341 #define MUX_PA03B_DAC_VREFP _L_(1) 1342 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 1343 #define PORT_PA03B_DAC_VREFP (_UL_(1) << 3) 1344 /* ========== PORT definition for CCL peripheral ========== */ 1345 #define PIN_PA04I_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux I */ 1346 #define MUX_PA04I_CCL_IN0 _L_(8) 1347 #define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) 1348 #define PORT_PA04I_CCL_IN0 (_UL_(1) << 4) 1349 #define PIN_PA16I_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux I */ 1350 #define MUX_PA16I_CCL_IN0 _L_(8) 1351 #define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) 1352 #define PORT_PA16I_CCL_IN0 (_UL_(1) << 16) 1353 #define PIN_PB22I_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux I */ 1354 #define MUX_PB22I_CCL_IN0 _L_(8) 1355 #define PINMUX_PB22I_CCL_IN0 ((PIN_PB22I_CCL_IN0 << 16) | MUX_PB22I_CCL_IN0) 1356 #define PORT_PB22I_CCL_IN0 (_UL_(1) << 22) 1357 #define PIN_PA05I_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux I */ 1358 #define MUX_PA05I_CCL_IN1 _L_(8) 1359 #define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) 1360 #define PORT_PA05I_CCL_IN1 (_UL_(1) << 5) 1361 #define PIN_PA17I_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux I */ 1362 #define MUX_PA17I_CCL_IN1 _L_(8) 1363 #define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) 1364 #define PORT_PA17I_CCL_IN1 (_UL_(1) << 17) 1365 #define PIN_PB00I_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux I */ 1366 #define MUX_PB00I_CCL_IN1 _L_(8) 1367 #define PINMUX_PB00I_CCL_IN1 ((PIN_PB00I_CCL_IN1 << 16) | MUX_PB00I_CCL_IN1) 1368 #define PORT_PB00I_CCL_IN1 (_UL_(1) << 0) 1369 #define PIN_PA06I_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux I */ 1370 #define MUX_PA06I_CCL_IN2 _L_(8) 1371 #define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) 1372 #define PORT_PA06I_CCL_IN2 (_UL_(1) << 6) 1373 #define PIN_PA18I_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux I */ 1374 #define MUX_PA18I_CCL_IN2 _L_(8) 1375 #define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) 1376 #define PORT_PA18I_CCL_IN2 (_UL_(1) << 18) 1377 #define PIN_PB01I_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux I */ 1378 #define MUX_PB01I_CCL_IN2 _L_(8) 1379 #define PINMUX_PB01I_CCL_IN2 ((PIN_PB01I_CCL_IN2 << 16) | MUX_PB01I_CCL_IN2) 1380 #define PORT_PB01I_CCL_IN2 (_UL_(1) << 1) 1381 #define PIN_PA08I_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux I */ 1382 #define MUX_PA08I_CCL_IN3 _L_(8) 1383 #define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) 1384 #define PORT_PA08I_CCL_IN3 (_UL_(1) << 8) 1385 #define PIN_PA30I_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux I */ 1386 #define MUX_PA30I_CCL_IN3 _L_(8) 1387 #define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) 1388 #define PORT_PA30I_CCL_IN3 (_UL_(1) << 30) 1389 #define PIN_PA09I_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux I */ 1390 #define MUX_PA09I_CCL_IN4 _L_(8) 1391 #define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) 1392 #define PORT_PA09I_CCL_IN4 (_UL_(1) << 9) 1393 #define PIN_PA10I_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux I */ 1394 #define MUX_PA10I_CCL_IN5 _L_(8) 1395 #define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) 1396 #define PORT_PA10I_CCL_IN5 (_UL_(1) << 10) 1397 #define PIN_PB10I_CCL_IN5 _L_(42) /**< \brief CCL signal: IN5 on PB10 mux I */ 1398 #define MUX_PB10I_CCL_IN5 _L_(8) 1399 #define PINMUX_PB10I_CCL_IN5 ((PIN_PB10I_CCL_IN5 << 16) | MUX_PB10I_CCL_IN5) 1400 #define PORT_PB10I_CCL_IN5 (_UL_(1) << 10) 1401 #define PIN_PA22I_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux I */ 1402 #define MUX_PA22I_CCL_IN6 _L_(8) 1403 #define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) 1404 #define PORT_PA22I_CCL_IN6 (_UL_(1) << 22) 1405 #define PIN_PB06I_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux I */ 1406 #define MUX_PB06I_CCL_IN6 _L_(8) 1407 #define PINMUX_PB06I_CCL_IN6 ((PIN_PB06I_CCL_IN6 << 16) | MUX_PB06I_CCL_IN6) 1408 #define PORT_PB06I_CCL_IN6 (_UL_(1) << 6) 1409 #define PIN_PA23I_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux I */ 1410 #define MUX_PA23I_CCL_IN7 _L_(8) 1411 #define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) 1412 #define PORT_PA23I_CCL_IN7 (_UL_(1) << 23) 1413 #define PIN_PB07I_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux I */ 1414 #define MUX_PB07I_CCL_IN7 _L_(8) 1415 #define PINMUX_PB07I_CCL_IN7 ((PIN_PB07I_CCL_IN7 << 16) | MUX_PB07I_CCL_IN7) 1416 #define PORT_PB07I_CCL_IN7 (_UL_(1) << 7) 1417 #define PIN_PA24I_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux I */ 1418 #define MUX_PA24I_CCL_IN8 _L_(8) 1419 #define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) 1420 #define PORT_PA24I_CCL_IN8 (_UL_(1) << 24) 1421 #define PIN_PB08I_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux I */ 1422 #define MUX_PB08I_CCL_IN8 _L_(8) 1423 #define PINMUX_PB08I_CCL_IN8 ((PIN_PB08I_CCL_IN8 << 16) | MUX_PB08I_CCL_IN8) 1424 #define PORT_PB08I_CCL_IN8 (_UL_(1) << 8) 1425 #define PIN_PB14I_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux I */ 1426 #define MUX_PB14I_CCL_IN9 _L_(8) 1427 #define PINMUX_PB14I_CCL_IN9 ((PIN_PB14I_CCL_IN9 << 16) | MUX_PB14I_CCL_IN9) 1428 #define PORT_PB14I_CCL_IN9 (_UL_(1) << 14) 1429 #define PIN_PB15I_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux I */ 1430 #define MUX_PB15I_CCL_IN10 _L_(8) 1431 #define PINMUX_PB15I_CCL_IN10 ((PIN_PB15I_CCL_IN10 << 16) | MUX_PB15I_CCL_IN10) 1432 #define PORT_PB15I_CCL_IN10 (_UL_(1) << 15) 1433 #define PIN_PB16I_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux I */ 1434 #define MUX_PB16I_CCL_IN11 _L_(8) 1435 #define PINMUX_PB16I_CCL_IN11 ((PIN_PB16I_CCL_IN11 << 16) | MUX_PB16I_CCL_IN11) 1436 #define PORT_PB16I_CCL_IN11 (_UL_(1) << 16) 1437 #define PIN_PA07I_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ 1438 #define MUX_PA07I_CCL_OUT0 _L_(8) 1439 #define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) 1440 #define PORT_PA07I_CCL_OUT0 (_UL_(1) << 7) 1441 #define PIN_PA19I_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ 1442 #define MUX_PA19I_CCL_OUT0 _L_(8) 1443 #define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) 1444 #define PORT_PA19I_CCL_OUT0 (_UL_(1) << 19) 1445 #define PIN_PB02I_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux I */ 1446 #define MUX_PB02I_CCL_OUT0 _L_(8) 1447 #define PINMUX_PB02I_CCL_OUT0 ((PIN_PB02I_CCL_OUT0 << 16) | MUX_PB02I_CCL_OUT0) 1448 #define PORT_PB02I_CCL_OUT0 (_UL_(1) << 2) 1449 #define PIN_PB23I_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux I */ 1450 #define MUX_PB23I_CCL_OUT0 _L_(8) 1451 #define PINMUX_PB23I_CCL_OUT0 ((PIN_PB23I_CCL_OUT0 << 16) | MUX_PB23I_CCL_OUT0) 1452 #define PORT_PB23I_CCL_OUT0 (_UL_(1) << 23) 1453 #define PIN_PA11I_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ 1454 #define MUX_PA11I_CCL_OUT1 _L_(8) 1455 #define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) 1456 #define PORT_PA11I_CCL_OUT1 (_UL_(1) << 11) 1457 #define PIN_PA31I_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ 1458 #define MUX_PA31I_CCL_OUT1 _L_(8) 1459 #define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) 1460 #define PORT_PA31I_CCL_OUT1 (_UL_(1) << 31) 1461 #define PIN_PB11I_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux I */ 1462 #define MUX_PB11I_CCL_OUT1 _L_(8) 1463 #define PINMUX_PB11I_CCL_OUT1 ((PIN_PB11I_CCL_OUT1 << 16) | MUX_PB11I_CCL_OUT1) 1464 #define PORT_PB11I_CCL_OUT1 (_UL_(1) << 11) 1465 #define PIN_PA25I_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ 1466 #define MUX_PA25I_CCL_OUT2 _L_(8) 1467 #define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) 1468 #define PORT_PA25I_CCL_OUT2 (_UL_(1) << 25) 1469 #define PIN_PB09I_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux I */ 1470 #define MUX_PB09I_CCL_OUT2 _L_(8) 1471 #define PINMUX_PB09I_CCL_OUT2 ((PIN_PB09I_CCL_OUT2 << 16) | MUX_PB09I_CCL_OUT2) 1472 #define PORT_PB09I_CCL_OUT2 (_UL_(1) << 9) 1473 #define PIN_PB17I_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux I */ 1474 #define MUX_PB17I_CCL_OUT3 _L_(8) 1475 #define PINMUX_PB17I_CCL_OUT3 ((PIN_PB17I_CCL_OUT3 << 16) | MUX_PB17I_CCL_OUT3) 1476 #define PORT_PB17I_CCL_OUT3 (_UL_(1) << 17) 1477 1478 #endif /* _SAMC21J17A_PIO_ */ 1479
