1 /** 2 * \file 3 * 4 * \brief Component description for SUPC 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_SUPC_COMPONENT_ 31 #define _SAMC21_SUPC_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR SUPC */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_SUPC Supply Controller */ 37 /*@{*/ 38 39 #define SUPC_U2117 40 #define REV_SUPC 0x211 41 42 /* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */ 47 uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */ 48 uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */ 49 uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */ 50 uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */ 51 uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */ 52 uint32_t :26; /*!< bit: 6..31 Reserved */ 53 } bit; /*!< Structure used for bit access */ 54 uint32_t reg; /*!< Type used for register access */ 55 } SUPC_INTENCLR_Type; 56 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 57 58 #define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */ 59 #define SUPC_INTENCLR_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */ 60 61 #define SUPC_INTENCLR_BODVDDRDY_Pos 0 /**< \brief (SUPC_INTENCLR) BODVDD Ready */ 62 #define SUPC_INTENCLR_BODVDDRDY (_U_(0x1) << SUPC_INTENCLR_BODVDDRDY_Pos) 63 #define SUPC_INTENCLR_BODVDDDET_Pos 1 /**< \brief (SUPC_INTENCLR) BODVDD Detection */ 64 #define SUPC_INTENCLR_BODVDDDET (_U_(0x1) << SUPC_INTENCLR_BODVDDDET_Pos) 65 #define SUPC_INTENCLR_BVDDSRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BODVDD Synchronization Ready */ 66 #define SUPC_INTENCLR_BVDDSRDY (_U_(0x1) << SUPC_INTENCLR_BVDDSRDY_Pos) 67 #define SUPC_INTENCLR_BODCORERDY_Pos 3 /**< \brief (SUPC_INTENCLR) BODCORE Ready */ 68 #define SUPC_INTENCLR_BODCORERDY (_U_(0x1) << SUPC_INTENCLR_BODCORERDY_Pos) 69 #define SUPC_INTENCLR_BODCOREDET_Pos 4 /**< \brief (SUPC_INTENCLR) BODCORE Detection */ 70 #define SUPC_INTENCLR_BODCOREDET (_U_(0x1) << SUPC_INTENCLR_BODCOREDET_Pos) 71 #define SUPC_INTENCLR_BCORESRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BODCORE Synchronization Ready */ 72 #define SUPC_INTENCLR_BCORESRDY (_U_(0x1) << SUPC_INTENCLR_BCORESRDY_Pos) 73 #define SUPC_INTENCLR_MASK _U_(0x0000003F) /**< \brief (SUPC_INTENCLR) MASK Register */ 74 75 /* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 76 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 77 typedef union { 78 struct { 79 uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */ 80 uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */ 81 uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */ 82 uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */ 83 uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */ 84 uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */ 85 uint32_t :26; /*!< bit: 6..31 Reserved */ 86 } bit; /*!< Structure used for bit access */ 87 uint32_t reg; /*!< Type used for register access */ 88 } SUPC_INTENSET_Type; 89 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 90 91 #define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */ 92 #define SUPC_INTENSET_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */ 93 94 #define SUPC_INTENSET_BODVDDRDY_Pos 0 /**< \brief (SUPC_INTENSET) BODVDD Ready */ 95 #define SUPC_INTENSET_BODVDDRDY (_U_(0x1) << SUPC_INTENSET_BODVDDRDY_Pos) 96 #define SUPC_INTENSET_BODVDDDET_Pos 1 /**< \brief (SUPC_INTENSET) BODVDD Detection */ 97 #define SUPC_INTENSET_BODVDDDET (_U_(0x1) << SUPC_INTENSET_BODVDDDET_Pos) 98 #define SUPC_INTENSET_BVDDSRDY_Pos 2 /**< \brief (SUPC_INTENSET) BODVDD Synchronization Ready */ 99 #define SUPC_INTENSET_BVDDSRDY (_U_(0x1) << SUPC_INTENSET_BVDDSRDY_Pos) 100 #define SUPC_INTENSET_BODCORERDY_Pos 3 /**< \brief (SUPC_INTENSET) BODCORE Ready */ 101 #define SUPC_INTENSET_BODCORERDY (_U_(0x1) << SUPC_INTENSET_BODCORERDY_Pos) 102 #define SUPC_INTENSET_BODCOREDET_Pos 4 /**< \brief (SUPC_INTENSET) BODCORE Detection */ 103 #define SUPC_INTENSET_BODCOREDET (_U_(0x1) << SUPC_INTENSET_BODCOREDET_Pos) 104 #define SUPC_INTENSET_BCORESRDY_Pos 5 /**< \brief (SUPC_INTENSET) BODCORE Synchronization Ready */ 105 #define SUPC_INTENSET_BCORESRDY (_U_(0x1) << SUPC_INTENSET_BCORESRDY_Pos) 106 #define SUPC_INTENSET_MASK _U_(0x0000003F) /**< \brief (SUPC_INTENSET) MASK Register */ 107 108 /* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 110 typedef union { // __I to avoid read-modify-write on write-to-clear register 111 struct { 112 __I uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */ 113 __I uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */ 114 __I uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */ 115 __I uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */ 116 __I uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */ 117 __I uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */ 118 __I uint32_t :26; /*!< bit: 6..31 Reserved */ 119 } bit; /*!< Structure used for bit access */ 120 uint32_t reg; /*!< Type used for register access */ 121 } SUPC_INTFLAG_Type; 122 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 123 124 #define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */ 125 #define SUPC_INTFLAG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 126 127 #define SUPC_INTFLAG_BODVDDRDY_Pos 0 /**< \brief (SUPC_INTFLAG) BODVDD Ready */ 128 #define SUPC_INTFLAG_BODVDDRDY (_U_(0x1) << SUPC_INTFLAG_BODVDDRDY_Pos) 129 #define SUPC_INTFLAG_BODVDDDET_Pos 1 /**< \brief (SUPC_INTFLAG) BODVDD Detection */ 130 #define SUPC_INTFLAG_BODVDDDET (_U_(0x1) << SUPC_INTFLAG_BODVDDDET_Pos) 131 #define SUPC_INTFLAG_BVDDSRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BODVDD Synchronization Ready */ 132 #define SUPC_INTFLAG_BVDDSRDY (_U_(0x1) << SUPC_INTFLAG_BVDDSRDY_Pos) 133 #define SUPC_INTFLAG_BODCORERDY_Pos 3 /**< \brief (SUPC_INTFLAG) BODCORE Ready */ 134 #define SUPC_INTFLAG_BODCORERDY (_U_(0x1) << SUPC_INTFLAG_BODCORERDY_Pos) 135 #define SUPC_INTFLAG_BODCOREDET_Pos 4 /**< \brief (SUPC_INTFLAG) BODCORE Detection */ 136 #define SUPC_INTFLAG_BODCOREDET (_U_(0x1) << SUPC_INTFLAG_BODCOREDET_Pos) 137 #define SUPC_INTFLAG_BCORESRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BODCORE Synchronization Ready */ 138 #define SUPC_INTFLAG_BCORESRDY (_U_(0x1) << SUPC_INTFLAG_BCORESRDY_Pos) 139 #define SUPC_INTFLAG_MASK _U_(0x0000003F) /**< \brief (SUPC_INTFLAG) MASK Register */ 140 141 /* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ 142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 143 typedef union { 144 struct { 145 uint32_t BODVDDRDY:1; /*!< bit: 0 BODVDD Ready */ 146 uint32_t BODVDDDET:1; /*!< bit: 1 BODVDD Detection */ 147 uint32_t BVDDSRDY:1; /*!< bit: 2 BODVDD Synchronization Ready */ 148 uint32_t BODCORERDY:1; /*!< bit: 3 BODCORE Ready */ 149 uint32_t BODCOREDET:1; /*!< bit: 4 BODCORE Detection */ 150 uint32_t BCORESRDY:1; /*!< bit: 5 BODCORE Synchronization Ready */ 151 uint32_t :26; /*!< bit: 6..31 Reserved */ 152 } bit; /*!< Structure used for bit access */ 153 uint32_t reg; /*!< Type used for register access */ 154 } SUPC_STATUS_Type; 155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 156 157 #define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */ 158 #define SUPC_STATUS_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */ 159 160 #define SUPC_STATUS_BODVDDRDY_Pos 0 /**< \brief (SUPC_STATUS) BODVDD Ready */ 161 #define SUPC_STATUS_BODVDDRDY (_U_(0x1) << SUPC_STATUS_BODVDDRDY_Pos) 162 #define SUPC_STATUS_BODVDDDET_Pos 1 /**< \brief (SUPC_STATUS) BODVDD Detection */ 163 #define SUPC_STATUS_BODVDDDET (_U_(0x1) << SUPC_STATUS_BODVDDDET_Pos) 164 #define SUPC_STATUS_BVDDSRDY_Pos 2 /**< \brief (SUPC_STATUS) BODVDD Synchronization Ready */ 165 #define SUPC_STATUS_BVDDSRDY (_U_(0x1) << SUPC_STATUS_BVDDSRDY_Pos) 166 #define SUPC_STATUS_BODCORERDY_Pos 3 /**< \brief (SUPC_STATUS) BODCORE Ready */ 167 #define SUPC_STATUS_BODCORERDY (_U_(0x1) << SUPC_STATUS_BODCORERDY_Pos) 168 #define SUPC_STATUS_BODCOREDET_Pos 4 /**< \brief (SUPC_STATUS) BODCORE Detection */ 169 #define SUPC_STATUS_BODCOREDET (_U_(0x1) << SUPC_STATUS_BODCOREDET_Pos) 170 #define SUPC_STATUS_BCORESRDY_Pos 5 /**< \brief (SUPC_STATUS) BODCORE Synchronization Ready */ 171 #define SUPC_STATUS_BCORESRDY (_U_(0x1) << SUPC_STATUS_BCORESRDY_Pos) 172 #define SUPC_STATUS_MASK _U_(0x0000003F) /**< \brief (SUPC_STATUS) MASK Register */ 173 174 /* -------- SUPC_BODVDD : (SUPC Offset: 0x10) (R/W 32) BODVDD Control -------- */ 175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 176 typedef union { 177 struct { 178 uint32_t :1; /*!< bit: 0 Reserved */ 179 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 180 uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ 181 uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ 182 uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ 183 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 184 uint32_t :1; /*!< bit: 7 Reserved */ 185 uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ 186 uint32_t :3; /*!< bit: 9..11 Reserved */ 187 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ 188 uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level for VDD */ 189 uint32_t :10; /*!< bit: 22..31 Reserved */ 190 } bit; /*!< Structure used for bit access */ 191 uint32_t reg; /*!< Type used for register access */ 192 } SUPC_BODVDD_Type; 193 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 194 195 #define SUPC_BODVDD_OFFSET 0x10 /**< \brief (SUPC_BODVDD offset) BODVDD Control */ 196 #define SUPC_BODVDD_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BODVDD reset_value) BODVDD Control */ 197 198 #define SUPC_BODVDD_ENABLE_Pos 1 /**< \brief (SUPC_BODVDD) Enable */ 199 #define SUPC_BODVDD_ENABLE (_U_(0x1) << SUPC_BODVDD_ENABLE_Pos) 200 #define SUPC_BODVDD_HYST_Pos 2 /**< \brief (SUPC_BODVDD) Hysteresis Enable */ 201 #define SUPC_BODVDD_HYST (_U_(0x1) << SUPC_BODVDD_HYST_Pos) 202 #define SUPC_BODVDD_ACTION_Pos 3 /**< \brief (SUPC_BODVDD) Action when Threshold Crossed */ 203 #define SUPC_BODVDD_ACTION_Msk (_U_(0x3) << SUPC_BODVDD_ACTION_Pos) 204 #define SUPC_BODVDD_ACTION(value) (SUPC_BODVDD_ACTION_Msk & ((value) << SUPC_BODVDD_ACTION_Pos)) 205 #define SUPC_BODVDD_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BODVDD) No action */ 206 #define SUPC_BODVDD_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BODVDD) The BOD33 generates a reset */ 207 #define SUPC_BODVDD_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BODVDD) The BOD33 generates an interrupt */ 208 #define SUPC_BODVDD_ACTION_NONE (SUPC_BODVDD_ACTION_NONE_Val << SUPC_BODVDD_ACTION_Pos) 209 #define SUPC_BODVDD_ACTION_RESET (SUPC_BODVDD_ACTION_RESET_Val << SUPC_BODVDD_ACTION_Pos) 210 #define SUPC_BODVDD_ACTION_INT (SUPC_BODVDD_ACTION_INT_Val << SUPC_BODVDD_ACTION_Pos) 211 #define SUPC_BODVDD_STDBYCFG_Pos 5 /**< \brief (SUPC_BODVDD) Configuration in Standby mode */ 212 #define SUPC_BODVDD_STDBYCFG (_U_(0x1) << SUPC_BODVDD_STDBYCFG_Pos) 213 #define SUPC_BODVDD_RUNSTDBY_Pos 6 /**< \brief (SUPC_BODVDD) Run during Standby */ 214 #define SUPC_BODVDD_RUNSTDBY (_U_(0x1) << SUPC_BODVDD_RUNSTDBY_Pos) 215 #define SUPC_BODVDD_ACTCFG_Pos 8 /**< \brief (SUPC_BODVDD) Configuration in Active mode */ 216 #define SUPC_BODVDD_ACTCFG (_U_(0x1) << SUPC_BODVDD_ACTCFG_Pos) 217 #define SUPC_BODVDD_PSEL_Pos 12 /**< \brief (SUPC_BODVDD) Prescaler Select */ 218 #define SUPC_BODVDD_PSEL_Msk (_U_(0xF) << SUPC_BODVDD_PSEL_Pos) 219 #define SUPC_BODVDD_PSEL(value) (SUPC_BODVDD_PSEL_Msk & ((value) << SUPC_BODVDD_PSEL_Pos)) 220 #define SUPC_BODVDD_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BODVDD) Divide clock by 2 */ 221 #define SUPC_BODVDD_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BODVDD) Divide clock by 4 */ 222 #define SUPC_BODVDD_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BODVDD) Divide clock by 8 */ 223 #define SUPC_BODVDD_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BODVDD) Divide clock by 16 */ 224 #define SUPC_BODVDD_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BODVDD) Divide clock by 32 */ 225 #define SUPC_BODVDD_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BODVDD) Divide clock by 64 */ 226 #define SUPC_BODVDD_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BODVDD) Divide clock by 128 */ 227 #define SUPC_BODVDD_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BODVDD) Divide clock by 256 */ 228 #define SUPC_BODVDD_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BODVDD) Divide clock by 512 */ 229 #define SUPC_BODVDD_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BODVDD) Divide clock by 1024 */ 230 #define SUPC_BODVDD_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BODVDD) Divide clock by 2048 */ 231 #define SUPC_BODVDD_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BODVDD) Divide clock by 4096 */ 232 #define SUPC_BODVDD_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BODVDD) Divide clock by 8192 */ 233 #define SUPC_BODVDD_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BODVDD) Divide clock by 16384 */ 234 #define SUPC_BODVDD_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BODVDD) Divide clock by 32768 */ 235 #define SUPC_BODVDD_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BODVDD) Divide clock by 65536 */ 236 #define SUPC_BODVDD_PSEL_DIV2 (SUPC_BODVDD_PSEL_DIV2_Val << SUPC_BODVDD_PSEL_Pos) 237 #define SUPC_BODVDD_PSEL_DIV4 (SUPC_BODVDD_PSEL_DIV4_Val << SUPC_BODVDD_PSEL_Pos) 238 #define SUPC_BODVDD_PSEL_DIV8 (SUPC_BODVDD_PSEL_DIV8_Val << SUPC_BODVDD_PSEL_Pos) 239 #define SUPC_BODVDD_PSEL_DIV16 (SUPC_BODVDD_PSEL_DIV16_Val << SUPC_BODVDD_PSEL_Pos) 240 #define SUPC_BODVDD_PSEL_DIV32 (SUPC_BODVDD_PSEL_DIV32_Val << SUPC_BODVDD_PSEL_Pos) 241 #define SUPC_BODVDD_PSEL_DIV64 (SUPC_BODVDD_PSEL_DIV64_Val << SUPC_BODVDD_PSEL_Pos) 242 #define SUPC_BODVDD_PSEL_DIV128 (SUPC_BODVDD_PSEL_DIV128_Val << SUPC_BODVDD_PSEL_Pos) 243 #define SUPC_BODVDD_PSEL_DIV256 (SUPC_BODVDD_PSEL_DIV256_Val << SUPC_BODVDD_PSEL_Pos) 244 #define SUPC_BODVDD_PSEL_DIV512 (SUPC_BODVDD_PSEL_DIV512_Val << SUPC_BODVDD_PSEL_Pos) 245 #define SUPC_BODVDD_PSEL_DIV1024 (SUPC_BODVDD_PSEL_DIV1024_Val << SUPC_BODVDD_PSEL_Pos) 246 #define SUPC_BODVDD_PSEL_DIV2048 (SUPC_BODVDD_PSEL_DIV2048_Val << SUPC_BODVDD_PSEL_Pos) 247 #define SUPC_BODVDD_PSEL_DIV4096 (SUPC_BODVDD_PSEL_DIV4096_Val << SUPC_BODVDD_PSEL_Pos) 248 #define SUPC_BODVDD_PSEL_DIV8192 (SUPC_BODVDD_PSEL_DIV8192_Val << SUPC_BODVDD_PSEL_Pos) 249 #define SUPC_BODVDD_PSEL_DIV16384 (SUPC_BODVDD_PSEL_DIV16384_Val << SUPC_BODVDD_PSEL_Pos) 250 #define SUPC_BODVDD_PSEL_DIV32768 (SUPC_BODVDD_PSEL_DIV32768_Val << SUPC_BODVDD_PSEL_Pos) 251 #define SUPC_BODVDD_PSEL_DIV65536 (SUPC_BODVDD_PSEL_DIV65536_Val << SUPC_BODVDD_PSEL_Pos) 252 #define SUPC_BODVDD_LEVEL_Pos 16 /**< \brief (SUPC_BODVDD) Threshold Level for VDD */ 253 #define SUPC_BODVDD_LEVEL_Msk (_U_(0x3F) << SUPC_BODVDD_LEVEL_Pos) 254 #define SUPC_BODVDD_LEVEL(value) (SUPC_BODVDD_LEVEL_Msk & ((value) << SUPC_BODVDD_LEVEL_Pos)) 255 #define SUPC_BODVDD_MASK _U_(0x003FF17E) /**< \brief (SUPC_BODVDD) MASK Register */ 256 257 /* -------- SUPC_BODCORE : (SUPC Offset: 0x14) (R/W 32) BODCORE Control -------- */ 258 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 259 typedef union { 260 struct { 261 uint32_t :1; /*!< bit: 0 Reserved */ 262 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 263 uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ 264 uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ 265 uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ 266 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 267 uint32_t :1; /*!< bit: 7 Reserved */ 268 uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ 269 uint32_t :3; /*!< bit: 9..11 Reserved */ 270 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ 271 uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */ 272 uint32_t :10; /*!< bit: 22..31 Reserved */ 273 } bit; /*!< Structure used for bit access */ 274 uint32_t reg; /*!< Type used for register access */ 275 } SUPC_BODCORE_Type; 276 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 277 278 #define SUPC_BODCORE_OFFSET 0x14 /**< \brief (SUPC_BODCORE offset) BODCORE Control */ 279 #define SUPC_BODCORE_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_BODCORE reset_value) BODCORE Control */ 280 281 #define SUPC_BODCORE_ENABLE_Pos 1 /**< \brief (SUPC_BODCORE) Enable */ 282 #define SUPC_BODCORE_ENABLE (_U_(0x1) << SUPC_BODCORE_ENABLE_Pos) 283 #define SUPC_BODCORE_HYST_Pos 2 /**< \brief (SUPC_BODCORE) Hysteresis Enable */ 284 #define SUPC_BODCORE_HYST (_U_(0x1) << SUPC_BODCORE_HYST_Pos) 285 #define SUPC_BODCORE_ACTION_Pos 3 /**< \brief (SUPC_BODCORE) Action when Threshold Crossed */ 286 #define SUPC_BODCORE_ACTION_Msk (_U_(0x3) << SUPC_BODCORE_ACTION_Pos) 287 #define SUPC_BODCORE_ACTION(value) (SUPC_BODCORE_ACTION_Msk & ((value) << SUPC_BODCORE_ACTION_Pos)) 288 #define SUPC_BODCORE_ACTION_NONE_Val _U_(0x0) /**< \brief (SUPC_BODCORE) No action */ 289 #define SUPC_BODCORE_ACTION_RESET_Val _U_(0x1) /**< \brief (SUPC_BODCORE) The BOD12 generates a reset */ 290 #define SUPC_BODCORE_ACTION_INT_Val _U_(0x2) /**< \brief (SUPC_BODCORE) The BOD12 generates an interrupt */ 291 #define SUPC_BODCORE_ACTION_NONE (SUPC_BODCORE_ACTION_NONE_Val << SUPC_BODCORE_ACTION_Pos) 292 #define SUPC_BODCORE_ACTION_RESET (SUPC_BODCORE_ACTION_RESET_Val << SUPC_BODCORE_ACTION_Pos) 293 #define SUPC_BODCORE_ACTION_INT (SUPC_BODCORE_ACTION_INT_Val << SUPC_BODCORE_ACTION_Pos) 294 #define SUPC_BODCORE_STDBYCFG_Pos 5 /**< \brief (SUPC_BODCORE) Configuration in Standby mode */ 295 #define SUPC_BODCORE_STDBYCFG (_U_(0x1) << SUPC_BODCORE_STDBYCFG_Pos) 296 #define SUPC_BODCORE_RUNSTDBY_Pos 6 /**< \brief (SUPC_BODCORE) Run during Standby */ 297 #define SUPC_BODCORE_RUNSTDBY (_U_(0x1) << SUPC_BODCORE_RUNSTDBY_Pos) 298 #define SUPC_BODCORE_ACTCFG_Pos 8 /**< \brief (SUPC_BODCORE) Configuration in Active mode */ 299 #define SUPC_BODCORE_ACTCFG (_U_(0x1) << SUPC_BODCORE_ACTCFG_Pos) 300 #define SUPC_BODCORE_PSEL_Pos 12 /**< \brief (SUPC_BODCORE) Prescaler Select */ 301 #define SUPC_BODCORE_PSEL_Msk (_U_(0xF) << SUPC_BODCORE_PSEL_Pos) 302 #define SUPC_BODCORE_PSEL(value) (SUPC_BODCORE_PSEL_Msk & ((value) << SUPC_BODCORE_PSEL_Pos)) 303 #define SUPC_BODCORE_PSEL_DIV2_Val _U_(0x0) /**< \brief (SUPC_BODCORE) Divide clock by 2 */ 304 #define SUPC_BODCORE_PSEL_DIV4_Val _U_(0x1) /**< \brief (SUPC_BODCORE) Divide clock by 4 */ 305 #define SUPC_BODCORE_PSEL_DIV8_Val _U_(0x2) /**< \brief (SUPC_BODCORE) Divide clock by 8 */ 306 #define SUPC_BODCORE_PSEL_DIV16_Val _U_(0x3) /**< \brief (SUPC_BODCORE) Divide clock by 16 */ 307 #define SUPC_BODCORE_PSEL_DIV32_Val _U_(0x4) /**< \brief (SUPC_BODCORE) Divide clock by 32 */ 308 #define SUPC_BODCORE_PSEL_DIV64_Val _U_(0x5) /**< \brief (SUPC_BODCORE) Divide clock by 64 */ 309 #define SUPC_BODCORE_PSEL_DIV128_Val _U_(0x6) /**< \brief (SUPC_BODCORE) Divide clock by 128 */ 310 #define SUPC_BODCORE_PSEL_DIV256_Val _U_(0x7) /**< \brief (SUPC_BODCORE) Divide clock by 256 */ 311 #define SUPC_BODCORE_PSEL_DIV512_Val _U_(0x8) /**< \brief (SUPC_BODCORE) Divide clock by 512 */ 312 #define SUPC_BODCORE_PSEL_DIV1024_Val _U_(0x9) /**< \brief (SUPC_BODCORE) Divide clock by 1024 */ 313 #define SUPC_BODCORE_PSEL_DIV2048_Val _U_(0xA) /**< \brief (SUPC_BODCORE) Divide clock by 2048 */ 314 #define SUPC_BODCORE_PSEL_DIV4096_Val _U_(0xB) /**< \brief (SUPC_BODCORE) Divide clock by 4096 */ 315 #define SUPC_BODCORE_PSEL_DIV8192_Val _U_(0xC) /**< \brief (SUPC_BODCORE) Divide clock by 8192 */ 316 #define SUPC_BODCORE_PSEL_DIV16384_Val _U_(0xD) /**< \brief (SUPC_BODCORE) Divide clock by 16384 */ 317 #define SUPC_BODCORE_PSEL_DIV32768_Val _U_(0xE) /**< \brief (SUPC_BODCORE) Divide clock by 32768 */ 318 #define SUPC_BODCORE_PSEL_DIV65536_Val _U_(0xF) /**< \brief (SUPC_BODCORE) Divide clock by 65536 */ 319 #define SUPC_BODCORE_PSEL_DIV2 (SUPC_BODCORE_PSEL_DIV2_Val << SUPC_BODCORE_PSEL_Pos) 320 #define SUPC_BODCORE_PSEL_DIV4 (SUPC_BODCORE_PSEL_DIV4_Val << SUPC_BODCORE_PSEL_Pos) 321 #define SUPC_BODCORE_PSEL_DIV8 (SUPC_BODCORE_PSEL_DIV8_Val << SUPC_BODCORE_PSEL_Pos) 322 #define SUPC_BODCORE_PSEL_DIV16 (SUPC_BODCORE_PSEL_DIV16_Val << SUPC_BODCORE_PSEL_Pos) 323 #define SUPC_BODCORE_PSEL_DIV32 (SUPC_BODCORE_PSEL_DIV32_Val << SUPC_BODCORE_PSEL_Pos) 324 #define SUPC_BODCORE_PSEL_DIV64 (SUPC_BODCORE_PSEL_DIV64_Val << SUPC_BODCORE_PSEL_Pos) 325 #define SUPC_BODCORE_PSEL_DIV128 (SUPC_BODCORE_PSEL_DIV128_Val << SUPC_BODCORE_PSEL_Pos) 326 #define SUPC_BODCORE_PSEL_DIV256 (SUPC_BODCORE_PSEL_DIV256_Val << SUPC_BODCORE_PSEL_Pos) 327 #define SUPC_BODCORE_PSEL_DIV512 (SUPC_BODCORE_PSEL_DIV512_Val << SUPC_BODCORE_PSEL_Pos) 328 #define SUPC_BODCORE_PSEL_DIV1024 (SUPC_BODCORE_PSEL_DIV1024_Val << SUPC_BODCORE_PSEL_Pos) 329 #define SUPC_BODCORE_PSEL_DIV2048 (SUPC_BODCORE_PSEL_DIV2048_Val << SUPC_BODCORE_PSEL_Pos) 330 #define SUPC_BODCORE_PSEL_DIV4096 (SUPC_BODCORE_PSEL_DIV4096_Val << SUPC_BODCORE_PSEL_Pos) 331 #define SUPC_BODCORE_PSEL_DIV8192 (SUPC_BODCORE_PSEL_DIV8192_Val << SUPC_BODCORE_PSEL_Pos) 332 #define SUPC_BODCORE_PSEL_DIV16384 (SUPC_BODCORE_PSEL_DIV16384_Val << SUPC_BODCORE_PSEL_Pos) 333 #define SUPC_BODCORE_PSEL_DIV32768 (SUPC_BODCORE_PSEL_DIV32768_Val << SUPC_BODCORE_PSEL_Pos) 334 #define SUPC_BODCORE_PSEL_DIV65536 (SUPC_BODCORE_PSEL_DIV65536_Val << SUPC_BODCORE_PSEL_Pos) 335 #define SUPC_BODCORE_LEVEL_Pos 16 /**< \brief (SUPC_BODCORE) Threshold Level */ 336 #define SUPC_BODCORE_LEVEL_Msk (_U_(0x3F) << SUPC_BODCORE_LEVEL_Pos) 337 #define SUPC_BODCORE_LEVEL(value) (SUPC_BODCORE_LEVEL_Msk & ((value) << SUPC_BODCORE_LEVEL_Pos)) 338 #define SUPC_BODCORE_MASK _U_(0x003FF17E) /**< \brief (SUPC_BODCORE) MASK Register */ 339 340 /* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ 341 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 342 typedef union { 343 struct { 344 uint32_t :1; /*!< bit: 0 Reserved */ 345 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 346 uint32_t :4; /*!< bit: 2.. 5 Reserved */ 347 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 348 uint32_t :25; /*!< bit: 7..31 Reserved */ 349 } bit; /*!< Structure used for bit access */ 350 uint32_t reg; /*!< Type used for register access */ 351 } SUPC_VREG_Type; 352 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 353 354 #define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */ 355 #define SUPC_VREG_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREG reset_value) VREG Control */ 356 357 #define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */ 358 #define SUPC_VREG_ENABLE (_U_(0x1) << SUPC_VREG_ENABLE_Pos) 359 #define SUPC_VREG_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREG) Run during Standby */ 360 #define SUPC_VREG_RUNSTDBY (_U_(0x1) << SUPC_VREG_RUNSTDBY_Pos) 361 #define SUPC_VREG_MASK _U_(0x00000042) /**< \brief (SUPC_VREG) MASK Register */ 362 363 /* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */ 364 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 365 typedef union { 366 struct { 367 uint32_t :1; /*!< bit: 0 Reserved */ 368 uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */ 369 uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */ 370 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 371 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 372 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */ 373 uint32_t :8; /*!< bit: 8..15 Reserved */ 374 uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */ 375 uint32_t :12; /*!< bit: 20..31 Reserved */ 376 } bit; /*!< Structure used for bit access */ 377 uint32_t reg; /*!< Type used for register access */ 378 } SUPC_VREF_Type; 379 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 380 381 #define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */ 382 #define SUPC_VREF_RESETVALUE _U_(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */ 383 384 #define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */ 385 #define SUPC_VREF_TSEN (_U_(0x1) << SUPC_VREF_TSEN_Pos) 386 #define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */ 387 #define SUPC_VREF_VREFOE (_U_(0x1) << SUPC_VREF_VREFOE_Pos) 388 #define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */ 389 #define SUPC_VREF_RUNSTDBY (_U_(0x1) << SUPC_VREF_RUNSTDBY_Pos) 390 #define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */ 391 #define SUPC_VREF_ONDEMAND (_U_(0x1) << SUPC_VREF_ONDEMAND_Pos) 392 #define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */ 393 #define SUPC_VREF_SEL_Msk (_U_(0xF) << SUPC_VREF_SEL_Pos) 394 #define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos)) 395 #define SUPC_VREF_SEL_1V024_Val _U_(0x0) /**< \brief (SUPC_VREF) 1.024V voltage reference typical value */ 396 #define SUPC_VREF_SEL_2V048_Val _U_(0x2) /**< \brief (SUPC_VREF) 2.048V voltage reference typical value */ 397 #define SUPC_VREF_SEL_4V096_Val _U_(0x3) /**< \brief (SUPC_VREF) 4.096V voltage reference typical value */ 398 #define SUPC_VREF_SEL_1V024 (SUPC_VREF_SEL_1V024_Val << SUPC_VREF_SEL_Pos) 399 #define SUPC_VREF_SEL_2V048 (SUPC_VREF_SEL_2V048_Val << SUPC_VREF_SEL_Pos) 400 #define SUPC_VREF_SEL_4V096 (SUPC_VREF_SEL_4V096_Val << SUPC_VREF_SEL_Pos) 401 #define SUPC_VREF_MASK _U_(0x000F00C6) /**< \brief (SUPC_VREF) MASK Register */ 402 403 /** \brief SUPC hardware registers */ 404 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 405 typedef struct { 406 __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 407 __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 408 __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 409 __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 410 __IO SUPC_BODVDD_Type BODVDD; /**< \brief Offset: 0x10 (R/W 32) BODVDD Control */ 411 __IO SUPC_BODCORE_Type BODCORE; /**< \brief Offset: 0x14 (R/W 32) BODCORE Control */ 412 __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */ 413 __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */ 414 } Supc; 415 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 416 417 /*@}*/ 418 419 #endif /* _SAMC21_SUPC_COMPONENT_ */ 420
