1 /** 2 * \file 3 * 4 * \brief Component description for SERCOM 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAMC21_SERCOM_COMPONENT_ 31 #define _SAMC21_SERCOM_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR SERCOM */ 35 /* ========================================================================== */ 36 /** \addtogroup SAMC21_SERCOM Serial Communication Interface */ 37 /*@{*/ 38 39 #define SERCOM_U2201 40 #define REV_SERCOM 0x311 41 42 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 49 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 50 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ 51 uint32_t :8; /*!< bit: 8..15 Reserved */ 52 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 53 uint32_t :3; /*!< bit: 17..19 Reserved */ 54 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 55 uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ 56 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ 57 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ 58 uint32_t :1; /*!< bit: 26 Reserved */ 59 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ 60 uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ 61 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ 62 uint32_t :1; /*!< bit: 31 Reserved */ 63 } bit; /*!< Structure used for bit access */ 64 uint32_t reg; /*!< Type used for register access */ 65 } SERCOM_I2CM_CTRLA_Type; 66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 67 68 #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ 69 #define SERCOM_I2CM_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ 70 71 #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ 72 #define SERCOM_I2CM_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos) 73 #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ 74 #define SERCOM_I2CM_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos) 75 #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ 76 #define SERCOM_I2CM_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos) 77 #define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)) 78 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ 79 #define SERCOM_I2CM_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) 80 #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ 81 #define SERCOM_I2CM_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos) 82 #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ 83 #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) 84 #define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)) 85 #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */ 86 #define SERCOM_I2CM_CTRLA_MEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) 87 #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */ 88 #define SERCOM_I2CM_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) 89 #define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */ 90 #define SERCOM_I2CM_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos) 91 #define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)) 92 #define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */ 93 #define SERCOM_I2CM_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos) 94 #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */ 95 #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U_(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos) 96 #define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)) 97 #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */ 98 #define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) 99 #define SERCOM_I2CM_CTRLA_MASK _U_(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ 100 101 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ 102 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 103 typedef union { 104 struct { 105 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 106 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 107 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 108 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 109 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ 110 uint32_t :8; /*!< bit: 8..15 Reserved */ 111 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 112 uint32_t :3; /*!< bit: 17..19 Reserved */ 113 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 114 uint32_t :1; /*!< bit: 22 Reserved */ 115 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ 116 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ 117 uint32_t :1; /*!< bit: 26 Reserved */ 118 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ 119 uint32_t :2; /*!< bit: 28..29 Reserved */ 120 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ 121 uint32_t :1; /*!< bit: 31 Reserved */ 122 } bit; /*!< Structure used for bit access */ 123 uint32_t reg; /*!< Type used for register access */ 124 } SERCOM_I2CS_CTRLA_Type; 125 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 126 127 #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ 128 #define SERCOM_I2CS_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ 129 130 #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ 131 #define SERCOM_I2CS_CTRLA_SWRST (_U_(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos) 132 #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ 133 #define SERCOM_I2CS_CTRLA_ENABLE (_U_(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos) 134 #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ 135 #define SERCOM_I2CS_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos) 136 #define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)) 137 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */ 138 #define SERCOM_I2CS_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) 139 #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ 140 #define SERCOM_I2CS_CTRLA_PINOUT (_U_(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos) 141 #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ 142 #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 143 #define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)) 144 #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */ 145 #define SERCOM_I2CS_CTRLA_SEXTTOEN (_U_(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) 146 #define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */ 147 #define SERCOM_I2CS_CTRLA_SPEED_Msk (_U_(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos) 148 #define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)) 149 #define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */ 150 #define SERCOM_I2CS_CTRLA_SCLSM (_U_(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos) 151 #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */ 152 #define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U_(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) 153 #define SERCOM_I2CS_CTRLA_MASK _U_(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ 154 155 /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ 156 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 157 typedef union { 158 struct { 159 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 160 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 161 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 162 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 163 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ 164 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 165 uint32_t :7; /*!< bit: 9..15 Reserved */ 166 uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ 167 uint32_t :2; /*!< bit: 18..19 Reserved */ 168 uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ 169 uint32_t :2; /*!< bit: 22..23 Reserved */ 170 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 171 uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ 172 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 173 uint32_t DORD:1; /*!< bit: 30 Data Order */ 174 uint32_t :1; /*!< bit: 31 Reserved */ 175 } bit; /*!< Structure used for bit access */ 176 uint32_t reg; /*!< Type used for register access */ 177 } SERCOM_SPI_CTRLA_Type; 178 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 179 180 #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ 181 #define SERCOM_SPI_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ 182 183 #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ 184 #define SERCOM_SPI_CTRLA_SWRST (_U_(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos) 185 #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ 186 #define SERCOM_SPI_CTRLA_ENABLE (_U_(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos) 187 #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ 188 #define SERCOM_SPI_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_SPI_CTRLA_MODE_Pos) 189 #define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)) 190 #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */ 191 #define SERCOM_SPI_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) 192 #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ 193 #define SERCOM_SPI_CTRLA_IBON (_U_(0x1) << SERCOM_SPI_CTRLA_IBON_Pos) 194 #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ 195 #define SERCOM_SPI_CTRLA_DOPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos) 196 #define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)) 197 #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ 198 #define SERCOM_SPI_CTRLA_DIPO_Msk (_U_(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos) 199 #define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)) 200 #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ 201 #define SERCOM_SPI_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_SPI_CTRLA_FORM_Pos) 202 #define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)) 203 #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ 204 #define SERCOM_SPI_CTRLA_CPHA (_U_(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos) 205 #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ 206 #define SERCOM_SPI_CTRLA_CPOL (_U_(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos) 207 #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ 208 #define SERCOM_SPI_CTRLA_DORD (_U_(0x1) << SERCOM_SPI_CTRLA_DORD_Pos) 209 #define SERCOM_SPI_CTRLA_MASK _U_(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ 210 211 /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ 212 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 213 typedef union { 214 struct { 215 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 216 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 217 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 218 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 219 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ 220 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 221 uint32_t :4; /*!< bit: 9..12 Reserved */ 222 uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ 223 uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ 224 uint32_t :2; /*!< bit: 18..19 Reserved */ 225 uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ 226 uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ 227 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 228 uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ 229 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 230 uint32_t DORD:1; /*!< bit: 30 Data Order */ 231 uint32_t :1; /*!< bit: 31 Reserved */ 232 } bit; /*!< Structure used for bit access */ 233 uint32_t reg; /*!< Type used for register access */ 234 } SERCOM_USART_CTRLA_Type; 235 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 236 237 #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ 238 #define SERCOM_USART_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ 239 240 #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ 241 #define SERCOM_USART_CTRLA_SWRST (_U_(0x1) << SERCOM_USART_CTRLA_SWRST_Pos) 242 #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ 243 #define SERCOM_USART_CTRLA_ENABLE (_U_(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos) 244 #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ 245 #define SERCOM_USART_CTRLA_MODE_Msk (_U_(0x7) << SERCOM_USART_CTRLA_MODE_Pos) 246 #define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)) 247 #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */ 248 #define SERCOM_USART_CTRLA_RUNSTDBY (_U_(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos) 249 #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ 250 #define SERCOM_USART_CTRLA_IBON (_U_(0x1) << SERCOM_USART_CTRLA_IBON_Pos) 251 #define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */ 252 #define SERCOM_USART_CTRLA_SAMPR_Msk (_U_(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos) 253 #define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)) 254 #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ 255 #define SERCOM_USART_CTRLA_TXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_TXPO_Pos) 256 #define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)) 257 #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ 258 #define SERCOM_USART_CTRLA_RXPO_Msk (_U_(0x3) << SERCOM_USART_CTRLA_RXPO_Pos) 259 #define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)) 260 #define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */ 261 #define SERCOM_USART_CTRLA_SAMPA_Msk (_U_(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos) 262 #define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)) 263 #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ 264 #define SERCOM_USART_CTRLA_FORM_Msk (_U_(0xF) << SERCOM_USART_CTRLA_FORM_Pos) 265 #define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)) 266 #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ 267 #define SERCOM_USART_CTRLA_CMODE (_U_(0x1) << SERCOM_USART_CTRLA_CMODE_Pos) 268 #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ 269 #define SERCOM_USART_CTRLA_CPOL (_U_(0x1) << SERCOM_USART_CTRLA_CPOL_Pos) 270 #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ 271 #define SERCOM_USART_CTRLA_DORD (_U_(0x1) << SERCOM_USART_CTRLA_DORD_Pos) 272 #define SERCOM_USART_CTRLA_MASK _U_(0x7FF3E19F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */ 273 274 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ 275 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 276 typedef union { 277 struct { 278 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 279 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 280 uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ 281 uint32_t :6; /*!< bit: 10..15 Reserved */ 282 uint32_t CMD:2; /*!< bit: 16..17 Command */ 283 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 284 uint32_t :13; /*!< bit: 19..31 Reserved */ 285 } bit; /*!< Structure used for bit access */ 286 uint32_t reg; /*!< Type used for register access */ 287 } SERCOM_I2CM_CTRLB_Type; 288 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 289 290 #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ 291 #define SERCOM_I2CM_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ 292 293 #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ 294 #define SERCOM_I2CM_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos) 295 #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ 296 #define SERCOM_I2CM_CTRLB_QCEN (_U_(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos) 297 #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ 298 #define SERCOM_I2CM_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos) 299 #define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)) 300 #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ 301 #define SERCOM_I2CM_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos) 302 #define SERCOM_I2CM_CTRLB_MASK _U_(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ 303 304 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ 305 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 306 typedef union { 307 struct { 308 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 309 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 310 uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ 311 uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ 312 uint32_t :3; /*!< bit: 11..13 Reserved */ 313 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 314 uint32_t CMD:2; /*!< bit: 16..17 Command */ 315 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 316 uint32_t :13; /*!< bit: 19..31 Reserved */ 317 } bit; /*!< Structure used for bit access */ 318 uint32_t reg; /*!< Type used for register access */ 319 } SERCOM_I2CS_CTRLB_Type; 320 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 321 322 #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ 323 #define SERCOM_I2CS_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ 324 325 #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ 326 #define SERCOM_I2CS_CTRLB_SMEN (_U_(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos) 327 #define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */ 328 #define SERCOM_I2CS_CTRLB_GCMD (_U_(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos) 329 #define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */ 330 #define SERCOM_I2CS_CTRLB_AACKEN (_U_(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos) 331 #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ 332 #define SERCOM_I2CS_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos) 333 #define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)) 334 #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ 335 #define SERCOM_I2CS_CTRLB_CMD_Msk (_U_(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos) 336 #define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)) 337 #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ 338 #define SERCOM_I2CS_CTRLB_ACKACT (_U_(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos) 339 #define SERCOM_I2CS_CTRLB_MASK _U_(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ 340 341 /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ 342 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 343 typedef union { 344 struct { 345 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 346 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 347 uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ 348 uint32_t :2; /*!< bit: 7.. 8 Reserved */ 349 uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ 350 uint32_t :3; /*!< bit: 10..12 Reserved */ 351 uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ 352 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 353 uint32_t :1; /*!< bit: 16 Reserved */ 354 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 355 uint32_t :14; /*!< bit: 18..31 Reserved */ 356 } bit; /*!< Structure used for bit access */ 357 uint32_t reg; /*!< Type used for register access */ 358 } SERCOM_SPI_CTRLB_Type; 359 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 360 361 #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ 362 #define SERCOM_SPI_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ 363 364 #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ 365 #define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos) 366 #define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)) 367 #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */ 368 #define SERCOM_SPI_CTRLB_PLOADEN (_U_(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos) 369 #define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */ 370 #define SERCOM_SPI_CTRLB_SSDE (_U_(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos) 371 #define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */ 372 #define SERCOM_SPI_CTRLB_MSSEN (_U_(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos) 373 #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ 374 #define SERCOM_SPI_CTRLB_AMODE_Msk (_U_(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos) 375 #define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)) 376 #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ 377 #define SERCOM_SPI_CTRLB_RXEN (_U_(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos) 378 #define SERCOM_SPI_CTRLB_MASK _U_(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ 379 380 /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ 381 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 382 typedef union { 383 struct { 384 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 385 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 386 uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ 387 uint32_t :1; /*!< bit: 7 Reserved */ 388 uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ 389 uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ 390 uint32_t ENC:1; /*!< bit: 10 Encoding Format */ 391 uint32_t :2; /*!< bit: 11..12 Reserved */ 392 uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ 393 uint32_t :2; /*!< bit: 14..15 Reserved */ 394 uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ 395 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 396 uint32_t :6; /*!< bit: 18..23 Reserved */ 397 uint32_t LINCMD:2; /*!< bit: 24..25 LIN Command */ 398 uint32_t :6; /*!< bit: 26..31 Reserved */ 399 } bit; /*!< Structure used for bit access */ 400 uint32_t reg; /*!< Type used for register access */ 401 } SERCOM_USART_CTRLB_Type; 402 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 403 404 #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ 405 #define SERCOM_USART_CTRLB_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ 406 407 #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ 408 #define SERCOM_USART_CTRLB_CHSIZE_Msk (_U_(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos) 409 #define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)) 410 #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ 411 #define SERCOM_USART_CTRLB_SBMODE (_U_(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos) 412 #define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */ 413 #define SERCOM_USART_CTRLB_COLDEN (_U_(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos) 414 #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ 415 #define SERCOM_USART_CTRLB_SFDE (_U_(0x1) << SERCOM_USART_CTRLB_SFDE_Pos) 416 #define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */ 417 #define SERCOM_USART_CTRLB_ENC (_U_(0x1) << SERCOM_USART_CTRLB_ENC_Pos) 418 #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ 419 #define SERCOM_USART_CTRLB_PMODE (_U_(0x1) << SERCOM_USART_CTRLB_PMODE_Pos) 420 #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ 421 #define SERCOM_USART_CTRLB_TXEN (_U_(0x1) << SERCOM_USART_CTRLB_TXEN_Pos) 422 #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ 423 #define SERCOM_USART_CTRLB_RXEN (_U_(0x1) << SERCOM_USART_CTRLB_RXEN_Pos) 424 #define SERCOM_USART_CTRLB_LINCMD_Pos 24 /**< \brief (SERCOM_USART_CTRLB) LIN Command */ 425 #define SERCOM_USART_CTRLB_LINCMD_Msk (_U_(0x3) << SERCOM_USART_CTRLB_LINCMD_Pos) 426 #define SERCOM_USART_CTRLB_LINCMD(value) (SERCOM_USART_CTRLB_LINCMD_Msk & ((value) << SERCOM_USART_CTRLB_LINCMD_Pos)) 427 #define SERCOM_USART_CTRLB_MASK _U_(0x03032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */ 428 429 /* -------- SERCOM_USART_CTRLC : (SERCOM Offset: 0x08) (R/W 32) USART USART Control C -------- */ 430 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 431 typedef union { 432 struct { 433 uint32_t GTIME:3; /*!< bit: 0.. 2 RS485 Guard Time */ 434 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 435 uint32_t BRKLEN:2; /*!< bit: 8.. 9 LIN Master Break Length */ 436 uint32_t HDRDLY:2; /*!< bit: 10..11 LIN Master Header Delay */ 437 uint32_t :20; /*!< bit: 12..31 Reserved */ 438 } bit; /*!< Structure used for bit access */ 439 uint32_t reg; /*!< Type used for register access */ 440 } SERCOM_USART_CTRLC_Type; 441 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 442 443 #define SERCOM_USART_CTRLC_OFFSET 0x08 /**< \brief (SERCOM_USART_CTRLC offset) USART Control C */ 444 #define SERCOM_USART_CTRLC_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_CTRLC reset_value) USART Control C */ 445 446 #define SERCOM_USART_CTRLC_GTIME_Pos 0 /**< \brief (SERCOM_USART_CTRLC) RS485 Guard Time */ 447 #define SERCOM_USART_CTRLC_GTIME_Msk (_U_(0x7) << SERCOM_USART_CTRLC_GTIME_Pos) 448 #define SERCOM_USART_CTRLC_GTIME(value) (SERCOM_USART_CTRLC_GTIME_Msk & ((value) << SERCOM_USART_CTRLC_GTIME_Pos)) 449 #define SERCOM_USART_CTRLC_BRKLEN_Pos 8 /**< \brief (SERCOM_USART_CTRLC) LIN Master Break Length */ 450 #define SERCOM_USART_CTRLC_BRKLEN_Msk (_U_(0x3) << SERCOM_USART_CTRLC_BRKLEN_Pos) 451 #define SERCOM_USART_CTRLC_BRKLEN(value) (SERCOM_USART_CTRLC_BRKLEN_Msk & ((value) << SERCOM_USART_CTRLC_BRKLEN_Pos)) 452 #define SERCOM_USART_CTRLC_HDRDLY_Pos 10 /**< \brief (SERCOM_USART_CTRLC) LIN Master Header Delay */ 453 #define SERCOM_USART_CTRLC_HDRDLY_Msk (_U_(0x3) << SERCOM_USART_CTRLC_HDRDLY_Pos) 454 #define SERCOM_USART_CTRLC_HDRDLY(value) (SERCOM_USART_CTRLC_HDRDLY_Msk & ((value) << SERCOM_USART_CTRLC_HDRDLY_Pos)) 455 #define SERCOM_USART_CTRLC_MASK _U_(0x00000F07) /**< \brief (SERCOM_USART_CTRLC) MASK Register */ 456 457 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ 458 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 459 typedef union { 460 struct { 461 uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ 462 uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ 463 uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ 464 uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ 465 } bit; /*!< Structure used for bit access */ 466 uint32_t reg; /*!< Type used for register access */ 467 } SERCOM_I2CM_BAUD_Type; 468 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 469 470 #define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ 471 #define SERCOM_I2CM_BAUD_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ 472 473 #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */ 474 #define SERCOM_I2CM_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos) 475 #define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)) 476 #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */ 477 #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos) 478 #define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)) 479 #define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */ 480 #define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos) 481 #define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)) 482 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */ 483 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U_(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos) 484 #define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)) 485 #define SERCOM_I2CM_BAUD_MASK _U_(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ 486 487 /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ 488 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 489 typedef union { 490 struct { 491 uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ 492 } bit; /*!< Structure used for bit access */ 493 uint8_t reg; /*!< Type used for register access */ 494 } SERCOM_SPI_BAUD_Type; 495 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 496 497 #define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ 498 #define SERCOM_SPI_BAUD_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ 499 500 #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */ 501 #define SERCOM_SPI_BAUD_BAUD_Msk (_U_(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos) 502 #define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)) 503 #define SERCOM_SPI_BAUD_MASK _U_(0xFF) /**< \brief (SERCOM_SPI_BAUD) MASK Register */ 504 505 /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ 506 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 507 typedef union { 508 struct { 509 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ 510 } bit; /*!< Structure used for bit access */ 511 struct { // FRAC mode 512 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ 513 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ 514 } FRAC; /*!< Structure used for FRAC */ 515 struct { // FRACFP mode 516 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ 517 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ 518 } FRACFP; /*!< Structure used for FRACFP */ 519 struct { // USARTFP mode 520 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ 521 } USARTFP; /*!< Structure used for USARTFP */ 522 uint16_t reg; /*!< Type used for register access */ 523 } SERCOM_USART_BAUD_Type; 524 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 525 526 #define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */ 527 #define SERCOM_USART_BAUD_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */ 528 529 #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */ 530 #define SERCOM_USART_BAUD_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos) 531 #define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)) 532 #define SERCOM_USART_BAUD_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD) MASK Register */ 533 534 // FRAC mode 535 #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */ 536 #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos) 537 #define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)) 538 #define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */ 539 #define SERCOM_USART_BAUD_FRAC_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos) 540 #define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)) 541 #define SERCOM_USART_BAUD_FRAC_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */ 542 543 // FRACFP mode 544 #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */ 545 #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U_(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) 546 #define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)) 547 #define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */ 548 #define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U_(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos) 549 #define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)) 550 #define SERCOM_USART_BAUD_FRACFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */ 551 552 // USARTFP mode 553 #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */ 554 #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U_(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) 555 #define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)) 556 #define SERCOM_USART_BAUD_USARTFP_MASK _U_(0xFFFF) /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */ 557 558 /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ 559 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 560 typedef union { 561 struct { 562 uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ 563 } bit; /*!< Structure used for bit access */ 564 uint8_t reg; /*!< Type used for register access */ 565 } SERCOM_USART_RXPL_Type; 566 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 567 568 #define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */ 569 #define SERCOM_USART_RXPL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */ 570 571 #define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */ 572 #define SERCOM_USART_RXPL_RXPL_Msk (_U_(0xFF) << SERCOM_USART_RXPL_RXPL_Pos) 573 #define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)) 574 #define SERCOM_USART_RXPL_MASK _U_(0xFF) /**< \brief (SERCOM_USART_RXPL) MASK Register */ 575 576 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ 577 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 578 typedef union { 579 struct { 580 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ 581 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ 582 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 583 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 584 } bit; /*!< Structure used for bit access */ 585 uint8_t reg; /*!< Type used for register access */ 586 } SERCOM_I2CM_INTENCLR_Type; 587 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 588 589 #define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ 590 #define SERCOM_I2CM_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ 591 592 #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */ 593 #define SERCOM_I2CM_INTENCLR_MB (_U_(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos) 594 #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */ 595 #define SERCOM_I2CM_INTENCLR_SB (_U_(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos) 596 #define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */ 597 #define SERCOM_I2CM_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos) 598 #define SERCOM_I2CM_INTENCLR_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ 599 600 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ 601 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 602 typedef union { 603 struct { 604 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ 605 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ 606 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ 607 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 608 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 609 } bit; /*!< Structure used for bit access */ 610 uint8_t reg; /*!< Type used for register access */ 611 } SERCOM_I2CS_INTENCLR_Type; 612 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 613 614 #define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ 615 #define SERCOM_I2CS_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ 616 617 #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */ 618 #define SERCOM_I2CS_INTENCLR_PREC (_U_(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos) 619 #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */ 620 #define SERCOM_I2CS_INTENCLR_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos) 621 #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */ 622 #define SERCOM_I2CS_INTENCLR_DRDY (_U_(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos) 623 #define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */ 624 #define SERCOM_I2CS_INTENCLR_ERROR (_U_(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos) 625 #define SERCOM_I2CS_INTENCLR_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ 626 627 /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ 628 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 629 typedef union { 630 struct { 631 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ 632 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ 633 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ 634 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ 635 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 636 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 637 } bit; /*!< Structure used for bit access */ 638 uint8_t reg; /*!< Type used for register access */ 639 } SERCOM_SPI_INTENCLR_Type; 640 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 641 642 #define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ 643 #define SERCOM_SPI_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ 644 645 #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */ 646 #define SERCOM_SPI_INTENCLR_DRE (_U_(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos) 647 #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */ 648 #define SERCOM_SPI_INTENCLR_TXC (_U_(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos) 649 #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */ 650 #define SERCOM_SPI_INTENCLR_RXC (_U_(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos) 651 #define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */ 652 #define SERCOM_SPI_INTENCLR_SSL (_U_(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos) 653 #define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */ 654 #define SERCOM_SPI_INTENCLR_ERROR (_U_(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos) 655 #define SERCOM_SPI_INTENCLR_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ 656 657 /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ 658 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 659 typedef union { 660 struct { 661 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ 662 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ 663 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ 664 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ 665 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ 666 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ 667 uint8_t :1; /*!< bit: 6 Reserved */ 668 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 669 } bit; /*!< Structure used for bit access */ 670 uint8_t reg; /*!< Type used for register access */ 671 } SERCOM_USART_INTENCLR_Type; 672 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 673 674 #define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ 675 #define SERCOM_USART_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ 676 677 #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */ 678 #define SERCOM_USART_INTENCLR_DRE (_U_(0x1) << SERCOM_USART_INTENCLR_DRE_Pos) 679 #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */ 680 #define SERCOM_USART_INTENCLR_TXC (_U_(0x1) << SERCOM_USART_INTENCLR_TXC_Pos) 681 #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */ 682 #define SERCOM_USART_INTENCLR_RXC (_U_(0x1) << SERCOM_USART_INTENCLR_RXC_Pos) 683 #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ 684 #define SERCOM_USART_INTENCLR_RXS (_U_(0x1) << SERCOM_USART_INTENCLR_RXS_Pos) 685 #define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */ 686 #define SERCOM_USART_INTENCLR_CTSIC (_U_(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos) 687 #define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */ 688 #define SERCOM_USART_INTENCLR_RXBRK (_U_(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos) 689 #define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */ 690 #define SERCOM_USART_INTENCLR_ERROR (_U_(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos) 691 #define SERCOM_USART_INTENCLR_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ 692 693 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ 694 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 695 typedef union { 696 struct { 697 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ 698 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ 699 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 700 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 701 } bit; /*!< Structure used for bit access */ 702 uint8_t reg; /*!< Type used for register access */ 703 } SERCOM_I2CM_INTENSET_Type; 704 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 705 706 #define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ 707 #define SERCOM_I2CM_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ 708 709 #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */ 710 #define SERCOM_I2CM_INTENSET_MB (_U_(0x1) << SERCOM_I2CM_INTENSET_MB_Pos) 711 #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */ 712 #define SERCOM_I2CM_INTENSET_SB (_U_(0x1) << SERCOM_I2CM_INTENSET_SB_Pos) 713 #define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */ 714 #define SERCOM_I2CM_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos) 715 #define SERCOM_I2CM_INTENSET_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ 716 717 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ 718 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 719 typedef union { 720 struct { 721 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ 722 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ 723 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ 724 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 725 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 726 } bit; /*!< Structure used for bit access */ 727 uint8_t reg; /*!< Type used for register access */ 728 } SERCOM_I2CS_INTENSET_Type; 729 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 730 731 #define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ 732 #define SERCOM_I2CS_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ 733 734 #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ 735 #define SERCOM_I2CS_INTENSET_PREC (_U_(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos) 736 #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ 737 #define SERCOM_I2CS_INTENSET_AMATCH (_U_(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos) 738 #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */ 739 #define SERCOM_I2CS_INTENSET_DRDY (_U_(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos) 740 #define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */ 741 #define SERCOM_I2CS_INTENSET_ERROR (_U_(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos) 742 #define SERCOM_I2CS_INTENSET_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ 743 744 /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ 745 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 746 typedef union { 747 struct { 748 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 749 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 750 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 751 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ 752 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 753 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 754 } bit; /*!< Structure used for bit access */ 755 uint8_t reg; /*!< Type used for register access */ 756 } SERCOM_SPI_INTENSET_Type; 757 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 758 759 #define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ 760 #define SERCOM_SPI_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ 761 762 #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ 763 #define SERCOM_SPI_INTENSET_DRE (_U_(0x1) << SERCOM_SPI_INTENSET_DRE_Pos) 764 #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ 765 #define SERCOM_SPI_INTENSET_TXC (_U_(0x1) << SERCOM_SPI_INTENSET_TXC_Pos) 766 #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ 767 #define SERCOM_SPI_INTENSET_RXC (_U_(0x1) << SERCOM_SPI_INTENSET_RXC_Pos) 768 #define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */ 769 #define SERCOM_SPI_INTENSET_SSL (_U_(0x1) << SERCOM_SPI_INTENSET_SSL_Pos) 770 #define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */ 771 #define SERCOM_SPI_INTENSET_ERROR (_U_(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos) 772 #define SERCOM_SPI_INTENSET_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ 773 774 /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ 775 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 776 typedef union { 777 struct { 778 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 779 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 780 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 781 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ 782 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ 783 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ 784 uint8_t :1; /*!< bit: 6 Reserved */ 785 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 786 } bit; /*!< Structure used for bit access */ 787 uint8_t reg; /*!< Type used for register access */ 788 } SERCOM_USART_INTENSET_Type; 789 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 790 791 #define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ 792 #define SERCOM_USART_INTENSET_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ 793 794 #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ 795 #define SERCOM_USART_INTENSET_DRE (_U_(0x1) << SERCOM_USART_INTENSET_DRE_Pos) 796 #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ 797 #define SERCOM_USART_INTENSET_TXC (_U_(0x1) << SERCOM_USART_INTENSET_TXC_Pos) 798 #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ 799 #define SERCOM_USART_INTENSET_RXC (_U_(0x1) << SERCOM_USART_INTENSET_RXC_Pos) 800 #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ 801 #define SERCOM_USART_INTENSET_RXS (_U_(0x1) << SERCOM_USART_INTENSET_RXS_Pos) 802 #define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */ 803 #define SERCOM_USART_INTENSET_CTSIC (_U_(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos) 804 #define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */ 805 #define SERCOM_USART_INTENSET_RXBRK (_U_(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos) 806 #define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */ 807 #define SERCOM_USART_INTENSET_ERROR (_U_(0x1) << SERCOM_USART_INTENSET_ERROR_Pos) 808 #define SERCOM_USART_INTENSET_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTENSET) MASK Register */ 809 810 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ 811 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 812 typedef union { // __I to avoid read-modify-write on write-to-clear register 813 struct { 814 __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ 815 __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ 816 __I uint8_t :5; /*!< bit: 2.. 6 Reserved */ 817 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 818 } bit; /*!< Structure used for bit access */ 819 uint8_t reg; /*!< Type used for register access */ 820 } SERCOM_I2CM_INTFLAG_Type; 821 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 822 823 #define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ 824 #define SERCOM_I2CM_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ 825 826 #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */ 827 #define SERCOM_I2CM_INTFLAG_MB (_U_(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos) 828 #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */ 829 #define SERCOM_I2CM_INTFLAG_SB (_U_(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos) 830 #define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */ 831 #define SERCOM_I2CM_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos) 832 #define SERCOM_I2CM_INTFLAG_MASK _U_(0x83) /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ 833 834 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ 835 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 836 typedef union { // __I to avoid read-modify-write on write-to-clear register 837 struct { 838 __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ 839 __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ 840 __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ 841 __I uint8_t :4; /*!< bit: 3.. 6 Reserved */ 842 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 843 } bit; /*!< Structure used for bit access */ 844 uint8_t reg; /*!< Type used for register access */ 845 } SERCOM_I2CS_INTFLAG_Type; 846 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 847 848 #define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ 849 #define SERCOM_I2CS_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ 850 851 #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */ 852 #define SERCOM_I2CS_INTFLAG_PREC (_U_(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos) 853 #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */ 854 #define SERCOM_I2CS_INTFLAG_AMATCH (_U_(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos) 855 #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */ 856 #define SERCOM_I2CS_INTFLAG_DRDY (_U_(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos) 857 #define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */ 858 #define SERCOM_I2CS_INTFLAG_ERROR (_U_(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos) 859 #define SERCOM_I2CS_INTFLAG_MASK _U_(0x87) /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ 860 861 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ 862 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 863 typedef union { // __I to avoid read-modify-write on write-to-clear register 864 struct { 865 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ 866 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ 867 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ 868 __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ 869 __I uint8_t :3; /*!< bit: 4.. 6 Reserved */ 870 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 871 } bit; /*!< Structure used for bit access */ 872 uint8_t reg; /*!< Type used for register access */ 873 } SERCOM_SPI_INTFLAG_Type; 874 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 875 876 #define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ 877 #define SERCOM_SPI_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ 878 879 #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */ 880 #define SERCOM_SPI_INTFLAG_DRE (_U_(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos) 881 #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */ 882 #define SERCOM_SPI_INTFLAG_TXC (_U_(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos) 883 #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */ 884 #define SERCOM_SPI_INTFLAG_RXC (_U_(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos) 885 #define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */ 886 #define SERCOM_SPI_INTFLAG_SSL (_U_(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos) 887 #define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */ 888 #define SERCOM_SPI_INTFLAG_ERROR (_U_(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos) 889 #define SERCOM_SPI_INTFLAG_MASK _U_(0x8F) /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ 890 891 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ 892 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 893 typedef union { // __I to avoid read-modify-write on write-to-clear register 894 struct { 895 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ 896 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ 897 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ 898 __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ 899 __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ 900 __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ 901 __I uint8_t :1; /*!< bit: 6 Reserved */ 902 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 903 } bit; /*!< Structure used for bit access */ 904 uint8_t reg; /*!< Type used for register access */ 905 } SERCOM_USART_INTFLAG_Type; 906 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 907 908 #define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ 909 #define SERCOM_USART_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ 910 911 #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */ 912 #define SERCOM_USART_INTFLAG_DRE (_U_(0x1) << SERCOM_USART_INTFLAG_DRE_Pos) 913 #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */ 914 #define SERCOM_USART_INTFLAG_TXC (_U_(0x1) << SERCOM_USART_INTFLAG_TXC_Pos) 915 #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */ 916 #define SERCOM_USART_INTFLAG_RXC (_U_(0x1) << SERCOM_USART_INTFLAG_RXC_Pos) 917 #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ 918 #define SERCOM_USART_INTFLAG_RXS (_U_(0x1) << SERCOM_USART_INTFLAG_RXS_Pos) 919 #define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */ 920 #define SERCOM_USART_INTFLAG_CTSIC (_U_(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos) 921 #define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */ 922 #define SERCOM_USART_INTFLAG_RXBRK (_U_(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos) 923 #define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */ 924 #define SERCOM_USART_INTFLAG_ERROR (_U_(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos) 925 #define SERCOM_USART_INTFLAG_MASK _U_(0xBF) /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ 926 927 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ 928 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 929 typedef union { 930 struct { 931 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 932 uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ 933 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 934 uint16_t :1; /*!< bit: 3 Reserved */ 935 uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ 936 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ 937 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 938 uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ 939 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ 940 uint16_t LENERR:1; /*!< bit: 10 Length Error */ 941 uint16_t :5; /*!< bit: 11..15 Reserved */ 942 } bit; /*!< Structure used for bit access */ 943 uint16_t reg; /*!< Type used for register access */ 944 } SERCOM_I2CM_STATUS_Type; 945 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 946 947 #define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ 948 #define SERCOM_I2CM_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ 949 950 #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ 951 #define SERCOM_I2CM_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos) 952 #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ 953 #define SERCOM_I2CM_STATUS_ARBLOST (_U_(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos) 954 #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ 955 #define SERCOM_I2CM_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos) 956 #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ 957 #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U_(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos) 958 #define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)) 959 #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */ 960 #define SERCOM_I2CM_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos) 961 #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ 962 #define SERCOM_I2CM_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos) 963 #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */ 964 #define SERCOM_I2CM_STATUS_MEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos) 965 #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */ 966 #define SERCOM_I2CM_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos) 967 #define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */ 968 #define SERCOM_I2CM_STATUS_LENERR (_U_(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos) 969 #define SERCOM_I2CM_STATUS_MASK _U_(0x07F7) /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ 970 971 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ 972 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 973 typedef union { 974 struct { 975 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 976 uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ 977 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 978 uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ 979 uint16_t SR:1; /*!< bit: 4 Repeated Start */ 980 uint16_t :1; /*!< bit: 5 Reserved */ 981 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ 982 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 983 uint16_t :1; /*!< bit: 8 Reserved */ 984 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ 985 uint16_t HS:1; /*!< bit: 10 High Speed */ 986 uint16_t :5; /*!< bit: 11..15 Reserved */ 987 } bit; /*!< Structure used for bit access */ 988 uint16_t reg; /*!< Type used for register access */ 989 } SERCOM_I2CS_STATUS_Type; 990 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 991 992 #define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ 993 #define SERCOM_I2CS_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ 994 995 #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ 996 #define SERCOM_I2CS_STATUS_BUSERR (_U_(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos) 997 #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ 998 #define SERCOM_I2CS_STATUS_COLL (_U_(0x1) << SERCOM_I2CS_STATUS_COLL_Pos) 999 #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ 1000 #define SERCOM_I2CS_STATUS_RXNACK (_U_(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos) 1001 #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */ 1002 #define SERCOM_I2CS_STATUS_DIR (_U_(0x1) << SERCOM_I2CS_STATUS_DIR_Pos) 1003 #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ 1004 #define SERCOM_I2CS_STATUS_SR (_U_(0x1) << SERCOM_I2CS_STATUS_SR_Pos) 1005 #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */ 1006 #define SERCOM_I2CS_STATUS_LOWTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos) 1007 #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ 1008 #define SERCOM_I2CS_STATUS_CLKHOLD (_U_(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos) 1009 #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */ 1010 #define SERCOM_I2CS_STATUS_SEXTTOUT (_U_(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos) 1011 #define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */ 1012 #define SERCOM_I2CS_STATUS_HS (_U_(0x1) << SERCOM_I2CS_STATUS_HS_Pos) 1013 #define SERCOM_I2CS_STATUS_MASK _U_(0x06DF) /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ 1014 1015 /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ 1016 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1017 typedef union { 1018 struct { 1019 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 1020 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 1021 uint16_t :13; /*!< bit: 3..15 Reserved */ 1022 } bit; /*!< Structure used for bit access */ 1023 uint16_t reg; /*!< Type used for register access */ 1024 } SERCOM_SPI_STATUS_Type; 1025 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1026 1027 #define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ 1028 #define SERCOM_SPI_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ 1029 1030 #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ 1031 #define SERCOM_SPI_STATUS_BUFOVF (_U_(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos) 1032 #define SERCOM_SPI_STATUS_MASK _U_(0x0004) /**< \brief (SERCOM_SPI_STATUS) MASK Register */ 1033 1034 /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ 1035 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1036 typedef union { 1037 struct { 1038 uint16_t PERR:1; /*!< bit: 0 Parity Error */ 1039 uint16_t FERR:1; /*!< bit: 1 Frame Error */ 1040 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 1041 uint16_t CTS:1; /*!< bit: 3 Clear To Send */ 1042 uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ 1043 uint16_t COLL:1; /*!< bit: 5 Collision Detected */ 1044 uint16_t TXE:1; /*!< bit: 6 Transmitter Empty */ 1045 uint16_t :9; /*!< bit: 7..15 Reserved */ 1046 } bit; /*!< Structure used for bit access */ 1047 uint16_t reg; /*!< Type used for register access */ 1048 } SERCOM_USART_STATUS_Type; 1049 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1050 1051 #define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */ 1052 #define SERCOM_USART_STATUS_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ 1053 1054 #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ 1055 #define SERCOM_USART_STATUS_PERR (_U_(0x1) << SERCOM_USART_STATUS_PERR_Pos) 1056 #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ 1057 #define SERCOM_USART_STATUS_FERR (_U_(0x1) << SERCOM_USART_STATUS_FERR_Pos) 1058 #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ 1059 #define SERCOM_USART_STATUS_BUFOVF (_U_(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos) 1060 #define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */ 1061 #define SERCOM_USART_STATUS_CTS (_U_(0x1) << SERCOM_USART_STATUS_CTS_Pos) 1062 #define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */ 1063 #define SERCOM_USART_STATUS_ISF (_U_(0x1) << SERCOM_USART_STATUS_ISF_Pos) 1064 #define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */ 1065 #define SERCOM_USART_STATUS_COLL (_U_(0x1) << SERCOM_USART_STATUS_COLL_Pos) 1066 #define SERCOM_USART_STATUS_TXE_Pos 6 /**< \brief (SERCOM_USART_STATUS) Transmitter Empty */ 1067 #define SERCOM_USART_STATUS_TXE (_U_(0x1) << SERCOM_USART_STATUS_TXE_Pos) 1068 #define SERCOM_USART_STATUS_MASK _U_(0x007F) /**< \brief (SERCOM_USART_STATUS) MASK Register */ 1069 1070 /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */ 1071 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1072 typedef union { 1073 struct { 1074 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1075 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1076 uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ 1077 uint32_t :29; /*!< bit: 3..31 Reserved */ 1078 } bit; /*!< Structure used for bit access */ 1079 uint32_t reg; /*!< Type used for register access */ 1080 } SERCOM_I2CM_SYNCBUSY_Type; 1081 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1082 1083 #define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */ 1084 #define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */ 1085 1086 #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */ 1087 #define SERCOM_I2CM_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos) 1088 #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1089 #define SERCOM_I2CM_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos) 1090 #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */ 1091 #define SERCOM_I2CM_SYNCBUSY_SYSOP (_U_(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos) 1092 #define SERCOM_I2CM_SYNCBUSY_MASK _U_(0x00000007) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */ 1093 1094 /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */ 1095 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1096 typedef union { 1097 struct { 1098 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1099 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1100 uint32_t :30; /*!< bit: 2..31 Reserved */ 1101 } bit; /*!< Structure used for bit access */ 1102 uint32_t reg; /*!< Type used for register access */ 1103 } SERCOM_I2CS_SYNCBUSY_Type; 1104 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1105 1106 #define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */ 1107 #define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */ 1108 1109 #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */ 1110 #define SERCOM_I2CS_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos) 1111 #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1112 #define SERCOM_I2CS_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos) 1113 #define SERCOM_I2CS_SYNCBUSY_MASK _U_(0x00000003) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */ 1114 1115 /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */ 1116 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1117 typedef union { 1118 struct { 1119 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1120 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1121 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ 1122 uint32_t :29; /*!< bit: 3..31 Reserved */ 1123 } bit; /*!< Structure used for bit access */ 1124 uint32_t reg; /*!< Type used for register access */ 1125 } SERCOM_SPI_SYNCBUSY_Type; 1126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1127 1128 #define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */ 1129 #define SERCOM_SPI_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */ 1130 1131 #define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */ 1132 #define SERCOM_SPI_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos) 1133 #define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1134 #define SERCOM_SPI_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos) 1135 #define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */ 1136 #define SERCOM_SPI_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos) 1137 #define SERCOM_SPI_SYNCBUSY_MASK _U_(0x00000007) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */ 1138 1139 /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */ 1140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1141 typedef union { 1142 struct { 1143 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1144 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1145 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ 1146 uint32_t :29; /*!< bit: 3..31 Reserved */ 1147 } bit; /*!< Structure used for bit access */ 1148 uint32_t reg; /*!< Type used for register access */ 1149 } SERCOM_USART_SYNCBUSY_Type; 1150 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1151 1152 #define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */ 1153 #define SERCOM_USART_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */ 1154 1155 #define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */ 1156 #define SERCOM_USART_SYNCBUSY_SWRST (_U_(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos) 1157 #define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1158 #define SERCOM_USART_SYNCBUSY_ENABLE (_U_(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos) 1159 #define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */ 1160 #define SERCOM_USART_SYNCBUSY_CTRLB (_U_(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos) 1161 #define SERCOM_USART_SYNCBUSY_MASK _U_(0x00000007) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */ 1162 1163 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ 1164 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1165 typedef union { 1166 struct { 1167 uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ 1168 uint32_t :2; /*!< bit: 11..12 Reserved */ 1169 uint32_t LENEN:1; /*!< bit: 13 Length Enable */ 1170 uint32_t HS:1; /*!< bit: 14 High Speed Mode */ 1171 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ 1172 uint32_t LEN:8; /*!< bit: 16..23 Length */ 1173 uint32_t :8; /*!< bit: 24..31 Reserved */ 1174 } bit; /*!< Structure used for bit access */ 1175 uint32_t reg; /*!< Type used for register access */ 1176 } SERCOM_I2CM_ADDR_Type; 1177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1178 1179 #define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ 1180 #define SERCOM_I2CM_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ 1181 1182 #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */ 1183 #define SERCOM_I2CM_ADDR_ADDR_Msk (_U_(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos) 1184 #define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)) 1185 #define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */ 1186 #define SERCOM_I2CM_ADDR_LENEN (_U_(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos) 1187 #define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */ 1188 #define SERCOM_I2CM_ADDR_HS (_U_(0x1) << SERCOM_I2CM_ADDR_HS_Pos) 1189 #define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */ 1190 #define SERCOM_I2CM_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos) 1191 #define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */ 1192 #define SERCOM_I2CM_ADDR_LEN_Msk (_U_(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos) 1193 #define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)) 1194 #define SERCOM_I2CM_ADDR_MASK _U_(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ 1195 1196 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ 1197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1198 typedef union { 1199 struct { 1200 uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ 1201 uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ 1202 uint32_t :4; /*!< bit: 11..14 Reserved */ 1203 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ 1204 uint32_t :1; /*!< bit: 16 Reserved */ 1205 uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ 1206 uint32_t :5; /*!< bit: 27..31 Reserved */ 1207 } bit; /*!< Structure used for bit access */ 1208 uint32_t reg; /*!< Type used for register access */ 1209 } SERCOM_I2CS_ADDR_Type; 1210 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1211 1212 #define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ 1213 #define SERCOM_I2CS_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ 1214 1215 #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ 1216 #define SERCOM_I2CS_ADDR_GENCEN (_U_(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos) 1217 #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */ 1218 #define SERCOM_I2CS_ADDR_ADDR_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos) 1219 #define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)) 1220 #define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */ 1221 #define SERCOM_I2CS_ADDR_TENBITEN (_U_(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos) 1222 #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ 1223 #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U_(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos) 1224 #define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)) 1225 #define SERCOM_I2CS_ADDR_MASK _U_(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ 1226 1227 /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ 1228 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1229 typedef union { 1230 struct { 1231 uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ 1232 uint32_t :8; /*!< bit: 8..15 Reserved */ 1233 uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ 1234 uint32_t :8; /*!< bit: 24..31 Reserved */ 1235 } bit; /*!< Structure used for bit access */ 1236 uint32_t reg; /*!< Type used for register access */ 1237 } SERCOM_SPI_ADDR_Type; 1238 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1239 1240 #define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ 1241 #define SERCOM_SPI_ADDR_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ 1242 1243 #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */ 1244 #define SERCOM_SPI_ADDR_ADDR_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos) 1245 #define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)) 1246 #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ 1247 #define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U_(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos) 1248 #define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)) 1249 #define SERCOM_SPI_ADDR_MASK _U_(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */ 1250 1251 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ 1252 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1253 typedef union { 1254 struct { 1255 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ 1256 } bit; /*!< Structure used for bit access */ 1257 uint8_t reg; /*!< Type used for register access */ 1258 } SERCOM_I2CM_DATA_Type; 1259 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1260 1261 #define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ 1262 #define SERCOM_I2CM_DATA_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ 1263 1264 #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */ 1265 #define SERCOM_I2CM_DATA_DATA_Msk (_U_(0xFF) << SERCOM_I2CM_DATA_DATA_Pos) 1266 #define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)) 1267 #define SERCOM_I2CM_DATA_MASK _U_(0xFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */ 1268 1269 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ 1270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1271 typedef union { 1272 struct { 1273 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ 1274 } bit; /*!< Structure used for bit access */ 1275 uint8_t reg; /*!< Type used for register access */ 1276 } SERCOM_I2CS_DATA_Type; 1277 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1278 1279 #define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ 1280 #define SERCOM_I2CS_DATA_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ 1281 1282 #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */ 1283 #define SERCOM_I2CS_DATA_DATA_Msk (_U_(0xFF) << SERCOM_I2CS_DATA_DATA_Pos) 1284 #define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)) 1285 #define SERCOM_I2CS_DATA_MASK _U_(0xFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */ 1286 1287 /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ 1288 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1289 typedef union { 1290 struct { 1291 uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ 1292 uint32_t :23; /*!< bit: 9..31 Reserved */ 1293 } bit; /*!< Structure used for bit access */ 1294 uint32_t reg; /*!< Type used for register access */ 1295 } SERCOM_SPI_DATA_Type; 1296 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1297 1298 #define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ 1299 #define SERCOM_SPI_DATA_RESETVALUE _U_(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ 1300 1301 #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */ 1302 #define SERCOM_SPI_DATA_DATA_Msk (_U_(0x1FF) << SERCOM_SPI_DATA_DATA_Pos) 1303 #define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)) 1304 #define SERCOM_SPI_DATA_MASK _U_(0x000001FF) /**< \brief (SERCOM_SPI_DATA) MASK Register */ 1305 1306 /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ 1307 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1308 typedef union { 1309 struct { 1310 uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ 1311 uint16_t :7; /*!< bit: 9..15 Reserved */ 1312 } bit; /*!< Structure used for bit access */ 1313 uint16_t reg; /*!< Type used for register access */ 1314 } SERCOM_USART_DATA_Type; 1315 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1316 1317 #define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */ 1318 #define SERCOM_USART_DATA_RESETVALUE _U_(0x0000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ 1319 1320 #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */ 1321 #define SERCOM_USART_DATA_DATA_Msk (_U_(0x1FF) << SERCOM_USART_DATA_DATA_Pos) 1322 #define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)) 1323 #define SERCOM_USART_DATA_MASK _U_(0x01FF) /**< \brief (SERCOM_USART_DATA) MASK Register */ 1324 1325 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ 1326 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1327 typedef union { 1328 struct { 1329 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ 1330 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 1331 } bit; /*!< Structure used for bit access */ 1332 uint8_t reg; /*!< Type used for register access */ 1333 } SERCOM_I2CM_DBGCTRL_Type; 1334 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1335 1336 #define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ 1337 #define SERCOM_I2CM_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ 1338 1339 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */ 1340 #define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) 1341 #define SERCOM_I2CM_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ 1342 1343 /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ 1344 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1345 typedef union { 1346 struct { 1347 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ 1348 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 1349 } bit; /*!< Structure used for bit access */ 1350 uint8_t reg; /*!< Type used for register access */ 1351 } SERCOM_SPI_DBGCTRL_Type; 1352 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1353 1354 #define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ 1355 #define SERCOM_SPI_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ 1356 1357 #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */ 1358 #define SERCOM_SPI_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) 1359 #define SERCOM_SPI_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ 1360 1361 /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ 1362 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1363 typedef union { 1364 struct { 1365 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ 1366 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 1367 } bit; /*!< Structure used for bit access */ 1368 uint8_t reg; /*!< Type used for register access */ 1369 } SERCOM_USART_DBGCTRL_Type; 1370 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1371 1372 #define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ 1373 #define SERCOM_USART_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ 1374 1375 #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */ 1376 #define SERCOM_USART_DBGCTRL_DBGSTOP (_U_(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) 1377 #define SERCOM_USART_DBGCTRL_MASK _U_(0x01) /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ 1378 1379 /** \brief SERCOM_I2CM hardware registers */ 1380 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1381 typedef struct { /* I2C Master Mode */ 1382 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ 1383 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ 1384 RoReg8 Reserved1[0x4]; 1385 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ 1386 RoReg8 Reserved2[0x4]; 1387 __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ 1388 RoReg8 Reserved3[0x1]; 1389 __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ 1390 RoReg8 Reserved4[0x1]; 1391 __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ 1392 RoReg8 Reserved5[0x1]; 1393 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ 1394 __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */ 1395 RoReg8 Reserved6[0x4]; 1396 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ 1397 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ 1398 RoReg8 Reserved7[0x7]; 1399 __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ 1400 } SercomI2cm; 1401 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1402 1403 /** \brief SERCOM_I2CS hardware registers */ 1404 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1405 typedef struct { /* I2C Slave Mode */ 1406 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ 1407 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ 1408 RoReg8 Reserved1[0xC]; 1409 __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ 1410 RoReg8 Reserved2[0x1]; 1411 __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ 1412 RoReg8 Reserved3[0x1]; 1413 __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ 1414 RoReg8 Reserved4[0x1]; 1415 __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ 1416 __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */ 1417 RoReg8 Reserved5[0x4]; 1418 __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ 1419 __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ 1420 } SercomI2cs; 1421 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1422 1423 /** \brief SERCOM_SPI hardware registers */ 1424 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1425 typedef struct { /* SPI Mode */ 1426 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ 1427 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ 1428 RoReg8 Reserved1[0x4]; 1429 __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ 1430 RoReg8 Reserved2[0x7]; 1431 __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ 1432 RoReg8 Reserved3[0x1]; 1433 __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ 1434 RoReg8 Reserved4[0x1]; 1435 __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ 1436 RoReg8 Reserved5[0x1]; 1437 __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ 1438 __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */ 1439 RoReg8 Reserved6[0x4]; 1440 __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ 1441 __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ 1442 RoReg8 Reserved7[0x4]; 1443 __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ 1444 } SercomSpi; 1445 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1446 1447 /** \brief SERCOM_USART hardware registers */ 1448 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1449 typedef struct { /* USART Mode */ 1450 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ 1451 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ 1452 __IO SERCOM_USART_CTRLC_Type CTRLC; /**< \brief Offset: 0x08 (R/W 32) USART Control C */ 1453 __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ 1454 __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ 1455 RoReg8 Reserved1[0x5]; 1456 __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ 1457 RoReg8 Reserved2[0x1]; 1458 __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ 1459 RoReg8 Reserved3[0x1]; 1460 __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ 1461 RoReg8 Reserved4[0x1]; 1462 __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ 1463 __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */ 1464 RoReg8 Reserved5[0x8]; 1465 __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ 1466 RoReg8 Reserved6[0x6]; 1467 __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ 1468 } SercomUsart; 1469 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1470 1471 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1472 typedef union { 1473 SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ 1474 SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ 1475 SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ 1476 SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ 1477 } Sercom; 1478 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1479 1480 /*@}*/ 1481 1482 #endif /* _SAMC21_SERCOM_COMPONENT_ */ 1483
