1 /** 2 * \file 3 * 4 * \brief Component description for RTC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_RTC_COMPONENT_H_ 32 #define _SAMV71_RTC_COMPONENT_H_ 33 #define _SAMV71_RTC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Real-time Clock 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR RTC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define RTC_6056 /**< (RTC) Module ID */ 46 #define REV_RTC ZB /**< (RTC) Module revision */ 47 48 /* -------- RTC_CR : (RTC Offset: 0x00) (R/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t UPDTIM:1; /**< bit: 0 Update Request Time Register */ 54 uint32_t UPDCAL:1; /**< bit: 1 Update Request Calendar Register */ 55 uint32_t :6; /**< bit: 2..7 Reserved */ 56 uint32_t TIMEVSEL:2; /**< bit: 8..9 Time Event Selection */ 57 uint32_t :6; /**< bit: 10..15 Reserved */ 58 uint32_t CALEVSEL:2; /**< bit: 16..17 Calendar Event Selection */ 59 uint32_t :14; /**< bit: 18..31 Reserved */ 60 } bit; /**< Structure used for bit access */ 61 uint32_t reg; /**< Type used for register access */ 62 } RTC_CR_Type; 63 #endif 64 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 65 66 #define RTC_CR_OFFSET (0x00) /**< (RTC_CR) Control Register Offset */ 67 68 #define RTC_CR_UPDTIM_Pos 0 /**< (RTC_CR) Update Request Time Register Position */ 69 #define RTC_CR_UPDTIM_Msk (_U_(0x1) << RTC_CR_UPDTIM_Pos) /**< (RTC_CR) Update Request Time Register Mask */ 70 #define RTC_CR_UPDTIM RTC_CR_UPDTIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CR_UPDTIM_Msk instead */ 71 #define RTC_CR_UPDCAL_Pos 1 /**< (RTC_CR) Update Request Calendar Register Position */ 72 #define RTC_CR_UPDCAL_Msk (_U_(0x1) << RTC_CR_UPDCAL_Pos) /**< (RTC_CR) Update Request Calendar Register Mask */ 73 #define RTC_CR_UPDCAL RTC_CR_UPDCAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CR_UPDCAL_Msk instead */ 74 #define RTC_CR_TIMEVSEL_Pos 8 /**< (RTC_CR) Time Event Selection Position */ 75 #define RTC_CR_TIMEVSEL_Msk (_U_(0x3) << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Time Event Selection Mask */ 76 #define RTC_CR_TIMEVSEL(value) (RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos)) 77 #define RTC_CR_TIMEVSEL_MINUTE_Val _U_(0x0) /**< (RTC_CR) Minute change */ 78 #define RTC_CR_TIMEVSEL_HOUR_Val _U_(0x1) /**< (RTC_CR) Hour change */ 79 #define RTC_CR_TIMEVSEL_MIDNIGHT_Val _U_(0x2) /**< (RTC_CR) Every day at midnight */ 80 #define RTC_CR_TIMEVSEL_NOON_Val _U_(0x3) /**< (RTC_CR) Every day at noon */ 81 #define RTC_CR_TIMEVSEL_MINUTE (RTC_CR_TIMEVSEL_MINUTE_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Minute change Position */ 82 #define RTC_CR_TIMEVSEL_HOUR (RTC_CR_TIMEVSEL_HOUR_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Hour change Position */ 83 #define RTC_CR_TIMEVSEL_MIDNIGHT (RTC_CR_TIMEVSEL_MIDNIGHT_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at midnight Position */ 84 #define RTC_CR_TIMEVSEL_NOON (RTC_CR_TIMEVSEL_NOON_Val << RTC_CR_TIMEVSEL_Pos) /**< (RTC_CR) Every day at noon Position */ 85 #define RTC_CR_CALEVSEL_Pos 16 /**< (RTC_CR) Calendar Event Selection Position */ 86 #define RTC_CR_CALEVSEL_Msk (_U_(0x3) << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Calendar Event Selection Mask */ 87 #define RTC_CR_CALEVSEL(value) (RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos)) 88 #define RTC_CR_CALEVSEL_WEEK_Val _U_(0x0) /**< (RTC_CR) Week change (every Monday at time 00:00:00) */ 89 #define RTC_CR_CALEVSEL_MONTH_Val _U_(0x1) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ 90 #define RTC_CR_CALEVSEL_YEAR_Val _U_(0x2) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) */ 91 #define RTC_CR_CALEVSEL_WEEK (RTC_CR_CALEVSEL_WEEK_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Week change (every Monday at time 00:00:00) Position */ 92 #define RTC_CR_CALEVSEL_MONTH (RTC_CR_CALEVSEL_MONTH_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Month change (every 01 of each month at time 00:00:00) Position */ 93 #define RTC_CR_CALEVSEL_YEAR (RTC_CR_CALEVSEL_YEAR_Val << RTC_CR_CALEVSEL_Pos) /**< (RTC_CR) Year change (every January 1 at time 00:00:00) Position */ 94 #define RTC_CR_MASK _U_(0x30303) /**< \deprecated (RTC_CR) Register MASK (Use RTC_CR_Msk instead) */ 95 #define RTC_CR_Msk _U_(0x30303) /**< (RTC_CR) Register Mask */ 96 97 98 /* -------- RTC_MR : (RTC Offset: 0x04) (R/W 32) Mode Register -------- */ 99 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 100 #if COMPONENT_TYPEDEF_STYLE == 'N' 101 typedef union { 102 struct { 103 uint32_t HRMOD:1; /**< bit: 0 12-/24-hour Mode */ 104 uint32_t PERSIAN:1; /**< bit: 1 PERSIAN Calendar */ 105 uint32_t :2; /**< bit: 2..3 Reserved */ 106 uint32_t NEGPPM:1; /**< bit: 4 NEGative PPM Correction */ 107 uint32_t :3; /**< bit: 5..7 Reserved */ 108 uint32_t CORRECTION:7; /**< bit: 8..14 Slow Clock Correction */ 109 uint32_t HIGHPPM:1; /**< bit: 15 HIGH PPM Correction */ 110 uint32_t OUT0:3; /**< bit: 16..18 RTCOUT0 OutputSource Selection */ 111 uint32_t :1; /**< bit: 19 Reserved */ 112 uint32_t OUT1:3; /**< bit: 20..22 RTCOUT1 Output Source Selection */ 113 uint32_t :1; /**< bit: 23 Reserved */ 114 uint32_t THIGH:3; /**< bit: 24..26 High Duration of the Output Pulse */ 115 uint32_t :1; /**< bit: 27 Reserved */ 116 uint32_t TPERIOD:2; /**< bit: 28..29 Period of the Output Pulse */ 117 uint32_t :2; /**< bit: 30..31 Reserved */ 118 } bit; /**< Structure used for bit access */ 119 uint32_t reg; /**< Type used for register access */ 120 } RTC_MR_Type; 121 #endif 122 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 123 124 #define RTC_MR_OFFSET (0x04) /**< (RTC_MR) Mode Register Offset */ 125 126 #define RTC_MR_HRMOD_Pos 0 /**< (RTC_MR) 12-/24-hour Mode Position */ 127 #define RTC_MR_HRMOD_Msk (_U_(0x1) << RTC_MR_HRMOD_Pos) /**< (RTC_MR) 12-/24-hour Mode Mask */ 128 #define RTC_MR_HRMOD RTC_MR_HRMOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_HRMOD_Msk instead */ 129 #define RTC_MR_PERSIAN_Pos 1 /**< (RTC_MR) PERSIAN Calendar Position */ 130 #define RTC_MR_PERSIAN_Msk (_U_(0x1) << RTC_MR_PERSIAN_Pos) /**< (RTC_MR) PERSIAN Calendar Mask */ 131 #define RTC_MR_PERSIAN RTC_MR_PERSIAN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_PERSIAN_Msk instead */ 132 #define RTC_MR_NEGPPM_Pos 4 /**< (RTC_MR) NEGative PPM Correction Position */ 133 #define RTC_MR_NEGPPM_Msk (_U_(0x1) << RTC_MR_NEGPPM_Pos) /**< (RTC_MR) NEGative PPM Correction Mask */ 134 #define RTC_MR_NEGPPM RTC_MR_NEGPPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_NEGPPM_Msk instead */ 135 #define RTC_MR_CORRECTION_Pos 8 /**< (RTC_MR) Slow Clock Correction Position */ 136 #define RTC_MR_CORRECTION_Msk (_U_(0x7F) << RTC_MR_CORRECTION_Pos) /**< (RTC_MR) Slow Clock Correction Mask */ 137 #define RTC_MR_CORRECTION(value) (RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos)) 138 #define RTC_MR_HIGHPPM_Pos 15 /**< (RTC_MR) HIGH PPM Correction Position */ 139 #define RTC_MR_HIGHPPM_Msk (_U_(0x1) << RTC_MR_HIGHPPM_Pos) /**< (RTC_MR) HIGH PPM Correction Mask */ 140 #define RTC_MR_HIGHPPM RTC_MR_HIGHPPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_MR_HIGHPPM_Msk instead */ 141 #define RTC_MR_OUT0_Pos 16 /**< (RTC_MR) RTCOUT0 OutputSource Selection Position */ 142 #define RTC_MR_OUT0_Msk (_U_(0x7) << RTC_MR_OUT0_Pos) /**< (RTC_MR) RTCOUT0 OutputSource Selection Mask */ 143 #define RTC_MR_OUT0(value) (RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos)) 144 #define RTC_MR_OUT0_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */ 145 #define RTC_MR_OUT0_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */ 146 #define RTC_MR_OUT0_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */ 147 #define RTC_MR_OUT0_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */ 148 #define RTC_MR_OUT0_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */ 149 #define RTC_MR_OUT0_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */ 150 #define RTC_MR_OUT0_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */ 151 #define RTC_MR_OUT0_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */ 152 #define RTC_MR_OUT0_NO_WAVE (RTC_MR_OUT0_NO_WAVE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */ 153 #define RTC_MR_OUT0_FREQ1HZ (RTC_MR_OUT0_FREQ1HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 1 Hz square wave Position */ 154 #define RTC_MR_OUT0_FREQ32HZ (RTC_MR_OUT0_FREQ32HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 32 Hz square wave Position */ 155 #define RTC_MR_OUT0_FREQ64HZ (RTC_MR_OUT0_FREQ64HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 64 Hz square wave Position */ 156 #define RTC_MR_OUT0_FREQ512HZ (RTC_MR_OUT0_FREQ512HZ_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) 512 Hz square wave Position */ 157 #define RTC_MR_OUT0_ALARM_TOGGLE (RTC_MR_OUT0_ALARM_TOGGLE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */ 158 #define RTC_MR_OUT0_ALARM_FLAG (RTC_MR_OUT0_ALARM_FLAG_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */ 159 #define RTC_MR_OUT0_PROG_PULSE (RTC_MR_OUT0_PROG_PULSE_Val << RTC_MR_OUT0_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */ 160 #define RTC_MR_OUT1_Pos 20 /**< (RTC_MR) RTCOUT1 Output Source Selection Position */ 161 #define RTC_MR_OUT1_Msk (_U_(0x7) << RTC_MR_OUT1_Pos) /**< (RTC_MR) RTCOUT1 Output Source Selection Mask */ 162 #define RTC_MR_OUT1(value) (RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos)) 163 #define RTC_MR_OUT1_NO_WAVE_Val _U_(0x0) /**< (RTC_MR) No waveform, stuck at '0' */ 164 #define RTC_MR_OUT1_FREQ1HZ_Val _U_(0x1) /**< (RTC_MR) 1 Hz square wave */ 165 #define RTC_MR_OUT1_FREQ32HZ_Val _U_(0x2) /**< (RTC_MR) 32 Hz square wave */ 166 #define RTC_MR_OUT1_FREQ64HZ_Val _U_(0x3) /**< (RTC_MR) 64 Hz square wave */ 167 #define RTC_MR_OUT1_FREQ512HZ_Val _U_(0x4) /**< (RTC_MR) 512 Hz square wave */ 168 #define RTC_MR_OUT1_ALARM_TOGGLE_Val _U_(0x5) /**< (RTC_MR) Output toggles when alarm flag rises */ 169 #define RTC_MR_OUT1_ALARM_FLAG_Val _U_(0x6) /**< (RTC_MR) Output is a copy of the alarm flag */ 170 #define RTC_MR_OUT1_PROG_PULSE_Val _U_(0x7) /**< (RTC_MR) Duty cycle programmable pulse */ 171 #define RTC_MR_OUT1_NO_WAVE (RTC_MR_OUT1_NO_WAVE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) No waveform, stuck at '0' Position */ 172 #define RTC_MR_OUT1_FREQ1HZ (RTC_MR_OUT1_FREQ1HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 1 Hz square wave Position */ 173 #define RTC_MR_OUT1_FREQ32HZ (RTC_MR_OUT1_FREQ32HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 32 Hz square wave Position */ 174 #define RTC_MR_OUT1_FREQ64HZ (RTC_MR_OUT1_FREQ64HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 64 Hz square wave Position */ 175 #define RTC_MR_OUT1_FREQ512HZ (RTC_MR_OUT1_FREQ512HZ_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) 512 Hz square wave Position */ 176 #define RTC_MR_OUT1_ALARM_TOGGLE (RTC_MR_OUT1_ALARM_TOGGLE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output toggles when alarm flag rises Position */ 177 #define RTC_MR_OUT1_ALARM_FLAG (RTC_MR_OUT1_ALARM_FLAG_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Output is a copy of the alarm flag Position */ 178 #define RTC_MR_OUT1_PROG_PULSE (RTC_MR_OUT1_PROG_PULSE_Val << RTC_MR_OUT1_Pos) /**< (RTC_MR) Duty cycle programmable pulse Position */ 179 #define RTC_MR_THIGH_Pos 24 /**< (RTC_MR) High Duration of the Output Pulse Position */ 180 #define RTC_MR_THIGH_Msk (_U_(0x7) << RTC_MR_THIGH_Pos) /**< (RTC_MR) High Duration of the Output Pulse Mask */ 181 #define RTC_MR_THIGH(value) (RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos)) 182 #define RTC_MR_THIGH_H_31MS_Val _U_(0x0) /**< (RTC_MR) 31.2 ms */ 183 #define RTC_MR_THIGH_H_16MS_Val _U_(0x1) /**< (RTC_MR) 15.6 ms */ 184 #define RTC_MR_THIGH_H_4MS_Val _U_(0x2) /**< (RTC_MR) 3.91 ms */ 185 #define RTC_MR_THIGH_H_976US_Val _U_(0x3) /**< (RTC_MR) 976 us */ 186 #define RTC_MR_THIGH_H_488US_Val _U_(0x4) /**< (RTC_MR) 488 us */ 187 #define RTC_MR_THIGH_H_122US_Val _U_(0x5) /**< (RTC_MR) 122 us */ 188 #define RTC_MR_THIGH_H_30US_Val _U_(0x6) /**< (RTC_MR) 30.5 us */ 189 #define RTC_MR_THIGH_H_15US_Val _U_(0x7) /**< (RTC_MR) 15.2 us */ 190 #define RTC_MR_THIGH_H_31MS (RTC_MR_THIGH_H_31MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 31.2 ms Position */ 191 #define RTC_MR_THIGH_H_16MS (RTC_MR_THIGH_H_16MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.6 ms Position */ 192 #define RTC_MR_THIGH_H_4MS (RTC_MR_THIGH_H_4MS_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 3.91 ms Position */ 193 #define RTC_MR_THIGH_H_976US (RTC_MR_THIGH_H_976US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 976 us Position */ 194 #define RTC_MR_THIGH_H_488US (RTC_MR_THIGH_H_488US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 488 us Position */ 195 #define RTC_MR_THIGH_H_122US (RTC_MR_THIGH_H_122US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 122 us Position */ 196 #define RTC_MR_THIGH_H_30US (RTC_MR_THIGH_H_30US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 30.5 us Position */ 197 #define RTC_MR_THIGH_H_15US (RTC_MR_THIGH_H_15US_Val << RTC_MR_THIGH_Pos) /**< (RTC_MR) 15.2 us Position */ 198 #define RTC_MR_TPERIOD_Pos 28 /**< (RTC_MR) Period of the Output Pulse Position */ 199 #define RTC_MR_TPERIOD_Msk (_U_(0x3) << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) Period of the Output Pulse Mask */ 200 #define RTC_MR_TPERIOD(value) (RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos)) 201 #define RTC_MR_TPERIOD_P_1S_Val _U_(0x0) /**< (RTC_MR) 1 second */ 202 #define RTC_MR_TPERIOD_P_500MS_Val _U_(0x1) /**< (RTC_MR) 500 ms */ 203 #define RTC_MR_TPERIOD_P_250MS_Val _U_(0x2) /**< (RTC_MR) 250 ms */ 204 #define RTC_MR_TPERIOD_P_125MS_Val _U_(0x3) /**< (RTC_MR) 125 ms */ 205 #define RTC_MR_TPERIOD_P_1S (RTC_MR_TPERIOD_P_1S_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 1 second Position */ 206 #define RTC_MR_TPERIOD_P_500MS (RTC_MR_TPERIOD_P_500MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 500 ms Position */ 207 #define RTC_MR_TPERIOD_P_250MS (RTC_MR_TPERIOD_P_250MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 250 ms Position */ 208 #define RTC_MR_TPERIOD_P_125MS (RTC_MR_TPERIOD_P_125MS_Val << RTC_MR_TPERIOD_Pos) /**< (RTC_MR) 125 ms Position */ 209 #define RTC_MR_MASK _U_(0x3777FF13) /**< \deprecated (RTC_MR) Register MASK (Use RTC_MR_Msk instead) */ 210 #define RTC_MR_Msk _U_(0x3777FF13) /**< (RTC_MR) Register Mask */ 211 212 213 /* -------- RTC_TIMR : (RTC Offset: 0x08) (R/W 32) Time Register -------- */ 214 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 215 #if COMPONENT_TYPEDEF_STYLE == 'N' 216 typedef union { 217 struct { 218 uint32_t SEC:7; /**< bit: 0..6 Current Second */ 219 uint32_t :1; /**< bit: 7 Reserved */ 220 uint32_t MIN:7; /**< bit: 8..14 Current Minute */ 221 uint32_t :1; /**< bit: 15 Reserved */ 222 uint32_t HOUR:6; /**< bit: 16..21 Current Hour */ 223 uint32_t AMPM:1; /**< bit: 22 Ante Meridiem Post Meridiem Indicator */ 224 uint32_t :9; /**< bit: 23..31 Reserved */ 225 } bit; /**< Structure used for bit access */ 226 uint32_t reg; /**< Type used for register access */ 227 } RTC_TIMR_Type; 228 #endif 229 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 230 231 #define RTC_TIMR_OFFSET (0x08) /**< (RTC_TIMR) Time Register Offset */ 232 233 #define RTC_TIMR_SEC_Pos 0 /**< (RTC_TIMR) Current Second Position */ 234 #define RTC_TIMR_SEC_Msk (_U_(0x7F) << RTC_TIMR_SEC_Pos) /**< (RTC_TIMR) Current Second Mask */ 235 #define RTC_TIMR_SEC(value) (RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos)) 236 #define RTC_TIMR_MIN_Pos 8 /**< (RTC_TIMR) Current Minute Position */ 237 #define RTC_TIMR_MIN_Msk (_U_(0x7F) << RTC_TIMR_MIN_Pos) /**< (RTC_TIMR) Current Minute Mask */ 238 #define RTC_TIMR_MIN(value) (RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos)) 239 #define RTC_TIMR_HOUR_Pos 16 /**< (RTC_TIMR) Current Hour Position */ 240 #define RTC_TIMR_HOUR_Msk (_U_(0x3F) << RTC_TIMR_HOUR_Pos) /**< (RTC_TIMR) Current Hour Mask */ 241 #define RTC_TIMR_HOUR(value) (RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos)) 242 #define RTC_TIMR_AMPM_Pos 22 /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Position */ 243 #define RTC_TIMR_AMPM_Msk (_U_(0x1) << RTC_TIMR_AMPM_Pos) /**< (RTC_TIMR) Ante Meridiem Post Meridiem Indicator Mask */ 244 #define RTC_TIMR_AMPM RTC_TIMR_AMPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMR_AMPM_Msk instead */ 245 #define RTC_TIMR_MASK _U_(0x7F7F7F) /**< \deprecated (RTC_TIMR) Register MASK (Use RTC_TIMR_Msk instead) */ 246 #define RTC_TIMR_Msk _U_(0x7F7F7F) /**< (RTC_TIMR) Register Mask */ 247 248 249 /* -------- RTC_CALR : (RTC Offset: 0x0c) (R/W 32) Calendar Register -------- */ 250 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 251 #if COMPONENT_TYPEDEF_STYLE == 'N' 252 typedef union { 253 struct { 254 uint32_t CENT:7; /**< bit: 0..6 Current Century */ 255 uint32_t :1; /**< bit: 7 Reserved */ 256 uint32_t YEAR:8; /**< bit: 8..15 Current Year */ 257 uint32_t MONTH:5; /**< bit: 16..20 Current Month */ 258 uint32_t DAY:3; /**< bit: 21..23 Current Day in Current Week */ 259 uint32_t DATE:6; /**< bit: 24..29 Current Day in Current Month */ 260 uint32_t :2; /**< bit: 30..31 Reserved */ 261 } bit; /**< Structure used for bit access */ 262 uint32_t reg; /**< Type used for register access */ 263 } RTC_CALR_Type; 264 #endif 265 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 266 267 #define RTC_CALR_OFFSET (0x0C) /**< (RTC_CALR) Calendar Register Offset */ 268 269 #define RTC_CALR_CENT_Pos 0 /**< (RTC_CALR) Current Century Position */ 270 #define RTC_CALR_CENT_Msk (_U_(0x7F) << RTC_CALR_CENT_Pos) /**< (RTC_CALR) Current Century Mask */ 271 #define RTC_CALR_CENT(value) (RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos)) 272 #define RTC_CALR_YEAR_Pos 8 /**< (RTC_CALR) Current Year Position */ 273 #define RTC_CALR_YEAR_Msk (_U_(0xFF) << RTC_CALR_YEAR_Pos) /**< (RTC_CALR) Current Year Mask */ 274 #define RTC_CALR_YEAR(value) (RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos)) 275 #define RTC_CALR_MONTH_Pos 16 /**< (RTC_CALR) Current Month Position */ 276 #define RTC_CALR_MONTH_Msk (_U_(0x1F) << RTC_CALR_MONTH_Pos) /**< (RTC_CALR) Current Month Mask */ 277 #define RTC_CALR_MONTH(value) (RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos)) 278 #define RTC_CALR_DAY_Pos 21 /**< (RTC_CALR) Current Day in Current Week Position */ 279 #define RTC_CALR_DAY_Msk (_U_(0x7) << RTC_CALR_DAY_Pos) /**< (RTC_CALR) Current Day in Current Week Mask */ 280 #define RTC_CALR_DAY(value) (RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos)) 281 #define RTC_CALR_DATE_Pos 24 /**< (RTC_CALR) Current Day in Current Month Position */ 282 #define RTC_CALR_DATE_Msk (_U_(0x3F) << RTC_CALR_DATE_Pos) /**< (RTC_CALR) Current Day in Current Month Mask */ 283 #define RTC_CALR_DATE(value) (RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos)) 284 #define RTC_CALR_MASK _U_(0x3FFFFF7F) /**< \deprecated (RTC_CALR) Register MASK (Use RTC_CALR_Msk instead) */ 285 #define RTC_CALR_Msk _U_(0x3FFFFF7F) /**< (RTC_CALR) Register Mask */ 286 287 288 /* -------- RTC_TIMALR : (RTC Offset: 0x10) (R/W 32) Time Alarm Register -------- */ 289 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 290 #if COMPONENT_TYPEDEF_STYLE == 'N' 291 typedef union { 292 struct { 293 uint32_t SEC:7; /**< bit: 0..6 Second Alarm */ 294 uint32_t SECEN:1; /**< bit: 7 Second Alarm Enable */ 295 uint32_t MIN:7; /**< bit: 8..14 Minute Alarm */ 296 uint32_t MINEN:1; /**< bit: 15 Minute Alarm Enable */ 297 uint32_t HOUR:6; /**< bit: 16..21 Hour Alarm */ 298 uint32_t AMPM:1; /**< bit: 22 AM/PM Indicator */ 299 uint32_t HOUREN:1; /**< bit: 23 Hour Alarm Enable */ 300 uint32_t :8; /**< bit: 24..31 Reserved */ 301 } bit; /**< Structure used for bit access */ 302 uint32_t reg; /**< Type used for register access */ 303 } RTC_TIMALR_Type; 304 #endif 305 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 306 307 #define RTC_TIMALR_OFFSET (0x10) /**< (RTC_TIMALR) Time Alarm Register Offset */ 308 309 #define RTC_TIMALR_SEC_Pos 0 /**< (RTC_TIMALR) Second Alarm Position */ 310 #define RTC_TIMALR_SEC_Msk (_U_(0x7F) << RTC_TIMALR_SEC_Pos) /**< (RTC_TIMALR) Second Alarm Mask */ 311 #define RTC_TIMALR_SEC(value) (RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos)) 312 #define RTC_TIMALR_SECEN_Pos 7 /**< (RTC_TIMALR) Second Alarm Enable Position */ 313 #define RTC_TIMALR_SECEN_Msk (_U_(0x1) << RTC_TIMALR_SECEN_Pos) /**< (RTC_TIMALR) Second Alarm Enable Mask */ 314 #define RTC_TIMALR_SECEN RTC_TIMALR_SECEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_SECEN_Msk instead */ 315 #define RTC_TIMALR_MIN_Pos 8 /**< (RTC_TIMALR) Minute Alarm Position */ 316 #define RTC_TIMALR_MIN_Msk (_U_(0x7F) << RTC_TIMALR_MIN_Pos) /**< (RTC_TIMALR) Minute Alarm Mask */ 317 #define RTC_TIMALR_MIN(value) (RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos)) 318 #define RTC_TIMALR_MINEN_Pos 15 /**< (RTC_TIMALR) Minute Alarm Enable Position */ 319 #define RTC_TIMALR_MINEN_Msk (_U_(0x1) << RTC_TIMALR_MINEN_Pos) /**< (RTC_TIMALR) Minute Alarm Enable Mask */ 320 #define RTC_TIMALR_MINEN RTC_TIMALR_MINEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_MINEN_Msk instead */ 321 #define RTC_TIMALR_HOUR_Pos 16 /**< (RTC_TIMALR) Hour Alarm Position */ 322 #define RTC_TIMALR_HOUR_Msk (_U_(0x3F) << RTC_TIMALR_HOUR_Pos) /**< (RTC_TIMALR) Hour Alarm Mask */ 323 #define RTC_TIMALR_HOUR(value) (RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos)) 324 #define RTC_TIMALR_AMPM_Pos 22 /**< (RTC_TIMALR) AM/PM Indicator Position */ 325 #define RTC_TIMALR_AMPM_Msk (_U_(0x1) << RTC_TIMALR_AMPM_Pos) /**< (RTC_TIMALR) AM/PM Indicator Mask */ 326 #define RTC_TIMALR_AMPM RTC_TIMALR_AMPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_AMPM_Msk instead */ 327 #define RTC_TIMALR_HOUREN_Pos 23 /**< (RTC_TIMALR) Hour Alarm Enable Position */ 328 #define RTC_TIMALR_HOUREN_Msk (_U_(0x1) << RTC_TIMALR_HOUREN_Pos) /**< (RTC_TIMALR) Hour Alarm Enable Mask */ 329 #define RTC_TIMALR_HOUREN RTC_TIMALR_HOUREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_TIMALR_HOUREN_Msk instead */ 330 #define RTC_TIMALR_MASK _U_(0xFFFFFF) /**< \deprecated (RTC_TIMALR) Register MASK (Use RTC_TIMALR_Msk instead) */ 331 #define RTC_TIMALR_Msk _U_(0xFFFFFF) /**< (RTC_TIMALR) Register Mask */ 332 333 334 /* -------- RTC_CALALR : (RTC Offset: 0x14) (R/W 32) Calendar Alarm Register -------- */ 335 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 336 #if COMPONENT_TYPEDEF_STYLE == 'N' 337 typedef union { 338 struct { 339 uint32_t :16; /**< bit: 0..15 Reserved */ 340 uint32_t MONTH:5; /**< bit: 16..20 Month Alarm */ 341 uint32_t :2; /**< bit: 21..22 Reserved */ 342 uint32_t MTHEN:1; /**< bit: 23 Month Alarm Enable */ 343 uint32_t DATE:6; /**< bit: 24..29 Date Alarm */ 344 uint32_t :1; /**< bit: 30 Reserved */ 345 uint32_t DATEEN:1; /**< bit: 31 Date Alarm Enable */ 346 } bit; /**< Structure used for bit access */ 347 uint32_t reg; /**< Type used for register access */ 348 } RTC_CALALR_Type; 349 #endif 350 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 351 352 #define RTC_CALALR_OFFSET (0x14) /**< (RTC_CALALR) Calendar Alarm Register Offset */ 353 354 #define RTC_CALALR_MONTH_Pos 16 /**< (RTC_CALALR) Month Alarm Position */ 355 #define RTC_CALALR_MONTH_Msk (_U_(0x1F) << RTC_CALALR_MONTH_Pos) /**< (RTC_CALALR) Month Alarm Mask */ 356 #define RTC_CALALR_MONTH(value) (RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos)) 357 #define RTC_CALALR_MTHEN_Pos 23 /**< (RTC_CALALR) Month Alarm Enable Position */ 358 #define RTC_CALALR_MTHEN_Msk (_U_(0x1) << RTC_CALALR_MTHEN_Pos) /**< (RTC_CALALR) Month Alarm Enable Mask */ 359 #define RTC_CALALR_MTHEN RTC_CALALR_MTHEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CALALR_MTHEN_Msk instead */ 360 #define RTC_CALALR_DATE_Pos 24 /**< (RTC_CALALR) Date Alarm Position */ 361 #define RTC_CALALR_DATE_Msk (_U_(0x3F) << RTC_CALALR_DATE_Pos) /**< (RTC_CALALR) Date Alarm Mask */ 362 #define RTC_CALALR_DATE(value) (RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos)) 363 #define RTC_CALALR_DATEEN_Pos 31 /**< (RTC_CALALR) Date Alarm Enable Position */ 364 #define RTC_CALALR_DATEEN_Msk (_U_(0x1) << RTC_CALALR_DATEEN_Pos) /**< (RTC_CALALR) Date Alarm Enable Mask */ 365 #define RTC_CALALR_DATEEN RTC_CALALR_DATEEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_CALALR_DATEEN_Msk instead */ 366 #define RTC_CALALR_MASK _U_(0xBF9F0000) /**< \deprecated (RTC_CALALR) Register MASK (Use RTC_CALALR_Msk instead) */ 367 #define RTC_CALALR_Msk _U_(0xBF9F0000) /**< (RTC_CALALR) Register Mask */ 368 369 370 /* -------- RTC_SR : (RTC Offset: 0x18) (R/ 32) Status Register -------- */ 371 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 372 #if COMPONENT_TYPEDEF_STYLE == 'N' 373 typedef union { 374 struct { 375 uint32_t ACKUPD:1; /**< bit: 0 Acknowledge for Update */ 376 uint32_t ALARM:1; /**< bit: 1 Alarm Flag */ 377 uint32_t SEC:1; /**< bit: 2 Second Event */ 378 uint32_t TIMEV:1; /**< bit: 3 Time Event */ 379 uint32_t CALEV:1; /**< bit: 4 Calendar Event */ 380 uint32_t TDERR:1; /**< bit: 5 Time and/or Date Free Running Error */ 381 uint32_t :26; /**< bit: 6..31 Reserved */ 382 } bit; /**< Structure used for bit access */ 383 uint32_t reg; /**< Type used for register access */ 384 } RTC_SR_Type; 385 #endif 386 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 387 388 #define RTC_SR_OFFSET (0x18) /**< (RTC_SR) Status Register Offset */ 389 390 #define RTC_SR_ACKUPD_Pos 0 /**< (RTC_SR) Acknowledge for Update Position */ 391 #define RTC_SR_ACKUPD_Msk (_U_(0x1) << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Acknowledge for Update Mask */ 392 #define RTC_SR_ACKUPD RTC_SR_ACKUPD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_ACKUPD_Msk instead */ 393 #define RTC_SR_ACKUPD_FREERUN_Val _U_(0x0) /**< (RTC_SR) Time and calendar registers cannot be updated. */ 394 #define RTC_SR_ACKUPD_UPDATE_Val _U_(0x1) /**< (RTC_SR) Time and calendar registers can be updated. */ 395 #define RTC_SR_ACKUPD_FREERUN (RTC_SR_ACKUPD_FREERUN_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers cannot be updated. Position */ 396 #define RTC_SR_ACKUPD_UPDATE (RTC_SR_ACKUPD_UPDATE_Val << RTC_SR_ACKUPD_Pos) /**< (RTC_SR) Time and calendar registers can be updated. Position */ 397 #define RTC_SR_ALARM_Pos 1 /**< (RTC_SR) Alarm Flag Position */ 398 #define RTC_SR_ALARM_Msk (_U_(0x1) << RTC_SR_ALARM_Pos) /**< (RTC_SR) Alarm Flag Mask */ 399 #define RTC_SR_ALARM RTC_SR_ALARM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_ALARM_Msk instead */ 400 #define RTC_SR_ALARM_NO_ALARMEVENT_Val _U_(0x0) /**< (RTC_SR) No alarm matching condition occurred. */ 401 #define RTC_SR_ALARM_ALARMEVENT_Val _U_(0x1) /**< (RTC_SR) An alarm matching condition has occurred. */ 402 #define RTC_SR_ALARM_NO_ALARMEVENT (RTC_SR_ALARM_NO_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) No alarm matching condition occurred. Position */ 403 #define RTC_SR_ALARM_ALARMEVENT (RTC_SR_ALARM_ALARMEVENT_Val << RTC_SR_ALARM_Pos) /**< (RTC_SR) An alarm matching condition has occurred. Position */ 404 #define RTC_SR_SEC_Pos 2 /**< (RTC_SR) Second Event Position */ 405 #define RTC_SR_SEC_Msk (_U_(0x1) << RTC_SR_SEC_Pos) /**< (RTC_SR) Second Event Mask */ 406 #define RTC_SR_SEC RTC_SR_SEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_SEC_Msk instead */ 407 #define RTC_SR_SEC_NO_SECEVENT_Val _U_(0x0) /**< (RTC_SR) No second event has occurred since the last clear. */ 408 #define RTC_SR_SEC_SECEVENT_Val _U_(0x1) /**< (RTC_SR) At least one second event has occurred since the last clear. */ 409 #define RTC_SR_SEC_NO_SECEVENT (RTC_SR_SEC_NO_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) No second event has occurred since the last clear. Position */ 410 #define RTC_SR_SEC_SECEVENT (RTC_SR_SEC_SECEVENT_Val << RTC_SR_SEC_Pos) /**< (RTC_SR) At least one second event has occurred since the last clear. Position */ 411 #define RTC_SR_TIMEV_Pos 3 /**< (RTC_SR) Time Event Position */ 412 #define RTC_SR_TIMEV_Msk (_U_(0x1) << RTC_SR_TIMEV_Pos) /**< (RTC_SR) Time Event Mask */ 413 #define RTC_SR_TIMEV RTC_SR_TIMEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_TIMEV_Msk instead */ 414 #define RTC_SR_TIMEV_NO_TIMEVENT_Val _U_(0x0) /**< (RTC_SR) No time event has occurred since the last clear. */ 415 #define RTC_SR_TIMEV_TIMEVENT_Val _U_(0x1) /**< (RTC_SR) At least one time event has occurred since the last clear. */ 416 #define RTC_SR_TIMEV_NO_TIMEVENT (RTC_SR_TIMEV_NO_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) No time event has occurred since the last clear. Position */ 417 #define RTC_SR_TIMEV_TIMEVENT (RTC_SR_TIMEV_TIMEVENT_Val << RTC_SR_TIMEV_Pos) /**< (RTC_SR) At least one time event has occurred since the last clear. Position */ 418 #define RTC_SR_CALEV_Pos 4 /**< (RTC_SR) Calendar Event Position */ 419 #define RTC_SR_CALEV_Msk (_U_(0x1) << RTC_SR_CALEV_Pos) /**< (RTC_SR) Calendar Event Mask */ 420 #define RTC_SR_CALEV RTC_SR_CALEV_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_CALEV_Msk instead */ 421 #define RTC_SR_CALEV_NO_CALEVENT_Val _U_(0x0) /**< (RTC_SR) No calendar event has occurred since the last clear. */ 422 #define RTC_SR_CALEV_CALEVENT_Val _U_(0x1) /**< (RTC_SR) At least one calendar event has occurred since the last clear. */ 423 #define RTC_SR_CALEV_NO_CALEVENT (RTC_SR_CALEV_NO_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) No calendar event has occurred since the last clear. Position */ 424 #define RTC_SR_CALEV_CALEVENT (RTC_SR_CALEV_CALEVENT_Val << RTC_SR_CALEV_Pos) /**< (RTC_SR) At least one calendar event has occurred since the last clear. Position */ 425 #define RTC_SR_TDERR_Pos 5 /**< (RTC_SR) Time and/or Date Free Running Error Position */ 426 #define RTC_SR_TDERR_Msk (_U_(0x1) << RTC_SR_TDERR_Pos) /**< (RTC_SR) Time and/or Date Free Running Error Mask */ 427 #define RTC_SR_TDERR RTC_SR_TDERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SR_TDERR_Msk instead */ 428 #define RTC_SR_TDERR_CORRECT_Val _U_(0x0) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ 429 #define RTC_SR_TDERR_ERR_TIMEDATE_Val _U_(0x1) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ 430 #define RTC_SR_TDERR_CORRECT (RTC_SR_TDERR_CORRECT_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). Position */ 431 #define RTC_SR_TDERR_ERR_TIMEDATE (RTC_SR_TDERR_ERR_TIMEDATE_Val << RTC_SR_TDERR_Pos) /**< (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. Position */ 432 #define RTC_SR_MASK _U_(0x3F) /**< \deprecated (RTC_SR) Register MASK (Use RTC_SR_Msk instead) */ 433 #define RTC_SR_Msk _U_(0x3F) /**< (RTC_SR) Register Mask */ 434 435 436 /* -------- RTC_SCCR : (RTC Offset: 0x1c) (/W 32) Status Clear Command Register -------- */ 437 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 438 #if COMPONENT_TYPEDEF_STYLE == 'N' 439 typedef union { 440 struct { 441 uint32_t ACKCLR:1; /**< bit: 0 Acknowledge Clear */ 442 uint32_t ALRCLR:1; /**< bit: 1 Alarm Clear */ 443 uint32_t SECCLR:1; /**< bit: 2 Second Clear */ 444 uint32_t TIMCLR:1; /**< bit: 3 Time Clear */ 445 uint32_t CALCLR:1; /**< bit: 4 Calendar Clear */ 446 uint32_t TDERRCLR:1; /**< bit: 5 Time and/or Date Free Running Error Clear */ 447 uint32_t :26; /**< bit: 6..31 Reserved */ 448 } bit; /**< Structure used for bit access */ 449 uint32_t reg; /**< Type used for register access */ 450 } RTC_SCCR_Type; 451 #endif 452 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 453 454 #define RTC_SCCR_OFFSET (0x1C) /**< (RTC_SCCR) Status Clear Command Register Offset */ 455 456 #define RTC_SCCR_ACKCLR_Pos 0 /**< (RTC_SCCR) Acknowledge Clear Position */ 457 #define RTC_SCCR_ACKCLR_Msk (_U_(0x1) << RTC_SCCR_ACKCLR_Pos) /**< (RTC_SCCR) Acknowledge Clear Mask */ 458 #define RTC_SCCR_ACKCLR RTC_SCCR_ACKCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_ACKCLR_Msk instead */ 459 #define RTC_SCCR_ALRCLR_Pos 1 /**< (RTC_SCCR) Alarm Clear Position */ 460 #define RTC_SCCR_ALRCLR_Msk (_U_(0x1) << RTC_SCCR_ALRCLR_Pos) /**< (RTC_SCCR) Alarm Clear Mask */ 461 #define RTC_SCCR_ALRCLR RTC_SCCR_ALRCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_ALRCLR_Msk instead */ 462 #define RTC_SCCR_SECCLR_Pos 2 /**< (RTC_SCCR) Second Clear Position */ 463 #define RTC_SCCR_SECCLR_Msk (_U_(0x1) << RTC_SCCR_SECCLR_Pos) /**< (RTC_SCCR) Second Clear Mask */ 464 #define RTC_SCCR_SECCLR RTC_SCCR_SECCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_SECCLR_Msk instead */ 465 #define RTC_SCCR_TIMCLR_Pos 3 /**< (RTC_SCCR) Time Clear Position */ 466 #define RTC_SCCR_TIMCLR_Msk (_U_(0x1) << RTC_SCCR_TIMCLR_Pos) /**< (RTC_SCCR) Time Clear Mask */ 467 #define RTC_SCCR_TIMCLR RTC_SCCR_TIMCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_TIMCLR_Msk instead */ 468 #define RTC_SCCR_CALCLR_Pos 4 /**< (RTC_SCCR) Calendar Clear Position */ 469 #define RTC_SCCR_CALCLR_Msk (_U_(0x1) << RTC_SCCR_CALCLR_Pos) /**< (RTC_SCCR) Calendar Clear Mask */ 470 #define RTC_SCCR_CALCLR RTC_SCCR_CALCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_CALCLR_Msk instead */ 471 #define RTC_SCCR_TDERRCLR_Pos 5 /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Position */ 472 #define RTC_SCCR_TDERRCLR_Msk (_U_(0x1) << RTC_SCCR_TDERRCLR_Pos) /**< (RTC_SCCR) Time and/or Date Free Running Error Clear Mask */ 473 #define RTC_SCCR_TDERRCLR RTC_SCCR_TDERRCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_SCCR_TDERRCLR_Msk instead */ 474 #define RTC_SCCR_MASK _U_(0x3F) /**< \deprecated (RTC_SCCR) Register MASK (Use RTC_SCCR_Msk instead) */ 475 #define RTC_SCCR_Msk _U_(0x3F) /**< (RTC_SCCR) Register Mask */ 476 477 478 /* -------- RTC_IER : (RTC Offset: 0x20) (/W 32) Interrupt Enable Register -------- */ 479 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 480 #if COMPONENT_TYPEDEF_STYLE == 'N' 481 typedef union { 482 struct { 483 uint32_t ACKEN:1; /**< bit: 0 Acknowledge Update Interrupt Enable */ 484 uint32_t ALREN:1; /**< bit: 1 Alarm Interrupt Enable */ 485 uint32_t SECEN:1; /**< bit: 2 Second Event Interrupt Enable */ 486 uint32_t TIMEN:1; /**< bit: 3 Time Event Interrupt Enable */ 487 uint32_t CALEN:1; /**< bit: 4 Calendar Event Interrupt Enable */ 488 uint32_t TDERREN:1; /**< bit: 5 Time and/or Date Error Interrupt Enable */ 489 uint32_t :26; /**< bit: 6..31 Reserved */ 490 } bit; /**< Structure used for bit access */ 491 uint32_t reg; /**< Type used for register access */ 492 } RTC_IER_Type; 493 #endif 494 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 495 496 #define RTC_IER_OFFSET (0x20) /**< (RTC_IER) Interrupt Enable Register Offset */ 497 498 #define RTC_IER_ACKEN_Pos 0 /**< (RTC_IER) Acknowledge Update Interrupt Enable Position */ 499 #define RTC_IER_ACKEN_Msk (_U_(0x1) << RTC_IER_ACKEN_Pos) /**< (RTC_IER) Acknowledge Update Interrupt Enable Mask */ 500 #define RTC_IER_ACKEN RTC_IER_ACKEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_ACKEN_Msk instead */ 501 #define RTC_IER_ALREN_Pos 1 /**< (RTC_IER) Alarm Interrupt Enable Position */ 502 #define RTC_IER_ALREN_Msk (_U_(0x1) << RTC_IER_ALREN_Pos) /**< (RTC_IER) Alarm Interrupt Enable Mask */ 503 #define RTC_IER_ALREN RTC_IER_ALREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_ALREN_Msk instead */ 504 #define RTC_IER_SECEN_Pos 2 /**< (RTC_IER) Second Event Interrupt Enable Position */ 505 #define RTC_IER_SECEN_Msk (_U_(0x1) << RTC_IER_SECEN_Pos) /**< (RTC_IER) Second Event Interrupt Enable Mask */ 506 #define RTC_IER_SECEN RTC_IER_SECEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_SECEN_Msk instead */ 507 #define RTC_IER_TIMEN_Pos 3 /**< (RTC_IER) Time Event Interrupt Enable Position */ 508 #define RTC_IER_TIMEN_Msk (_U_(0x1) << RTC_IER_TIMEN_Pos) /**< (RTC_IER) Time Event Interrupt Enable Mask */ 509 #define RTC_IER_TIMEN RTC_IER_TIMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_TIMEN_Msk instead */ 510 #define RTC_IER_CALEN_Pos 4 /**< (RTC_IER) Calendar Event Interrupt Enable Position */ 511 #define RTC_IER_CALEN_Msk (_U_(0x1) << RTC_IER_CALEN_Pos) /**< (RTC_IER) Calendar Event Interrupt Enable Mask */ 512 #define RTC_IER_CALEN RTC_IER_CALEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_CALEN_Msk instead */ 513 #define RTC_IER_TDERREN_Pos 5 /**< (RTC_IER) Time and/or Date Error Interrupt Enable Position */ 514 #define RTC_IER_TDERREN_Msk (_U_(0x1) << RTC_IER_TDERREN_Pos) /**< (RTC_IER) Time and/or Date Error Interrupt Enable Mask */ 515 #define RTC_IER_TDERREN RTC_IER_TDERREN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IER_TDERREN_Msk instead */ 516 #define RTC_IER_MASK _U_(0x3F) /**< \deprecated (RTC_IER) Register MASK (Use RTC_IER_Msk instead) */ 517 #define RTC_IER_Msk _U_(0x3F) /**< (RTC_IER) Register Mask */ 518 519 520 /* -------- RTC_IDR : (RTC Offset: 0x24) (/W 32) Interrupt Disable Register -------- */ 521 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 522 #if COMPONENT_TYPEDEF_STYLE == 'N' 523 typedef union { 524 struct { 525 uint32_t ACKDIS:1; /**< bit: 0 Acknowledge Update Interrupt Disable */ 526 uint32_t ALRDIS:1; /**< bit: 1 Alarm Interrupt Disable */ 527 uint32_t SECDIS:1; /**< bit: 2 Second Event Interrupt Disable */ 528 uint32_t TIMDIS:1; /**< bit: 3 Time Event Interrupt Disable */ 529 uint32_t CALDIS:1; /**< bit: 4 Calendar Event Interrupt Disable */ 530 uint32_t TDERRDIS:1; /**< bit: 5 Time and/or Date Error Interrupt Disable */ 531 uint32_t :26; /**< bit: 6..31 Reserved */ 532 } bit; /**< Structure used for bit access */ 533 uint32_t reg; /**< Type used for register access */ 534 } RTC_IDR_Type; 535 #endif 536 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 537 538 #define RTC_IDR_OFFSET (0x24) /**< (RTC_IDR) Interrupt Disable Register Offset */ 539 540 #define RTC_IDR_ACKDIS_Pos 0 /**< (RTC_IDR) Acknowledge Update Interrupt Disable Position */ 541 #define RTC_IDR_ACKDIS_Msk (_U_(0x1) << RTC_IDR_ACKDIS_Pos) /**< (RTC_IDR) Acknowledge Update Interrupt Disable Mask */ 542 #define RTC_IDR_ACKDIS RTC_IDR_ACKDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_ACKDIS_Msk instead */ 543 #define RTC_IDR_ALRDIS_Pos 1 /**< (RTC_IDR) Alarm Interrupt Disable Position */ 544 #define RTC_IDR_ALRDIS_Msk (_U_(0x1) << RTC_IDR_ALRDIS_Pos) /**< (RTC_IDR) Alarm Interrupt Disable Mask */ 545 #define RTC_IDR_ALRDIS RTC_IDR_ALRDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_ALRDIS_Msk instead */ 546 #define RTC_IDR_SECDIS_Pos 2 /**< (RTC_IDR) Second Event Interrupt Disable Position */ 547 #define RTC_IDR_SECDIS_Msk (_U_(0x1) << RTC_IDR_SECDIS_Pos) /**< (RTC_IDR) Second Event Interrupt Disable Mask */ 548 #define RTC_IDR_SECDIS RTC_IDR_SECDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_SECDIS_Msk instead */ 549 #define RTC_IDR_TIMDIS_Pos 3 /**< (RTC_IDR) Time Event Interrupt Disable Position */ 550 #define RTC_IDR_TIMDIS_Msk (_U_(0x1) << RTC_IDR_TIMDIS_Pos) /**< (RTC_IDR) Time Event Interrupt Disable Mask */ 551 #define RTC_IDR_TIMDIS RTC_IDR_TIMDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_TIMDIS_Msk instead */ 552 #define RTC_IDR_CALDIS_Pos 4 /**< (RTC_IDR) Calendar Event Interrupt Disable Position */ 553 #define RTC_IDR_CALDIS_Msk (_U_(0x1) << RTC_IDR_CALDIS_Pos) /**< (RTC_IDR) Calendar Event Interrupt Disable Mask */ 554 #define RTC_IDR_CALDIS RTC_IDR_CALDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_CALDIS_Msk instead */ 555 #define RTC_IDR_TDERRDIS_Pos 5 /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Position */ 556 #define RTC_IDR_TDERRDIS_Msk (_U_(0x1) << RTC_IDR_TDERRDIS_Pos) /**< (RTC_IDR) Time and/or Date Error Interrupt Disable Mask */ 557 #define RTC_IDR_TDERRDIS RTC_IDR_TDERRDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IDR_TDERRDIS_Msk instead */ 558 #define RTC_IDR_MASK _U_(0x3F) /**< \deprecated (RTC_IDR) Register MASK (Use RTC_IDR_Msk instead) */ 559 #define RTC_IDR_Msk _U_(0x3F) /**< (RTC_IDR) Register Mask */ 560 561 562 /* -------- RTC_IMR : (RTC Offset: 0x28) (R/ 32) Interrupt Mask Register -------- */ 563 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 564 #if COMPONENT_TYPEDEF_STYLE == 'N' 565 typedef union { 566 struct { 567 uint32_t ACK:1; /**< bit: 0 Acknowledge Update Interrupt Mask */ 568 uint32_t ALR:1; /**< bit: 1 Alarm Interrupt Mask */ 569 uint32_t SEC:1; /**< bit: 2 Second Event Interrupt Mask */ 570 uint32_t TIM:1; /**< bit: 3 Time Event Interrupt Mask */ 571 uint32_t CAL:1; /**< bit: 4 Calendar Event Interrupt Mask */ 572 uint32_t TDERR:1; /**< bit: 5 Time and/or Date Error Mask */ 573 uint32_t :26; /**< bit: 6..31 Reserved */ 574 } bit; /**< Structure used for bit access */ 575 uint32_t reg; /**< Type used for register access */ 576 } RTC_IMR_Type; 577 #endif 578 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 579 580 #define RTC_IMR_OFFSET (0x28) /**< (RTC_IMR) Interrupt Mask Register Offset */ 581 582 #define RTC_IMR_ACK_Pos 0 /**< (RTC_IMR) Acknowledge Update Interrupt Mask Position */ 583 #define RTC_IMR_ACK_Msk (_U_(0x1) << RTC_IMR_ACK_Pos) /**< (RTC_IMR) Acknowledge Update Interrupt Mask Mask */ 584 #define RTC_IMR_ACK RTC_IMR_ACK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_ACK_Msk instead */ 585 #define RTC_IMR_ALR_Pos 1 /**< (RTC_IMR) Alarm Interrupt Mask Position */ 586 #define RTC_IMR_ALR_Msk (_U_(0x1) << RTC_IMR_ALR_Pos) /**< (RTC_IMR) Alarm Interrupt Mask Mask */ 587 #define RTC_IMR_ALR RTC_IMR_ALR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_ALR_Msk instead */ 588 #define RTC_IMR_SEC_Pos 2 /**< (RTC_IMR) Second Event Interrupt Mask Position */ 589 #define RTC_IMR_SEC_Msk (_U_(0x1) << RTC_IMR_SEC_Pos) /**< (RTC_IMR) Second Event Interrupt Mask Mask */ 590 #define RTC_IMR_SEC RTC_IMR_SEC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_SEC_Msk instead */ 591 #define RTC_IMR_TIM_Pos 3 /**< (RTC_IMR) Time Event Interrupt Mask Position */ 592 #define RTC_IMR_TIM_Msk (_U_(0x1) << RTC_IMR_TIM_Pos) /**< (RTC_IMR) Time Event Interrupt Mask Mask */ 593 #define RTC_IMR_TIM RTC_IMR_TIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_TIM_Msk instead */ 594 #define RTC_IMR_CAL_Pos 4 /**< (RTC_IMR) Calendar Event Interrupt Mask Position */ 595 #define RTC_IMR_CAL_Msk (_U_(0x1) << RTC_IMR_CAL_Pos) /**< (RTC_IMR) Calendar Event Interrupt Mask Mask */ 596 #define RTC_IMR_CAL RTC_IMR_CAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_CAL_Msk instead */ 597 #define RTC_IMR_TDERR_Pos 5 /**< (RTC_IMR) Time and/or Date Error Mask Position */ 598 #define RTC_IMR_TDERR_Msk (_U_(0x1) << RTC_IMR_TDERR_Pos) /**< (RTC_IMR) Time and/or Date Error Mask Mask */ 599 #define RTC_IMR_TDERR RTC_IMR_TDERR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_IMR_TDERR_Msk instead */ 600 #define RTC_IMR_MASK _U_(0x3F) /**< \deprecated (RTC_IMR) Register MASK (Use RTC_IMR_Msk instead) */ 601 #define RTC_IMR_Msk _U_(0x3F) /**< (RTC_IMR) Register Mask */ 602 603 604 /* -------- RTC_VER : (RTC Offset: 0x2c) (R/ 32) Valid Entry Register -------- */ 605 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 606 #if COMPONENT_TYPEDEF_STYLE == 'N' 607 typedef union { 608 struct { 609 uint32_t NVTIM:1; /**< bit: 0 Non-valid Time */ 610 uint32_t NVCAL:1; /**< bit: 1 Non-valid Calendar */ 611 uint32_t NVTIMALR:1; /**< bit: 2 Non-valid Time Alarm */ 612 uint32_t NVCALALR:1; /**< bit: 3 Non-valid Calendar Alarm */ 613 uint32_t :28; /**< bit: 4..31 Reserved */ 614 } bit; /**< Structure used for bit access */ 615 uint32_t reg; /**< Type used for register access */ 616 } RTC_VER_Type; 617 #endif 618 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 619 620 #define RTC_VER_OFFSET (0x2C) /**< (RTC_VER) Valid Entry Register Offset */ 621 622 #define RTC_VER_NVTIM_Pos 0 /**< (RTC_VER) Non-valid Time Position */ 623 #define RTC_VER_NVTIM_Msk (_U_(0x1) << RTC_VER_NVTIM_Pos) /**< (RTC_VER) Non-valid Time Mask */ 624 #define RTC_VER_NVTIM RTC_VER_NVTIM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVTIM_Msk instead */ 625 #define RTC_VER_NVCAL_Pos 1 /**< (RTC_VER) Non-valid Calendar Position */ 626 #define RTC_VER_NVCAL_Msk (_U_(0x1) << RTC_VER_NVCAL_Pos) /**< (RTC_VER) Non-valid Calendar Mask */ 627 #define RTC_VER_NVCAL RTC_VER_NVCAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVCAL_Msk instead */ 628 #define RTC_VER_NVTIMALR_Pos 2 /**< (RTC_VER) Non-valid Time Alarm Position */ 629 #define RTC_VER_NVTIMALR_Msk (_U_(0x1) << RTC_VER_NVTIMALR_Pos) /**< (RTC_VER) Non-valid Time Alarm Mask */ 630 #define RTC_VER_NVTIMALR RTC_VER_NVTIMALR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVTIMALR_Msk instead */ 631 #define RTC_VER_NVCALALR_Pos 3 /**< (RTC_VER) Non-valid Calendar Alarm Position */ 632 #define RTC_VER_NVCALALR_Msk (_U_(0x1) << RTC_VER_NVCALALR_Pos) /**< (RTC_VER) Non-valid Calendar Alarm Mask */ 633 #define RTC_VER_NVCALALR RTC_VER_NVCALALR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RTC_VER_NVCALALR_Msk instead */ 634 #define RTC_VER_MASK _U_(0x0F) /**< \deprecated (RTC_VER) Register MASK (Use RTC_VER_Msk instead) */ 635 #define RTC_VER_Msk _U_(0x0F) /**< (RTC_VER) Register Mask */ 636 637 638 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 639 #if COMPONENT_TYPEDEF_STYLE == 'R' 640 /** \brief RTC hardware registers */ 641 typedef struct { 642 __IO uint32_t RTC_CR; /**< (RTC Offset: 0x00) Control Register */ 643 __IO uint32_t RTC_MR; /**< (RTC Offset: 0x04) Mode Register */ 644 __IO uint32_t RTC_TIMR; /**< (RTC Offset: 0x08) Time Register */ 645 __IO uint32_t RTC_CALR; /**< (RTC Offset: 0x0C) Calendar Register */ 646 __IO uint32_t RTC_TIMALR; /**< (RTC Offset: 0x10) Time Alarm Register */ 647 __IO uint32_t RTC_CALALR; /**< (RTC Offset: 0x14) Calendar Alarm Register */ 648 __I uint32_t RTC_SR; /**< (RTC Offset: 0x18) Status Register */ 649 __O uint32_t RTC_SCCR; /**< (RTC Offset: 0x1C) Status Clear Command Register */ 650 __O uint32_t RTC_IER; /**< (RTC Offset: 0x20) Interrupt Enable Register */ 651 __O uint32_t RTC_IDR; /**< (RTC Offset: 0x24) Interrupt Disable Register */ 652 __I uint32_t RTC_IMR; /**< (RTC Offset: 0x28) Interrupt Mask Register */ 653 __I uint32_t RTC_VER; /**< (RTC Offset: 0x2C) Valid Entry Register */ 654 } Rtc; 655 656 #elif COMPONENT_TYPEDEF_STYLE == 'N' 657 /** \brief RTC hardware registers */ 658 typedef struct { 659 __IO RTC_CR_Type RTC_CR; /**< Offset: 0x00 (R/W 32) Control Register */ 660 __IO RTC_MR_Type RTC_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 661 __IO RTC_TIMR_Type RTC_TIMR; /**< Offset: 0x08 (R/W 32) Time Register */ 662 __IO RTC_CALR_Type RTC_CALR; /**< Offset: 0x0C (R/W 32) Calendar Register */ 663 __IO RTC_TIMALR_Type RTC_TIMALR; /**< Offset: 0x10 (R/W 32) Time Alarm Register */ 664 __IO RTC_CALALR_Type RTC_CALALR; /**< Offset: 0x14 (R/W 32) Calendar Alarm Register */ 665 __I RTC_SR_Type RTC_SR; /**< Offset: 0x18 (R/ 32) Status Register */ 666 __O RTC_SCCR_Type RTC_SCCR; /**< Offset: 0x1C ( /W 32) Status Clear Command Register */ 667 __O RTC_IER_Type RTC_IER; /**< Offset: 0x20 ( /W 32) Interrupt Enable Register */ 668 __O RTC_IDR_Type RTC_IDR; /**< Offset: 0x24 ( /W 32) Interrupt Disable Register */ 669 __I RTC_IMR_Type RTC_IMR; /**< Offset: 0x28 (R/ 32) Interrupt Mask Register */ 670 __I RTC_VER_Type RTC_VER; /**< Offset: 0x2C (R/ 32) Valid Entry Register */ 671 } Rtc; 672 673 #else /* COMPONENT_TYPEDEF_STYLE */ 674 #error Unknown component typedef style 675 #endif /* COMPONENT_TYPEDEF_STYLE */ 676 677 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 678 /** @} end of Real-time Clock */ 679 680 #endif /* _SAMV71_RTC_COMPONENT_H_ */ 681
