1 /** 2 * \file 3 * 4 * \brief Component description for MCAN 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_MCAN_COMPONENT_H_ 32 #define _SAMV71_MCAN_COMPONENT_H_ 33 #define _SAMV71_MCAN_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Controller Area Network 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR MCAN */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define MCAN_11273 /**< (MCAN) Module ID */ 46 #define REV_MCAN N /**< (MCAN) Module revision */ 47 48 /* -------- MCAN_RXBE_0 : (MCAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t ID:29; /**< bit: 0..28 Identifier */ 54 uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ 55 uint32_t XTD:1; /**< bit: 30 Extended Identifier */ 56 uint32_t ESI:1; /**< bit: 31 Error State Indicator */ 57 } bit; /**< Structure used for bit access */ 58 uint32_t reg; /**< Type used for register access */ 59 } MCAN_RXBE_0_Type; 60 #endif 61 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 #define MCAN_RXBE_0_OFFSET (0x00) /**< (MCAN_RXBE_0) Rx Buffer Element 0 Offset */ 64 65 #define MCAN_RXBE_0_ID_Pos 0 /**< (MCAN_RXBE_0) Identifier Position */ 66 #define MCAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_RXBE_0_ID_Pos) /**< (MCAN_RXBE_0) Identifier Mask */ 67 #define MCAN_RXBE_0_ID(value) (MCAN_RXBE_0_ID_Msk & ((value) << MCAN_RXBE_0_ID_Pos)) 68 #define MCAN_RXBE_0_RTR_Pos 29 /**< (MCAN_RXBE_0) Remote Transmission Request Position */ 69 #define MCAN_RXBE_0_RTR_Msk (_U_(0x1) << MCAN_RXBE_0_RTR_Pos) /**< (MCAN_RXBE_0) Remote Transmission Request Mask */ 70 #define MCAN_RXBE_0_RTR MCAN_RXBE_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_0_RTR_Msk instead */ 71 #define MCAN_RXBE_0_XTD_Pos 30 /**< (MCAN_RXBE_0) Extended Identifier Position */ 72 #define MCAN_RXBE_0_XTD_Msk (_U_(0x1) << MCAN_RXBE_0_XTD_Pos) /**< (MCAN_RXBE_0) Extended Identifier Mask */ 73 #define MCAN_RXBE_0_XTD MCAN_RXBE_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_0_XTD_Msk instead */ 74 #define MCAN_RXBE_0_ESI_Pos 31 /**< (MCAN_RXBE_0) Error State Indicator Position */ 75 #define MCAN_RXBE_0_ESI_Msk (_U_(0x1) << MCAN_RXBE_0_ESI_Pos) /**< (MCAN_RXBE_0) Error State Indicator Mask */ 76 #define MCAN_RXBE_0_ESI MCAN_RXBE_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_0_ESI_Msk instead */ 77 #define MCAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXBE_0) Register MASK (Use MCAN_RXBE_0_Msk instead) */ 78 #define MCAN_RXBE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXBE_0) Register Mask */ 79 80 81 /* -------- MCAN_RXBE_1 : (MCAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ 82 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 83 #if COMPONENT_TYPEDEF_STYLE == 'N' 84 typedef union { 85 struct { 86 uint32_t RXTS:16; /**< bit: 0..15 Rx Timestamp */ 87 uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ 88 uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ 89 uint32_t FDF:1; /**< bit: 21 FD Format */ 90 uint32_t :2; /**< bit: 22..23 Reserved */ 91 uint32_t FIDX:7; /**< bit: 24..30 Filter Index */ 92 uint32_t ANMF:1; /**< bit: 31 Accepted Non-matching Frame */ 93 } bit; /**< Structure used for bit access */ 94 uint32_t reg; /**< Type used for register access */ 95 } MCAN_RXBE_1_Type; 96 #endif 97 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 #define MCAN_RXBE_1_OFFSET (0x04) /**< (MCAN_RXBE_1) Rx Buffer Element 1 Offset */ 100 101 #define MCAN_RXBE_1_RXTS_Pos 0 /**< (MCAN_RXBE_1) Rx Timestamp Position */ 102 #define MCAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << MCAN_RXBE_1_RXTS_Pos) /**< (MCAN_RXBE_1) Rx Timestamp Mask */ 103 #define MCAN_RXBE_1_RXTS(value) (MCAN_RXBE_1_RXTS_Msk & ((value) << MCAN_RXBE_1_RXTS_Pos)) 104 #define MCAN_RXBE_1_DLC_Pos 16 /**< (MCAN_RXBE_1) Data Length Code Position */ 105 #define MCAN_RXBE_1_DLC_Msk (_U_(0xF) << MCAN_RXBE_1_DLC_Pos) /**< (MCAN_RXBE_1) Data Length Code Mask */ 106 #define MCAN_RXBE_1_DLC(value) (MCAN_RXBE_1_DLC_Msk & ((value) << MCAN_RXBE_1_DLC_Pos)) 107 #define MCAN_RXBE_1_BRS_Pos 20 /**< (MCAN_RXBE_1) Bit Rate Switch Position */ 108 #define MCAN_RXBE_1_BRS_Msk (_U_(0x1) << MCAN_RXBE_1_BRS_Pos) /**< (MCAN_RXBE_1) Bit Rate Switch Mask */ 109 #define MCAN_RXBE_1_BRS MCAN_RXBE_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_1_BRS_Msk instead */ 110 #define MCAN_RXBE_1_FDF_Pos 21 /**< (MCAN_RXBE_1) FD Format Position */ 111 #define MCAN_RXBE_1_FDF_Msk (_U_(0x1) << MCAN_RXBE_1_FDF_Pos) /**< (MCAN_RXBE_1) FD Format Mask */ 112 #define MCAN_RXBE_1_FDF MCAN_RXBE_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_1_FDF_Msk instead */ 113 #define MCAN_RXBE_1_FIDX_Pos 24 /**< (MCAN_RXBE_1) Filter Index Position */ 114 #define MCAN_RXBE_1_FIDX_Msk (_U_(0x7F) << MCAN_RXBE_1_FIDX_Pos) /**< (MCAN_RXBE_1) Filter Index Mask */ 115 #define MCAN_RXBE_1_FIDX(value) (MCAN_RXBE_1_FIDX_Msk & ((value) << MCAN_RXBE_1_FIDX_Pos)) 116 #define MCAN_RXBE_1_ANMF_Pos 31 /**< (MCAN_RXBE_1) Accepted Non-matching Frame Position */ 117 #define MCAN_RXBE_1_ANMF_Msk (_U_(0x1) << MCAN_RXBE_1_ANMF_Pos) /**< (MCAN_RXBE_1) Accepted Non-matching Frame Mask */ 118 #define MCAN_RXBE_1_ANMF MCAN_RXBE_1_ANMF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXBE_1_ANMF_Msk instead */ 119 #define MCAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \deprecated (MCAN_RXBE_1) Register MASK (Use MCAN_RXBE_1_Msk instead) */ 120 #define MCAN_RXBE_1_Msk _U_(0xFF3FFFFF) /**< (MCAN_RXBE_1) Register Mask */ 121 122 123 /* -------- MCAN_RXBE_DATA : (MCAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ 124 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 125 #if COMPONENT_TYPEDEF_STYLE == 'N' 126 typedef union { 127 struct { 128 uint32_t DB0:8; /**< bit: 0..7 Data Byte 0 */ 129 uint32_t DB1:8; /**< bit: 8..15 Data Byte 1 */ 130 uint32_t DB2:8; /**< bit: 16..23 Data Byte 2 */ 131 uint32_t DB3:8; /**< bit: 24..31 Data Byte 3 */ 132 } bit; /**< Structure used for bit access */ 133 uint32_t reg; /**< Type used for register access */ 134 } MCAN_RXBE_DATA_Type; 135 #endif 136 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 137 138 #define MCAN_RXBE_DATA_OFFSET (0x08) /**< (MCAN_RXBE_DATA) Rx Buffer Element Data Offset */ 139 140 #define MCAN_RXBE_DATA_DB0_Pos 0 /**< (MCAN_RXBE_DATA) Data Byte 0 Position */ 141 #define MCAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB0_Pos) /**< (MCAN_RXBE_DATA) Data Byte 0 Mask */ 142 #define MCAN_RXBE_DATA_DB0(value) (MCAN_RXBE_DATA_DB0_Msk & ((value) << MCAN_RXBE_DATA_DB0_Pos)) 143 #define MCAN_RXBE_DATA_DB1_Pos 8 /**< (MCAN_RXBE_DATA) Data Byte 1 Position */ 144 #define MCAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB1_Pos) /**< (MCAN_RXBE_DATA) Data Byte 1 Mask */ 145 #define MCAN_RXBE_DATA_DB1(value) (MCAN_RXBE_DATA_DB1_Msk & ((value) << MCAN_RXBE_DATA_DB1_Pos)) 146 #define MCAN_RXBE_DATA_DB2_Pos 16 /**< (MCAN_RXBE_DATA) Data Byte 2 Position */ 147 #define MCAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB2_Pos) /**< (MCAN_RXBE_DATA) Data Byte 2 Mask */ 148 #define MCAN_RXBE_DATA_DB2(value) (MCAN_RXBE_DATA_DB2_Msk & ((value) << MCAN_RXBE_DATA_DB2_Pos)) 149 #define MCAN_RXBE_DATA_DB3_Pos 24 /**< (MCAN_RXBE_DATA) Data Byte 3 Position */ 150 #define MCAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << MCAN_RXBE_DATA_DB3_Pos) /**< (MCAN_RXBE_DATA) Data Byte 3 Mask */ 151 #define MCAN_RXBE_DATA_DB3(value) (MCAN_RXBE_DATA_DB3_Msk & ((value) << MCAN_RXBE_DATA_DB3_Pos)) 152 #define MCAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXBE_DATA) Register MASK (Use MCAN_RXBE_DATA_Msk instead) */ 153 #define MCAN_RXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXBE_DATA) Register Mask */ 154 155 156 /* -------- MCAN_RXF0E_0 : (MCAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ 157 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 158 #if COMPONENT_TYPEDEF_STYLE == 'N' 159 typedef union { 160 struct { 161 uint32_t ID:29; /**< bit: 0..28 Identifier */ 162 uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ 163 uint32_t XTD:1; /**< bit: 30 Extended Identifier */ 164 uint32_t ESI:1; /**< bit: 31 Error State Indicator */ 165 } bit; /**< Structure used for bit access */ 166 uint32_t reg; /**< Type used for register access */ 167 } MCAN_RXF0E_0_Type; 168 #endif 169 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 170 171 #define MCAN_RXF0E_0_OFFSET (0x00) /**< (MCAN_RXF0E_0) Rx FIFO 0 Element 0 Offset */ 172 173 #define MCAN_RXF0E_0_ID_Pos 0 /**< (MCAN_RXF0E_0) Identifier Position */ 174 #define MCAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_RXF0E_0_ID_Pos) /**< (MCAN_RXF0E_0) Identifier Mask */ 175 #define MCAN_RXF0E_0_ID(value) (MCAN_RXF0E_0_ID_Msk & ((value) << MCAN_RXF0E_0_ID_Pos)) 176 #define MCAN_RXF0E_0_RTR_Pos 29 /**< (MCAN_RXF0E_0) Remote Transmission Request Position */ 177 #define MCAN_RXF0E_0_RTR_Msk (_U_(0x1) << MCAN_RXF0E_0_RTR_Pos) /**< (MCAN_RXF0E_0) Remote Transmission Request Mask */ 178 #define MCAN_RXF0E_0_RTR MCAN_RXF0E_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_0_RTR_Msk instead */ 179 #define MCAN_RXF0E_0_XTD_Pos 30 /**< (MCAN_RXF0E_0) Extended Identifier Position */ 180 #define MCAN_RXF0E_0_XTD_Msk (_U_(0x1) << MCAN_RXF0E_0_XTD_Pos) /**< (MCAN_RXF0E_0) Extended Identifier Mask */ 181 #define MCAN_RXF0E_0_XTD MCAN_RXF0E_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_0_XTD_Msk instead */ 182 #define MCAN_RXF0E_0_ESI_Pos 31 /**< (MCAN_RXF0E_0) Error State Indicator Position */ 183 #define MCAN_RXF0E_0_ESI_Msk (_U_(0x1) << MCAN_RXF0E_0_ESI_Pos) /**< (MCAN_RXF0E_0) Error State Indicator Mask */ 184 #define MCAN_RXF0E_0_ESI MCAN_RXF0E_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_0_ESI_Msk instead */ 185 #define MCAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXF0E_0) Register MASK (Use MCAN_RXF0E_0_Msk instead) */ 186 #define MCAN_RXF0E_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF0E_0) Register Mask */ 187 188 189 /* -------- MCAN_RXF0E_1 : (MCAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ 190 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 191 #if COMPONENT_TYPEDEF_STYLE == 'N' 192 typedef union { 193 struct { 194 uint32_t RXTS:16; /**< bit: 0..15 Rx Timestamp */ 195 uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ 196 uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ 197 uint32_t FDF:1; /**< bit: 21 FD Format */ 198 uint32_t :2; /**< bit: 22..23 Reserved */ 199 uint32_t FIDX:7; /**< bit: 24..30 Filter Index */ 200 uint32_t ANMF:1; /**< bit: 31 Accepted Non-matching Frame */ 201 } bit; /**< Structure used for bit access */ 202 uint32_t reg; /**< Type used for register access */ 203 } MCAN_RXF0E_1_Type; 204 #endif 205 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 206 207 #define MCAN_RXF0E_1_OFFSET (0x04) /**< (MCAN_RXF0E_1) Rx FIFO 0 Element 1 Offset */ 208 209 #define MCAN_RXF0E_1_RXTS_Pos 0 /**< (MCAN_RXF0E_1) Rx Timestamp Position */ 210 #define MCAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << MCAN_RXF0E_1_RXTS_Pos) /**< (MCAN_RXF0E_1) Rx Timestamp Mask */ 211 #define MCAN_RXF0E_1_RXTS(value) (MCAN_RXF0E_1_RXTS_Msk & ((value) << MCAN_RXF0E_1_RXTS_Pos)) 212 #define MCAN_RXF0E_1_DLC_Pos 16 /**< (MCAN_RXF0E_1) Data Length Code Position */ 213 #define MCAN_RXF0E_1_DLC_Msk (_U_(0xF) << MCAN_RXF0E_1_DLC_Pos) /**< (MCAN_RXF0E_1) Data Length Code Mask */ 214 #define MCAN_RXF0E_1_DLC(value) (MCAN_RXF0E_1_DLC_Msk & ((value) << MCAN_RXF0E_1_DLC_Pos)) 215 #define MCAN_RXF0E_1_BRS_Pos 20 /**< (MCAN_RXF0E_1) Bit Rate Switch Position */ 216 #define MCAN_RXF0E_1_BRS_Msk (_U_(0x1) << MCAN_RXF0E_1_BRS_Pos) /**< (MCAN_RXF0E_1) Bit Rate Switch Mask */ 217 #define MCAN_RXF0E_1_BRS MCAN_RXF0E_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_1_BRS_Msk instead */ 218 #define MCAN_RXF0E_1_FDF_Pos 21 /**< (MCAN_RXF0E_1) FD Format Position */ 219 #define MCAN_RXF0E_1_FDF_Msk (_U_(0x1) << MCAN_RXF0E_1_FDF_Pos) /**< (MCAN_RXF0E_1) FD Format Mask */ 220 #define MCAN_RXF0E_1_FDF MCAN_RXF0E_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_1_FDF_Msk instead */ 221 #define MCAN_RXF0E_1_FIDX_Pos 24 /**< (MCAN_RXF0E_1) Filter Index Position */ 222 #define MCAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << MCAN_RXF0E_1_FIDX_Pos) /**< (MCAN_RXF0E_1) Filter Index Mask */ 223 #define MCAN_RXF0E_1_FIDX(value) (MCAN_RXF0E_1_FIDX_Msk & ((value) << MCAN_RXF0E_1_FIDX_Pos)) 224 #define MCAN_RXF0E_1_ANMF_Pos 31 /**< (MCAN_RXF0E_1) Accepted Non-matching Frame Position */ 225 #define MCAN_RXF0E_1_ANMF_Msk (_U_(0x1) << MCAN_RXF0E_1_ANMF_Pos) /**< (MCAN_RXF0E_1) Accepted Non-matching Frame Mask */ 226 #define MCAN_RXF0E_1_ANMF MCAN_RXF0E_1_ANMF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0E_1_ANMF_Msk instead */ 227 #define MCAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \deprecated (MCAN_RXF0E_1) Register MASK (Use MCAN_RXF0E_1_Msk instead) */ 228 #define MCAN_RXF0E_1_Msk _U_(0xFF3FFFFF) /**< (MCAN_RXF0E_1) Register Mask */ 229 230 231 /* -------- MCAN_RXF0E_DATA : (MCAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ 232 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 233 #if COMPONENT_TYPEDEF_STYLE == 'N' 234 typedef union { 235 struct { 236 uint32_t DB0:8; /**< bit: 0..7 Data Byte 0 */ 237 uint32_t DB1:8; /**< bit: 8..15 Data Byte 1 */ 238 uint32_t DB2:8; /**< bit: 16..23 Data Byte 2 */ 239 uint32_t DB3:8; /**< bit: 24..31 Data Byte 3 */ 240 } bit; /**< Structure used for bit access */ 241 uint32_t reg; /**< Type used for register access */ 242 } MCAN_RXF0E_DATA_Type; 243 #endif 244 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 245 246 #define MCAN_RXF0E_DATA_OFFSET (0x08) /**< (MCAN_RXF0E_DATA) Rx FIFO 0 Element Data Offset */ 247 248 #define MCAN_RXF0E_DATA_DB0_Pos 0 /**< (MCAN_RXF0E_DATA) Data Byte 0 Position */ 249 #define MCAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB0_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 0 Mask */ 250 #define MCAN_RXF0E_DATA_DB0(value) (MCAN_RXF0E_DATA_DB0_Msk & ((value) << MCAN_RXF0E_DATA_DB0_Pos)) 251 #define MCAN_RXF0E_DATA_DB1_Pos 8 /**< (MCAN_RXF0E_DATA) Data Byte 1 Position */ 252 #define MCAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB1_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 1 Mask */ 253 #define MCAN_RXF0E_DATA_DB1(value) (MCAN_RXF0E_DATA_DB1_Msk & ((value) << MCAN_RXF0E_DATA_DB1_Pos)) 254 #define MCAN_RXF0E_DATA_DB2_Pos 16 /**< (MCAN_RXF0E_DATA) Data Byte 2 Position */ 255 #define MCAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB2_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 2 Mask */ 256 #define MCAN_RXF0E_DATA_DB2(value) (MCAN_RXF0E_DATA_DB2_Msk & ((value) << MCAN_RXF0E_DATA_DB2_Pos)) 257 #define MCAN_RXF0E_DATA_DB3_Pos 24 /**< (MCAN_RXF0E_DATA) Data Byte 3 Position */ 258 #define MCAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << MCAN_RXF0E_DATA_DB3_Pos) /**< (MCAN_RXF0E_DATA) Data Byte 3 Mask */ 259 #define MCAN_RXF0E_DATA_DB3(value) (MCAN_RXF0E_DATA_DB3_Msk & ((value) << MCAN_RXF0E_DATA_DB3_Pos)) 260 #define MCAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXF0E_DATA) Register MASK (Use MCAN_RXF0E_DATA_Msk instead) */ 261 #define MCAN_RXF0E_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF0E_DATA) Register Mask */ 262 263 264 /* -------- MCAN_RXF1E_0 : (MCAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ 265 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 266 #if COMPONENT_TYPEDEF_STYLE == 'N' 267 typedef union { 268 struct { 269 uint32_t ID:29; /**< bit: 0..28 Identifier */ 270 uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ 271 uint32_t XTD:1; /**< bit: 30 Extended Identifier */ 272 uint32_t ESI:1; /**< bit: 31 Error State Indicator */ 273 } bit; /**< Structure used for bit access */ 274 uint32_t reg; /**< Type used for register access */ 275 } MCAN_RXF1E_0_Type; 276 #endif 277 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 278 279 #define MCAN_RXF1E_0_OFFSET (0x00) /**< (MCAN_RXF1E_0) Rx FIFO 1 Element 0 Offset */ 280 281 #define MCAN_RXF1E_0_ID_Pos 0 /**< (MCAN_RXF1E_0) Identifier Position */ 282 #define MCAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_RXF1E_0_ID_Pos) /**< (MCAN_RXF1E_0) Identifier Mask */ 283 #define MCAN_RXF1E_0_ID(value) (MCAN_RXF1E_0_ID_Msk & ((value) << MCAN_RXF1E_0_ID_Pos)) 284 #define MCAN_RXF1E_0_RTR_Pos 29 /**< (MCAN_RXF1E_0) Remote Transmission Request Position */ 285 #define MCAN_RXF1E_0_RTR_Msk (_U_(0x1) << MCAN_RXF1E_0_RTR_Pos) /**< (MCAN_RXF1E_0) Remote Transmission Request Mask */ 286 #define MCAN_RXF1E_0_RTR MCAN_RXF1E_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_0_RTR_Msk instead */ 287 #define MCAN_RXF1E_0_XTD_Pos 30 /**< (MCAN_RXF1E_0) Extended Identifier Position */ 288 #define MCAN_RXF1E_0_XTD_Msk (_U_(0x1) << MCAN_RXF1E_0_XTD_Pos) /**< (MCAN_RXF1E_0) Extended Identifier Mask */ 289 #define MCAN_RXF1E_0_XTD MCAN_RXF1E_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_0_XTD_Msk instead */ 290 #define MCAN_RXF1E_0_ESI_Pos 31 /**< (MCAN_RXF1E_0) Error State Indicator Position */ 291 #define MCAN_RXF1E_0_ESI_Msk (_U_(0x1) << MCAN_RXF1E_0_ESI_Pos) /**< (MCAN_RXF1E_0) Error State Indicator Mask */ 292 #define MCAN_RXF1E_0_ESI MCAN_RXF1E_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_0_ESI_Msk instead */ 293 #define MCAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXF1E_0) Register MASK (Use MCAN_RXF1E_0_Msk instead) */ 294 #define MCAN_RXF1E_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF1E_0) Register Mask */ 295 296 297 /* -------- MCAN_RXF1E_1 : (MCAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ 298 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 299 #if COMPONENT_TYPEDEF_STYLE == 'N' 300 typedef union { 301 struct { 302 uint32_t RXTS:16; /**< bit: 0..15 Rx Timestamp */ 303 uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ 304 uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ 305 uint32_t FDF:1; /**< bit: 21 FD Format */ 306 uint32_t :2; /**< bit: 22..23 Reserved */ 307 uint32_t FIDX:7; /**< bit: 24..30 Filter Index */ 308 uint32_t ANMF:1; /**< bit: 31 Accepted Non-matching Frame */ 309 } bit; /**< Structure used for bit access */ 310 uint32_t reg; /**< Type used for register access */ 311 } MCAN_RXF1E_1_Type; 312 #endif 313 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 314 315 #define MCAN_RXF1E_1_OFFSET (0x04) /**< (MCAN_RXF1E_1) Rx FIFO 1 Element 1 Offset */ 316 317 #define MCAN_RXF1E_1_RXTS_Pos 0 /**< (MCAN_RXF1E_1) Rx Timestamp Position */ 318 #define MCAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << MCAN_RXF1E_1_RXTS_Pos) /**< (MCAN_RXF1E_1) Rx Timestamp Mask */ 319 #define MCAN_RXF1E_1_RXTS(value) (MCAN_RXF1E_1_RXTS_Msk & ((value) << MCAN_RXF1E_1_RXTS_Pos)) 320 #define MCAN_RXF1E_1_DLC_Pos 16 /**< (MCAN_RXF1E_1) Data Length Code Position */ 321 #define MCAN_RXF1E_1_DLC_Msk (_U_(0xF) << MCAN_RXF1E_1_DLC_Pos) /**< (MCAN_RXF1E_1) Data Length Code Mask */ 322 #define MCAN_RXF1E_1_DLC(value) (MCAN_RXF1E_1_DLC_Msk & ((value) << MCAN_RXF1E_1_DLC_Pos)) 323 #define MCAN_RXF1E_1_BRS_Pos 20 /**< (MCAN_RXF1E_1) Bit Rate Switch Position */ 324 #define MCAN_RXF1E_1_BRS_Msk (_U_(0x1) << MCAN_RXF1E_1_BRS_Pos) /**< (MCAN_RXF1E_1) Bit Rate Switch Mask */ 325 #define MCAN_RXF1E_1_BRS MCAN_RXF1E_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_1_BRS_Msk instead */ 326 #define MCAN_RXF1E_1_FDF_Pos 21 /**< (MCAN_RXF1E_1) FD Format Position */ 327 #define MCAN_RXF1E_1_FDF_Msk (_U_(0x1) << MCAN_RXF1E_1_FDF_Pos) /**< (MCAN_RXF1E_1) FD Format Mask */ 328 #define MCAN_RXF1E_1_FDF MCAN_RXF1E_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_1_FDF_Msk instead */ 329 #define MCAN_RXF1E_1_FIDX_Pos 24 /**< (MCAN_RXF1E_1) Filter Index Position */ 330 #define MCAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << MCAN_RXF1E_1_FIDX_Pos) /**< (MCAN_RXF1E_1) Filter Index Mask */ 331 #define MCAN_RXF1E_1_FIDX(value) (MCAN_RXF1E_1_FIDX_Msk & ((value) << MCAN_RXF1E_1_FIDX_Pos)) 332 #define MCAN_RXF1E_1_ANMF_Pos 31 /**< (MCAN_RXF1E_1) Accepted Non-matching Frame Position */ 333 #define MCAN_RXF1E_1_ANMF_Msk (_U_(0x1) << MCAN_RXF1E_1_ANMF_Pos) /**< (MCAN_RXF1E_1) Accepted Non-matching Frame Mask */ 334 #define MCAN_RXF1E_1_ANMF MCAN_RXF1E_1_ANMF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1E_1_ANMF_Msk instead */ 335 #define MCAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \deprecated (MCAN_RXF1E_1) Register MASK (Use MCAN_RXF1E_1_Msk instead) */ 336 #define MCAN_RXF1E_1_Msk _U_(0xFF3FFFFF) /**< (MCAN_RXF1E_1) Register Mask */ 337 338 339 /* -------- MCAN_RXF1E_DATA : (MCAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ 340 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 341 #if COMPONENT_TYPEDEF_STYLE == 'N' 342 typedef union { 343 struct { 344 uint32_t DB0:8; /**< bit: 0..7 Data Byte 0 */ 345 uint32_t DB1:8; /**< bit: 8..15 Data Byte 1 */ 346 uint32_t DB2:8; /**< bit: 16..23 Data Byte 2 */ 347 uint32_t DB3:8; /**< bit: 24..31 Data Byte 3 */ 348 } bit; /**< Structure used for bit access */ 349 uint32_t reg; /**< Type used for register access */ 350 } MCAN_RXF1E_DATA_Type; 351 #endif 352 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 353 354 #define MCAN_RXF1E_DATA_OFFSET (0x08) /**< (MCAN_RXF1E_DATA) Rx FIFO 1 Element Data Offset */ 355 356 #define MCAN_RXF1E_DATA_DB0_Pos 0 /**< (MCAN_RXF1E_DATA) Data Byte 0 Position */ 357 #define MCAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB0_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 0 Mask */ 358 #define MCAN_RXF1E_DATA_DB0(value) (MCAN_RXF1E_DATA_DB0_Msk & ((value) << MCAN_RXF1E_DATA_DB0_Pos)) 359 #define MCAN_RXF1E_DATA_DB1_Pos 8 /**< (MCAN_RXF1E_DATA) Data Byte 1 Position */ 360 #define MCAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB1_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 1 Mask */ 361 #define MCAN_RXF1E_DATA_DB1(value) (MCAN_RXF1E_DATA_DB1_Msk & ((value) << MCAN_RXF1E_DATA_DB1_Pos)) 362 #define MCAN_RXF1E_DATA_DB2_Pos 16 /**< (MCAN_RXF1E_DATA) Data Byte 2 Position */ 363 #define MCAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB2_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 2 Mask */ 364 #define MCAN_RXF1E_DATA_DB2(value) (MCAN_RXF1E_DATA_DB2_Msk & ((value) << MCAN_RXF1E_DATA_DB2_Pos)) 365 #define MCAN_RXF1E_DATA_DB3_Pos 24 /**< (MCAN_RXF1E_DATA) Data Byte 3 Position */ 366 #define MCAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << MCAN_RXF1E_DATA_DB3_Pos) /**< (MCAN_RXF1E_DATA) Data Byte 3 Mask */ 367 #define MCAN_RXF1E_DATA_DB3(value) (MCAN_RXF1E_DATA_DB3_Msk & ((value) << MCAN_RXF1E_DATA_DB3_Pos)) 368 #define MCAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_RXF1E_DATA) Register MASK (Use MCAN_RXF1E_DATA_Msk instead) */ 369 #define MCAN_RXF1E_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_RXF1E_DATA) Register Mask */ 370 371 372 /* -------- MCAN_TXBE_0 : (MCAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ 373 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 374 #if COMPONENT_TYPEDEF_STYLE == 'N' 375 typedef union { 376 struct { 377 uint32_t ID:29; /**< bit: 0..28 Identifier */ 378 uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ 379 uint32_t XTD:1; /**< bit: 30 Extended Identifier */ 380 uint32_t ESI:1; /**< bit: 31 Error State Indicator */ 381 } bit; /**< Structure used for bit access */ 382 uint32_t reg; /**< Type used for register access */ 383 } MCAN_TXBE_0_Type; 384 #endif 385 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 386 387 #define MCAN_TXBE_0_OFFSET (0x00) /**< (MCAN_TXBE_0) Tx Buffer Element 0 Offset */ 388 389 #define MCAN_TXBE_0_ID_Pos 0 /**< (MCAN_TXBE_0) Identifier Position */ 390 #define MCAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_TXBE_0_ID_Pos) /**< (MCAN_TXBE_0) Identifier Mask */ 391 #define MCAN_TXBE_0_ID(value) (MCAN_TXBE_0_ID_Msk & ((value) << MCAN_TXBE_0_ID_Pos)) 392 #define MCAN_TXBE_0_RTR_Pos 29 /**< (MCAN_TXBE_0) Remote Transmission Request Position */ 393 #define MCAN_TXBE_0_RTR_Msk (_U_(0x1) << MCAN_TXBE_0_RTR_Pos) /**< (MCAN_TXBE_0) Remote Transmission Request Mask */ 394 #define MCAN_TXBE_0_RTR MCAN_TXBE_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_0_RTR_Msk instead */ 395 #define MCAN_TXBE_0_XTD_Pos 30 /**< (MCAN_TXBE_0) Extended Identifier Position */ 396 #define MCAN_TXBE_0_XTD_Msk (_U_(0x1) << MCAN_TXBE_0_XTD_Pos) /**< (MCAN_TXBE_0) Extended Identifier Mask */ 397 #define MCAN_TXBE_0_XTD MCAN_TXBE_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_0_XTD_Msk instead */ 398 #define MCAN_TXBE_0_ESI_Pos 31 /**< (MCAN_TXBE_0) Error State Indicator Position */ 399 #define MCAN_TXBE_0_ESI_Msk (_U_(0x1) << MCAN_TXBE_0_ESI_Pos) /**< (MCAN_TXBE_0) Error State Indicator Mask */ 400 #define MCAN_TXBE_0_ESI MCAN_TXBE_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_0_ESI_Msk instead */ 401 #define MCAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBE_0) Register MASK (Use MCAN_TXBE_0_Msk instead) */ 402 #define MCAN_TXBE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBE_0) Register Mask */ 403 404 405 /* -------- MCAN_TXBE_1 : (MCAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ 406 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 407 #if COMPONENT_TYPEDEF_STYLE == 'N' 408 typedef union { 409 struct { 410 uint32_t :16; /**< bit: 0..15 Reserved */ 411 uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ 412 uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ 413 uint32_t FDF:1; /**< bit: 21 FD Format */ 414 uint32_t :1; /**< bit: 22 Reserved */ 415 uint32_t EFC:1; /**< bit: 23 Event FIFO Control */ 416 uint32_t MM:8; /**< bit: 24..31 Message Marker */ 417 } bit; /**< Structure used for bit access */ 418 uint32_t reg; /**< Type used for register access */ 419 } MCAN_TXBE_1_Type; 420 #endif 421 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 422 423 #define MCAN_TXBE_1_OFFSET (0x04) /**< (MCAN_TXBE_1) Tx Buffer Element 1 Offset */ 424 425 #define MCAN_TXBE_1_DLC_Pos 16 /**< (MCAN_TXBE_1) Data Length Code Position */ 426 #define MCAN_TXBE_1_DLC_Msk (_U_(0xF) << MCAN_TXBE_1_DLC_Pos) /**< (MCAN_TXBE_1) Data Length Code Mask */ 427 #define MCAN_TXBE_1_DLC(value) (MCAN_TXBE_1_DLC_Msk & ((value) << MCAN_TXBE_1_DLC_Pos)) 428 #define MCAN_TXBE_1_BRS_Pos 20 /**< (MCAN_TXBE_1) Bit Rate Switch Position */ 429 #define MCAN_TXBE_1_BRS_Msk (_U_(0x1) << MCAN_TXBE_1_BRS_Pos) /**< (MCAN_TXBE_1) Bit Rate Switch Mask */ 430 #define MCAN_TXBE_1_BRS MCAN_TXBE_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_1_BRS_Msk instead */ 431 #define MCAN_TXBE_1_FDF_Pos 21 /**< (MCAN_TXBE_1) FD Format Position */ 432 #define MCAN_TXBE_1_FDF_Msk (_U_(0x1) << MCAN_TXBE_1_FDF_Pos) /**< (MCAN_TXBE_1) FD Format Mask */ 433 #define MCAN_TXBE_1_FDF MCAN_TXBE_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_1_FDF_Msk instead */ 434 #define MCAN_TXBE_1_EFC_Pos 23 /**< (MCAN_TXBE_1) Event FIFO Control Position */ 435 #define MCAN_TXBE_1_EFC_Msk (_U_(0x1) << MCAN_TXBE_1_EFC_Pos) /**< (MCAN_TXBE_1) Event FIFO Control Mask */ 436 #define MCAN_TXBE_1_EFC MCAN_TXBE_1_EFC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBE_1_EFC_Msk instead */ 437 #define MCAN_TXBE_1_MM_Pos 24 /**< (MCAN_TXBE_1) Message Marker Position */ 438 #define MCAN_TXBE_1_MM_Msk (_U_(0xFF) << MCAN_TXBE_1_MM_Pos) /**< (MCAN_TXBE_1) Message Marker Mask */ 439 #define MCAN_TXBE_1_MM(value) (MCAN_TXBE_1_MM_Msk & ((value) << MCAN_TXBE_1_MM_Pos)) 440 #define MCAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \deprecated (MCAN_TXBE_1) Register MASK (Use MCAN_TXBE_1_Msk instead) */ 441 #define MCAN_TXBE_1_Msk _U_(0xFFBF0000) /**< (MCAN_TXBE_1) Register Mask */ 442 443 444 /* -------- MCAN_TXBE_DATA : (MCAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ 445 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 446 #if COMPONENT_TYPEDEF_STYLE == 'N' 447 typedef union { 448 struct { 449 uint32_t DB0:8; /**< bit: 0..7 Data Byte 0 */ 450 uint32_t DB1:8; /**< bit: 8..15 Data Byte 1 */ 451 uint32_t DB2:8; /**< bit: 16..23 Data Byte 2 */ 452 uint32_t DB3:8; /**< bit: 24..31 Data Byte 3 */ 453 } bit; /**< Structure used for bit access */ 454 uint32_t reg; /**< Type used for register access */ 455 } MCAN_TXBE_DATA_Type; 456 #endif 457 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 458 459 #define MCAN_TXBE_DATA_OFFSET (0x08) /**< (MCAN_TXBE_DATA) Tx Buffer Element Data Offset */ 460 461 #define MCAN_TXBE_DATA_DB0_Pos 0 /**< (MCAN_TXBE_DATA) Data Byte 0 Position */ 462 #define MCAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB0_Pos) /**< (MCAN_TXBE_DATA) Data Byte 0 Mask */ 463 #define MCAN_TXBE_DATA_DB0(value) (MCAN_TXBE_DATA_DB0_Msk & ((value) << MCAN_TXBE_DATA_DB0_Pos)) 464 #define MCAN_TXBE_DATA_DB1_Pos 8 /**< (MCAN_TXBE_DATA) Data Byte 1 Position */ 465 #define MCAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB1_Pos) /**< (MCAN_TXBE_DATA) Data Byte 1 Mask */ 466 #define MCAN_TXBE_DATA_DB1(value) (MCAN_TXBE_DATA_DB1_Msk & ((value) << MCAN_TXBE_DATA_DB1_Pos)) 467 #define MCAN_TXBE_DATA_DB2_Pos 16 /**< (MCAN_TXBE_DATA) Data Byte 2 Position */ 468 #define MCAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB2_Pos) /**< (MCAN_TXBE_DATA) Data Byte 2 Mask */ 469 #define MCAN_TXBE_DATA_DB2(value) (MCAN_TXBE_DATA_DB2_Msk & ((value) << MCAN_TXBE_DATA_DB2_Pos)) 470 #define MCAN_TXBE_DATA_DB3_Pos 24 /**< (MCAN_TXBE_DATA) Data Byte 3 Position */ 471 #define MCAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << MCAN_TXBE_DATA_DB3_Pos) /**< (MCAN_TXBE_DATA) Data Byte 3 Mask */ 472 #define MCAN_TXBE_DATA_DB3(value) (MCAN_TXBE_DATA_DB3_Msk & ((value) << MCAN_TXBE_DATA_DB3_Pos)) 473 #define MCAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBE_DATA) Register MASK (Use MCAN_TXBE_DATA_Msk instead) */ 474 #define MCAN_TXBE_DATA_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBE_DATA) Register Mask */ 475 476 477 /* -------- MCAN_TXEFE_0 : (MCAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ 478 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 479 #if COMPONENT_TYPEDEF_STYLE == 'N' 480 typedef union { 481 struct { 482 uint32_t ID:29; /**< bit: 0..28 Identifier */ 483 uint32_t RTR:1; /**< bit: 29 Remote Transmission Request */ 484 uint32_t XTD:1; /**< bit: 30 Extended Identifier */ 485 uint32_t ESI:1; /**< bit: 31 Error State Indicator */ 486 } bit; /**< Structure used for bit access */ 487 uint32_t reg; /**< Type used for register access */ 488 } MCAN_TXEFE_0_Type; 489 #endif 490 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 491 492 #define MCAN_TXEFE_0_OFFSET (0x00) /**< (MCAN_TXEFE_0) Tx Event FIFO Element 0 Offset */ 493 494 #define MCAN_TXEFE_0_ID_Pos 0 /**< (MCAN_TXEFE_0) Identifier Position */ 495 #define MCAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << MCAN_TXEFE_0_ID_Pos) /**< (MCAN_TXEFE_0) Identifier Mask */ 496 #define MCAN_TXEFE_0_ID(value) (MCAN_TXEFE_0_ID_Msk & ((value) << MCAN_TXEFE_0_ID_Pos)) 497 #define MCAN_TXEFE_0_RTR_Pos 29 /**< (MCAN_TXEFE_0) Remote Transmission Request Position */ 498 #define MCAN_TXEFE_0_RTR_Msk (_U_(0x1) << MCAN_TXEFE_0_RTR_Pos) /**< (MCAN_TXEFE_0) Remote Transmission Request Mask */ 499 #define MCAN_TXEFE_0_RTR MCAN_TXEFE_0_RTR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_0_RTR_Msk instead */ 500 #define MCAN_TXEFE_0_XTD_Pos 30 /**< (MCAN_TXEFE_0) Extended Identifier Position */ 501 #define MCAN_TXEFE_0_XTD_Msk (_U_(0x1) << MCAN_TXEFE_0_XTD_Pos) /**< (MCAN_TXEFE_0) Extended Identifier Mask */ 502 #define MCAN_TXEFE_0_XTD MCAN_TXEFE_0_XTD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_0_XTD_Msk instead */ 503 #define MCAN_TXEFE_0_ESI_Pos 31 /**< (MCAN_TXEFE_0) Error State Indicator Position */ 504 #define MCAN_TXEFE_0_ESI_Msk (_U_(0x1) << MCAN_TXEFE_0_ESI_Pos) /**< (MCAN_TXEFE_0) Error State Indicator Mask */ 505 #define MCAN_TXEFE_0_ESI MCAN_TXEFE_0_ESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_0_ESI_Msk instead */ 506 #define MCAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXEFE_0) Register MASK (Use MCAN_TXEFE_0_Msk instead) */ 507 #define MCAN_TXEFE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXEFE_0) Register Mask */ 508 509 510 /* -------- MCAN_TXEFE_1 : (MCAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ 511 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 512 #if COMPONENT_TYPEDEF_STYLE == 'N' 513 typedef union { 514 struct { 515 uint32_t TXTS:16; /**< bit: 0..15 Tx Timestamp */ 516 uint32_t DLC:4; /**< bit: 16..19 Data Length Code */ 517 uint32_t BRS:1; /**< bit: 20 Bit Rate Switch */ 518 uint32_t FDF:1; /**< bit: 21 FD Format */ 519 uint32_t ET:2; /**< bit: 22..23 Event Type */ 520 uint32_t MM:8; /**< bit: 24..31 Message Marker */ 521 } bit; /**< Structure used for bit access */ 522 uint32_t reg; /**< Type used for register access */ 523 } MCAN_TXEFE_1_Type; 524 #endif 525 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 526 527 #define MCAN_TXEFE_1_OFFSET (0x04) /**< (MCAN_TXEFE_1) Tx Event FIFO Element 1 Offset */ 528 529 #define MCAN_TXEFE_1_TXTS_Pos 0 /**< (MCAN_TXEFE_1) Tx Timestamp Position */ 530 #define MCAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << MCAN_TXEFE_1_TXTS_Pos) /**< (MCAN_TXEFE_1) Tx Timestamp Mask */ 531 #define MCAN_TXEFE_1_TXTS(value) (MCAN_TXEFE_1_TXTS_Msk & ((value) << MCAN_TXEFE_1_TXTS_Pos)) 532 #define MCAN_TXEFE_1_DLC_Pos 16 /**< (MCAN_TXEFE_1) Data Length Code Position */ 533 #define MCAN_TXEFE_1_DLC_Msk (_U_(0xF) << MCAN_TXEFE_1_DLC_Pos) /**< (MCAN_TXEFE_1) Data Length Code Mask */ 534 #define MCAN_TXEFE_1_DLC(value) (MCAN_TXEFE_1_DLC_Msk & ((value) << MCAN_TXEFE_1_DLC_Pos)) 535 #define MCAN_TXEFE_1_BRS_Pos 20 /**< (MCAN_TXEFE_1) Bit Rate Switch Position */ 536 #define MCAN_TXEFE_1_BRS_Msk (_U_(0x1) << MCAN_TXEFE_1_BRS_Pos) /**< (MCAN_TXEFE_1) Bit Rate Switch Mask */ 537 #define MCAN_TXEFE_1_BRS MCAN_TXEFE_1_BRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_1_BRS_Msk instead */ 538 #define MCAN_TXEFE_1_FDF_Pos 21 /**< (MCAN_TXEFE_1) FD Format Position */ 539 #define MCAN_TXEFE_1_FDF_Msk (_U_(0x1) << MCAN_TXEFE_1_FDF_Pos) /**< (MCAN_TXEFE_1) FD Format Mask */ 540 #define MCAN_TXEFE_1_FDF MCAN_TXEFE_1_FDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFE_1_FDF_Msk instead */ 541 #define MCAN_TXEFE_1_ET_Pos 22 /**< (MCAN_TXEFE_1) Event Type Position */ 542 #define MCAN_TXEFE_1_ET_Msk (_U_(0x3) << MCAN_TXEFE_1_ET_Pos) /**< (MCAN_TXEFE_1) Event Type Mask */ 543 #define MCAN_TXEFE_1_ET(value) (MCAN_TXEFE_1_ET_Msk & ((value) << MCAN_TXEFE_1_ET_Pos)) 544 #define MCAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< (MCAN_TXEFE_1) Tx event */ 545 #define MCAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< (MCAN_TXEFE_1) Transmission in spite of cancellation */ 546 #define MCAN_TXEFE_1_ET_TXE (MCAN_TXEFE_1_ET_TXE_Val << MCAN_TXEFE_1_ET_Pos) /**< (MCAN_TXEFE_1) Tx event Position */ 547 #define MCAN_TXEFE_1_ET_TXC (MCAN_TXEFE_1_ET_TXC_Val << MCAN_TXEFE_1_ET_Pos) /**< (MCAN_TXEFE_1) Transmission in spite of cancellation Position */ 548 #define MCAN_TXEFE_1_MM_Pos 24 /**< (MCAN_TXEFE_1) Message Marker Position */ 549 #define MCAN_TXEFE_1_MM_Msk (_U_(0xFF) << MCAN_TXEFE_1_MM_Pos) /**< (MCAN_TXEFE_1) Message Marker Mask */ 550 #define MCAN_TXEFE_1_MM(value) (MCAN_TXEFE_1_MM_Msk & ((value) << MCAN_TXEFE_1_MM_Pos)) 551 #define MCAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXEFE_1) Register MASK (Use MCAN_TXEFE_1_Msk instead) */ 552 #define MCAN_TXEFE_1_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXEFE_1) Register Mask */ 553 554 555 /* -------- MCAN_SIDFE_0 : (MCAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element 0 -------- */ 556 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 557 #if COMPONENT_TYPEDEF_STYLE == 'N' 558 typedef union { 559 struct { 560 uint32_t SFID2:11; /**< bit: 0..10 Standard Filter ID 2 */ 561 uint32_t :5; /**< bit: 11..15 Reserved */ 562 uint32_t SFID1:11; /**< bit: 16..26 Standard Filter ID 1 */ 563 uint32_t SFEC:3; /**< bit: 27..29 Standard Filter Element Configuration */ 564 uint32_t SFT:2; /**< bit: 30..31 Standard Filter Type */ 565 } bit; /**< Structure used for bit access */ 566 uint32_t reg; /**< Type used for register access */ 567 } MCAN_SIDFE_0_Type; 568 #endif 569 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 570 571 #define MCAN_SIDFE_0_OFFSET (0x00) /**< (MCAN_SIDFE_0) Standard Message ID Filter Element 0 Offset */ 572 573 #define MCAN_SIDFE_0_SFID2_Pos 0 /**< (MCAN_SIDFE_0) Standard Filter ID 2 Position */ 574 #define MCAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << MCAN_SIDFE_0_SFID2_Pos) /**< (MCAN_SIDFE_0) Standard Filter ID 2 Mask */ 575 #define MCAN_SIDFE_0_SFID2(value) (MCAN_SIDFE_0_SFID2_Msk & ((value) << MCAN_SIDFE_0_SFID2_Pos)) 576 #define MCAN_SIDFE_0_SFID1_Pos 16 /**< (MCAN_SIDFE_0) Standard Filter ID 1 Position */ 577 #define MCAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << MCAN_SIDFE_0_SFID1_Pos) /**< (MCAN_SIDFE_0) Standard Filter ID 1 Mask */ 578 #define MCAN_SIDFE_0_SFID1(value) (MCAN_SIDFE_0_SFID1_Msk & ((value) << MCAN_SIDFE_0_SFID1_Pos)) 579 #define MCAN_SIDFE_0_SFEC_Pos 27 /**< (MCAN_SIDFE_0) Standard Filter Element Configuration Position */ 580 #define MCAN_SIDFE_0_SFEC_Msk (_U_(0x7) << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Standard Filter Element Configuration Mask */ 581 #define MCAN_SIDFE_0_SFEC(value) (MCAN_SIDFE_0_SFEC_Msk & ((value) << MCAN_SIDFE_0_SFEC_Pos)) 582 #define MCAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< (MCAN_SIDFE_0) Disable filter element */ 583 #define MCAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< (MCAN_SIDFE_0) Store in Rx FIFO 0 if filter matches */ 584 #define MCAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< (MCAN_SIDFE_0) Store in Rx FIFO 1 if filter matches */ 585 #define MCAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< (MCAN_SIDFE_0) Reject ID if filter matches */ 586 #define MCAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< (MCAN_SIDFE_0) Set priority if filter matches */ 587 #define MCAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 0 if filter matches */ 588 #define MCAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 1 if filter matches */ 589 #define MCAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< (MCAN_SIDFE_0) Store into Rx Buffer */ 590 #define MCAN_SIDFE_0_SFEC_DISABLE (MCAN_SIDFE_0_SFEC_DISABLE_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Disable filter element Position */ 591 #define MCAN_SIDFE_0_SFEC_STF0M (MCAN_SIDFE_0_SFEC_STF0M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Store in Rx FIFO 0 if filter matches Position */ 592 #define MCAN_SIDFE_0_SFEC_STF1M (MCAN_SIDFE_0_SFEC_STF1M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Store in Rx FIFO 1 if filter matches Position */ 593 #define MCAN_SIDFE_0_SFEC_REJECT (MCAN_SIDFE_0_SFEC_REJECT_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Reject ID if filter matches Position */ 594 #define MCAN_SIDFE_0_SFEC_PRIORITY (MCAN_SIDFE_0_SFEC_PRIORITY_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Set priority if filter matches Position */ 595 #define MCAN_SIDFE_0_SFEC_PRIF0M (MCAN_SIDFE_0_SFEC_PRIF0M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 0 if filter matches Position */ 596 #define MCAN_SIDFE_0_SFEC_PRIF1M (MCAN_SIDFE_0_SFEC_PRIF1M_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Set priority and store in FIFO 1 if filter matches Position */ 597 #define MCAN_SIDFE_0_SFEC_STRXBUF (MCAN_SIDFE_0_SFEC_STRXBUF_Val << MCAN_SIDFE_0_SFEC_Pos) /**< (MCAN_SIDFE_0) Store into Rx Buffer Position */ 598 #define MCAN_SIDFE_0_SFT_Pos 30 /**< (MCAN_SIDFE_0) Standard Filter Type Position */ 599 #define MCAN_SIDFE_0_SFT_Msk (_U_(0x3) << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Standard Filter Type Mask */ 600 #define MCAN_SIDFE_0_SFT(value) (MCAN_SIDFE_0_SFT_Msk & ((value) << MCAN_SIDFE_0_SFT_Pos)) 601 #define MCAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< (MCAN_SIDFE_0) Range filter from SFID1 to SFID2 */ 602 #define MCAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< (MCAN_SIDFE_0) Dual ID filter for SF1ID or SF2ID */ 603 #define MCAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< (MCAN_SIDFE_0) Classic filter */ 604 #define MCAN_SIDFE_0_SFT_RANGE (MCAN_SIDFE_0_SFT_RANGE_Val << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Range filter from SFID1 to SFID2 Position */ 605 #define MCAN_SIDFE_0_SFT_DUAL (MCAN_SIDFE_0_SFT_DUAL_Val << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Dual ID filter for SF1ID or SF2ID Position */ 606 #define MCAN_SIDFE_0_SFT_CLASSIC (MCAN_SIDFE_0_SFT_CLASSIC_Val << MCAN_SIDFE_0_SFT_Pos) /**< (MCAN_SIDFE_0) Classic filter Position */ 607 #define MCAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \deprecated (MCAN_SIDFE_0) Register MASK (Use MCAN_SIDFE_0_Msk instead) */ 608 #define MCAN_SIDFE_0_Msk _U_(0xFFFF07FF) /**< (MCAN_SIDFE_0) Register Mask */ 609 610 611 /* -------- MCAN_XIDFE_0 : (MCAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ 612 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 613 #if COMPONENT_TYPEDEF_STYLE == 'N' 614 typedef union { 615 struct { 616 uint32_t EFID1:29; /**< bit: 0..28 Extended Filter ID 1 */ 617 uint32_t EFEC:3; /**< bit: 29..31 Extended Filter Element Configuration */ 618 } bit; /**< Structure used for bit access */ 619 uint32_t reg; /**< Type used for register access */ 620 } MCAN_XIDFE_0_Type; 621 #endif 622 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 623 624 #define MCAN_XIDFE_0_OFFSET (0x00) /**< (MCAN_XIDFE_0) Extended Message ID Filter Element 0 Offset */ 625 626 #define MCAN_XIDFE_0_EFID1_Pos 0 /**< (MCAN_XIDFE_0) Extended Filter ID 1 Position */ 627 #define MCAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << MCAN_XIDFE_0_EFID1_Pos) /**< (MCAN_XIDFE_0) Extended Filter ID 1 Mask */ 628 #define MCAN_XIDFE_0_EFID1(value) (MCAN_XIDFE_0_EFID1_Msk & ((value) << MCAN_XIDFE_0_EFID1_Pos)) 629 #define MCAN_XIDFE_0_EFEC_Pos 29 /**< (MCAN_XIDFE_0) Extended Filter Element Configuration Position */ 630 #define MCAN_XIDFE_0_EFEC_Msk (_U_(0x7) << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Extended Filter Element Configuration Mask */ 631 #define MCAN_XIDFE_0_EFEC(value) (MCAN_XIDFE_0_EFEC_Msk & ((value) << MCAN_XIDFE_0_EFEC_Pos)) 632 #define MCAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< (MCAN_XIDFE_0) Disable filter element */ 633 #define MCAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< (MCAN_XIDFE_0) Store in Rx FIFO 0 if filter matches */ 634 #define MCAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< (MCAN_XIDFE_0) Store in Rx FIFO 1 if filter matches */ 635 #define MCAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< (MCAN_XIDFE_0) Reject ID if filter matches */ 636 #define MCAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< (MCAN_XIDFE_0) Set priority if filter matches */ 637 #define MCAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 0 if filter matches */ 638 #define MCAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 1 if filter matches */ 639 #define MCAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< (MCAN_XIDFE_0) Store into Rx Buffer */ 640 #define MCAN_XIDFE_0_EFEC_DISABLE (MCAN_XIDFE_0_EFEC_DISABLE_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Disable filter element Position */ 641 #define MCAN_XIDFE_0_EFEC_STF0M (MCAN_XIDFE_0_EFEC_STF0M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Store in Rx FIFO 0 if filter matches Position */ 642 #define MCAN_XIDFE_0_EFEC_STF1M (MCAN_XIDFE_0_EFEC_STF1M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Store in Rx FIFO 1 if filter matches Position */ 643 #define MCAN_XIDFE_0_EFEC_REJECT (MCAN_XIDFE_0_EFEC_REJECT_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Reject ID if filter matches Position */ 644 #define MCAN_XIDFE_0_EFEC_PRIORITY (MCAN_XIDFE_0_EFEC_PRIORITY_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Set priority if filter matches Position */ 645 #define MCAN_XIDFE_0_EFEC_PRIF0M (MCAN_XIDFE_0_EFEC_PRIF0M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 0 if filter matches Position */ 646 #define MCAN_XIDFE_0_EFEC_PRIF1M (MCAN_XIDFE_0_EFEC_PRIF1M_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Set priority and store in FIFO 1 if filter matches Position */ 647 #define MCAN_XIDFE_0_EFEC_STRXBUF (MCAN_XIDFE_0_EFEC_STRXBUF_Val << MCAN_XIDFE_0_EFEC_Pos) /**< (MCAN_XIDFE_0) Store into Rx Buffer Position */ 648 #define MCAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_XIDFE_0) Register MASK (Use MCAN_XIDFE_0_Msk instead) */ 649 #define MCAN_XIDFE_0_Msk _U_(0xFFFFFFFF) /**< (MCAN_XIDFE_0) Register Mask */ 650 651 652 /* -------- MCAN_XIDFE_1 : (MCAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ 653 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 654 #if COMPONENT_TYPEDEF_STYLE == 'N' 655 typedef union { 656 struct { 657 uint32_t EFID2:29; /**< bit: 0..28 Extended Filter ID 2 */ 658 uint32_t :1; /**< bit: 29 Reserved */ 659 uint32_t EFT:2; /**< bit: 30..31 Extended Filter Type */ 660 } bit; /**< Structure used for bit access */ 661 uint32_t reg; /**< Type used for register access */ 662 } MCAN_XIDFE_1_Type; 663 #endif 664 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 665 666 #define MCAN_XIDFE_1_OFFSET (0x04) /**< (MCAN_XIDFE_1) Extended Message ID Filter Element 1 Offset */ 667 668 #define MCAN_XIDFE_1_EFID2_Pos 0 /**< (MCAN_XIDFE_1) Extended Filter ID 2 Position */ 669 #define MCAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << MCAN_XIDFE_1_EFID2_Pos) /**< (MCAN_XIDFE_1) Extended Filter ID 2 Mask */ 670 #define MCAN_XIDFE_1_EFID2(value) (MCAN_XIDFE_1_EFID2_Msk & ((value) << MCAN_XIDFE_1_EFID2_Pos)) 671 #define MCAN_XIDFE_1_EFT_Pos 30 /**< (MCAN_XIDFE_1) Extended Filter Type Position */ 672 #define MCAN_XIDFE_1_EFT_Msk (_U_(0x3) << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Extended Filter Type Mask */ 673 #define MCAN_XIDFE_1_EFT(value) (MCAN_XIDFE_1_EFT_Msk & ((value) << MCAN_XIDFE_1_EFT_Pos)) 674 #define MCAN_XIDFE_1_EFT_RANGE_Val _U_(0x0) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 */ 675 #define MCAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< (MCAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ 676 #define MCAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< (MCAN_XIDFE_1) Classic filter */ 677 #define MCAN_XIDFE_1_EFT_RANGE_NO_XIDAM_Val _U_(0x3) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ 678 #define MCAN_XIDFE_1_EFT_RANGE (MCAN_XIDFE_1_EFT_RANGE_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 Position */ 679 #define MCAN_XIDFE_1_EFT_DUAL (MCAN_XIDFE_1_EFT_DUAL_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 Position */ 680 #define MCAN_XIDFE_1_EFT_CLASSIC (MCAN_XIDFE_1_EFT_CLASSIC_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Classic filter Position */ 681 #define MCAN_XIDFE_1_EFT_RANGE_NO_XIDAM (MCAN_XIDFE_1_EFT_RANGE_NO_XIDAM_Val << MCAN_XIDFE_1_EFT_Pos) /**< (MCAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask Position */ 682 #define MCAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \deprecated (MCAN_XIDFE_1) Register MASK (Use MCAN_XIDFE_1_Msk instead) */ 683 #define MCAN_XIDFE_1_Msk _U_(0xDFFFFFFF) /**< (MCAN_XIDFE_1) Register Mask */ 684 685 686 /* -------- MCAN_CREL : (MCAN Offset: 0x00) (R/ 32) Core Release Register -------- */ 687 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 688 #if COMPONENT_TYPEDEF_STYLE == 'N' 689 typedef union { 690 struct { 691 uint32_t DAY:8; /**< bit: 0..7 Timestamp Day */ 692 uint32_t MON:8; /**< bit: 8..15 Timestamp Month */ 693 uint32_t YEAR:4; /**< bit: 16..19 Timestamp Year */ 694 uint32_t SUBSTEP:4; /**< bit: 20..23 Sub-step of Core Release */ 695 uint32_t STEP:4; /**< bit: 24..27 Step of Core Release */ 696 uint32_t REL:4; /**< bit: 28..31 Core Release */ 697 } bit; /**< Structure used for bit access */ 698 uint32_t reg; /**< Type used for register access */ 699 } MCAN_CREL_Type; 700 #endif 701 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 702 703 #define MCAN_CREL_OFFSET (0x00) /**< (MCAN_CREL) Core Release Register Offset */ 704 705 #define MCAN_CREL_DAY_Pos 0 /**< (MCAN_CREL) Timestamp Day Position */ 706 #define MCAN_CREL_DAY_Msk (_U_(0xFF) << MCAN_CREL_DAY_Pos) /**< (MCAN_CREL) Timestamp Day Mask */ 707 #define MCAN_CREL_DAY(value) (MCAN_CREL_DAY_Msk & ((value) << MCAN_CREL_DAY_Pos)) 708 #define MCAN_CREL_MON_Pos 8 /**< (MCAN_CREL) Timestamp Month Position */ 709 #define MCAN_CREL_MON_Msk (_U_(0xFF) << MCAN_CREL_MON_Pos) /**< (MCAN_CREL) Timestamp Month Mask */ 710 #define MCAN_CREL_MON(value) (MCAN_CREL_MON_Msk & ((value) << MCAN_CREL_MON_Pos)) 711 #define MCAN_CREL_YEAR_Pos 16 /**< (MCAN_CREL) Timestamp Year Position */ 712 #define MCAN_CREL_YEAR_Msk (_U_(0xF) << MCAN_CREL_YEAR_Pos) /**< (MCAN_CREL) Timestamp Year Mask */ 713 #define MCAN_CREL_YEAR(value) (MCAN_CREL_YEAR_Msk & ((value) << MCAN_CREL_YEAR_Pos)) 714 #define MCAN_CREL_SUBSTEP_Pos 20 /**< (MCAN_CREL) Sub-step of Core Release Position */ 715 #define MCAN_CREL_SUBSTEP_Msk (_U_(0xF) << MCAN_CREL_SUBSTEP_Pos) /**< (MCAN_CREL) Sub-step of Core Release Mask */ 716 #define MCAN_CREL_SUBSTEP(value) (MCAN_CREL_SUBSTEP_Msk & ((value) << MCAN_CREL_SUBSTEP_Pos)) 717 #define MCAN_CREL_STEP_Pos 24 /**< (MCAN_CREL) Step of Core Release Position */ 718 #define MCAN_CREL_STEP_Msk (_U_(0xF) << MCAN_CREL_STEP_Pos) /**< (MCAN_CREL) Step of Core Release Mask */ 719 #define MCAN_CREL_STEP(value) (MCAN_CREL_STEP_Msk & ((value) << MCAN_CREL_STEP_Pos)) 720 #define MCAN_CREL_REL_Pos 28 /**< (MCAN_CREL) Core Release Position */ 721 #define MCAN_CREL_REL_Msk (_U_(0xF) << MCAN_CREL_REL_Pos) /**< (MCAN_CREL) Core Release Mask */ 722 #define MCAN_CREL_REL(value) (MCAN_CREL_REL_Msk & ((value) << MCAN_CREL_REL_Pos)) 723 #define MCAN_CREL_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_CREL) Register MASK (Use MCAN_CREL_Msk instead) */ 724 #define MCAN_CREL_Msk _U_(0xFFFFFFFF) /**< (MCAN_CREL) Register Mask */ 725 726 727 /* -------- MCAN_ENDN : (MCAN Offset: 0x04) (R/ 32) Endian Register -------- */ 728 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 729 #if COMPONENT_TYPEDEF_STYLE == 'N' 730 typedef union { 731 struct { 732 uint32_t ETV:32; /**< bit: 0..31 Endianness Test Value */ 733 } bit; /**< Structure used for bit access */ 734 uint32_t reg; /**< Type used for register access */ 735 } MCAN_ENDN_Type; 736 #endif 737 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 738 739 #define MCAN_ENDN_OFFSET (0x04) /**< (MCAN_ENDN) Endian Register Offset */ 740 741 #define MCAN_ENDN_ETV_Pos 0 /**< (MCAN_ENDN) Endianness Test Value Position */ 742 #define MCAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << MCAN_ENDN_ETV_Pos) /**< (MCAN_ENDN) Endianness Test Value Mask */ 743 #define MCAN_ENDN_ETV(value) (MCAN_ENDN_ETV_Msk & ((value) << MCAN_ENDN_ETV_Pos)) 744 #define MCAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_ENDN) Register MASK (Use MCAN_ENDN_Msk instead) */ 745 #define MCAN_ENDN_Msk _U_(0xFFFFFFFF) /**< (MCAN_ENDN) Register Mask */ 746 747 748 /* -------- MCAN_CUST : (MCAN Offset: 0x08) (R/W 32) Customer Register -------- */ 749 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 750 #if COMPONENT_TYPEDEF_STYLE == 'N' 751 typedef union { 752 struct { 753 uint32_t CSV:32; /**< bit: 0..31 Customer-specific Value */ 754 } bit; /**< Structure used for bit access */ 755 uint32_t reg; /**< Type used for register access */ 756 } MCAN_CUST_Type; 757 #endif 758 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 759 760 #define MCAN_CUST_OFFSET (0x08) /**< (MCAN_CUST) Customer Register Offset */ 761 762 #define MCAN_CUST_CSV_Pos 0 /**< (MCAN_CUST) Customer-specific Value Position */ 763 #define MCAN_CUST_CSV_Msk (_U_(0xFFFFFFFF) << MCAN_CUST_CSV_Pos) /**< (MCAN_CUST) Customer-specific Value Mask */ 764 #define MCAN_CUST_CSV(value) (MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos)) 765 #define MCAN_CUST_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_CUST) Register MASK (Use MCAN_CUST_Msk instead) */ 766 #define MCAN_CUST_Msk _U_(0xFFFFFFFF) /**< (MCAN_CUST) Register Mask */ 767 768 769 /* -------- MCAN_DBTP : (MCAN Offset: 0x0c) (R/W 32) Data Bit Timing and Prescaler Register -------- */ 770 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 771 #if COMPONENT_TYPEDEF_STYLE == 'N' 772 typedef union { 773 struct { 774 uint32_t DSJW:3; /**< bit: 0..2 Data (Re) Synchronization Jump Width */ 775 uint32_t :1; /**< bit: 3 Reserved */ 776 uint32_t DTSEG2:4; /**< bit: 4..7 Data Time Segment After Sample Point */ 777 uint32_t DTSEG1:5; /**< bit: 8..12 Data Time Segment Before Sample Point */ 778 uint32_t :3; /**< bit: 13..15 Reserved */ 779 uint32_t DBRP:5; /**< bit: 16..20 Data Bit Rate Prescaler */ 780 uint32_t :2; /**< bit: 21..22 Reserved */ 781 uint32_t TDC:1; /**< bit: 23 Transmitter Delay Compensation */ 782 uint32_t :8; /**< bit: 24..31 Reserved */ 783 } bit; /**< Structure used for bit access */ 784 uint32_t reg; /**< Type used for register access */ 785 } MCAN_DBTP_Type; 786 #endif 787 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 788 789 #define MCAN_DBTP_OFFSET (0x0C) /**< (MCAN_DBTP) Data Bit Timing and Prescaler Register Offset */ 790 791 #define MCAN_DBTP_DSJW_Pos 0 /**< (MCAN_DBTP) Data (Re) Synchronization Jump Width Position */ 792 #define MCAN_DBTP_DSJW_Msk (_U_(0x7) << MCAN_DBTP_DSJW_Pos) /**< (MCAN_DBTP) Data (Re) Synchronization Jump Width Mask */ 793 #define MCAN_DBTP_DSJW(value) (MCAN_DBTP_DSJW_Msk & ((value) << MCAN_DBTP_DSJW_Pos)) 794 #define MCAN_DBTP_DTSEG2_Pos 4 /**< (MCAN_DBTP) Data Time Segment After Sample Point Position */ 795 #define MCAN_DBTP_DTSEG2_Msk (_U_(0xF) << MCAN_DBTP_DTSEG2_Pos) /**< (MCAN_DBTP) Data Time Segment After Sample Point Mask */ 796 #define MCAN_DBTP_DTSEG2(value) (MCAN_DBTP_DTSEG2_Msk & ((value) << MCAN_DBTP_DTSEG2_Pos)) 797 #define MCAN_DBTP_DTSEG1_Pos 8 /**< (MCAN_DBTP) Data Time Segment Before Sample Point Position */ 798 #define MCAN_DBTP_DTSEG1_Msk (_U_(0x1F) << MCAN_DBTP_DTSEG1_Pos) /**< (MCAN_DBTP) Data Time Segment Before Sample Point Mask */ 799 #define MCAN_DBTP_DTSEG1(value) (MCAN_DBTP_DTSEG1_Msk & ((value) << MCAN_DBTP_DTSEG1_Pos)) 800 #define MCAN_DBTP_DBRP_Pos 16 /**< (MCAN_DBTP) Data Bit Rate Prescaler Position */ 801 #define MCAN_DBTP_DBRP_Msk (_U_(0x1F) << MCAN_DBTP_DBRP_Pos) /**< (MCAN_DBTP) Data Bit Rate Prescaler Mask */ 802 #define MCAN_DBTP_DBRP(value) (MCAN_DBTP_DBRP_Msk & ((value) << MCAN_DBTP_DBRP_Pos)) 803 #define MCAN_DBTP_TDC_Pos 23 /**< (MCAN_DBTP) Transmitter Delay Compensation Position */ 804 #define MCAN_DBTP_TDC_Msk (_U_(0x1) << MCAN_DBTP_TDC_Pos) /**< (MCAN_DBTP) Transmitter Delay Compensation Mask */ 805 #define MCAN_DBTP_TDC MCAN_DBTP_TDC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_DBTP_TDC_Msk instead */ 806 #define MCAN_DBTP_TDC_DISABLED_Val _U_(0x0) /**< (MCAN_DBTP) Transmitter Delay Compensation disabled. */ 807 #define MCAN_DBTP_TDC_ENABLED_Val _U_(0x1) /**< (MCAN_DBTP) Transmitter Delay Compensation enabled. */ 808 #define MCAN_DBTP_TDC_DISABLED (MCAN_DBTP_TDC_DISABLED_Val << MCAN_DBTP_TDC_Pos) /**< (MCAN_DBTP) Transmitter Delay Compensation disabled. Position */ 809 #define MCAN_DBTP_TDC_ENABLED (MCAN_DBTP_TDC_ENABLED_Val << MCAN_DBTP_TDC_Pos) /**< (MCAN_DBTP) Transmitter Delay Compensation enabled. Position */ 810 #define MCAN_DBTP_MASK _U_(0x9F1FF7) /**< \deprecated (MCAN_DBTP) Register MASK (Use MCAN_DBTP_Msk instead) */ 811 #define MCAN_DBTP_Msk _U_(0x9F1FF7) /**< (MCAN_DBTP) Register Mask */ 812 813 814 /* -------- MCAN_TEST : (MCAN Offset: 0x10) (R/W 32) Test Register -------- */ 815 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 816 #if COMPONENT_TYPEDEF_STYLE == 'N' 817 typedef union { 818 struct { 819 uint32_t :4; /**< bit: 0..3 Reserved */ 820 uint32_t LBCK:1; /**< bit: 4 Loop Back Mode (read/write) */ 821 uint32_t TX:2; /**< bit: 5..6 Control of Transmit Pin (read/write) */ 822 uint32_t RX:1; /**< bit: 7 Receive Pin (read-only) */ 823 uint32_t :24; /**< bit: 8..31 Reserved */ 824 } bit; /**< Structure used for bit access */ 825 uint32_t reg; /**< Type used for register access */ 826 } MCAN_TEST_Type; 827 #endif 828 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 829 830 #define MCAN_TEST_OFFSET (0x10) /**< (MCAN_TEST) Test Register Offset */ 831 832 #define MCAN_TEST_LBCK_Pos 4 /**< (MCAN_TEST) Loop Back Mode (read/write) Position */ 833 #define MCAN_TEST_LBCK_Msk (_U_(0x1) << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Loop Back Mode (read/write) Mask */ 834 #define MCAN_TEST_LBCK MCAN_TEST_LBCK_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TEST_LBCK_Msk instead */ 835 #define MCAN_TEST_LBCK_DISABLED_Val _U_(0x0) /**< (MCAN_TEST) Reset value. Loop Back mode is disabled. */ 836 #define MCAN_TEST_LBCK_ENABLED_Val _U_(0x1) /**< (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). */ 837 #define MCAN_TEST_LBCK_DISABLED (MCAN_TEST_LBCK_DISABLED_Val << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Reset value. Loop Back mode is disabled. Position */ 838 #define MCAN_TEST_LBCK_ENABLED (MCAN_TEST_LBCK_ENABLED_Val << MCAN_TEST_LBCK_Pos) /**< (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). Position */ 839 #define MCAN_TEST_TX_Pos 5 /**< (MCAN_TEST) Control of Transmit Pin (read/write) Position */ 840 #define MCAN_TEST_TX_Msk (_U_(0x3) << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Control of Transmit Pin (read/write) Mask */ 841 #define MCAN_TEST_TX(value) (MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos)) 842 #define MCAN_TEST_TX_RESET_Val _U_(0x0) /**< (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ 843 #define MCAN_TEST_TX_SAMPLE_POINT_MONITORING_Val _U_(0x1) /**< (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ 844 #define MCAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< (MCAN_TEST) Dominant ('0') level at pin CANTX. */ 845 #define MCAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< (MCAN_TEST) Recessive ('1') at pin CANTX. */ 846 #define MCAN_TEST_TX_RESET (MCAN_TEST_TX_RESET_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. Position */ 847 #define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (MCAN_TEST_TX_SAMPLE_POINT_MONITORING_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Sample Point can be monitored at pin CANTX. Position */ 848 #define MCAN_TEST_TX_DOMINANT (MCAN_TEST_TX_DOMINANT_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Dominant ('0') level at pin CANTX. Position */ 849 #define MCAN_TEST_TX_RECESSIVE (MCAN_TEST_TX_RECESSIVE_Val << MCAN_TEST_TX_Pos) /**< (MCAN_TEST) Recessive ('1') at pin CANTX. Position */ 850 #define MCAN_TEST_RX_Pos 7 /**< (MCAN_TEST) Receive Pin (read-only) Position */ 851 #define MCAN_TEST_RX_Msk (_U_(0x1) << MCAN_TEST_RX_Pos) /**< (MCAN_TEST) Receive Pin (read-only) Mask */ 852 #define MCAN_TEST_RX MCAN_TEST_RX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TEST_RX_Msk instead */ 853 #define MCAN_TEST_MASK _U_(0xF0) /**< \deprecated (MCAN_TEST) Register MASK (Use MCAN_TEST_Msk instead) */ 854 #define MCAN_TEST_Msk _U_(0xF0) /**< (MCAN_TEST) Register Mask */ 855 856 857 /* -------- MCAN_RWD : (MCAN Offset: 0x14) (R/W 32) RAM Watchdog Register -------- */ 858 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 859 #if COMPONENT_TYPEDEF_STYLE == 'N' 860 typedef union { 861 struct { 862 uint32_t WDC:8; /**< bit: 0..7 Watchdog Configuration (read/write) */ 863 uint32_t WDV:8; /**< bit: 8..15 Watchdog Value (read-only) */ 864 uint32_t :16; /**< bit: 16..31 Reserved */ 865 } bit; /**< Structure used for bit access */ 866 uint32_t reg; /**< Type used for register access */ 867 } MCAN_RWD_Type; 868 #endif 869 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 870 871 #define MCAN_RWD_OFFSET (0x14) /**< (MCAN_RWD) RAM Watchdog Register Offset */ 872 873 #define MCAN_RWD_WDC_Pos 0 /**< (MCAN_RWD) Watchdog Configuration (read/write) Position */ 874 #define MCAN_RWD_WDC_Msk (_U_(0xFF) << MCAN_RWD_WDC_Pos) /**< (MCAN_RWD) Watchdog Configuration (read/write) Mask */ 875 #define MCAN_RWD_WDC(value) (MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos)) 876 #define MCAN_RWD_WDV_Pos 8 /**< (MCAN_RWD) Watchdog Value (read-only) Position */ 877 #define MCAN_RWD_WDV_Msk (_U_(0xFF) << MCAN_RWD_WDV_Pos) /**< (MCAN_RWD) Watchdog Value (read-only) Mask */ 878 #define MCAN_RWD_WDV(value) (MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos)) 879 #define MCAN_RWD_MASK _U_(0xFFFF) /**< \deprecated (MCAN_RWD) Register MASK (Use MCAN_RWD_Msk instead) */ 880 #define MCAN_RWD_Msk _U_(0xFFFF) /**< (MCAN_RWD) Register Mask */ 881 882 883 /* -------- MCAN_CCCR : (MCAN Offset: 0x18) (R/W 32) CC Control Register -------- */ 884 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 885 #if COMPONENT_TYPEDEF_STYLE == 'N' 886 typedef union { 887 struct { 888 uint32_t INIT:1; /**< bit: 0 Initialization (read/write) */ 889 uint32_t CCE:1; /**< bit: 1 Configuration Change Enable (read/write, write protection) */ 890 uint32_t ASM:1; /**< bit: 2 Restricted Operation Mode (read/write, write protection against '1') */ 891 uint32_t CSA:1; /**< bit: 3 Clock Stop Acknowledge (read-only) */ 892 uint32_t CSR:1; /**< bit: 4 Clock Stop Request (read/write) */ 893 uint32_t MON:1; /**< bit: 5 Bus Monitoring Mode (read/write, write protection against '1') */ 894 uint32_t DAR:1; /**< bit: 6 Disable Automatic Retransmission (read/write, write protection) */ 895 uint32_t TEST:1; /**< bit: 7 Test Mode Enable (read/write, write protection against '1') */ 896 uint32_t FDOE:1; /**< bit: 8 CAN FD Operation Enable (read/write, write protection) */ 897 uint32_t BRSE:1; /**< bit: 9 Bit Rate Switching Enable (read/write, write protection) */ 898 uint32_t :2; /**< bit: 10..11 Reserved */ 899 uint32_t PXHD:1; /**< bit: 12 Protocol Exception Event Handling (read/write, write protection) */ 900 uint32_t EFBI:1; /**< bit: 13 Edge Filtering during Bus Integration (read/write, write protection) */ 901 uint32_t TXP:1; /**< bit: 14 Transmit Pause (read/write, write protection) */ 902 uint32_t NISO:1; /**< bit: 15 Non-ISO Operation */ 903 uint32_t :16; /**< bit: 16..31 Reserved */ 904 } bit; /**< Structure used for bit access */ 905 uint32_t reg; /**< Type used for register access */ 906 } MCAN_CCCR_Type; 907 #endif 908 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 909 910 #define MCAN_CCCR_OFFSET (0x18) /**< (MCAN_CCCR) CC Control Register Offset */ 911 912 #define MCAN_CCCR_INIT_Pos 0 /**< (MCAN_CCCR) Initialization (read/write) Position */ 913 #define MCAN_CCCR_INIT_Msk (_U_(0x1) << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Initialization (read/write) Mask */ 914 #define MCAN_CCCR_INIT MCAN_CCCR_INIT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_INIT_Msk instead */ 915 #define MCAN_CCCR_INIT_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Normal operation. */ 916 #define MCAN_CCCR_INIT_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Initialization is started. */ 917 #define MCAN_CCCR_INIT_DISABLED (MCAN_CCCR_INIT_DISABLED_Val << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Normal operation. Position */ 918 #define MCAN_CCCR_INIT_ENABLED (MCAN_CCCR_INIT_ENABLED_Val << MCAN_CCCR_INIT_Pos) /**< (MCAN_CCCR) Initialization is started. Position */ 919 #define MCAN_CCCR_CCE_Pos 1 /**< (MCAN_CCCR) Configuration Change Enable (read/write, write protection) Position */ 920 #define MCAN_CCCR_CCE_Msk (_U_(0x1) << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) Configuration Change Enable (read/write, write protection) Mask */ 921 #define MCAN_CCCR_CCE MCAN_CCCR_CCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_CCE_Msk instead */ 922 #define MCAN_CCCR_CCE_PROTECTED_Val _U_(0x0) /**< (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ 923 #define MCAN_CCCR_CCE_CONFIGURABLE_Val _U_(0x1) /**< (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ 924 #define MCAN_CCCR_CCE_PROTECTED (MCAN_CCCR_CCE_PROTECTED_Val << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) The processor has no write access to the protected configuration registers. Position */ 925 #define MCAN_CCCR_CCE_CONFIGURABLE (MCAN_CCCR_CCE_CONFIGURABLE_Val << MCAN_CCCR_CCE_Pos) /**< (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). Position */ 926 #define MCAN_CCCR_ASM_Pos 2 /**< (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') Position */ 927 #define MCAN_CCCR_ASM_Msk (_U_(0x1) << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') Mask */ 928 #define MCAN_CCCR_ASM MCAN_CCCR_ASM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_ASM_Msk instead */ 929 #define MCAN_CCCR_ASM_NORMAL_Val _U_(0x0) /**< (MCAN_CCCR) Normal CAN operation. */ 930 #define MCAN_CCCR_ASM_RESTRICTED_Val _U_(0x1) /**< (MCAN_CCCR) Restricted Operation mode active. */ 931 #define MCAN_CCCR_ASM_NORMAL (MCAN_CCCR_ASM_NORMAL_Val << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Normal CAN operation. Position */ 932 #define MCAN_CCCR_ASM_RESTRICTED (MCAN_CCCR_ASM_RESTRICTED_Val << MCAN_CCCR_ASM_Pos) /**< (MCAN_CCCR) Restricted Operation mode active. Position */ 933 #define MCAN_CCCR_CSA_Pos 3 /**< (MCAN_CCCR) Clock Stop Acknowledge (read-only) Position */ 934 #define MCAN_CCCR_CSA_Msk (_U_(0x1) << MCAN_CCCR_CSA_Pos) /**< (MCAN_CCCR) Clock Stop Acknowledge (read-only) Mask */ 935 #define MCAN_CCCR_CSA MCAN_CCCR_CSA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_CSA_Msk instead */ 936 #define MCAN_CCCR_CSR_Pos 4 /**< (MCAN_CCCR) Clock Stop Request (read/write) Position */ 937 #define MCAN_CCCR_CSR_Msk (_U_(0x1) << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) Clock Stop Request (read/write) Mask */ 938 #define MCAN_CCCR_CSR MCAN_CCCR_CSR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_CSR_Msk instead */ 939 #define MCAN_CCCR_CSR_NO_CLOCK_STOP_Val _U_(0x0) /**< (MCAN_CCCR) No clock stop is requested. */ 940 #define MCAN_CCCR_CSR_CLOCK_STOP_Val _U_(0x1) /**< (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ 941 #define MCAN_CCCR_CSR_NO_CLOCK_STOP (MCAN_CCCR_CSR_NO_CLOCK_STOP_Val << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) No clock stop is requested. Position */ 942 #define MCAN_CCCR_CSR_CLOCK_STOP (MCAN_CCCR_CSR_CLOCK_STOP_Val << MCAN_CCCR_CSR_Pos) /**< (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. Position */ 943 #define MCAN_CCCR_MON_Pos 5 /**< (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') Position */ 944 #define MCAN_CCCR_MON_Msk (_U_(0x1) << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') Mask */ 945 #define MCAN_CCCR_MON MCAN_CCCR_MON_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_MON_Msk instead */ 946 #define MCAN_CCCR_MON_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Bus Monitoring mode is disabled. */ 947 #define MCAN_CCCR_MON_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Bus Monitoring mode is enabled. */ 948 #define MCAN_CCCR_MON_DISABLED (MCAN_CCCR_MON_DISABLED_Val << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring mode is disabled. Position */ 949 #define MCAN_CCCR_MON_ENABLED (MCAN_CCCR_MON_ENABLED_Val << MCAN_CCCR_MON_Pos) /**< (MCAN_CCCR) Bus Monitoring mode is enabled. Position */ 950 #define MCAN_CCCR_DAR_Pos 6 /**< (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) Position */ 951 #define MCAN_CCCR_DAR_Msk (_U_(0x1) << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) Mask */ 952 #define MCAN_CCCR_DAR MCAN_CCCR_DAR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_DAR_Msk instead */ 953 #define MCAN_CCCR_DAR_AUTO_RETX_Val _U_(0x0) /**< (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ 954 #define MCAN_CCCR_DAR_NO_AUTO_RETX_Val _U_(0x1) /**< (MCAN_CCCR) Automatic retransmission disabled. */ 955 #define MCAN_CCCR_DAR_AUTO_RETX (MCAN_CCCR_DAR_AUTO_RETX_Val << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. Position */ 956 #define MCAN_CCCR_DAR_NO_AUTO_RETX (MCAN_CCCR_DAR_NO_AUTO_RETX_Val << MCAN_CCCR_DAR_Pos) /**< (MCAN_CCCR) Automatic retransmission disabled. Position */ 957 #define MCAN_CCCR_TEST_Pos 7 /**< (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') Position */ 958 #define MCAN_CCCR_TEST_Msk (_U_(0x1) << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') Mask */ 959 #define MCAN_CCCR_TEST MCAN_CCCR_TEST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_TEST_Msk instead */ 960 #define MCAN_CCCR_TEST_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ 961 #define MCAN_CCCR_TEST_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ 962 #define MCAN_CCCR_TEST_DISABLED (MCAN_CCCR_TEST_DISABLED_Val << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. Position */ 963 #define MCAN_CCCR_TEST_ENABLED (MCAN_CCCR_TEST_ENABLED_Val << MCAN_CCCR_TEST_Pos) /**< (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. Position */ 964 #define MCAN_CCCR_FDOE_Pos 8 /**< (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) Position */ 965 #define MCAN_CCCR_FDOE_Msk (_U_(0x1) << MCAN_CCCR_FDOE_Pos) /**< (MCAN_CCCR) CAN FD Operation Enable (read/write, write protection) Mask */ 966 #define MCAN_CCCR_FDOE MCAN_CCCR_FDOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_FDOE_Msk instead */ 967 #define MCAN_CCCR_FDOE_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) FD operation disabled. */ 968 #define MCAN_CCCR_FDOE_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) FD operation enabled. */ 969 #define MCAN_CCCR_FDOE_DISABLED (MCAN_CCCR_FDOE_DISABLED_Val << MCAN_CCCR_FDOE_Pos) /**< (MCAN_CCCR) FD operation disabled. Position */ 970 #define MCAN_CCCR_FDOE_ENABLED (MCAN_CCCR_FDOE_ENABLED_Val << MCAN_CCCR_FDOE_Pos) /**< (MCAN_CCCR) FD operation enabled. Position */ 971 #define MCAN_CCCR_BRSE_Pos 9 /**< (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) Position */ 972 #define MCAN_CCCR_BRSE_Msk (_U_(0x1) << MCAN_CCCR_BRSE_Pos) /**< (MCAN_CCCR) Bit Rate Switching Enable (read/write, write protection) Mask */ 973 #define MCAN_CCCR_BRSE MCAN_CCCR_BRSE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_BRSE_Msk instead */ 974 #define MCAN_CCCR_BRSE_DISABLED_Val _U_(0x0) /**< (MCAN_CCCR) Bit rate switching for transmissions disabled. */ 975 #define MCAN_CCCR_BRSE_ENABLED_Val _U_(0x1) /**< (MCAN_CCCR) Bit rate switching for transmissions enabled. */ 976 #define MCAN_CCCR_BRSE_DISABLED (MCAN_CCCR_BRSE_DISABLED_Val << MCAN_CCCR_BRSE_Pos) /**< (MCAN_CCCR) Bit rate switching for transmissions disabled. Position */ 977 #define MCAN_CCCR_BRSE_ENABLED (MCAN_CCCR_BRSE_ENABLED_Val << MCAN_CCCR_BRSE_Pos) /**< (MCAN_CCCR) Bit rate switching for transmissions enabled. Position */ 978 #define MCAN_CCCR_PXHD_Pos 12 /**< (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) Position */ 979 #define MCAN_CCCR_PXHD_Msk (_U_(0x1) << MCAN_CCCR_PXHD_Pos) /**< (MCAN_CCCR) Protocol Exception Event Handling (read/write, write protection) Mask */ 980 #define MCAN_CCCR_PXHD MCAN_CCCR_PXHD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_PXHD_Msk instead */ 981 #define MCAN_CCCR_EFBI_Pos 13 /**< (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) Position */ 982 #define MCAN_CCCR_EFBI_Msk (_U_(0x1) << MCAN_CCCR_EFBI_Pos) /**< (MCAN_CCCR) Edge Filtering during Bus Integration (read/write, write protection) Mask */ 983 #define MCAN_CCCR_EFBI MCAN_CCCR_EFBI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_EFBI_Msk instead */ 984 #define MCAN_CCCR_TXP_Pos 14 /**< (MCAN_CCCR) Transmit Pause (read/write, write protection) Position */ 985 #define MCAN_CCCR_TXP_Msk (_U_(0x1) << MCAN_CCCR_TXP_Pos) /**< (MCAN_CCCR) Transmit Pause (read/write, write protection) Mask */ 986 #define MCAN_CCCR_TXP MCAN_CCCR_TXP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_TXP_Msk instead */ 987 #define MCAN_CCCR_NISO_Pos 15 /**< (MCAN_CCCR) Non-ISO Operation Position */ 988 #define MCAN_CCCR_NISO_Msk (_U_(0x1) << MCAN_CCCR_NISO_Pos) /**< (MCAN_CCCR) Non-ISO Operation Mask */ 989 #define MCAN_CCCR_NISO MCAN_CCCR_NISO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_CCCR_NISO_Msk instead */ 990 #define MCAN_CCCR_MASK _U_(0xF3FF) /**< \deprecated (MCAN_CCCR) Register MASK (Use MCAN_CCCR_Msk instead) */ 991 #define MCAN_CCCR_Msk _U_(0xF3FF) /**< (MCAN_CCCR) Register Mask */ 992 993 994 /* -------- MCAN_NBTP : (MCAN Offset: 0x1c) (R/W 32) Nominal Bit Timing and Prescaler Register -------- */ 995 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 996 #if COMPONENT_TYPEDEF_STYLE == 'N' 997 typedef union { 998 struct { 999 uint32_t NTSEG2:7; /**< bit: 0..6 Nominal Time Segment After Sample Point */ 1000 uint32_t :1; /**< bit: 7 Reserved */ 1001 uint32_t NTSEG1:8; /**< bit: 8..15 Nominal Time Segment Before Sample Point */ 1002 uint32_t NBRP:9; /**< bit: 16..24 Nominal Bit Rate Prescaler */ 1003 uint32_t NSJW:7; /**< bit: 25..31 Nominal (Re) Synchronization Jump Width */ 1004 } bit; /**< Structure used for bit access */ 1005 uint32_t reg; /**< Type used for register access */ 1006 } MCAN_NBTP_Type; 1007 #endif 1008 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1009 1010 #define MCAN_NBTP_OFFSET (0x1C) /**< (MCAN_NBTP) Nominal Bit Timing and Prescaler Register Offset */ 1011 1012 #define MCAN_NBTP_NTSEG2_Pos 0 /**< (MCAN_NBTP) Nominal Time Segment After Sample Point Position */ 1013 #define MCAN_NBTP_NTSEG2_Msk (_U_(0x7F) << MCAN_NBTP_NTSEG2_Pos) /**< (MCAN_NBTP) Nominal Time Segment After Sample Point Mask */ 1014 #define MCAN_NBTP_NTSEG2(value) (MCAN_NBTP_NTSEG2_Msk & ((value) << MCAN_NBTP_NTSEG2_Pos)) 1015 #define MCAN_NBTP_NTSEG1_Pos 8 /**< (MCAN_NBTP) Nominal Time Segment Before Sample Point Position */ 1016 #define MCAN_NBTP_NTSEG1_Msk (_U_(0xFF) << MCAN_NBTP_NTSEG1_Pos) /**< (MCAN_NBTP) Nominal Time Segment Before Sample Point Mask */ 1017 #define MCAN_NBTP_NTSEG1(value) (MCAN_NBTP_NTSEG1_Msk & ((value) << MCAN_NBTP_NTSEG1_Pos)) 1018 #define MCAN_NBTP_NBRP_Pos 16 /**< (MCAN_NBTP) Nominal Bit Rate Prescaler Position */ 1019 #define MCAN_NBTP_NBRP_Msk (_U_(0x1FF) << MCAN_NBTP_NBRP_Pos) /**< (MCAN_NBTP) Nominal Bit Rate Prescaler Mask */ 1020 #define MCAN_NBTP_NBRP(value) (MCAN_NBTP_NBRP_Msk & ((value) << MCAN_NBTP_NBRP_Pos)) 1021 #define MCAN_NBTP_NSJW_Pos 25 /**< (MCAN_NBTP) Nominal (Re) Synchronization Jump Width Position */ 1022 #define MCAN_NBTP_NSJW_Msk (_U_(0x7F) << MCAN_NBTP_NSJW_Pos) /**< (MCAN_NBTP) Nominal (Re) Synchronization Jump Width Mask */ 1023 #define MCAN_NBTP_NSJW(value) (MCAN_NBTP_NSJW_Msk & ((value) << MCAN_NBTP_NSJW_Pos)) 1024 #define MCAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \deprecated (MCAN_NBTP) Register MASK (Use MCAN_NBTP_Msk instead) */ 1025 #define MCAN_NBTP_Msk _U_(0xFFFFFF7F) /**< (MCAN_NBTP) Register Mask */ 1026 1027 1028 /* -------- MCAN_TSCC : (MCAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration Register -------- */ 1029 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1030 #if COMPONENT_TYPEDEF_STYLE == 'N' 1031 typedef union { 1032 struct { 1033 uint32_t TSS:2; /**< bit: 0..1 Timestamp Select */ 1034 uint32_t :14; /**< bit: 2..15 Reserved */ 1035 uint32_t TCP:4; /**< bit: 16..19 Timestamp Counter Prescaler */ 1036 uint32_t :12; /**< bit: 20..31 Reserved */ 1037 } bit; /**< Structure used for bit access */ 1038 uint32_t reg; /**< Type used for register access */ 1039 } MCAN_TSCC_Type; 1040 #endif 1041 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1042 1043 #define MCAN_TSCC_OFFSET (0x20) /**< (MCAN_TSCC) Timestamp Counter Configuration Register Offset */ 1044 1045 #define MCAN_TSCC_TSS_Pos 0 /**< (MCAN_TSCC) Timestamp Select Position */ 1046 #define MCAN_TSCC_TSS_Msk (_U_(0x3) << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp Select Mask */ 1047 #define MCAN_TSCC_TSS(value) (MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos)) 1048 #define MCAN_TSCC_TSS_ALWAYS_0_Val _U_(0x0) /**< (MCAN_TSCC) Timestamp counter value always 0x0000 */ 1049 #define MCAN_TSCC_TSS_TCP_INC_Val _U_(0x1) /**< (MCAN_TSCC) Timestamp counter value incremented according to TCP */ 1050 #define MCAN_TSCC_TSS_EXT_TIMESTAMP_Val _U_(0x2) /**< (MCAN_TSCC) External timestamp counter value used */ 1051 #define MCAN_TSCC_TSS_ALWAYS_0 (MCAN_TSCC_TSS_ALWAYS_0_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp counter value always 0x0000 Position */ 1052 #define MCAN_TSCC_TSS_TCP_INC (MCAN_TSCC_TSS_TCP_INC_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) Timestamp counter value incremented according to TCP Position */ 1053 #define MCAN_TSCC_TSS_EXT_TIMESTAMP (MCAN_TSCC_TSS_EXT_TIMESTAMP_Val << MCAN_TSCC_TSS_Pos) /**< (MCAN_TSCC) External timestamp counter value used Position */ 1054 #define MCAN_TSCC_TCP_Pos 16 /**< (MCAN_TSCC) Timestamp Counter Prescaler Position */ 1055 #define MCAN_TSCC_TCP_Msk (_U_(0xF) << MCAN_TSCC_TCP_Pos) /**< (MCAN_TSCC) Timestamp Counter Prescaler Mask */ 1056 #define MCAN_TSCC_TCP(value) (MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos)) 1057 #define MCAN_TSCC_MASK _U_(0xF0003) /**< \deprecated (MCAN_TSCC) Register MASK (Use MCAN_TSCC_Msk instead) */ 1058 #define MCAN_TSCC_Msk _U_(0xF0003) /**< (MCAN_TSCC) Register Mask */ 1059 1060 1061 /* -------- MCAN_TSCV : (MCAN Offset: 0x24) (R/W 32) Timestamp Counter Value Register -------- */ 1062 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1063 #if COMPONENT_TYPEDEF_STYLE == 'N' 1064 typedef union { 1065 struct { 1066 uint32_t TSC:16; /**< bit: 0..15 Timestamp Counter (cleared on write) */ 1067 uint32_t :16; /**< bit: 16..31 Reserved */ 1068 } bit; /**< Structure used for bit access */ 1069 uint32_t reg; /**< Type used for register access */ 1070 } MCAN_TSCV_Type; 1071 #endif 1072 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1073 1074 #define MCAN_TSCV_OFFSET (0x24) /**< (MCAN_TSCV) Timestamp Counter Value Register Offset */ 1075 1076 #define MCAN_TSCV_TSC_Pos 0 /**< (MCAN_TSCV) Timestamp Counter (cleared on write) Position */ 1077 #define MCAN_TSCV_TSC_Msk (_U_(0xFFFF) << MCAN_TSCV_TSC_Pos) /**< (MCAN_TSCV) Timestamp Counter (cleared on write) Mask */ 1078 #define MCAN_TSCV_TSC(value) (MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos)) 1079 #define MCAN_TSCV_MASK _U_(0xFFFF) /**< \deprecated (MCAN_TSCV) Register MASK (Use MCAN_TSCV_Msk instead) */ 1080 #define MCAN_TSCV_Msk _U_(0xFFFF) /**< (MCAN_TSCV) Register Mask */ 1081 1082 1083 /* -------- MCAN_TOCC : (MCAN Offset: 0x28) (R/W 32) Timeout Counter Configuration Register -------- */ 1084 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1085 #if COMPONENT_TYPEDEF_STYLE == 'N' 1086 typedef union { 1087 struct { 1088 uint32_t ETOC:1; /**< bit: 0 Enable Timeout Counter */ 1089 uint32_t TOS:2; /**< bit: 1..2 Timeout Select */ 1090 uint32_t :13; /**< bit: 3..15 Reserved */ 1091 uint32_t TOP:16; /**< bit: 16..31 Timeout Period */ 1092 } bit; /**< Structure used for bit access */ 1093 uint32_t reg; /**< Type used for register access */ 1094 } MCAN_TOCC_Type; 1095 #endif 1096 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1097 1098 #define MCAN_TOCC_OFFSET (0x28) /**< (MCAN_TOCC) Timeout Counter Configuration Register Offset */ 1099 1100 #define MCAN_TOCC_ETOC_Pos 0 /**< (MCAN_TOCC) Enable Timeout Counter Position */ 1101 #define MCAN_TOCC_ETOC_Msk (_U_(0x1) << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Enable Timeout Counter Mask */ 1102 #define MCAN_TOCC_ETOC MCAN_TOCC_ETOC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TOCC_ETOC_Msk instead */ 1103 #define MCAN_TOCC_ETOC_NO_TIMEOUT_Val _U_(0x0) /**< (MCAN_TOCC) Timeout Counter disabled. */ 1104 #define MCAN_TOCC_ETOC_TOS_CONTROLLED_Val _U_(0x1) /**< (MCAN_TOCC) Timeout Counter enabled. */ 1105 #define MCAN_TOCC_ETOC_NO_TIMEOUT (MCAN_TOCC_ETOC_NO_TIMEOUT_Val << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Timeout Counter disabled. Position */ 1106 #define MCAN_TOCC_ETOC_TOS_CONTROLLED (MCAN_TOCC_ETOC_TOS_CONTROLLED_Val << MCAN_TOCC_ETOC_Pos) /**< (MCAN_TOCC) Timeout Counter enabled. Position */ 1107 #define MCAN_TOCC_TOS_Pos 1 /**< (MCAN_TOCC) Timeout Select Position */ 1108 #define MCAN_TOCC_TOS_Msk (_U_(0x3) << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout Select Mask */ 1109 #define MCAN_TOCC_TOS(value) (MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos)) 1110 #define MCAN_TOCC_TOS_CONTINUOUS_Val _U_(0x0) /**< (MCAN_TOCC) Continuous operation */ 1111 #define MCAN_TOCC_TOS_TX_EV_TIMEOUT_Val _U_(0x1) /**< (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ 1112 #define MCAN_TOCC_TOS_RX0_EV_TIMEOUT_Val _U_(0x2) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ 1113 #define MCAN_TOCC_TOS_RX1_EV_TIMEOUT_Val _U_(0x3) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ 1114 #define MCAN_TOCC_TOS_CONTINUOUS (MCAN_TOCC_TOS_CONTINUOUS_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Continuous operation Position */ 1115 #define MCAN_TOCC_TOS_TX_EV_TIMEOUT (MCAN_TOCC_TOS_TX_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Tx Event FIFO Position */ 1116 #define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (MCAN_TOCC_TOS_RX0_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 0 Position */ 1117 #define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (MCAN_TOCC_TOS_RX1_EV_TIMEOUT_Val << MCAN_TOCC_TOS_Pos) /**< (MCAN_TOCC) Timeout controlled by Receive FIFO 1 Position */ 1118 #define MCAN_TOCC_TOP_Pos 16 /**< (MCAN_TOCC) Timeout Period Position */ 1119 #define MCAN_TOCC_TOP_Msk (_U_(0xFFFF) << MCAN_TOCC_TOP_Pos) /**< (MCAN_TOCC) Timeout Period Mask */ 1120 #define MCAN_TOCC_TOP(value) (MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos)) 1121 #define MCAN_TOCC_MASK _U_(0xFFFF0007) /**< \deprecated (MCAN_TOCC) Register MASK (Use MCAN_TOCC_Msk instead) */ 1122 #define MCAN_TOCC_Msk _U_(0xFFFF0007) /**< (MCAN_TOCC) Register Mask */ 1123 1124 1125 /* -------- MCAN_TOCV : (MCAN Offset: 0x2c) (R/W 32) Timeout Counter Value Register -------- */ 1126 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1127 #if COMPONENT_TYPEDEF_STYLE == 'N' 1128 typedef union { 1129 struct { 1130 uint32_t TOC:16; /**< bit: 0..15 Timeout Counter (cleared on write) */ 1131 uint32_t :16; /**< bit: 16..31 Reserved */ 1132 } bit; /**< Structure used for bit access */ 1133 uint32_t reg; /**< Type used for register access */ 1134 } MCAN_TOCV_Type; 1135 #endif 1136 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1137 1138 #define MCAN_TOCV_OFFSET (0x2C) /**< (MCAN_TOCV) Timeout Counter Value Register Offset */ 1139 1140 #define MCAN_TOCV_TOC_Pos 0 /**< (MCAN_TOCV) Timeout Counter (cleared on write) Position */ 1141 #define MCAN_TOCV_TOC_Msk (_U_(0xFFFF) << MCAN_TOCV_TOC_Pos) /**< (MCAN_TOCV) Timeout Counter (cleared on write) Mask */ 1142 #define MCAN_TOCV_TOC(value) (MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos)) 1143 #define MCAN_TOCV_MASK _U_(0xFFFF) /**< \deprecated (MCAN_TOCV) Register MASK (Use MCAN_TOCV_Msk instead) */ 1144 #define MCAN_TOCV_Msk _U_(0xFFFF) /**< (MCAN_TOCV) Register Mask */ 1145 1146 1147 /* -------- MCAN_ECR : (MCAN Offset: 0x40) (R/ 32) Error Counter Register -------- */ 1148 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1149 #if COMPONENT_TYPEDEF_STYLE == 'N' 1150 typedef union { 1151 struct { 1152 uint32_t TEC:8; /**< bit: 0..7 Transmit Error Counter */ 1153 uint32_t REC:7; /**< bit: 8..14 Receive Error Counter */ 1154 uint32_t RP:1; /**< bit: 15 Receive Error Passive */ 1155 uint32_t CEL:8; /**< bit: 16..23 CAN Error Logging (cleared on read) */ 1156 uint32_t :8; /**< bit: 24..31 Reserved */ 1157 } bit; /**< Structure used for bit access */ 1158 uint32_t reg; /**< Type used for register access */ 1159 } MCAN_ECR_Type; 1160 #endif 1161 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1162 1163 #define MCAN_ECR_OFFSET (0x40) /**< (MCAN_ECR) Error Counter Register Offset */ 1164 1165 #define MCAN_ECR_TEC_Pos 0 /**< (MCAN_ECR) Transmit Error Counter Position */ 1166 #define MCAN_ECR_TEC_Msk (_U_(0xFF) << MCAN_ECR_TEC_Pos) /**< (MCAN_ECR) Transmit Error Counter Mask */ 1167 #define MCAN_ECR_TEC(value) (MCAN_ECR_TEC_Msk & ((value) << MCAN_ECR_TEC_Pos)) 1168 #define MCAN_ECR_REC_Pos 8 /**< (MCAN_ECR) Receive Error Counter Position */ 1169 #define MCAN_ECR_REC_Msk (_U_(0x7F) << MCAN_ECR_REC_Pos) /**< (MCAN_ECR) Receive Error Counter Mask */ 1170 #define MCAN_ECR_REC(value) (MCAN_ECR_REC_Msk & ((value) << MCAN_ECR_REC_Pos)) 1171 #define MCAN_ECR_RP_Pos 15 /**< (MCAN_ECR) Receive Error Passive Position */ 1172 #define MCAN_ECR_RP_Msk (_U_(0x1) << MCAN_ECR_RP_Pos) /**< (MCAN_ECR) Receive Error Passive Mask */ 1173 #define MCAN_ECR_RP MCAN_ECR_RP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ECR_RP_Msk instead */ 1174 #define MCAN_ECR_CEL_Pos 16 /**< (MCAN_ECR) CAN Error Logging (cleared on read) Position */ 1175 #define MCAN_ECR_CEL_Msk (_U_(0xFF) << MCAN_ECR_CEL_Pos) /**< (MCAN_ECR) CAN Error Logging (cleared on read) Mask */ 1176 #define MCAN_ECR_CEL(value) (MCAN_ECR_CEL_Msk & ((value) << MCAN_ECR_CEL_Pos)) 1177 #define MCAN_ECR_MASK _U_(0xFFFFFF) /**< \deprecated (MCAN_ECR) Register MASK (Use MCAN_ECR_Msk instead) */ 1178 #define MCAN_ECR_Msk _U_(0xFFFFFF) /**< (MCAN_ECR) Register Mask */ 1179 1180 1181 /* -------- MCAN_PSR : (MCAN Offset: 0x44) (R/ 32) Protocol Status Register -------- */ 1182 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1183 #if COMPONENT_TYPEDEF_STYLE == 'N' 1184 typedef union { 1185 struct { 1186 uint32_t LEC:3; /**< bit: 0..2 Last Error Code (set to 111 on read) */ 1187 uint32_t ACT:2; /**< bit: 3..4 Activity */ 1188 uint32_t EP:1; /**< bit: 5 Error Passive */ 1189 uint32_t EW:1; /**< bit: 6 Warning Status */ 1190 uint32_t BO:1; /**< bit: 7 Bus_Off Status */ 1191 uint32_t DLEC:3; /**< bit: 8..10 Data Phase Last Error Code (set to 111 on read) */ 1192 uint32_t RESI:1; /**< bit: 11 ESI Flag of Last Received CAN FD Message (cleared on read) */ 1193 uint32_t RBRS:1; /**< bit: 12 BRS Flag of Last Received CAN FD Message (cleared on read) */ 1194 uint32_t RFDF:1; /**< bit: 13 Received a CAN FD Message (cleared on read) */ 1195 uint32_t PXE:1; /**< bit: 14 Protocol Exception Event (cleared on read) */ 1196 uint32_t :1; /**< bit: 15 Reserved */ 1197 uint32_t TDCV:7; /**< bit: 16..22 Transmitter Delay Compensation Value */ 1198 uint32_t :9; /**< bit: 23..31 Reserved */ 1199 } bit; /**< Structure used for bit access */ 1200 uint32_t reg; /**< Type used for register access */ 1201 } MCAN_PSR_Type; 1202 #endif 1203 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1204 1205 #define MCAN_PSR_OFFSET (0x44) /**< (MCAN_PSR) Protocol Status Register Offset */ 1206 1207 #define MCAN_PSR_LEC_Pos 0 /**< (MCAN_PSR) Last Error Code (set to 111 on read) Position */ 1208 #define MCAN_PSR_LEC_Msk (_U_(0x7) << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) Last Error Code (set to 111 on read) Mask */ 1209 #define MCAN_PSR_LEC(value) (MCAN_PSR_LEC_Msk & ((value) << MCAN_PSR_LEC_Pos)) 1210 #define MCAN_PSR_LEC_NO_ERROR_Val _U_(0x0) /**< (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ 1211 #define MCAN_PSR_LEC_STUFF_ERROR_Val _U_(0x1) /**< (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. */ 1212 #define MCAN_PSR_LEC_FORM_ERROR_Val _U_(0x2) /**< (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ 1213 #define MCAN_PSR_LEC_ACK_ERROR_Val _U_(0x3) /**< (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ 1214 #define MCAN_PSR_LEC_BIT1_ERROR_Val _U_(0x4) /**< (MCAN_PSR) During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ 1215 #define MCAN_PSR_LEC_BIT0_ERROR_Val _U_(0x5) /**< (MCAN_PSR) During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ 1216 #define MCAN_PSR_LEC_CRC_ERROR_Val _U_(0x6) /**< (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data. */ 1217 #define MCAN_PSR_LEC_NO_CHANGE_Val _U_(0x7) /**< (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ 1218 #define MCAN_PSR_LEC_NO_ERROR (MCAN_PSR_LEC_NO_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. Position */ 1219 #define MCAN_PSR_LEC_STUFF_ERROR (MCAN_PSR_LEC_STUFF_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. Position */ 1220 #define MCAN_PSR_LEC_FORM_ERROR (MCAN_PSR_LEC_FORM_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) A fixed format part of a received frame has the wrong format. Position */ 1221 #define MCAN_PSR_LEC_ACK_ERROR (MCAN_PSR_LEC_ACK_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. Position */ 1222 #define MCAN_PSR_LEC_BIT1_ERROR (MCAN_PSR_LEC_BIT1_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) During transmission of a message (with the exception of the arbitration field), the device tried to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. Position */ 1223 #define MCAN_PSR_LEC_BIT0_ERROR (MCAN_PSR_LEC_BIT0_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) During transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device tried to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery, this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). Position */ 1224 #define MCAN_PSR_LEC_CRC_ERROR (MCAN_PSR_LEC_CRC_ERROR_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match the CRC calculated from the received data. Position */ 1225 #define MCAN_PSR_LEC_NO_CHANGE (MCAN_PSR_LEC_NO_CHANGE_Val << MCAN_PSR_LEC_Pos) /**< (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. Position */ 1226 #define MCAN_PSR_ACT_Pos 3 /**< (MCAN_PSR) Activity Position */ 1227 #define MCAN_PSR_ACT_Msk (_U_(0x3) << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Activity Mask */ 1228 #define MCAN_PSR_ACT(value) (MCAN_PSR_ACT_Msk & ((value) << MCAN_PSR_ACT_Pos)) 1229 #define MCAN_PSR_ACT_SYNCHRONIZING_Val _U_(0x0) /**< (MCAN_PSR) Node is synchronizing on CAN communication */ 1230 #define MCAN_PSR_ACT_IDLE_Val _U_(0x1) /**< (MCAN_PSR) Node is neither receiver nor transmitter */ 1231 #define MCAN_PSR_ACT_RECEIVER_Val _U_(0x2) /**< (MCAN_PSR) Node is operating as receiver */ 1232 #define MCAN_PSR_ACT_TRANSMITTER_Val _U_(0x3) /**< (MCAN_PSR) Node is operating as transmitter */ 1233 #define MCAN_PSR_ACT_SYNCHRONIZING (MCAN_PSR_ACT_SYNCHRONIZING_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is synchronizing on CAN communication Position */ 1234 #define MCAN_PSR_ACT_IDLE (MCAN_PSR_ACT_IDLE_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is neither receiver nor transmitter Position */ 1235 #define MCAN_PSR_ACT_RECEIVER (MCAN_PSR_ACT_RECEIVER_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is operating as receiver Position */ 1236 #define MCAN_PSR_ACT_TRANSMITTER (MCAN_PSR_ACT_TRANSMITTER_Val << MCAN_PSR_ACT_Pos) /**< (MCAN_PSR) Node is operating as transmitter Position */ 1237 #define MCAN_PSR_EP_Pos 5 /**< (MCAN_PSR) Error Passive Position */ 1238 #define MCAN_PSR_EP_Msk (_U_(0x1) << MCAN_PSR_EP_Pos) /**< (MCAN_PSR) Error Passive Mask */ 1239 #define MCAN_PSR_EP MCAN_PSR_EP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_EP_Msk instead */ 1240 #define MCAN_PSR_EW_Pos 6 /**< (MCAN_PSR) Warning Status Position */ 1241 #define MCAN_PSR_EW_Msk (_U_(0x1) << MCAN_PSR_EW_Pos) /**< (MCAN_PSR) Warning Status Mask */ 1242 #define MCAN_PSR_EW MCAN_PSR_EW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_EW_Msk instead */ 1243 #define MCAN_PSR_BO_Pos 7 /**< (MCAN_PSR) Bus_Off Status Position */ 1244 #define MCAN_PSR_BO_Msk (_U_(0x1) << MCAN_PSR_BO_Pos) /**< (MCAN_PSR) Bus_Off Status Mask */ 1245 #define MCAN_PSR_BO MCAN_PSR_BO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_BO_Msk instead */ 1246 #define MCAN_PSR_DLEC_Pos 8 /**< (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) Position */ 1247 #define MCAN_PSR_DLEC_Msk (_U_(0x7) << MCAN_PSR_DLEC_Pos) /**< (MCAN_PSR) Data Phase Last Error Code (set to 111 on read) Mask */ 1248 #define MCAN_PSR_DLEC(value) (MCAN_PSR_DLEC_Msk & ((value) << MCAN_PSR_DLEC_Pos)) 1249 #define MCAN_PSR_RESI_Pos 11 /**< (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) Position */ 1250 #define MCAN_PSR_RESI_Msk (_U_(0x1) << MCAN_PSR_RESI_Pos) /**< (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) Mask */ 1251 #define MCAN_PSR_RESI MCAN_PSR_RESI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_RESI_Msk instead */ 1252 #define MCAN_PSR_RBRS_Pos 12 /**< (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) Position */ 1253 #define MCAN_PSR_RBRS_Msk (_U_(0x1) << MCAN_PSR_RBRS_Pos) /**< (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) Mask */ 1254 #define MCAN_PSR_RBRS MCAN_PSR_RBRS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_RBRS_Msk instead */ 1255 #define MCAN_PSR_RFDF_Pos 13 /**< (MCAN_PSR) Received a CAN FD Message (cleared on read) Position */ 1256 #define MCAN_PSR_RFDF_Msk (_U_(0x1) << MCAN_PSR_RFDF_Pos) /**< (MCAN_PSR) Received a CAN FD Message (cleared on read) Mask */ 1257 #define MCAN_PSR_RFDF MCAN_PSR_RFDF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_RFDF_Msk instead */ 1258 #define MCAN_PSR_PXE_Pos 14 /**< (MCAN_PSR) Protocol Exception Event (cleared on read) Position */ 1259 #define MCAN_PSR_PXE_Msk (_U_(0x1) << MCAN_PSR_PXE_Pos) /**< (MCAN_PSR) Protocol Exception Event (cleared on read) Mask */ 1260 #define MCAN_PSR_PXE MCAN_PSR_PXE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_PSR_PXE_Msk instead */ 1261 #define MCAN_PSR_TDCV_Pos 16 /**< (MCAN_PSR) Transmitter Delay Compensation Value Position */ 1262 #define MCAN_PSR_TDCV_Msk (_U_(0x7F) << MCAN_PSR_TDCV_Pos) /**< (MCAN_PSR) Transmitter Delay Compensation Value Mask */ 1263 #define MCAN_PSR_TDCV(value) (MCAN_PSR_TDCV_Msk & ((value) << MCAN_PSR_TDCV_Pos)) 1264 #define MCAN_PSR_MASK _U_(0x7F7FFF) /**< \deprecated (MCAN_PSR) Register MASK (Use MCAN_PSR_Msk instead) */ 1265 #define MCAN_PSR_Msk _U_(0x7F7FFF) /**< (MCAN_PSR) Register Mask */ 1266 1267 1268 /* -------- MCAN_TDCR : (MCAN Offset: 0x48) (R/W 32) Transmit Delay Compensation Register -------- */ 1269 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1270 #if COMPONENT_TYPEDEF_STYLE == 'N' 1271 typedef union { 1272 struct { 1273 uint32_t TDCF:7; /**< bit: 0..6 Transmitter Delay Compensation Filter */ 1274 uint32_t :1; /**< bit: 7 Reserved */ 1275 uint32_t TDCO:7; /**< bit: 8..14 Transmitter Delay Compensation Offset */ 1276 uint32_t :17; /**< bit: 15..31 Reserved */ 1277 } bit; /**< Structure used for bit access */ 1278 uint32_t reg; /**< Type used for register access */ 1279 } MCAN_TDCR_Type; 1280 #endif 1281 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1282 1283 #define MCAN_TDCR_OFFSET (0x48) /**< (MCAN_TDCR) Transmit Delay Compensation Register Offset */ 1284 1285 #define MCAN_TDCR_TDCF_Pos 0 /**< (MCAN_TDCR) Transmitter Delay Compensation Filter Position */ 1286 #define MCAN_TDCR_TDCF_Msk (_U_(0x7F) << MCAN_TDCR_TDCF_Pos) /**< (MCAN_TDCR) Transmitter Delay Compensation Filter Mask */ 1287 #define MCAN_TDCR_TDCF(value) (MCAN_TDCR_TDCF_Msk & ((value) << MCAN_TDCR_TDCF_Pos)) 1288 #define MCAN_TDCR_TDCO_Pos 8 /**< (MCAN_TDCR) Transmitter Delay Compensation Offset Position */ 1289 #define MCAN_TDCR_TDCO_Msk (_U_(0x7F) << MCAN_TDCR_TDCO_Pos) /**< (MCAN_TDCR) Transmitter Delay Compensation Offset Mask */ 1290 #define MCAN_TDCR_TDCO(value) (MCAN_TDCR_TDCO_Msk & ((value) << MCAN_TDCR_TDCO_Pos)) 1291 #define MCAN_TDCR_MASK _U_(0x7F7F) /**< \deprecated (MCAN_TDCR) Register MASK (Use MCAN_TDCR_Msk instead) */ 1292 #define MCAN_TDCR_Msk _U_(0x7F7F) /**< (MCAN_TDCR) Register Mask */ 1293 1294 1295 /* -------- MCAN_IR : (MCAN Offset: 0x50) (R/W 32) Interrupt Register -------- */ 1296 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1297 #if COMPONENT_TYPEDEF_STYLE == 'N' 1298 typedef union { 1299 struct { 1300 uint32_t RF0N:1; /**< bit: 0 Receive FIFO 0 New Message */ 1301 uint32_t RF0W:1; /**< bit: 1 Receive FIFO 0 Watermark Reached */ 1302 uint32_t RF0F:1; /**< bit: 2 Receive FIFO 0 Full */ 1303 uint32_t RF0L:1; /**< bit: 3 Receive FIFO 0 Message Lost */ 1304 uint32_t RF1N:1; /**< bit: 4 Receive FIFO 1 New Message */ 1305 uint32_t RF1W:1; /**< bit: 5 Receive FIFO 1 Watermark Reached */ 1306 uint32_t RF1F:1; /**< bit: 6 Receive FIFO 1 Full */ 1307 uint32_t RF1L:1; /**< bit: 7 Receive FIFO 1 Message Lost */ 1308 uint32_t HPM:1; /**< bit: 8 High Priority Message */ 1309 uint32_t TC:1; /**< bit: 9 Transmission Completed */ 1310 uint32_t TCF:1; /**< bit: 10 Transmission Cancellation Finished */ 1311 uint32_t TFE:1; /**< bit: 11 Tx FIFO Empty */ 1312 uint32_t TEFN:1; /**< bit: 12 Tx Event FIFO New Entry */ 1313 uint32_t TEFW:1; /**< bit: 13 Tx Event FIFO Watermark Reached */ 1314 uint32_t TEFF:1; /**< bit: 14 Tx Event FIFO Full */ 1315 uint32_t TEFL:1; /**< bit: 15 Tx Event FIFO Element Lost */ 1316 uint32_t TSW:1; /**< bit: 16 Timestamp Wraparound */ 1317 uint32_t MRAF:1; /**< bit: 17 Message RAM Access Failure */ 1318 uint32_t TOO:1; /**< bit: 18 Timeout Occurred */ 1319 uint32_t DRX:1; /**< bit: 19 Message stored to Dedicated Receive Buffer */ 1320 uint32_t :2; /**< bit: 20..21 Reserved */ 1321 uint32_t ELO:1; /**< bit: 22 Error Logging Overflow */ 1322 uint32_t EP:1; /**< bit: 23 Error Passive */ 1323 uint32_t EW:1; /**< bit: 24 Warning Status */ 1324 uint32_t BO:1; /**< bit: 25 Bus_Off Status */ 1325 uint32_t WDI:1; /**< bit: 26 Watchdog Interrupt */ 1326 uint32_t PEA:1; /**< bit: 27 Protocol Error in Arbitration Phase */ 1327 uint32_t PED:1; /**< bit: 28 Protocol Error in Data Phase */ 1328 uint32_t ARA:1; /**< bit: 29 Access to Reserved Address */ 1329 uint32_t :2; /**< bit: 30..31 Reserved */ 1330 } bit; /**< Structure used for bit access */ 1331 uint32_t reg; /**< Type used for register access */ 1332 } MCAN_IR_Type; 1333 #endif 1334 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1335 1336 #define MCAN_IR_OFFSET (0x50) /**< (MCAN_IR) Interrupt Register Offset */ 1337 1338 #define MCAN_IR_RF0N_Pos 0 /**< (MCAN_IR) Receive FIFO 0 New Message Position */ 1339 #define MCAN_IR_RF0N_Msk (_U_(0x1) << MCAN_IR_RF0N_Pos) /**< (MCAN_IR) Receive FIFO 0 New Message Mask */ 1340 #define MCAN_IR_RF0N MCAN_IR_RF0N_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF0N_Msk instead */ 1341 #define MCAN_IR_RF0W_Pos 1 /**< (MCAN_IR) Receive FIFO 0 Watermark Reached Position */ 1342 #define MCAN_IR_RF0W_Msk (_U_(0x1) << MCAN_IR_RF0W_Pos) /**< (MCAN_IR) Receive FIFO 0 Watermark Reached Mask */ 1343 #define MCAN_IR_RF0W MCAN_IR_RF0W_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF0W_Msk instead */ 1344 #define MCAN_IR_RF0F_Pos 2 /**< (MCAN_IR) Receive FIFO 0 Full Position */ 1345 #define MCAN_IR_RF0F_Msk (_U_(0x1) << MCAN_IR_RF0F_Pos) /**< (MCAN_IR) Receive FIFO 0 Full Mask */ 1346 #define MCAN_IR_RF0F MCAN_IR_RF0F_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF0F_Msk instead */ 1347 #define MCAN_IR_RF0L_Pos 3 /**< (MCAN_IR) Receive FIFO 0 Message Lost Position */ 1348 #define MCAN_IR_RF0L_Msk (_U_(0x1) << MCAN_IR_RF0L_Pos) /**< (MCAN_IR) Receive FIFO 0 Message Lost Mask */ 1349 #define MCAN_IR_RF0L MCAN_IR_RF0L_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF0L_Msk instead */ 1350 #define MCAN_IR_RF1N_Pos 4 /**< (MCAN_IR) Receive FIFO 1 New Message Position */ 1351 #define MCAN_IR_RF1N_Msk (_U_(0x1) << MCAN_IR_RF1N_Pos) /**< (MCAN_IR) Receive FIFO 1 New Message Mask */ 1352 #define MCAN_IR_RF1N MCAN_IR_RF1N_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF1N_Msk instead */ 1353 #define MCAN_IR_RF1W_Pos 5 /**< (MCAN_IR) Receive FIFO 1 Watermark Reached Position */ 1354 #define MCAN_IR_RF1W_Msk (_U_(0x1) << MCAN_IR_RF1W_Pos) /**< (MCAN_IR) Receive FIFO 1 Watermark Reached Mask */ 1355 #define MCAN_IR_RF1W MCAN_IR_RF1W_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF1W_Msk instead */ 1356 #define MCAN_IR_RF1F_Pos 6 /**< (MCAN_IR) Receive FIFO 1 Full Position */ 1357 #define MCAN_IR_RF1F_Msk (_U_(0x1) << MCAN_IR_RF1F_Pos) /**< (MCAN_IR) Receive FIFO 1 Full Mask */ 1358 #define MCAN_IR_RF1F MCAN_IR_RF1F_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF1F_Msk instead */ 1359 #define MCAN_IR_RF1L_Pos 7 /**< (MCAN_IR) Receive FIFO 1 Message Lost Position */ 1360 #define MCAN_IR_RF1L_Msk (_U_(0x1) << MCAN_IR_RF1L_Pos) /**< (MCAN_IR) Receive FIFO 1 Message Lost Mask */ 1361 #define MCAN_IR_RF1L MCAN_IR_RF1L_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_RF1L_Msk instead */ 1362 #define MCAN_IR_HPM_Pos 8 /**< (MCAN_IR) High Priority Message Position */ 1363 #define MCAN_IR_HPM_Msk (_U_(0x1) << MCAN_IR_HPM_Pos) /**< (MCAN_IR) High Priority Message Mask */ 1364 #define MCAN_IR_HPM MCAN_IR_HPM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_HPM_Msk instead */ 1365 #define MCAN_IR_TC_Pos 9 /**< (MCAN_IR) Transmission Completed Position */ 1366 #define MCAN_IR_TC_Msk (_U_(0x1) << MCAN_IR_TC_Pos) /**< (MCAN_IR) Transmission Completed Mask */ 1367 #define MCAN_IR_TC MCAN_IR_TC_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TC_Msk instead */ 1368 #define MCAN_IR_TCF_Pos 10 /**< (MCAN_IR) Transmission Cancellation Finished Position */ 1369 #define MCAN_IR_TCF_Msk (_U_(0x1) << MCAN_IR_TCF_Pos) /**< (MCAN_IR) Transmission Cancellation Finished Mask */ 1370 #define MCAN_IR_TCF MCAN_IR_TCF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TCF_Msk instead */ 1371 #define MCAN_IR_TFE_Pos 11 /**< (MCAN_IR) Tx FIFO Empty Position */ 1372 #define MCAN_IR_TFE_Msk (_U_(0x1) << MCAN_IR_TFE_Pos) /**< (MCAN_IR) Tx FIFO Empty Mask */ 1373 #define MCAN_IR_TFE MCAN_IR_TFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TFE_Msk instead */ 1374 #define MCAN_IR_TEFN_Pos 12 /**< (MCAN_IR) Tx Event FIFO New Entry Position */ 1375 #define MCAN_IR_TEFN_Msk (_U_(0x1) << MCAN_IR_TEFN_Pos) /**< (MCAN_IR) Tx Event FIFO New Entry Mask */ 1376 #define MCAN_IR_TEFN MCAN_IR_TEFN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TEFN_Msk instead */ 1377 #define MCAN_IR_TEFW_Pos 13 /**< (MCAN_IR) Tx Event FIFO Watermark Reached Position */ 1378 #define MCAN_IR_TEFW_Msk (_U_(0x1) << MCAN_IR_TEFW_Pos) /**< (MCAN_IR) Tx Event FIFO Watermark Reached Mask */ 1379 #define MCAN_IR_TEFW MCAN_IR_TEFW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TEFW_Msk instead */ 1380 #define MCAN_IR_TEFF_Pos 14 /**< (MCAN_IR) Tx Event FIFO Full Position */ 1381 #define MCAN_IR_TEFF_Msk (_U_(0x1) << MCAN_IR_TEFF_Pos) /**< (MCAN_IR) Tx Event FIFO Full Mask */ 1382 #define MCAN_IR_TEFF MCAN_IR_TEFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TEFF_Msk instead */ 1383 #define MCAN_IR_TEFL_Pos 15 /**< (MCAN_IR) Tx Event FIFO Element Lost Position */ 1384 #define MCAN_IR_TEFL_Msk (_U_(0x1) << MCAN_IR_TEFL_Pos) /**< (MCAN_IR) Tx Event FIFO Element Lost Mask */ 1385 #define MCAN_IR_TEFL MCAN_IR_TEFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TEFL_Msk instead */ 1386 #define MCAN_IR_TSW_Pos 16 /**< (MCAN_IR) Timestamp Wraparound Position */ 1387 #define MCAN_IR_TSW_Msk (_U_(0x1) << MCAN_IR_TSW_Pos) /**< (MCAN_IR) Timestamp Wraparound Mask */ 1388 #define MCAN_IR_TSW MCAN_IR_TSW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TSW_Msk instead */ 1389 #define MCAN_IR_MRAF_Pos 17 /**< (MCAN_IR) Message RAM Access Failure Position */ 1390 #define MCAN_IR_MRAF_Msk (_U_(0x1) << MCAN_IR_MRAF_Pos) /**< (MCAN_IR) Message RAM Access Failure Mask */ 1391 #define MCAN_IR_MRAF MCAN_IR_MRAF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_MRAF_Msk instead */ 1392 #define MCAN_IR_TOO_Pos 18 /**< (MCAN_IR) Timeout Occurred Position */ 1393 #define MCAN_IR_TOO_Msk (_U_(0x1) << MCAN_IR_TOO_Pos) /**< (MCAN_IR) Timeout Occurred Mask */ 1394 #define MCAN_IR_TOO MCAN_IR_TOO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_TOO_Msk instead */ 1395 #define MCAN_IR_DRX_Pos 19 /**< (MCAN_IR) Message stored to Dedicated Receive Buffer Position */ 1396 #define MCAN_IR_DRX_Msk (_U_(0x1) << MCAN_IR_DRX_Pos) /**< (MCAN_IR) Message stored to Dedicated Receive Buffer Mask */ 1397 #define MCAN_IR_DRX MCAN_IR_DRX_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_DRX_Msk instead */ 1398 #define MCAN_IR_ELO_Pos 22 /**< (MCAN_IR) Error Logging Overflow Position */ 1399 #define MCAN_IR_ELO_Msk (_U_(0x1) << MCAN_IR_ELO_Pos) /**< (MCAN_IR) Error Logging Overflow Mask */ 1400 #define MCAN_IR_ELO MCAN_IR_ELO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_ELO_Msk instead */ 1401 #define MCAN_IR_EP_Pos 23 /**< (MCAN_IR) Error Passive Position */ 1402 #define MCAN_IR_EP_Msk (_U_(0x1) << MCAN_IR_EP_Pos) /**< (MCAN_IR) Error Passive Mask */ 1403 #define MCAN_IR_EP MCAN_IR_EP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_EP_Msk instead */ 1404 #define MCAN_IR_EW_Pos 24 /**< (MCAN_IR) Warning Status Position */ 1405 #define MCAN_IR_EW_Msk (_U_(0x1) << MCAN_IR_EW_Pos) /**< (MCAN_IR) Warning Status Mask */ 1406 #define MCAN_IR_EW MCAN_IR_EW_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_EW_Msk instead */ 1407 #define MCAN_IR_BO_Pos 25 /**< (MCAN_IR) Bus_Off Status Position */ 1408 #define MCAN_IR_BO_Msk (_U_(0x1) << MCAN_IR_BO_Pos) /**< (MCAN_IR) Bus_Off Status Mask */ 1409 #define MCAN_IR_BO MCAN_IR_BO_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_BO_Msk instead */ 1410 #define MCAN_IR_WDI_Pos 26 /**< (MCAN_IR) Watchdog Interrupt Position */ 1411 #define MCAN_IR_WDI_Msk (_U_(0x1) << MCAN_IR_WDI_Pos) /**< (MCAN_IR) Watchdog Interrupt Mask */ 1412 #define MCAN_IR_WDI MCAN_IR_WDI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_WDI_Msk instead */ 1413 #define MCAN_IR_PEA_Pos 27 /**< (MCAN_IR) Protocol Error in Arbitration Phase Position */ 1414 #define MCAN_IR_PEA_Msk (_U_(0x1) << MCAN_IR_PEA_Pos) /**< (MCAN_IR) Protocol Error in Arbitration Phase Mask */ 1415 #define MCAN_IR_PEA MCAN_IR_PEA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_PEA_Msk instead */ 1416 #define MCAN_IR_PED_Pos 28 /**< (MCAN_IR) Protocol Error in Data Phase Position */ 1417 #define MCAN_IR_PED_Msk (_U_(0x1) << MCAN_IR_PED_Pos) /**< (MCAN_IR) Protocol Error in Data Phase Mask */ 1418 #define MCAN_IR_PED MCAN_IR_PED_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_PED_Msk instead */ 1419 #define MCAN_IR_ARA_Pos 29 /**< (MCAN_IR) Access to Reserved Address Position */ 1420 #define MCAN_IR_ARA_Msk (_U_(0x1) << MCAN_IR_ARA_Pos) /**< (MCAN_IR) Access to Reserved Address Mask */ 1421 #define MCAN_IR_ARA MCAN_IR_ARA_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IR_ARA_Msk instead */ 1422 #define MCAN_IR_MASK _U_(0x3FCFFFFF) /**< \deprecated (MCAN_IR) Register MASK (Use MCAN_IR_Msk instead) */ 1423 #define MCAN_IR_Msk _U_(0x3FCFFFFF) /**< (MCAN_IR) Register Mask */ 1424 1425 1426 /* -------- MCAN_IE : (MCAN Offset: 0x54) (R/W 32) Interrupt Enable Register -------- */ 1427 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1428 #if COMPONENT_TYPEDEF_STYLE == 'N' 1429 typedef union { 1430 struct { 1431 uint32_t RF0NE:1; /**< bit: 0 Receive FIFO 0 New Message Interrupt Enable */ 1432 uint32_t RF0WE:1; /**< bit: 1 Receive FIFO 0 Watermark Reached Interrupt Enable */ 1433 uint32_t RF0FE:1; /**< bit: 2 Receive FIFO 0 Full Interrupt Enable */ 1434 uint32_t RF0LE:1; /**< bit: 3 Receive FIFO 0 Message Lost Interrupt Enable */ 1435 uint32_t RF1NE:1; /**< bit: 4 Receive FIFO 1 New Message Interrupt Enable */ 1436 uint32_t RF1WE:1; /**< bit: 5 Receive FIFO 1 Watermark Reached Interrupt Enable */ 1437 uint32_t RF1FE:1; /**< bit: 6 Receive FIFO 1 Full Interrupt Enable */ 1438 uint32_t RF1LE:1; /**< bit: 7 Receive FIFO 1 Message Lost Interrupt Enable */ 1439 uint32_t HPME:1; /**< bit: 8 High Priority Message Interrupt Enable */ 1440 uint32_t TCE:1; /**< bit: 9 Transmission Completed Interrupt Enable */ 1441 uint32_t TCFE:1; /**< bit: 10 Transmission Cancellation Finished Interrupt Enable */ 1442 uint32_t TFEE:1; /**< bit: 11 Tx FIFO Empty Interrupt Enable */ 1443 uint32_t TEFNE:1; /**< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ 1444 uint32_t TEFWE:1; /**< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ 1445 uint32_t TEFFE:1; /**< bit: 14 Tx Event FIFO Full Interrupt Enable */ 1446 uint32_t TEFLE:1; /**< bit: 15 Tx Event FIFO Event Lost Interrupt Enable */ 1447 uint32_t TSWE:1; /**< bit: 16 Timestamp Wraparound Interrupt Enable */ 1448 uint32_t MRAFE:1; /**< bit: 17 Message RAM Access Failure Interrupt Enable */ 1449 uint32_t TOOE:1; /**< bit: 18 Timeout Occurred Interrupt Enable */ 1450 uint32_t DRXE:1; /**< bit: 19 Message stored to Dedicated Receive Buffer Interrupt Enable */ 1451 uint32_t :2; /**< bit: 20..21 Reserved */ 1452 uint32_t ELOE:1; /**< bit: 22 Error Logging Overflow Interrupt Enable */ 1453 uint32_t EPE:1; /**< bit: 23 Error Passive Interrupt Enable */ 1454 uint32_t EWE:1; /**< bit: 24 Warning Status Interrupt Enable */ 1455 uint32_t BOE:1; /**< bit: 25 Bus_Off Status Interrupt Enable */ 1456 uint32_t WDIE:1; /**< bit: 26 Watchdog Interrupt Enable */ 1457 uint32_t PEAE:1; /**< bit: 27 Protocol Error in Arbitration Phase Enable */ 1458 uint32_t PEDE:1; /**< bit: 28 Protocol Error in Data Phase Enable */ 1459 uint32_t ARAE:1; /**< bit: 29 Access to Reserved Address Enable */ 1460 uint32_t :2; /**< bit: 30..31 Reserved */ 1461 } bit; /**< Structure used for bit access */ 1462 uint32_t reg; /**< Type used for register access */ 1463 } MCAN_IE_Type; 1464 #endif 1465 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1466 1467 #define MCAN_IE_OFFSET (0x54) /**< (MCAN_IE) Interrupt Enable Register Offset */ 1468 1469 #define MCAN_IE_RF0NE_Pos 0 /**< (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable Position */ 1470 #define MCAN_IE_RF0NE_Msk (_U_(0x1) << MCAN_IE_RF0NE_Pos) /**< (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable Mask */ 1471 #define MCAN_IE_RF0NE MCAN_IE_RF0NE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF0NE_Msk instead */ 1472 #define MCAN_IE_RF0WE_Pos 1 /**< (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable Position */ 1473 #define MCAN_IE_RF0WE_Msk (_U_(0x1) << MCAN_IE_RF0WE_Pos) /**< (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable Mask */ 1474 #define MCAN_IE_RF0WE MCAN_IE_RF0WE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF0WE_Msk instead */ 1475 #define MCAN_IE_RF0FE_Pos 2 /**< (MCAN_IE) Receive FIFO 0 Full Interrupt Enable Position */ 1476 #define MCAN_IE_RF0FE_Msk (_U_(0x1) << MCAN_IE_RF0FE_Pos) /**< (MCAN_IE) Receive FIFO 0 Full Interrupt Enable Mask */ 1477 #define MCAN_IE_RF0FE MCAN_IE_RF0FE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF0FE_Msk instead */ 1478 #define MCAN_IE_RF0LE_Pos 3 /**< (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable Position */ 1479 #define MCAN_IE_RF0LE_Msk (_U_(0x1) << MCAN_IE_RF0LE_Pos) /**< (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable Mask */ 1480 #define MCAN_IE_RF0LE MCAN_IE_RF0LE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF0LE_Msk instead */ 1481 #define MCAN_IE_RF1NE_Pos 4 /**< (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable Position */ 1482 #define MCAN_IE_RF1NE_Msk (_U_(0x1) << MCAN_IE_RF1NE_Pos) /**< (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable Mask */ 1483 #define MCAN_IE_RF1NE MCAN_IE_RF1NE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF1NE_Msk instead */ 1484 #define MCAN_IE_RF1WE_Pos 5 /**< (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable Position */ 1485 #define MCAN_IE_RF1WE_Msk (_U_(0x1) << MCAN_IE_RF1WE_Pos) /**< (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable Mask */ 1486 #define MCAN_IE_RF1WE MCAN_IE_RF1WE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF1WE_Msk instead */ 1487 #define MCAN_IE_RF1FE_Pos 6 /**< (MCAN_IE) Receive FIFO 1 Full Interrupt Enable Position */ 1488 #define MCAN_IE_RF1FE_Msk (_U_(0x1) << MCAN_IE_RF1FE_Pos) /**< (MCAN_IE) Receive FIFO 1 Full Interrupt Enable Mask */ 1489 #define MCAN_IE_RF1FE MCAN_IE_RF1FE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF1FE_Msk instead */ 1490 #define MCAN_IE_RF1LE_Pos 7 /**< (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable Position */ 1491 #define MCAN_IE_RF1LE_Msk (_U_(0x1) << MCAN_IE_RF1LE_Pos) /**< (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable Mask */ 1492 #define MCAN_IE_RF1LE MCAN_IE_RF1LE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_RF1LE_Msk instead */ 1493 #define MCAN_IE_HPME_Pos 8 /**< (MCAN_IE) High Priority Message Interrupt Enable Position */ 1494 #define MCAN_IE_HPME_Msk (_U_(0x1) << MCAN_IE_HPME_Pos) /**< (MCAN_IE) High Priority Message Interrupt Enable Mask */ 1495 #define MCAN_IE_HPME MCAN_IE_HPME_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_HPME_Msk instead */ 1496 #define MCAN_IE_TCE_Pos 9 /**< (MCAN_IE) Transmission Completed Interrupt Enable Position */ 1497 #define MCAN_IE_TCE_Msk (_U_(0x1) << MCAN_IE_TCE_Pos) /**< (MCAN_IE) Transmission Completed Interrupt Enable Mask */ 1498 #define MCAN_IE_TCE MCAN_IE_TCE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TCE_Msk instead */ 1499 #define MCAN_IE_TCFE_Pos 10 /**< (MCAN_IE) Transmission Cancellation Finished Interrupt Enable Position */ 1500 #define MCAN_IE_TCFE_Msk (_U_(0x1) << MCAN_IE_TCFE_Pos) /**< (MCAN_IE) Transmission Cancellation Finished Interrupt Enable Mask */ 1501 #define MCAN_IE_TCFE MCAN_IE_TCFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TCFE_Msk instead */ 1502 #define MCAN_IE_TFEE_Pos 11 /**< (MCAN_IE) Tx FIFO Empty Interrupt Enable Position */ 1503 #define MCAN_IE_TFEE_Msk (_U_(0x1) << MCAN_IE_TFEE_Pos) /**< (MCAN_IE) Tx FIFO Empty Interrupt Enable Mask */ 1504 #define MCAN_IE_TFEE MCAN_IE_TFEE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TFEE_Msk instead */ 1505 #define MCAN_IE_TEFNE_Pos 12 /**< (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable Position */ 1506 #define MCAN_IE_TEFNE_Msk (_U_(0x1) << MCAN_IE_TEFNE_Pos) /**< (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable Mask */ 1507 #define MCAN_IE_TEFNE MCAN_IE_TEFNE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TEFNE_Msk instead */ 1508 #define MCAN_IE_TEFWE_Pos 13 /**< (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Position */ 1509 #define MCAN_IE_TEFWE_Msk (_U_(0x1) << MCAN_IE_TEFWE_Pos) /**< (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable Mask */ 1510 #define MCAN_IE_TEFWE MCAN_IE_TEFWE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TEFWE_Msk instead */ 1511 #define MCAN_IE_TEFFE_Pos 14 /**< (MCAN_IE) Tx Event FIFO Full Interrupt Enable Position */ 1512 #define MCAN_IE_TEFFE_Msk (_U_(0x1) << MCAN_IE_TEFFE_Pos) /**< (MCAN_IE) Tx Event FIFO Full Interrupt Enable Mask */ 1513 #define MCAN_IE_TEFFE MCAN_IE_TEFFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TEFFE_Msk instead */ 1514 #define MCAN_IE_TEFLE_Pos 15 /**< (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable Position */ 1515 #define MCAN_IE_TEFLE_Msk (_U_(0x1) << MCAN_IE_TEFLE_Pos) /**< (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable Mask */ 1516 #define MCAN_IE_TEFLE MCAN_IE_TEFLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TEFLE_Msk instead */ 1517 #define MCAN_IE_TSWE_Pos 16 /**< (MCAN_IE) Timestamp Wraparound Interrupt Enable Position */ 1518 #define MCAN_IE_TSWE_Msk (_U_(0x1) << MCAN_IE_TSWE_Pos) /**< (MCAN_IE) Timestamp Wraparound Interrupt Enable Mask */ 1519 #define MCAN_IE_TSWE MCAN_IE_TSWE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TSWE_Msk instead */ 1520 #define MCAN_IE_MRAFE_Pos 17 /**< (MCAN_IE) Message RAM Access Failure Interrupt Enable Position */ 1521 #define MCAN_IE_MRAFE_Msk (_U_(0x1) << MCAN_IE_MRAFE_Pos) /**< (MCAN_IE) Message RAM Access Failure Interrupt Enable Mask */ 1522 #define MCAN_IE_MRAFE MCAN_IE_MRAFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_MRAFE_Msk instead */ 1523 #define MCAN_IE_TOOE_Pos 18 /**< (MCAN_IE) Timeout Occurred Interrupt Enable Position */ 1524 #define MCAN_IE_TOOE_Msk (_U_(0x1) << MCAN_IE_TOOE_Pos) /**< (MCAN_IE) Timeout Occurred Interrupt Enable Mask */ 1525 #define MCAN_IE_TOOE MCAN_IE_TOOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_TOOE_Msk instead */ 1526 #define MCAN_IE_DRXE_Pos 19 /**< (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable Position */ 1527 #define MCAN_IE_DRXE_Msk (_U_(0x1) << MCAN_IE_DRXE_Pos) /**< (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable Mask */ 1528 #define MCAN_IE_DRXE MCAN_IE_DRXE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_DRXE_Msk instead */ 1529 #define MCAN_IE_ELOE_Pos 22 /**< (MCAN_IE) Error Logging Overflow Interrupt Enable Position */ 1530 #define MCAN_IE_ELOE_Msk (_U_(0x1) << MCAN_IE_ELOE_Pos) /**< (MCAN_IE) Error Logging Overflow Interrupt Enable Mask */ 1531 #define MCAN_IE_ELOE MCAN_IE_ELOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_ELOE_Msk instead */ 1532 #define MCAN_IE_EPE_Pos 23 /**< (MCAN_IE) Error Passive Interrupt Enable Position */ 1533 #define MCAN_IE_EPE_Msk (_U_(0x1) << MCAN_IE_EPE_Pos) /**< (MCAN_IE) Error Passive Interrupt Enable Mask */ 1534 #define MCAN_IE_EPE MCAN_IE_EPE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_EPE_Msk instead */ 1535 #define MCAN_IE_EWE_Pos 24 /**< (MCAN_IE) Warning Status Interrupt Enable Position */ 1536 #define MCAN_IE_EWE_Msk (_U_(0x1) << MCAN_IE_EWE_Pos) /**< (MCAN_IE) Warning Status Interrupt Enable Mask */ 1537 #define MCAN_IE_EWE MCAN_IE_EWE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_EWE_Msk instead */ 1538 #define MCAN_IE_BOE_Pos 25 /**< (MCAN_IE) Bus_Off Status Interrupt Enable Position */ 1539 #define MCAN_IE_BOE_Msk (_U_(0x1) << MCAN_IE_BOE_Pos) /**< (MCAN_IE) Bus_Off Status Interrupt Enable Mask */ 1540 #define MCAN_IE_BOE MCAN_IE_BOE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_BOE_Msk instead */ 1541 #define MCAN_IE_WDIE_Pos 26 /**< (MCAN_IE) Watchdog Interrupt Enable Position */ 1542 #define MCAN_IE_WDIE_Msk (_U_(0x1) << MCAN_IE_WDIE_Pos) /**< (MCAN_IE) Watchdog Interrupt Enable Mask */ 1543 #define MCAN_IE_WDIE MCAN_IE_WDIE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_WDIE_Msk instead */ 1544 #define MCAN_IE_PEAE_Pos 27 /**< (MCAN_IE) Protocol Error in Arbitration Phase Enable Position */ 1545 #define MCAN_IE_PEAE_Msk (_U_(0x1) << MCAN_IE_PEAE_Pos) /**< (MCAN_IE) Protocol Error in Arbitration Phase Enable Mask */ 1546 #define MCAN_IE_PEAE MCAN_IE_PEAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_PEAE_Msk instead */ 1547 #define MCAN_IE_PEDE_Pos 28 /**< (MCAN_IE) Protocol Error in Data Phase Enable Position */ 1548 #define MCAN_IE_PEDE_Msk (_U_(0x1) << MCAN_IE_PEDE_Pos) /**< (MCAN_IE) Protocol Error in Data Phase Enable Mask */ 1549 #define MCAN_IE_PEDE MCAN_IE_PEDE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_PEDE_Msk instead */ 1550 #define MCAN_IE_ARAE_Pos 29 /**< (MCAN_IE) Access to Reserved Address Enable Position */ 1551 #define MCAN_IE_ARAE_Msk (_U_(0x1) << MCAN_IE_ARAE_Pos) /**< (MCAN_IE) Access to Reserved Address Enable Mask */ 1552 #define MCAN_IE_ARAE MCAN_IE_ARAE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_IE_ARAE_Msk instead */ 1553 #define MCAN_IE_MASK _U_(0x3FCFFFFF) /**< \deprecated (MCAN_IE) Register MASK (Use MCAN_IE_Msk instead) */ 1554 #define MCAN_IE_Msk _U_(0x3FCFFFFF) /**< (MCAN_IE) Register Mask */ 1555 1556 1557 /* -------- MCAN_ILS : (MCAN Offset: 0x58) (R/W 32) Interrupt Line Select Register -------- */ 1558 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1559 #if COMPONENT_TYPEDEF_STYLE == 'N' 1560 typedef union { 1561 struct { 1562 uint32_t RF0NL:1; /**< bit: 0 Receive FIFO 0 New Message Interrupt Line */ 1563 uint32_t RF0WL:1; /**< bit: 1 Receive FIFO 0 Watermark Reached Interrupt Line */ 1564 uint32_t RF0FL:1; /**< bit: 2 Receive FIFO 0 Full Interrupt Line */ 1565 uint32_t RF0LL:1; /**< bit: 3 Receive FIFO 0 Message Lost Interrupt Line */ 1566 uint32_t RF1NL:1; /**< bit: 4 Receive FIFO 1 New Message Interrupt Line */ 1567 uint32_t RF1WL:1; /**< bit: 5 Receive FIFO 1 Watermark Reached Interrupt Line */ 1568 uint32_t RF1FL:1; /**< bit: 6 Receive FIFO 1 Full Interrupt Line */ 1569 uint32_t RF1LL:1; /**< bit: 7 Receive FIFO 1 Message Lost Interrupt Line */ 1570 uint32_t HPML:1; /**< bit: 8 High Priority Message Interrupt Line */ 1571 uint32_t TCL:1; /**< bit: 9 Transmission Completed Interrupt Line */ 1572 uint32_t TCFL:1; /**< bit: 10 Transmission Cancellation Finished Interrupt Line */ 1573 uint32_t TFEL:1; /**< bit: 11 Tx FIFO Empty Interrupt Line */ 1574 uint32_t TEFNL:1; /**< bit: 12 Tx Event FIFO New Entry Interrupt Line */ 1575 uint32_t TEFWL:1; /**< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ 1576 uint32_t TEFFL:1; /**< bit: 14 Tx Event FIFO Full Interrupt Line */ 1577 uint32_t TEFLL:1; /**< bit: 15 Tx Event FIFO Event Lost Interrupt Line */ 1578 uint32_t TSWL:1; /**< bit: 16 Timestamp Wraparound Interrupt Line */ 1579 uint32_t MRAFL:1; /**< bit: 17 Message RAM Access Failure Interrupt Line */ 1580 uint32_t TOOL:1; /**< bit: 18 Timeout Occurred Interrupt Line */ 1581 uint32_t DRXL:1; /**< bit: 19 Message stored to Dedicated Receive Buffer Interrupt Line */ 1582 uint32_t :2; /**< bit: 20..21 Reserved */ 1583 uint32_t ELOL:1; /**< bit: 22 Error Logging Overflow Interrupt Line */ 1584 uint32_t EPL:1; /**< bit: 23 Error Passive Interrupt Line */ 1585 uint32_t EWL:1; /**< bit: 24 Warning Status Interrupt Line */ 1586 uint32_t BOL:1; /**< bit: 25 Bus_Off Status Interrupt Line */ 1587 uint32_t WDIL:1; /**< bit: 26 Watchdog Interrupt Line */ 1588 uint32_t PEAL:1; /**< bit: 27 Protocol Error in Arbitration Phase Line */ 1589 uint32_t PEDL:1; /**< bit: 28 Protocol Error in Data Phase Line */ 1590 uint32_t ARAL:1; /**< bit: 29 Access to Reserved Address Line */ 1591 uint32_t :2; /**< bit: 30..31 Reserved */ 1592 } bit; /**< Structure used for bit access */ 1593 uint32_t reg; /**< Type used for register access */ 1594 } MCAN_ILS_Type; 1595 #endif 1596 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1597 1598 #define MCAN_ILS_OFFSET (0x58) /**< (MCAN_ILS) Interrupt Line Select Register Offset */ 1599 1600 #define MCAN_ILS_RF0NL_Pos 0 /**< (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line Position */ 1601 #define MCAN_ILS_RF0NL_Msk (_U_(0x1) << MCAN_ILS_RF0NL_Pos) /**< (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line Mask */ 1602 #define MCAN_ILS_RF0NL MCAN_ILS_RF0NL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF0NL_Msk instead */ 1603 #define MCAN_ILS_RF0WL_Pos 1 /**< (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line Position */ 1604 #define MCAN_ILS_RF0WL_Msk (_U_(0x1) << MCAN_ILS_RF0WL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line Mask */ 1605 #define MCAN_ILS_RF0WL MCAN_ILS_RF0WL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF0WL_Msk instead */ 1606 #define MCAN_ILS_RF0FL_Pos 2 /**< (MCAN_ILS) Receive FIFO 0 Full Interrupt Line Position */ 1607 #define MCAN_ILS_RF0FL_Msk (_U_(0x1) << MCAN_ILS_RF0FL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Full Interrupt Line Mask */ 1608 #define MCAN_ILS_RF0FL MCAN_ILS_RF0FL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF0FL_Msk instead */ 1609 #define MCAN_ILS_RF0LL_Pos 3 /**< (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line Position */ 1610 #define MCAN_ILS_RF0LL_Msk (_U_(0x1) << MCAN_ILS_RF0LL_Pos) /**< (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line Mask */ 1611 #define MCAN_ILS_RF0LL MCAN_ILS_RF0LL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF0LL_Msk instead */ 1612 #define MCAN_ILS_RF1NL_Pos 4 /**< (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line Position */ 1613 #define MCAN_ILS_RF1NL_Msk (_U_(0x1) << MCAN_ILS_RF1NL_Pos) /**< (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line Mask */ 1614 #define MCAN_ILS_RF1NL MCAN_ILS_RF1NL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF1NL_Msk instead */ 1615 #define MCAN_ILS_RF1WL_Pos 5 /**< (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line Position */ 1616 #define MCAN_ILS_RF1WL_Msk (_U_(0x1) << MCAN_ILS_RF1WL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line Mask */ 1617 #define MCAN_ILS_RF1WL MCAN_ILS_RF1WL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF1WL_Msk instead */ 1618 #define MCAN_ILS_RF1FL_Pos 6 /**< (MCAN_ILS) Receive FIFO 1 Full Interrupt Line Position */ 1619 #define MCAN_ILS_RF1FL_Msk (_U_(0x1) << MCAN_ILS_RF1FL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Full Interrupt Line Mask */ 1620 #define MCAN_ILS_RF1FL MCAN_ILS_RF1FL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF1FL_Msk instead */ 1621 #define MCAN_ILS_RF1LL_Pos 7 /**< (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line Position */ 1622 #define MCAN_ILS_RF1LL_Msk (_U_(0x1) << MCAN_ILS_RF1LL_Pos) /**< (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line Mask */ 1623 #define MCAN_ILS_RF1LL MCAN_ILS_RF1LL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_RF1LL_Msk instead */ 1624 #define MCAN_ILS_HPML_Pos 8 /**< (MCAN_ILS) High Priority Message Interrupt Line Position */ 1625 #define MCAN_ILS_HPML_Msk (_U_(0x1) << MCAN_ILS_HPML_Pos) /**< (MCAN_ILS) High Priority Message Interrupt Line Mask */ 1626 #define MCAN_ILS_HPML MCAN_ILS_HPML_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_HPML_Msk instead */ 1627 #define MCAN_ILS_TCL_Pos 9 /**< (MCAN_ILS) Transmission Completed Interrupt Line Position */ 1628 #define MCAN_ILS_TCL_Msk (_U_(0x1) << MCAN_ILS_TCL_Pos) /**< (MCAN_ILS) Transmission Completed Interrupt Line Mask */ 1629 #define MCAN_ILS_TCL MCAN_ILS_TCL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TCL_Msk instead */ 1630 #define MCAN_ILS_TCFL_Pos 10 /**< (MCAN_ILS) Transmission Cancellation Finished Interrupt Line Position */ 1631 #define MCAN_ILS_TCFL_Msk (_U_(0x1) << MCAN_ILS_TCFL_Pos) /**< (MCAN_ILS) Transmission Cancellation Finished Interrupt Line Mask */ 1632 #define MCAN_ILS_TCFL MCAN_ILS_TCFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TCFL_Msk instead */ 1633 #define MCAN_ILS_TFEL_Pos 11 /**< (MCAN_ILS) Tx FIFO Empty Interrupt Line Position */ 1634 #define MCAN_ILS_TFEL_Msk (_U_(0x1) << MCAN_ILS_TFEL_Pos) /**< (MCAN_ILS) Tx FIFO Empty Interrupt Line Mask */ 1635 #define MCAN_ILS_TFEL MCAN_ILS_TFEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TFEL_Msk instead */ 1636 #define MCAN_ILS_TEFNL_Pos 12 /**< (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line Position */ 1637 #define MCAN_ILS_TEFNL_Msk (_U_(0x1) << MCAN_ILS_TEFNL_Pos) /**< (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line Mask */ 1638 #define MCAN_ILS_TEFNL MCAN_ILS_TEFNL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TEFNL_Msk instead */ 1639 #define MCAN_ILS_TEFWL_Pos 13 /**< (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Position */ 1640 #define MCAN_ILS_TEFWL_Msk (_U_(0x1) << MCAN_ILS_TEFWL_Pos) /**< (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line Mask */ 1641 #define MCAN_ILS_TEFWL MCAN_ILS_TEFWL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TEFWL_Msk instead */ 1642 #define MCAN_ILS_TEFFL_Pos 14 /**< (MCAN_ILS) Tx Event FIFO Full Interrupt Line Position */ 1643 #define MCAN_ILS_TEFFL_Msk (_U_(0x1) << MCAN_ILS_TEFFL_Pos) /**< (MCAN_ILS) Tx Event FIFO Full Interrupt Line Mask */ 1644 #define MCAN_ILS_TEFFL MCAN_ILS_TEFFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TEFFL_Msk instead */ 1645 #define MCAN_ILS_TEFLL_Pos 15 /**< (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line Position */ 1646 #define MCAN_ILS_TEFLL_Msk (_U_(0x1) << MCAN_ILS_TEFLL_Pos) /**< (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line Mask */ 1647 #define MCAN_ILS_TEFLL MCAN_ILS_TEFLL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TEFLL_Msk instead */ 1648 #define MCAN_ILS_TSWL_Pos 16 /**< (MCAN_ILS) Timestamp Wraparound Interrupt Line Position */ 1649 #define MCAN_ILS_TSWL_Msk (_U_(0x1) << MCAN_ILS_TSWL_Pos) /**< (MCAN_ILS) Timestamp Wraparound Interrupt Line Mask */ 1650 #define MCAN_ILS_TSWL MCAN_ILS_TSWL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TSWL_Msk instead */ 1651 #define MCAN_ILS_MRAFL_Pos 17 /**< (MCAN_ILS) Message RAM Access Failure Interrupt Line Position */ 1652 #define MCAN_ILS_MRAFL_Msk (_U_(0x1) << MCAN_ILS_MRAFL_Pos) /**< (MCAN_ILS) Message RAM Access Failure Interrupt Line Mask */ 1653 #define MCAN_ILS_MRAFL MCAN_ILS_MRAFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_MRAFL_Msk instead */ 1654 #define MCAN_ILS_TOOL_Pos 18 /**< (MCAN_ILS) Timeout Occurred Interrupt Line Position */ 1655 #define MCAN_ILS_TOOL_Msk (_U_(0x1) << MCAN_ILS_TOOL_Pos) /**< (MCAN_ILS) Timeout Occurred Interrupt Line Mask */ 1656 #define MCAN_ILS_TOOL MCAN_ILS_TOOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_TOOL_Msk instead */ 1657 #define MCAN_ILS_DRXL_Pos 19 /**< (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line Position */ 1658 #define MCAN_ILS_DRXL_Msk (_U_(0x1) << MCAN_ILS_DRXL_Pos) /**< (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line Mask */ 1659 #define MCAN_ILS_DRXL MCAN_ILS_DRXL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_DRXL_Msk instead */ 1660 #define MCAN_ILS_ELOL_Pos 22 /**< (MCAN_ILS) Error Logging Overflow Interrupt Line Position */ 1661 #define MCAN_ILS_ELOL_Msk (_U_(0x1) << MCAN_ILS_ELOL_Pos) /**< (MCAN_ILS) Error Logging Overflow Interrupt Line Mask */ 1662 #define MCAN_ILS_ELOL MCAN_ILS_ELOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_ELOL_Msk instead */ 1663 #define MCAN_ILS_EPL_Pos 23 /**< (MCAN_ILS) Error Passive Interrupt Line Position */ 1664 #define MCAN_ILS_EPL_Msk (_U_(0x1) << MCAN_ILS_EPL_Pos) /**< (MCAN_ILS) Error Passive Interrupt Line Mask */ 1665 #define MCAN_ILS_EPL MCAN_ILS_EPL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_EPL_Msk instead */ 1666 #define MCAN_ILS_EWL_Pos 24 /**< (MCAN_ILS) Warning Status Interrupt Line Position */ 1667 #define MCAN_ILS_EWL_Msk (_U_(0x1) << MCAN_ILS_EWL_Pos) /**< (MCAN_ILS) Warning Status Interrupt Line Mask */ 1668 #define MCAN_ILS_EWL MCAN_ILS_EWL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_EWL_Msk instead */ 1669 #define MCAN_ILS_BOL_Pos 25 /**< (MCAN_ILS) Bus_Off Status Interrupt Line Position */ 1670 #define MCAN_ILS_BOL_Msk (_U_(0x1) << MCAN_ILS_BOL_Pos) /**< (MCAN_ILS) Bus_Off Status Interrupt Line Mask */ 1671 #define MCAN_ILS_BOL MCAN_ILS_BOL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_BOL_Msk instead */ 1672 #define MCAN_ILS_WDIL_Pos 26 /**< (MCAN_ILS) Watchdog Interrupt Line Position */ 1673 #define MCAN_ILS_WDIL_Msk (_U_(0x1) << MCAN_ILS_WDIL_Pos) /**< (MCAN_ILS) Watchdog Interrupt Line Mask */ 1674 #define MCAN_ILS_WDIL MCAN_ILS_WDIL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_WDIL_Msk instead */ 1675 #define MCAN_ILS_PEAL_Pos 27 /**< (MCAN_ILS) Protocol Error in Arbitration Phase Line Position */ 1676 #define MCAN_ILS_PEAL_Msk (_U_(0x1) << MCAN_ILS_PEAL_Pos) /**< (MCAN_ILS) Protocol Error in Arbitration Phase Line Mask */ 1677 #define MCAN_ILS_PEAL MCAN_ILS_PEAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_PEAL_Msk instead */ 1678 #define MCAN_ILS_PEDL_Pos 28 /**< (MCAN_ILS) Protocol Error in Data Phase Line Position */ 1679 #define MCAN_ILS_PEDL_Msk (_U_(0x1) << MCAN_ILS_PEDL_Pos) /**< (MCAN_ILS) Protocol Error in Data Phase Line Mask */ 1680 #define MCAN_ILS_PEDL MCAN_ILS_PEDL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_PEDL_Msk instead */ 1681 #define MCAN_ILS_ARAL_Pos 29 /**< (MCAN_ILS) Access to Reserved Address Line Position */ 1682 #define MCAN_ILS_ARAL_Msk (_U_(0x1) << MCAN_ILS_ARAL_Pos) /**< (MCAN_ILS) Access to Reserved Address Line Mask */ 1683 #define MCAN_ILS_ARAL MCAN_ILS_ARAL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILS_ARAL_Msk instead */ 1684 #define MCAN_ILS_MASK _U_(0x3FCFFFFF) /**< \deprecated (MCAN_ILS) Register MASK (Use MCAN_ILS_Msk instead) */ 1685 #define MCAN_ILS_Msk _U_(0x3FCFFFFF) /**< (MCAN_ILS) Register Mask */ 1686 1687 1688 /* -------- MCAN_ILE : (MCAN Offset: 0x5c) (R/W 32) Interrupt Line Enable Register -------- */ 1689 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1690 #if COMPONENT_TYPEDEF_STYLE == 'N' 1691 typedef union { 1692 struct { 1693 uint32_t EINT0:1; /**< bit: 0 Enable Interrupt Line 0 */ 1694 uint32_t EINT1:1; /**< bit: 1 Enable Interrupt Line 1 */ 1695 uint32_t :30; /**< bit: 2..31 Reserved */ 1696 } bit; /**< Structure used for bit access */ 1697 struct { 1698 uint32_t EINT:2; /**< bit: 0..1 Enable Interrupt Line x */ 1699 uint32_t :30; /**< bit: 2..31 Reserved */ 1700 } vec; /**< Structure used for vec access */ 1701 uint32_t reg; /**< Type used for register access */ 1702 } MCAN_ILE_Type; 1703 #endif 1704 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1705 1706 #define MCAN_ILE_OFFSET (0x5C) /**< (MCAN_ILE) Interrupt Line Enable Register Offset */ 1707 1708 #define MCAN_ILE_EINT0_Pos 0 /**< (MCAN_ILE) Enable Interrupt Line 0 Position */ 1709 #define MCAN_ILE_EINT0_Msk (_U_(0x1) << MCAN_ILE_EINT0_Pos) /**< (MCAN_ILE) Enable Interrupt Line 0 Mask */ 1710 #define MCAN_ILE_EINT0 MCAN_ILE_EINT0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILE_EINT0_Msk instead */ 1711 #define MCAN_ILE_EINT1_Pos 1 /**< (MCAN_ILE) Enable Interrupt Line 1 Position */ 1712 #define MCAN_ILE_EINT1_Msk (_U_(0x1) << MCAN_ILE_EINT1_Pos) /**< (MCAN_ILE) Enable Interrupt Line 1 Mask */ 1713 #define MCAN_ILE_EINT1 MCAN_ILE_EINT1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_ILE_EINT1_Msk instead */ 1714 #define MCAN_ILE_MASK _U_(0x03) /**< \deprecated (MCAN_ILE) Register MASK (Use MCAN_ILE_Msk instead) */ 1715 #define MCAN_ILE_Msk _U_(0x03) /**< (MCAN_ILE) Register Mask */ 1716 1717 #define MCAN_ILE_EINT_Pos 0 /**< (MCAN_ILE Position) Enable Interrupt Line x */ 1718 #define MCAN_ILE_EINT_Msk (_U_(0x3) << MCAN_ILE_EINT_Pos) /**< (MCAN_ILE Mask) EINT */ 1719 #define MCAN_ILE_EINT(value) (MCAN_ILE_EINT_Msk & ((value) << MCAN_ILE_EINT_Pos)) 1720 1721 /* -------- MCAN_GFC : (MCAN Offset: 0x80) (R/W 32) Global Filter Configuration Register -------- */ 1722 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1723 #if COMPONENT_TYPEDEF_STYLE == 'N' 1724 typedef union { 1725 struct { 1726 uint32_t RRFE:1; /**< bit: 0 Reject Remote Frames Extended */ 1727 uint32_t RRFS:1; /**< bit: 1 Reject Remote Frames Standard */ 1728 uint32_t ANFE:2; /**< bit: 2..3 Accept Non-matching Frames Extended */ 1729 uint32_t ANFS:2; /**< bit: 4..5 Accept Non-matching Frames Standard */ 1730 uint32_t :26; /**< bit: 6..31 Reserved */ 1731 } bit; /**< Structure used for bit access */ 1732 uint32_t reg; /**< Type used for register access */ 1733 } MCAN_GFC_Type; 1734 #endif 1735 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1736 1737 #define MCAN_GFC_OFFSET (0x80) /**< (MCAN_GFC) Global Filter Configuration Register Offset */ 1738 1739 #define MCAN_GFC_RRFE_Pos 0 /**< (MCAN_GFC) Reject Remote Frames Extended Position */ 1740 #define MCAN_GFC_RRFE_Msk (_U_(0x1) << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Reject Remote Frames Extended Mask */ 1741 #define MCAN_GFC_RRFE MCAN_GFC_RRFE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_GFC_RRFE_Msk instead */ 1742 #define MCAN_GFC_RRFE_FILTER_Val _U_(0x0) /**< (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ 1743 #define MCAN_GFC_RRFE_REJECT_Val _U_(0x1) /**< (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ 1744 #define MCAN_GFC_RRFE_FILTER (MCAN_GFC_RRFE_FILTER_Val << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Filter remote frames with 29-bit extended IDs. Position */ 1745 #define MCAN_GFC_RRFE_REJECT (MCAN_GFC_RRFE_REJECT_Val << MCAN_GFC_RRFE_Pos) /**< (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. Position */ 1746 #define MCAN_GFC_RRFS_Pos 1 /**< (MCAN_GFC) Reject Remote Frames Standard Position */ 1747 #define MCAN_GFC_RRFS_Msk (_U_(0x1) << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Reject Remote Frames Standard Mask */ 1748 #define MCAN_GFC_RRFS MCAN_GFC_RRFS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_GFC_RRFS_Msk instead */ 1749 #define MCAN_GFC_RRFS_FILTER_Val _U_(0x0) /**< (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ 1750 #define MCAN_GFC_RRFS_REJECT_Val _U_(0x1) /**< (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ 1751 #define MCAN_GFC_RRFS_FILTER (MCAN_GFC_RRFS_FILTER_Val << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Filter remote frames with 11-bit standard IDs. Position */ 1752 #define MCAN_GFC_RRFS_REJECT (MCAN_GFC_RRFS_REJECT_Val << MCAN_GFC_RRFS_Pos) /**< (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. Position */ 1753 #define MCAN_GFC_ANFE_Pos 2 /**< (MCAN_GFC) Accept Non-matching Frames Extended Position */ 1754 #define MCAN_GFC_ANFE_Msk (_U_(0x3) << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept Non-matching Frames Extended Mask */ 1755 #define MCAN_GFC_ANFE(value) (MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos)) 1756 #define MCAN_GFC_ANFE_RX_FIFO_0_Val _U_(0x0) /**< (MCAN_GFC) Accept in Rx FIFO 0 */ 1757 #define MCAN_GFC_ANFE_RX_FIFO_1_Val _U_(0x1) /**< (MCAN_GFC) Accept in Rx FIFO 1 */ 1758 #define MCAN_GFC_ANFE_RX_FIFO_0 (MCAN_GFC_ANFE_RX_FIFO_0_Val << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 0 Position */ 1759 #define MCAN_GFC_ANFE_RX_FIFO_1 (MCAN_GFC_ANFE_RX_FIFO_1_Val << MCAN_GFC_ANFE_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 1 Position */ 1760 #define MCAN_GFC_ANFS_Pos 4 /**< (MCAN_GFC) Accept Non-matching Frames Standard Position */ 1761 #define MCAN_GFC_ANFS_Msk (_U_(0x3) << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept Non-matching Frames Standard Mask */ 1762 #define MCAN_GFC_ANFS(value) (MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos)) 1763 #define MCAN_GFC_ANFS_RX_FIFO_0_Val _U_(0x0) /**< (MCAN_GFC) Accept in Rx FIFO 0 */ 1764 #define MCAN_GFC_ANFS_RX_FIFO_1_Val _U_(0x1) /**< (MCAN_GFC) Accept in Rx FIFO 1 */ 1765 #define MCAN_GFC_ANFS_RX_FIFO_0 (MCAN_GFC_ANFS_RX_FIFO_0_Val << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 0 Position */ 1766 #define MCAN_GFC_ANFS_RX_FIFO_1 (MCAN_GFC_ANFS_RX_FIFO_1_Val << MCAN_GFC_ANFS_Pos) /**< (MCAN_GFC) Accept in Rx FIFO 1 Position */ 1767 #define MCAN_GFC_MASK _U_(0x3F) /**< \deprecated (MCAN_GFC) Register MASK (Use MCAN_GFC_Msk instead) */ 1768 #define MCAN_GFC_Msk _U_(0x3F) /**< (MCAN_GFC) Register Mask */ 1769 1770 1771 /* -------- MCAN_SIDFC : (MCAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration Register -------- */ 1772 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1773 #if COMPONENT_TYPEDEF_STYLE == 'N' 1774 typedef union { 1775 struct { 1776 uint32_t :2; /**< bit: 0..1 Reserved */ 1777 uint32_t FLSSA:14; /**< bit: 2..15 Filter List Standard Start Address */ 1778 uint32_t LSS:8; /**< bit: 16..23 List Size Standard */ 1779 uint32_t :8; /**< bit: 24..31 Reserved */ 1780 } bit; /**< Structure used for bit access */ 1781 uint32_t reg; /**< Type used for register access */ 1782 } MCAN_SIDFC_Type; 1783 #endif 1784 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1785 1786 #define MCAN_SIDFC_OFFSET (0x84) /**< (MCAN_SIDFC) Standard ID Filter Configuration Register Offset */ 1787 1788 #define MCAN_SIDFC_FLSSA_Pos 2 /**< (MCAN_SIDFC) Filter List Standard Start Address Position */ 1789 #define MCAN_SIDFC_FLSSA_Msk (_U_(0x3FFF) << MCAN_SIDFC_FLSSA_Pos) /**< (MCAN_SIDFC) Filter List Standard Start Address Mask */ 1790 #define MCAN_SIDFC_FLSSA(value) (MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos)) 1791 #define MCAN_SIDFC_LSS_Pos 16 /**< (MCAN_SIDFC) List Size Standard Position */ 1792 #define MCAN_SIDFC_LSS_Msk (_U_(0xFF) << MCAN_SIDFC_LSS_Pos) /**< (MCAN_SIDFC) List Size Standard Mask */ 1793 #define MCAN_SIDFC_LSS(value) (MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos)) 1794 #define MCAN_SIDFC_MASK _U_(0xFFFFFC) /**< \deprecated (MCAN_SIDFC) Register MASK (Use MCAN_SIDFC_Msk instead) */ 1795 #define MCAN_SIDFC_Msk _U_(0xFFFFFC) /**< (MCAN_SIDFC) Register Mask */ 1796 1797 1798 /* -------- MCAN_XIDFC : (MCAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration Register -------- */ 1799 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1800 #if COMPONENT_TYPEDEF_STYLE == 'N' 1801 typedef union { 1802 struct { 1803 uint32_t :2; /**< bit: 0..1 Reserved */ 1804 uint32_t FLESA:14; /**< bit: 2..15 Filter List Extended Start Address */ 1805 uint32_t LSE:7; /**< bit: 16..22 List Size Extended */ 1806 uint32_t :9; /**< bit: 23..31 Reserved */ 1807 } bit; /**< Structure used for bit access */ 1808 uint32_t reg; /**< Type used for register access */ 1809 } MCAN_XIDFC_Type; 1810 #endif 1811 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1812 1813 #define MCAN_XIDFC_OFFSET (0x88) /**< (MCAN_XIDFC) Extended ID Filter Configuration Register Offset */ 1814 1815 #define MCAN_XIDFC_FLESA_Pos 2 /**< (MCAN_XIDFC) Filter List Extended Start Address Position */ 1816 #define MCAN_XIDFC_FLESA_Msk (_U_(0x3FFF) << MCAN_XIDFC_FLESA_Pos) /**< (MCAN_XIDFC) Filter List Extended Start Address Mask */ 1817 #define MCAN_XIDFC_FLESA(value) (MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos)) 1818 #define MCAN_XIDFC_LSE_Pos 16 /**< (MCAN_XIDFC) List Size Extended Position */ 1819 #define MCAN_XIDFC_LSE_Msk (_U_(0x7F) << MCAN_XIDFC_LSE_Pos) /**< (MCAN_XIDFC) List Size Extended Mask */ 1820 #define MCAN_XIDFC_LSE(value) (MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos)) 1821 #define MCAN_XIDFC_MASK _U_(0x7FFFFC) /**< \deprecated (MCAN_XIDFC) Register MASK (Use MCAN_XIDFC_Msk instead) */ 1822 #define MCAN_XIDFC_Msk _U_(0x7FFFFC) /**< (MCAN_XIDFC) Register Mask */ 1823 1824 1825 /* -------- MCAN_XIDAM : (MCAN Offset: 0x90) (R/W 32) Extended ID AND Mask Register -------- */ 1826 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1827 #if COMPONENT_TYPEDEF_STYLE == 'N' 1828 typedef union { 1829 struct { 1830 uint32_t EIDM:29; /**< bit: 0..28 Extended ID Mask */ 1831 uint32_t :3; /**< bit: 29..31 Reserved */ 1832 } bit; /**< Structure used for bit access */ 1833 uint32_t reg; /**< Type used for register access */ 1834 } MCAN_XIDAM_Type; 1835 #endif 1836 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1837 1838 #define MCAN_XIDAM_OFFSET (0x90) /**< (MCAN_XIDAM) Extended ID AND Mask Register Offset */ 1839 1840 #define MCAN_XIDAM_EIDM_Pos 0 /**< (MCAN_XIDAM) Extended ID Mask Position */ 1841 #define MCAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << MCAN_XIDAM_EIDM_Pos) /**< (MCAN_XIDAM) Extended ID Mask Mask */ 1842 #define MCAN_XIDAM_EIDM(value) (MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos)) 1843 #define MCAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \deprecated (MCAN_XIDAM) Register MASK (Use MCAN_XIDAM_Msk instead) */ 1844 #define MCAN_XIDAM_Msk _U_(0x1FFFFFFF) /**< (MCAN_XIDAM) Register Mask */ 1845 1846 1847 /* -------- MCAN_HPMS : (MCAN Offset: 0x94) (R/ 32) High Priority Message Status Register -------- */ 1848 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1849 #if COMPONENT_TYPEDEF_STYLE == 'N' 1850 typedef union { 1851 struct { 1852 uint32_t BIDX:6; /**< bit: 0..5 Buffer Index */ 1853 uint32_t MSI:2; /**< bit: 6..7 Message Storage Indicator */ 1854 uint32_t FIDX:7; /**< bit: 8..14 Filter Index */ 1855 uint32_t FLST:1; /**< bit: 15 Filter List */ 1856 uint32_t :16; /**< bit: 16..31 Reserved */ 1857 } bit; /**< Structure used for bit access */ 1858 uint32_t reg; /**< Type used for register access */ 1859 } MCAN_HPMS_Type; 1860 #endif 1861 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1862 1863 #define MCAN_HPMS_OFFSET (0x94) /**< (MCAN_HPMS) High Priority Message Status Register Offset */ 1864 1865 #define MCAN_HPMS_BIDX_Pos 0 /**< (MCAN_HPMS) Buffer Index Position */ 1866 #define MCAN_HPMS_BIDX_Msk (_U_(0x3F) << MCAN_HPMS_BIDX_Pos) /**< (MCAN_HPMS) Buffer Index Mask */ 1867 #define MCAN_HPMS_BIDX(value) (MCAN_HPMS_BIDX_Msk & ((value) << MCAN_HPMS_BIDX_Pos)) 1868 #define MCAN_HPMS_MSI_Pos 6 /**< (MCAN_HPMS) Message Storage Indicator Position */ 1869 #define MCAN_HPMS_MSI_Msk (_U_(0x3) << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message Storage Indicator Mask */ 1870 #define MCAN_HPMS_MSI(value) (MCAN_HPMS_MSI_Msk & ((value) << MCAN_HPMS_MSI_Pos)) 1871 #define MCAN_HPMS_MSI_NO_FIFO_SEL_Val _U_(0x0) /**< (MCAN_HPMS) No FIFO selected. */ 1872 #define MCAN_HPMS_MSI_LOST_Val _U_(0x1) /**< (MCAN_HPMS) FIFO message lost. */ 1873 #define MCAN_HPMS_MSI_FIFO_0_Val _U_(0x2) /**< (MCAN_HPMS) Message stored in FIFO 0. */ 1874 #define MCAN_HPMS_MSI_FIFO_1_Val _U_(0x3) /**< (MCAN_HPMS) Message stored in FIFO 1. */ 1875 #define MCAN_HPMS_MSI_NO_FIFO_SEL (MCAN_HPMS_MSI_NO_FIFO_SEL_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) No FIFO selected. Position */ 1876 #define MCAN_HPMS_MSI_LOST (MCAN_HPMS_MSI_LOST_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) FIFO message lost. Position */ 1877 #define MCAN_HPMS_MSI_FIFO_0 (MCAN_HPMS_MSI_FIFO_0_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message stored in FIFO 0. Position */ 1878 #define MCAN_HPMS_MSI_FIFO_1 (MCAN_HPMS_MSI_FIFO_1_Val << MCAN_HPMS_MSI_Pos) /**< (MCAN_HPMS) Message stored in FIFO 1. Position */ 1879 #define MCAN_HPMS_FIDX_Pos 8 /**< (MCAN_HPMS) Filter Index Position */ 1880 #define MCAN_HPMS_FIDX_Msk (_U_(0x7F) << MCAN_HPMS_FIDX_Pos) /**< (MCAN_HPMS) Filter Index Mask */ 1881 #define MCAN_HPMS_FIDX(value) (MCAN_HPMS_FIDX_Msk & ((value) << MCAN_HPMS_FIDX_Pos)) 1882 #define MCAN_HPMS_FLST_Pos 15 /**< (MCAN_HPMS) Filter List Position */ 1883 #define MCAN_HPMS_FLST_Msk (_U_(0x1) << MCAN_HPMS_FLST_Pos) /**< (MCAN_HPMS) Filter List Mask */ 1884 #define MCAN_HPMS_FLST MCAN_HPMS_FLST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_HPMS_FLST_Msk instead */ 1885 #define MCAN_HPMS_MASK _U_(0xFFFF) /**< \deprecated (MCAN_HPMS) Register MASK (Use MCAN_HPMS_Msk instead) */ 1886 #define MCAN_HPMS_Msk _U_(0xFFFF) /**< (MCAN_HPMS) Register Mask */ 1887 1888 1889 /* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) (R/W 32) New Data 1 Register -------- */ 1890 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 1891 #if COMPONENT_TYPEDEF_STYLE == 'N' 1892 typedef union { 1893 struct { 1894 uint32_t ND0:1; /**< bit: 0 New Data */ 1895 uint32_t ND1:1; /**< bit: 1 New Data */ 1896 uint32_t ND2:1; /**< bit: 2 New Data */ 1897 uint32_t ND3:1; /**< bit: 3 New Data */ 1898 uint32_t ND4:1; /**< bit: 4 New Data */ 1899 uint32_t ND5:1; /**< bit: 5 New Data */ 1900 uint32_t ND6:1; /**< bit: 6 New Data */ 1901 uint32_t ND7:1; /**< bit: 7 New Data */ 1902 uint32_t ND8:1; /**< bit: 8 New Data */ 1903 uint32_t ND9:1; /**< bit: 9 New Data */ 1904 uint32_t ND10:1; /**< bit: 10 New Data */ 1905 uint32_t ND11:1; /**< bit: 11 New Data */ 1906 uint32_t ND12:1; /**< bit: 12 New Data */ 1907 uint32_t ND13:1; /**< bit: 13 New Data */ 1908 uint32_t ND14:1; /**< bit: 14 New Data */ 1909 uint32_t ND15:1; /**< bit: 15 New Data */ 1910 uint32_t ND16:1; /**< bit: 16 New Data */ 1911 uint32_t ND17:1; /**< bit: 17 New Data */ 1912 uint32_t ND18:1; /**< bit: 18 New Data */ 1913 uint32_t ND19:1; /**< bit: 19 New Data */ 1914 uint32_t ND20:1; /**< bit: 20 New Data */ 1915 uint32_t ND21:1; /**< bit: 21 New Data */ 1916 uint32_t ND22:1; /**< bit: 22 New Data */ 1917 uint32_t ND23:1; /**< bit: 23 New Data */ 1918 uint32_t ND24:1; /**< bit: 24 New Data */ 1919 uint32_t ND25:1; /**< bit: 25 New Data */ 1920 uint32_t ND26:1; /**< bit: 26 New Data */ 1921 uint32_t ND27:1; /**< bit: 27 New Data */ 1922 uint32_t ND28:1; /**< bit: 28 New Data */ 1923 uint32_t ND29:1; /**< bit: 29 New Data */ 1924 uint32_t ND30:1; /**< bit: 30 New Data */ 1925 uint32_t ND31:1; /**< bit: 31 New Data */ 1926 } bit; /**< Structure used for bit access */ 1927 struct { 1928 uint32_t ND:32; /**< bit: 0..31 New Data */ 1929 } vec; /**< Structure used for vec access */ 1930 uint32_t reg; /**< Type used for register access */ 1931 } MCAN_NDAT1_Type; 1932 #endif 1933 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 1934 1935 #define MCAN_NDAT1_OFFSET (0x98) /**< (MCAN_NDAT1) New Data 1 Register Offset */ 1936 1937 #define MCAN_NDAT1_ND0_Pos 0 /**< (MCAN_NDAT1) New Data Position */ 1938 #define MCAN_NDAT1_ND0_Msk (_U_(0x1) << MCAN_NDAT1_ND0_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1939 #define MCAN_NDAT1_ND0 MCAN_NDAT1_ND0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND0_Msk instead */ 1940 #define MCAN_NDAT1_ND1_Pos 1 /**< (MCAN_NDAT1) New Data Position */ 1941 #define MCAN_NDAT1_ND1_Msk (_U_(0x1) << MCAN_NDAT1_ND1_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1942 #define MCAN_NDAT1_ND1 MCAN_NDAT1_ND1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND1_Msk instead */ 1943 #define MCAN_NDAT1_ND2_Pos 2 /**< (MCAN_NDAT1) New Data Position */ 1944 #define MCAN_NDAT1_ND2_Msk (_U_(0x1) << MCAN_NDAT1_ND2_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1945 #define MCAN_NDAT1_ND2 MCAN_NDAT1_ND2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND2_Msk instead */ 1946 #define MCAN_NDAT1_ND3_Pos 3 /**< (MCAN_NDAT1) New Data Position */ 1947 #define MCAN_NDAT1_ND3_Msk (_U_(0x1) << MCAN_NDAT1_ND3_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1948 #define MCAN_NDAT1_ND3 MCAN_NDAT1_ND3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND3_Msk instead */ 1949 #define MCAN_NDAT1_ND4_Pos 4 /**< (MCAN_NDAT1) New Data Position */ 1950 #define MCAN_NDAT1_ND4_Msk (_U_(0x1) << MCAN_NDAT1_ND4_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1951 #define MCAN_NDAT1_ND4 MCAN_NDAT1_ND4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND4_Msk instead */ 1952 #define MCAN_NDAT1_ND5_Pos 5 /**< (MCAN_NDAT1) New Data Position */ 1953 #define MCAN_NDAT1_ND5_Msk (_U_(0x1) << MCAN_NDAT1_ND5_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1954 #define MCAN_NDAT1_ND5 MCAN_NDAT1_ND5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND5_Msk instead */ 1955 #define MCAN_NDAT1_ND6_Pos 6 /**< (MCAN_NDAT1) New Data Position */ 1956 #define MCAN_NDAT1_ND6_Msk (_U_(0x1) << MCAN_NDAT1_ND6_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1957 #define MCAN_NDAT1_ND6 MCAN_NDAT1_ND6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND6_Msk instead */ 1958 #define MCAN_NDAT1_ND7_Pos 7 /**< (MCAN_NDAT1) New Data Position */ 1959 #define MCAN_NDAT1_ND7_Msk (_U_(0x1) << MCAN_NDAT1_ND7_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1960 #define MCAN_NDAT1_ND7 MCAN_NDAT1_ND7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND7_Msk instead */ 1961 #define MCAN_NDAT1_ND8_Pos 8 /**< (MCAN_NDAT1) New Data Position */ 1962 #define MCAN_NDAT1_ND8_Msk (_U_(0x1) << MCAN_NDAT1_ND8_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1963 #define MCAN_NDAT1_ND8 MCAN_NDAT1_ND8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND8_Msk instead */ 1964 #define MCAN_NDAT1_ND9_Pos 9 /**< (MCAN_NDAT1) New Data Position */ 1965 #define MCAN_NDAT1_ND9_Msk (_U_(0x1) << MCAN_NDAT1_ND9_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1966 #define MCAN_NDAT1_ND9 MCAN_NDAT1_ND9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND9_Msk instead */ 1967 #define MCAN_NDAT1_ND10_Pos 10 /**< (MCAN_NDAT1) New Data Position */ 1968 #define MCAN_NDAT1_ND10_Msk (_U_(0x1) << MCAN_NDAT1_ND10_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1969 #define MCAN_NDAT1_ND10 MCAN_NDAT1_ND10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND10_Msk instead */ 1970 #define MCAN_NDAT1_ND11_Pos 11 /**< (MCAN_NDAT1) New Data Position */ 1971 #define MCAN_NDAT1_ND11_Msk (_U_(0x1) << MCAN_NDAT1_ND11_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1972 #define MCAN_NDAT1_ND11 MCAN_NDAT1_ND11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND11_Msk instead */ 1973 #define MCAN_NDAT1_ND12_Pos 12 /**< (MCAN_NDAT1) New Data Position */ 1974 #define MCAN_NDAT1_ND12_Msk (_U_(0x1) << MCAN_NDAT1_ND12_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1975 #define MCAN_NDAT1_ND12 MCAN_NDAT1_ND12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND12_Msk instead */ 1976 #define MCAN_NDAT1_ND13_Pos 13 /**< (MCAN_NDAT1) New Data Position */ 1977 #define MCAN_NDAT1_ND13_Msk (_U_(0x1) << MCAN_NDAT1_ND13_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1978 #define MCAN_NDAT1_ND13 MCAN_NDAT1_ND13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND13_Msk instead */ 1979 #define MCAN_NDAT1_ND14_Pos 14 /**< (MCAN_NDAT1) New Data Position */ 1980 #define MCAN_NDAT1_ND14_Msk (_U_(0x1) << MCAN_NDAT1_ND14_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1981 #define MCAN_NDAT1_ND14 MCAN_NDAT1_ND14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND14_Msk instead */ 1982 #define MCAN_NDAT1_ND15_Pos 15 /**< (MCAN_NDAT1) New Data Position */ 1983 #define MCAN_NDAT1_ND15_Msk (_U_(0x1) << MCAN_NDAT1_ND15_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1984 #define MCAN_NDAT1_ND15 MCAN_NDAT1_ND15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND15_Msk instead */ 1985 #define MCAN_NDAT1_ND16_Pos 16 /**< (MCAN_NDAT1) New Data Position */ 1986 #define MCAN_NDAT1_ND16_Msk (_U_(0x1) << MCAN_NDAT1_ND16_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1987 #define MCAN_NDAT1_ND16 MCAN_NDAT1_ND16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND16_Msk instead */ 1988 #define MCAN_NDAT1_ND17_Pos 17 /**< (MCAN_NDAT1) New Data Position */ 1989 #define MCAN_NDAT1_ND17_Msk (_U_(0x1) << MCAN_NDAT1_ND17_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1990 #define MCAN_NDAT1_ND17 MCAN_NDAT1_ND17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND17_Msk instead */ 1991 #define MCAN_NDAT1_ND18_Pos 18 /**< (MCAN_NDAT1) New Data Position */ 1992 #define MCAN_NDAT1_ND18_Msk (_U_(0x1) << MCAN_NDAT1_ND18_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1993 #define MCAN_NDAT1_ND18 MCAN_NDAT1_ND18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND18_Msk instead */ 1994 #define MCAN_NDAT1_ND19_Pos 19 /**< (MCAN_NDAT1) New Data Position */ 1995 #define MCAN_NDAT1_ND19_Msk (_U_(0x1) << MCAN_NDAT1_ND19_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1996 #define MCAN_NDAT1_ND19 MCAN_NDAT1_ND19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND19_Msk instead */ 1997 #define MCAN_NDAT1_ND20_Pos 20 /**< (MCAN_NDAT1) New Data Position */ 1998 #define MCAN_NDAT1_ND20_Msk (_U_(0x1) << MCAN_NDAT1_ND20_Pos) /**< (MCAN_NDAT1) New Data Mask */ 1999 #define MCAN_NDAT1_ND20 MCAN_NDAT1_ND20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND20_Msk instead */ 2000 #define MCAN_NDAT1_ND21_Pos 21 /**< (MCAN_NDAT1) New Data Position */ 2001 #define MCAN_NDAT1_ND21_Msk (_U_(0x1) << MCAN_NDAT1_ND21_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2002 #define MCAN_NDAT1_ND21 MCAN_NDAT1_ND21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND21_Msk instead */ 2003 #define MCAN_NDAT1_ND22_Pos 22 /**< (MCAN_NDAT1) New Data Position */ 2004 #define MCAN_NDAT1_ND22_Msk (_U_(0x1) << MCAN_NDAT1_ND22_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2005 #define MCAN_NDAT1_ND22 MCAN_NDAT1_ND22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND22_Msk instead */ 2006 #define MCAN_NDAT1_ND23_Pos 23 /**< (MCAN_NDAT1) New Data Position */ 2007 #define MCAN_NDAT1_ND23_Msk (_U_(0x1) << MCAN_NDAT1_ND23_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2008 #define MCAN_NDAT1_ND23 MCAN_NDAT1_ND23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND23_Msk instead */ 2009 #define MCAN_NDAT1_ND24_Pos 24 /**< (MCAN_NDAT1) New Data Position */ 2010 #define MCAN_NDAT1_ND24_Msk (_U_(0x1) << MCAN_NDAT1_ND24_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2011 #define MCAN_NDAT1_ND24 MCAN_NDAT1_ND24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND24_Msk instead */ 2012 #define MCAN_NDAT1_ND25_Pos 25 /**< (MCAN_NDAT1) New Data Position */ 2013 #define MCAN_NDAT1_ND25_Msk (_U_(0x1) << MCAN_NDAT1_ND25_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2014 #define MCAN_NDAT1_ND25 MCAN_NDAT1_ND25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND25_Msk instead */ 2015 #define MCAN_NDAT1_ND26_Pos 26 /**< (MCAN_NDAT1) New Data Position */ 2016 #define MCAN_NDAT1_ND26_Msk (_U_(0x1) << MCAN_NDAT1_ND26_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2017 #define MCAN_NDAT1_ND26 MCAN_NDAT1_ND26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND26_Msk instead */ 2018 #define MCAN_NDAT1_ND27_Pos 27 /**< (MCAN_NDAT1) New Data Position */ 2019 #define MCAN_NDAT1_ND27_Msk (_U_(0x1) << MCAN_NDAT1_ND27_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2020 #define MCAN_NDAT1_ND27 MCAN_NDAT1_ND27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND27_Msk instead */ 2021 #define MCAN_NDAT1_ND28_Pos 28 /**< (MCAN_NDAT1) New Data Position */ 2022 #define MCAN_NDAT1_ND28_Msk (_U_(0x1) << MCAN_NDAT1_ND28_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2023 #define MCAN_NDAT1_ND28 MCAN_NDAT1_ND28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND28_Msk instead */ 2024 #define MCAN_NDAT1_ND29_Pos 29 /**< (MCAN_NDAT1) New Data Position */ 2025 #define MCAN_NDAT1_ND29_Msk (_U_(0x1) << MCAN_NDAT1_ND29_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2026 #define MCAN_NDAT1_ND29 MCAN_NDAT1_ND29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND29_Msk instead */ 2027 #define MCAN_NDAT1_ND30_Pos 30 /**< (MCAN_NDAT1) New Data Position */ 2028 #define MCAN_NDAT1_ND30_Msk (_U_(0x1) << MCAN_NDAT1_ND30_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2029 #define MCAN_NDAT1_ND30 MCAN_NDAT1_ND30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND30_Msk instead */ 2030 #define MCAN_NDAT1_ND31_Pos 31 /**< (MCAN_NDAT1) New Data Position */ 2031 #define MCAN_NDAT1_ND31_Msk (_U_(0x1) << MCAN_NDAT1_ND31_Pos) /**< (MCAN_NDAT1) New Data Mask */ 2032 #define MCAN_NDAT1_ND31 MCAN_NDAT1_ND31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT1_ND31_Msk instead */ 2033 #define MCAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_NDAT1) Register MASK (Use MCAN_NDAT1_Msk instead) */ 2034 #define MCAN_NDAT1_Msk _U_(0xFFFFFFFF) /**< (MCAN_NDAT1) Register Mask */ 2035 2036 #define MCAN_NDAT1_ND_Pos 0 /**< (MCAN_NDAT1 Position) New Data */ 2037 #define MCAN_NDAT1_ND_Msk (_U_(0xFFFFFFFF) << MCAN_NDAT1_ND_Pos) /**< (MCAN_NDAT1 Mask) ND */ 2038 #define MCAN_NDAT1_ND(value) (MCAN_NDAT1_ND_Msk & ((value) << MCAN_NDAT1_ND_Pos)) 2039 2040 /* -------- MCAN_NDAT2 : (MCAN Offset: 0x9c) (R/W 32) New Data 2 Register -------- */ 2041 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2042 #if COMPONENT_TYPEDEF_STYLE == 'N' 2043 typedef union { 2044 struct { 2045 uint32_t ND32:1; /**< bit: 0 New Data */ 2046 uint32_t ND33:1; /**< bit: 1 New Data */ 2047 uint32_t ND34:1; /**< bit: 2 New Data */ 2048 uint32_t ND35:1; /**< bit: 3 New Data */ 2049 uint32_t ND36:1; /**< bit: 4 New Data */ 2050 uint32_t ND37:1; /**< bit: 5 New Data */ 2051 uint32_t ND38:1; /**< bit: 6 New Data */ 2052 uint32_t ND39:1; /**< bit: 7 New Data */ 2053 uint32_t ND40:1; /**< bit: 8 New Data */ 2054 uint32_t ND41:1; /**< bit: 9 New Data */ 2055 uint32_t ND42:1; /**< bit: 10 New Data */ 2056 uint32_t ND43:1; /**< bit: 11 New Data */ 2057 uint32_t ND44:1; /**< bit: 12 New Data */ 2058 uint32_t ND45:1; /**< bit: 13 New Data */ 2059 uint32_t ND46:1; /**< bit: 14 New Data */ 2060 uint32_t ND47:1; /**< bit: 15 New Data */ 2061 uint32_t ND48:1; /**< bit: 16 New Data */ 2062 uint32_t ND49:1; /**< bit: 17 New Data */ 2063 uint32_t ND50:1; /**< bit: 18 New Data */ 2064 uint32_t ND51:1; /**< bit: 19 New Data */ 2065 uint32_t ND52:1; /**< bit: 20 New Data */ 2066 uint32_t ND53:1; /**< bit: 21 New Data */ 2067 uint32_t ND54:1; /**< bit: 22 New Data */ 2068 uint32_t ND55:1; /**< bit: 23 New Data */ 2069 uint32_t ND56:1; /**< bit: 24 New Data */ 2070 uint32_t ND57:1; /**< bit: 25 New Data */ 2071 uint32_t ND58:1; /**< bit: 26 New Data */ 2072 uint32_t ND59:1; /**< bit: 27 New Data */ 2073 uint32_t ND60:1; /**< bit: 28 New Data */ 2074 uint32_t ND61:1; /**< bit: 29 New Data */ 2075 uint32_t ND62:1; /**< bit: 30 New Data */ 2076 uint32_t ND63:1; /**< bit: 31 New Data */ 2077 } bit; /**< Structure used for bit access */ 2078 struct { 2079 uint32_t ND:32; /**< bit: 0..31 New Data */ 2080 } vec; /**< Structure used for vec access */ 2081 uint32_t reg; /**< Type used for register access */ 2082 } MCAN_NDAT2_Type; 2083 #endif 2084 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2085 2086 #define MCAN_NDAT2_OFFSET (0x9C) /**< (MCAN_NDAT2) New Data 2 Register Offset */ 2087 2088 #define MCAN_NDAT2_ND32_Pos 0 /**< (MCAN_NDAT2) New Data Position */ 2089 #define MCAN_NDAT2_ND32_Msk (_U_(0x1) << MCAN_NDAT2_ND32_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2090 #define MCAN_NDAT2_ND32 MCAN_NDAT2_ND32_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND32_Msk instead */ 2091 #define MCAN_NDAT2_ND33_Pos 1 /**< (MCAN_NDAT2) New Data Position */ 2092 #define MCAN_NDAT2_ND33_Msk (_U_(0x1) << MCAN_NDAT2_ND33_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2093 #define MCAN_NDAT2_ND33 MCAN_NDAT2_ND33_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND33_Msk instead */ 2094 #define MCAN_NDAT2_ND34_Pos 2 /**< (MCAN_NDAT2) New Data Position */ 2095 #define MCAN_NDAT2_ND34_Msk (_U_(0x1) << MCAN_NDAT2_ND34_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2096 #define MCAN_NDAT2_ND34 MCAN_NDAT2_ND34_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND34_Msk instead */ 2097 #define MCAN_NDAT2_ND35_Pos 3 /**< (MCAN_NDAT2) New Data Position */ 2098 #define MCAN_NDAT2_ND35_Msk (_U_(0x1) << MCAN_NDAT2_ND35_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2099 #define MCAN_NDAT2_ND35 MCAN_NDAT2_ND35_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND35_Msk instead */ 2100 #define MCAN_NDAT2_ND36_Pos 4 /**< (MCAN_NDAT2) New Data Position */ 2101 #define MCAN_NDAT2_ND36_Msk (_U_(0x1) << MCAN_NDAT2_ND36_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2102 #define MCAN_NDAT2_ND36 MCAN_NDAT2_ND36_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND36_Msk instead */ 2103 #define MCAN_NDAT2_ND37_Pos 5 /**< (MCAN_NDAT2) New Data Position */ 2104 #define MCAN_NDAT2_ND37_Msk (_U_(0x1) << MCAN_NDAT2_ND37_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2105 #define MCAN_NDAT2_ND37 MCAN_NDAT2_ND37_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND37_Msk instead */ 2106 #define MCAN_NDAT2_ND38_Pos 6 /**< (MCAN_NDAT2) New Data Position */ 2107 #define MCAN_NDAT2_ND38_Msk (_U_(0x1) << MCAN_NDAT2_ND38_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2108 #define MCAN_NDAT2_ND38 MCAN_NDAT2_ND38_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND38_Msk instead */ 2109 #define MCAN_NDAT2_ND39_Pos 7 /**< (MCAN_NDAT2) New Data Position */ 2110 #define MCAN_NDAT2_ND39_Msk (_U_(0x1) << MCAN_NDAT2_ND39_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2111 #define MCAN_NDAT2_ND39 MCAN_NDAT2_ND39_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND39_Msk instead */ 2112 #define MCAN_NDAT2_ND40_Pos 8 /**< (MCAN_NDAT2) New Data Position */ 2113 #define MCAN_NDAT2_ND40_Msk (_U_(0x1) << MCAN_NDAT2_ND40_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2114 #define MCAN_NDAT2_ND40 MCAN_NDAT2_ND40_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND40_Msk instead */ 2115 #define MCAN_NDAT2_ND41_Pos 9 /**< (MCAN_NDAT2) New Data Position */ 2116 #define MCAN_NDAT2_ND41_Msk (_U_(0x1) << MCAN_NDAT2_ND41_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2117 #define MCAN_NDAT2_ND41 MCAN_NDAT2_ND41_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND41_Msk instead */ 2118 #define MCAN_NDAT2_ND42_Pos 10 /**< (MCAN_NDAT2) New Data Position */ 2119 #define MCAN_NDAT2_ND42_Msk (_U_(0x1) << MCAN_NDAT2_ND42_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2120 #define MCAN_NDAT2_ND42 MCAN_NDAT2_ND42_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND42_Msk instead */ 2121 #define MCAN_NDAT2_ND43_Pos 11 /**< (MCAN_NDAT2) New Data Position */ 2122 #define MCAN_NDAT2_ND43_Msk (_U_(0x1) << MCAN_NDAT2_ND43_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2123 #define MCAN_NDAT2_ND43 MCAN_NDAT2_ND43_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND43_Msk instead */ 2124 #define MCAN_NDAT2_ND44_Pos 12 /**< (MCAN_NDAT2) New Data Position */ 2125 #define MCAN_NDAT2_ND44_Msk (_U_(0x1) << MCAN_NDAT2_ND44_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2126 #define MCAN_NDAT2_ND44 MCAN_NDAT2_ND44_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND44_Msk instead */ 2127 #define MCAN_NDAT2_ND45_Pos 13 /**< (MCAN_NDAT2) New Data Position */ 2128 #define MCAN_NDAT2_ND45_Msk (_U_(0x1) << MCAN_NDAT2_ND45_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2129 #define MCAN_NDAT2_ND45 MCAN_NDAT2_ND45_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND45_Msk instead */ 2130 #define MCAN_NDAT2_ND46_Pos 14 /**< (MCAN_NDAT2) New Data Position */ 2131 #define MCAN_NDAT2_ND46_Msk (_U_(0x1) << MCAN_NDAT2_ND46_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2132 #define MCAN_NDAT2_ND46 MCAN_NDAT2_ND46_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND46_Msk instead */ 2133 #define MCAN_NDAT2_ND47_Pos 15 /**< (MCAN_NDAT2) New Data Position */ 2134 #define MCAN_NDAT2_ND47_Msk (_U_(0x1) << MCAN_NDAT2_ND47_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2135 #define MCAN_NDAT2_ND47 MCAN_NDAT2_ND47_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND47_Msk instead */ 2136 #define MCAN_NDAT2_ND48_Pos 16 /**< (MCAN_NDAT2) New Data Position */ 2137 #define MCAN_NDAT2_ND48_Msk (_U_(0x1) << MCAN_NDAT2_ND48_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2138 #define MCAN_NDAT2_ND48 MCAN_NDAT2_ND48_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND48_Msk instead */ 2139 #define MCAN_NDAT2_ND49_Pos 17 /**< (MCAN_NDAT2) New Data Position */ 2140 #define MCAN_NDAT2_ND49_Msk (_U_(0x1) << MCAN_NDAT2_ND49_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2141 #define MCAN_NDAT2_ND49 MCAN_NDAT2_ND49_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND49_Msk instead */ 2142 #define MCAN_NDAT2_ND50_Pos 18 /**< (MCAN_NDAT2) New Data Position */ 2143 #define MCAN_NDAT2_ND50_Msk (_U_(0x1) << MCAN_NDAT2_ND50_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2144 #define MCAN_NDAT2_ND50 MCAN_NDAT2_ND50_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND50_Msk instead */ 2145 #define MCAN_NDAT2_ND51_Pos 19 /**< (MCAN_NDAT2) New Data Position */ 2146 #define MCAN_NDAT2_ND51_Msk (_U_(0x1) << MCAN_NDAT2_ND51_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2147 #define MCAN_NDAT2_ND51 MCAN_NDAT2_ND51_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND51_Msk instead */ 2148 #define MCAN_NDAT2_ND52_Pos 20 /**< (MCAN_NDAT2) New Data Position */ 2149 #define MCAN_NDAT2_ND52_Msk (_U_(0x1) << MCAN_NDAT2_ND52_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2150 #define MCAN_NDAT2_ND52 MCAN_NDAT2_ND52_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND52_Msk instead */ 2151 #define MCAN_NDAT2_ND53_Pos 21 /**< (MCAN_NDAT2) New Data Position */ 2152 #define MCAN_NDAT2_ND53_Msk (_U_(0x1) << MCAN_NDAT2_ND53_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2153 #define MCAN_NDAT2_ND53 MCAN_NDAT2_ND53_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND53_Msk instead */ 2154 #define MCAN_NDAT2_ND54_Pos 22 /**< (MCAN_NDAT2) New Data Position */ 2155 #define MCAN_NDAT2_ND54_Msk (_U_(0x1) << MCAN_NDAT2_ND54_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2156 #define MCAN_NDAT2_ND54 MCAN_NDAT2_ND54_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND54_Msk instead */ 2157 #define MCAN_NDAT2_ND55_Pos 23 /**< (MCAN_NDAT2) New Data Position */ 2158 #define MCAN_NDAT2_ND55_Msk (_U_(0x1) << MCAN_NDAT2_ND55_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2159 #define MCAN_NDAT2_ND55 MCAN_NDAT2_ND55_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND55_Msk instead */ 2160 #define MCAN_NDAT2_ND56_Pos 24 /**< (MCAN_NDAT2) New Data Position */ 2161 #define MCAN_NDAT2_ND56_Msk (_U_(0x1) << MCAN_NDAT2_ND56_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2162 #define MCAN_NDAT2_ND56 MCAN_NDAT2_ND56_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND56_Msk instead */ 2163 #define MCAN_NDAT2_ND57_Pos 25 /**< (MCAN_NDAT2) New Data Position */ 2164 #define MCAN_NDAT2_ND57_Msk (_U_(0x1) << MCAN_NDAT2_ND57_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2165 #define MCAN_NDAT2_ND57 MCAN_NDAT2_ND57_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND57_Msk instead */ 2166 #define MCAN_NDAT2_ND58_Pos 26 /**< (MCAN_NDAT2) New Data Position */ 2167 #define MCAN_NDAT2_ND58_Msk (_U_(0x1) << MCAN_NDAT2_ND58_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2168 #define MCAN_NDAT2_ND58 MCAN_NDAT2_ND58_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND58_Msk instead */ 2169 #define MCAN_NDAT2_ND59_Pos 27 /**< (MCAN_NDAT2) New Data Position */ 2170 #define MCAN_NDAT2_ND59_Msk (_U_(0x1) << MCAN_NDAT2_ND59_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2171 #define MCAN_NDAT2_ND59 MCAN_NDAT2_ND59_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND59_Msk instead */ 2172 #define MCAN_NDAT2_ND60_Pos 28 /**< (MCAN_NDAT2) New Data Position */ 2173 #define MCAN_NDAT2_ND60_Msk (_U_(0x1) << MCAN_NDAT2_ND60_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2174 #define MCAN_NDAT2_ND60 MCAN_NDAT2_ND60_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND60_Msk instead */ 2175 #define MCAN_NDAT2_ND61_Pos 29 /**< (MCAN_NDAT2) New Data Position */ 2176 #define MCAN_NDAT2_ND61_Msk (_U_(0x1) << MCAN_NDAT2_ND61_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2177 #define MCAN_NDAT2_ND61 MCAN_NDAT2_ND61_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND61_Msk instead */ 2178 #define MCAN_NDAT2_ND62_Pos 30 /**< (MCAN_NDAT2) New Data Position */ 2179 #define MCAN_NDAT2_ND62_Msk (_U_(0x1) << MCAN_NDAT2_ND62_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2180 #define MCAN_NDAT2_ND62 MCAN_NDAT2_ND62_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND62_Msk instead */ 2181 #define MCAN_NDAT2_ND63_Pos 31 /**< (MCAN_NDAT2) New Data Position */ 2182 #define MCAN_NDAT2_ND63_Msk (_U_(0x1) << MCAN_NDAT2_ND63_Pos) /**< (MCAN_NDAT2) New Data Mask */ 2183 #define MCAN_NDAT2_ND63 MCAN_NDAT2_ND63_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_NDAT2_ND63_Msk instead */ 2184 #define MCAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_NDAT2) Register MASK (Use MCAN_NDAT2_Msk instead) */ 2185 #define MCAN_NDAT2_Msk _U_(0xFFFFFFFF) /**< (MCAN_NDAT2) Register Mask */ 2186 2187 #define MCAN_NDAT2_ND_Pos 0 /**< (MCAN_NDAT2 Position) New Data */ 2188 #define MCAN_NDAT2_ND_Msk (_U_(0xFFFFFFFF) << MCAN_NDAT2_ND_Pos) /**< (MCAN_NDAT2 Mask) ND */ 2189 #define MCAN_NDAT2_ND(value) (MCAN_NDAT2_ND_Msk & ((value) << MCAN_NDAT2_ND_Pos)) 2190 2191 /* -------- MCAN_RXF0C : (MCAN Offset: 0xa0) (R/W 32) Receive FIFO 0 Configuration Register -------- */ 2192 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2193 #if COMPONENT_TYPEDEF_STYLE == 'N' 2194 typedef union { 2195 struct { 2196 uint32_t :2; /**< bit: 0..1 Reserved */ 2197 uint32_t F0SA:14; /**< bit: 2..15 Receive FIFO 0 Start Address */ 2198 uint32_t F0S:7; /**< bit: 16..22 Receive FIFO 0 Start Address */ 2199 uint32_t :1; /**< bit: 23 Reserved */ 2200 uint32_t F0WM:7; /**< bit: 24..30 Receive FIFO 0 Watermark */ 2201 uint32_t F0OM:1; /**< bit: 31 FIFO 0 Operation Mode */ 2202 } bit; /**< Structure used for bit access */ 2203 uint32_t reg; /**< Type used for register access */ 2204 } MCAN_RXF0C_Type; 2205 #endif 2206 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2207 2208 #define MCAN_RXF0C_OFFSET (0xA0) /**< (MCAN_RXF0C) Receive FIFO 0 Configuration Register Offset */ 2209 2210 #define MCAN_RXF0C_F0SA_Pos 2 /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Position */ 2211 #define MCAN_RXF0C_F0SA_Msk (_U_(0x3FFF) << MCAN_RXF0C_F0SA_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Mask */ 2212 #define MCAN_RXF0C_F0SA(value) (MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos)) 2213 #define MCAN_RXF0C_F0S_Pos 16 /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Position */ 2214 #define MCAN_RXF0C_F0S_Msk (_U_(0x7F) << MCAN_RXF0C_F0S_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Start Address Mask */ 2215 #define MCAN_RXF0C_F0S(value) (MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos)) 2216 #define MCAN_RXF0C_F0WM_Pos 24 /**< (MCAN_RXF0C) Receive FIFO 0 Watermark Position */ 2217 #define MCAN_RXF0C_F0WM_Msk (_U_(0x7F) << MCAN_RXF0C_F0WM_Pos) /**< (MCAN_RXF0C) Receive FIFO 0 Watermark Mask */ 2218 #define MCAN_RXF0C_F0WM(value) (MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos)) 2219 #define MCAN_RXF0C_F0OM_Pos 31 /**< (MCAN_RXF0C) FIFO 0 Operation Mode Position */ 2220 #define MCAN_RXF0C_F0OM_Msk (_U_(0x1) << MCAN_RXF0C_F0OM_Pos) /**< (MCAN_RXF0C) FIFO 0 Operation Mode Mask */ 2221 #define MCAN_RXF0C_F0OM MCAN_RXF0C_F0OM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0C_F0OM_Msk instead */ 2222 #define MCAN_RXF0C_MASK _U_(0xFF7FFFFC) /**< \deprecated (MCAN_RXF0C) Register MASK (Use MCAN_RXF0C_Msk instead) */ 2223 #define MCAN_RXF0C_Msk _U_(0xFF7FFFFC) /**< (MCAN_RXF0C) Register Mask */ 2224 2225 2226 /* -------- MCAN_RXF0S : (MCAN Offset: 0xa4) (R/ 32) Receive FIFO 0 Status Register -------- */ 2227 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2228 #if COMPONENT_TYPEDEF_STYLE == 'N' 2229 typedef union { 2230 struct { 2231 uint32_t F0FL:7; /**< bit: 0..6 Receive FIFO 0 Fill Level */ 2232 uint32_t :1; /**< bit: 7 Reserved */ 2233 uint32_t F0GI:6; /**< bit: 8..13 Receive FIFO 0 Get Index */ 2234 uint32_t :2; /**< bit: 14..15 Reserved */ 2235 uint32_t F0PI:6; /**< bit: 16..21 Receive FIFO 0 Put Index */ 2236 uint32_t :2; /**< bit: 22..23 Reserved */ 2237 uint32_t F0F:1; /**< bit: 24 Receive FIFO 0 Fill Level */ 2238 uint32_t RF0L:1; /**< bit: 25 Receive FIFO 0 Message Lost */ 2239 uint32_t :6; /**< bit: 26..31 Reserved */ 2240 } bit; /**< Structure used for bit access */ 2241 uint32_t reg; /**< Type used for register access */ 2242 } MCAN_RXF0S_Type; 2243 #endif 2244 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2245 2246 #define MCAN_RXF0S_OFFSET (0xA4) /**< (MCAN_RXF0S) Receive FIFO 0 Status Register Offset */ 2247 2248 #define MCAN_RXF0S_F0FL_Pos 0 /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Position */ 2249 #define MCAN_RXF0S_F0FL_Msk (_U_(0x7F) << MCAN_RXF0S_F0FL_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Mask */ 2250 #define MCAN_RXF0S_F0FL(value) (MCAN_RXF0S_F0FL_Msk & ((value) << MCAN_RXF0S_F0FL_Pos)) 2251 #define MCAN_RXF0S_F0GI_Pos 8 /**< (MCAN_RXF0S) Receive FIFO 0 Get Index Position */ 2252 #define MCAN_RXF0S_F0GI_Msk (_U_(0x3F) << MCAN_RXF0S_F0GI_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Get Index Mask */ 2253 #define MCAN_RXF0S_F0GI(value) (MCAN_RXF0S_F0GI_Msk & ((value) << MCAN_RXF0S_F0GI_Pos)) 2254 #define MCAN_RXF0S_F0PI_Pos 16 /**< (MCAN_RXF0S) Receive FIFO 0 Put Index Position */ 2255 #define MCAN_RXF0S_F0PI_Msk (_U_(0x3F) << MCAN_RXF0S_F0PI_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Put Index Mask */ 2256 #define MCAN_RXF0S_F0PI(value) (MCAN_RXF0S_F0PI_Msk & ((value) << MCAN_RXF0S_F0PI_Pos)) 2257 #define MCAN_RXF0S_F0F_Pos 24 /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Position */ 2258 #define MCAN_RXF0S_F0F_Msk (_U_(0x1) << MCAN_RXF0S_F0F_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Fill Level Mask */ 2259 #define MCAN_RXF0S_F0F MCAN_RXF0S_F0F_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0S_F0F_Msk instead */ 2260 #define MCAN_RXF0S_RF0L_Pos 25 /**< (MCAN_RXF0S) Receive FIFO 0 Message Lost Position */ 2261 #define MCAN_RXF0S_RF0L_Msk (_U_(0x1) << MCAN_RXF0S_RF0L_Pos) /**< (MCAN_RXF0S) Receive FIFO 0 Message Lost Mask */ 2262 #define MCAN_RXF0S_RF0L MCAN_RXF0S_RF0L_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF0S_RF0L_Msk instead */ 2263 #define MCAN_RXF0S_MASK _U_(0x33F3F7F) /**< \deprecated (MCAN_RXF0S) Register MASK (Use MCAN_RXF0S_Msk instead) */ 2264 #define MCAN_RXF0S_Msk _U_(0x33F3F7F) /**< (MCAN_RXF0S) Register Mask */ 2265 2266 2267 /* -------- MCAN_RXF0A : (MCAN Offset: 0xa8) (R/W 32) Receive FIFO 0 Acknowledge Register -------- */ 2268 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2269 #if COMPONENT_TYPEDEF_STYLE == 'N' 2270 typedef union { 2271 struct { 2272 uint32_t F0AI:6; /**< bit: 0..5 Receive FIFO 0 Acknowledge Index */ 2273 uint32_t :26; /**< bit: 6..31 Reserved */ 2274 } bit; /**< Structure used for bit access */ 2275 uint32_t reg; /**< Type used for register access */ 2276 } MCAN_RXF0A_Type; 2277 #endif 2278 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2279 2280 #define MCAN_RXF0A_OFFSET (0xA8) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Register Offset */ 2281 2282 #define MCAN_RXF0A_F0AI_Pos 0 /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index Position */ 2283 #define MCAN_RXF0A_F0AI_Msk (_U_(0x3F) << MCAN_RXF0A_F0AI_Pos) /**< (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index Mask */ 2284 #define MCAN_RXF0A_F0AI(value) (MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos)) 2285 #define MCAN_RXF0A_MASK _U_(0x3F) /**< \deprecated (MCAN_RXF0A) Register MASK (Use MCAN_RXF0A_Msk instead) */ 2286 #define MCAN_RXF0A_Msk _U_(0x3F) /**< (MCAN_RXF0A) Register Mask */ 2287 2288 2289 /* -------- MCAN_RXBC : (MCAN Offset: 0xac) (R/W 32) Receive Rx Buffer Configuration Register -------- */ 2290 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2291 #if COMPONENT_TYPEDEF_STYLE == 'N' 2292 typedef union { 2293 struct { 2294 uint32_t :2; /**< bit: 0..1 Reserved */ 2295 uint32_t RBSA:14; /**< bit: 2..15 Receive Buffer Start Address */ 2296 uint32_t :16; /**< bit: 16..31 Reserved */ 2297 } bit; /**< Structure used for bit access */ 2298 uint32_t reg; /**< Type used for register access */ 2299 } MCAN_RXBC_Type; 2300 #endif 2301 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2302 2303 #define MCAN_RXBC_OFFSET (0xAC) /**< (MCAN_RXBC) Receive Rx Buffer Configuration Register Offset */ 2304 2305 #define MCAN_RXBC_RBSA_Pos 2 /**< (MCAN_RXBC) Receive Buffer Start Address Position */ 2306 #define MCAN_RXBC_RBSA_Msk (_U_(0x3FFF) << MCAN_RXBC_RBSA_Pos) /**< (MCAN_RXBC) Receive Buffer Start Address Mask */ 2307 #define MCAN_RXBC_RBSA(value) (MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos)) 2308 #define MCAN_RXBC_MASK _U_(0xFFFC) /**< \deprecated (MCAN_RXBC) Register MASK (Use MCAN_RXBC_Msk instead) */ 2309 #define MCAN_RXBC_Msk _U_(0xFFFC) /**< (MCAN_RXBC) Register Mask */ 2310 2311 2312 /* -------- MCAN_RXF1C : (MCAN Offset: 0xb0) (R/W 32) Receive FIFO 1 Configuration Register -------- */ 2313 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2314 #if COMPONENT_TYPEDEF_STYLE == 'N' 2315 typedef union { 2316 struct { 2317 uint32_t :2; /**< bit: 0..1 Reserved */ 2318 uint32_t F1SA:14; /**< bit: 2..15 Receive FIFO 1 Start Address */ 2319 uint32_t F1S:7; /**< bit: 16..22 Receive FIFO 1 Start Address */ 2320 uint32_t :1; /**< bit: 23 Reserved */ 2321 uint32_t F1WM:7; /**< bit: 24..30 Receive FIFO 1 Watermark */ 2322 uint32_t F1OM:1; /**< bit: 31 FIFO 1 Operation Mode */ 2323 } bit; /**< Structure used for bit access */ 2324 uint32_t reg; /**< Type used for register access */ 2325 } MCAN_RXF1C_Type; 2326 #endif 2327 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2328 2329 #define MCAN_RXF1C_OFFSET (0xB0) /**< (MCAN_RXF1C) Receive FIFO 1 Configuration Register Offset */ 2330 2331 #define MCAN_RXF1C_F1SA_Pos 2 /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Position */ 2332 #define MCAN_RXF1C_F1SA_Msk (_U_(0x3FFF) << MCAN_RXF1C_F1SA_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Mask */ 2333 #define MCAN_RXF1C_F1SA(value) (MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos)) 2334 #define MCAN_RXF1C_F1S_Pos 16 /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Position */ 2335 #define MCAN_RXF1C_F1S_Msk (_U_(0x7F) << MCAN_RXF1C_F1S_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Start Address Mask */ 2336 #define MCAN_RXF1C_F1S(value) (MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos)) 2337 #define MCAN_RXF1C_F1WM_Pos 24 /**< (MCAN_RXF1C) Receive FIFO 1 Watermark Position */ 2338 #define MCAN_RXF1C_F1WM_Msk (_U_(0x7F) << MCAN_RXF1C_F1WM_Pos) /**< (MCAN_RXF1C) Receive FIFO 1 Watermark Mask */ 2339 #define MCAN_RXF1C_F1WM(value) (MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos)) 2340 #define MCAN_RXF1C_F1OM_Pos 31 /**< (MCAN_RXF1C) FIFO 1 Operation Mode Position */ 2341 #define MCAN_RXF1C_F1OM_Msk (_U_(0x1) << MCAN_RXF1C_F1OM_Pos) /**< (MCAN_RXF1C) FIFO 1 Operation Mode Mask */ 2342 #define MCAN_RXF1C_F1OM MCAN_RXF1C_F1OM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1C_F1OM_Msk instead */ 2343 #define MCAN_RXF1C_MASK _U_(0xFF7FFFFC) /**< \deprecated (MCAN_RXF1C) Register MASK (Use MCAN_RXF1C_Msk instead) */ 2344 #define MCAN_RXF1C_Msk _U_(0xFF7FFFFC) /**< (MCAN_RXF1C) Register Mask */ 2345 2346 2347 /* -------- MCAN_RXF1S : (MCAN Offset: 0xb4) (R/ 32) Receive FIFO 1 Status Register -------- */ 2348 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2349 #if COMPONENT_TYPEDEF_STYLE == 'N' 2350 typedef union { 2351 struct { 2352 uint32_t F1FL:7; /**< bit: 0..6 Receive FIFO 1 Fill Level */ 2353 uint32_t :1; /**< bit: 7 Reserved */ 2354 uint32_t F1GI:6; /**< bit: 8..13 Receive FIFO 1 Get Index */ 2355 uint32_t :2; /**< bit: 14..15 Reserved */ 2356 uint32_t F1PI:6; /**< bit: 16..21 Receive FIFO 1 Put Index */ 2357 uint32_t :2; /**< bit: 22..23 Reserved */ 2358 uint32_t F1F:1; /**< bit: 24 Receive FIFO 1 Fill Level */ 2359 uint32_t RF1L:1; /**< bit: 25 Receive FIFO 1 Message Lost */ 2360 uint32_t :4; /**< bit: 26..29 Reserved */ 2361 uint32_t DMS:2; /**< bit: 30..31 Debug Message Status */ 2362 } bit; /**< Structure used for bit access */ 2363 uint32_t reg; /**< Type used for register access */ 2364 } MCAN_RXF1S_Type; 2365 #endif 2366 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2367 2368 #define MCAN_RXF1S_OFFSET (0xB4) /**< (MCAN_RXF1S) Receive FIFO 1 Status Register Offset */ 2369 2370 #define MCAN_RXF1S_F1FL_Pos 0 /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Position */ 2371 #define MCAN_RXF1S_F1FL_Msk (_U_(0x7F) << MCAN_RXF1S_F1FL_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Mask */ 2372 #define MCAN_RXF1S_F1FL(value) (MCAN_RXF1S_F1FL_Msk & ((value) << MCAN_RXF1S_F1FL_Pos)) 2373 #define MCAN_RXF1S_F1GI_Pos 8 /**< (MCAN_RXF1S) Receive FIFO 1 Get Index Position */ 2374 #define MCAN_RXF1S_F1GI_Msk (_U_(0x3F) << MCAN_RXF1S_F1GI_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Get Index Mask */ 2375 #define MCAN_RXF1S_F1GI(value) (MCAN_RXF1S_F1GI_Msk & ((value) << MCAN_RXF1S_F1GI_Pos)) 2376 #define MCAN_RXF1S_F1PI_Pos 16 /**< (MCAN_RXF1S) Receive FIFO 1 Put Index Position */ 2377 #define MCAN_RXF1S_F1PI_Msk (_U_(0x3F) << MCAN_RXF1S_F1PI_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Put Index Mask */ 2378 #define MCAN_RXF1S_F1PI(value) (MCAN_RXF1S_F1PI_Msk & ((value) << MCAN_RXF1S_F1PI_Pos)) 2379 #define MCAN_RXF1S_F1F_Pos 24 /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Position */ 2380 #define MCAN_RXF1S_F1F_Msk (_U_(0x1) << MCAN_RXF1S_F1F_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Fill Level Mask */ 2381 #define MCAN_RXF1S_F1F MCAN_RXF1S_F1F_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1S_F1F_Msk instead */ 2382 #define MCAN_RXF1S_RF1L_Pos 25 /**< (MCAN_RXF1S) Receive FIFO 1 Message Lost Position */ 2383 #define MCAN_RXF1S_RF1L_Msk (_U_(0x1) << MCAN_RXF1S_RF1L_Pos) /**< (MCAN_RXF1S) Receive FIFO 1 Message Lost Mask */ 2384 #define MCAN_RXF1S_RF1L MCAN_RXF1S_RF1L_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_RXF1S_RF1L_Msk instead */ 2385 #define MCAN_RXF1S_DMS_Pos 30 /**< (MCAN_RXF1S) Debug Message Status Position */ 2386 #define MCAN_RXF1S_DMS_Msk (_U_(0x3) << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug Message Status Mask */ 2387 #define MCAN_RXF1S_DMS(value) (MCAN_RXF1S_DMS_Msk & ((value) << MCAN_RXF1S_DMS_Pos)) 2388 #define MCAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ 2389 #define MCAN_RXF1S_DMS_MSG_A_Val _U_(0x1) /**< (MCAN_RXF1S) Debug message A received. */ 2390 #define MCAN_RXF1S_DMS_MSG_AB_Val _U_(0x2) /**< (MCAN_RXF1S) Debug messages A, B received. */ 2391 #define MCAN_RXF1S_DMS_MSG_ABC_Val _U_(0x3) /**< (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ 2392 #define MCAN_RXF1S_DMS_IDLE (MCAN_RXF1S_DMS_IDLE_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. Position */ 2393 #define MCAN_RXF1S_DMS_MSG_A (MCAN_RXF1S_DMS_MSG_A_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug message A received. Position */ 2394 #define MCAN_RXF1S_DMS_MSG_AB (MCAN_RXF1S_DMS_MSG_AB_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug messages A, B received. Position */ 2395 #define MCAN_RXF1S_DMS_MSG_ABC (MCAN_RXF1S_DMS_MSG_ABC_Val << MCAN_RXF1S_DMS_Pos) /**< (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. Position */ 2396 #define MCAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \deprecated (MCAN_RXF1S) Register MASK (Use MCAN_RXF1S_Msk instead) */ 2397 #define MCAN_RXF1S_Msk _U_(0xC33F3F7F) /**< (MCAN_RXF1S) Register Mask */ 2398 2399 2400 /* -------- MCAN_RXF1A : (MCAN Offset: 0xb8) (R/W 32) Receive FIFO 1 Acknowledge Register -------- */ 2401 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2402 #if COMPONENT_TYPEDEF_STYLE == 'N' 2403 typedef union { 2404 struct { 2405 uint32_t F1AI:6; /**< bit: 0..5 Receive FIFO 1 Acknowledge Index */ 2406 uint32_t :26; /**< bit: 6..31 Reserved */ 2407 } bit; /**< Structure used for bit access */ 2408 uint32_t reg; /**< Type used for register access */ 2409 } MCAN_RXF1A_Type; 2410 #endif 2411 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2412 2413 #define MCAN_RXF1A_OFFSET (0xB8) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Register Offset */ 2414 2415 #define MCAN_RXF1A_F1AI_Pos 0 /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index Position */ 2416 #define MCAN_RXF1A_F1AI_Msk (_U_(0x3F) << MCAN_RXF1A_F1AI_Pos) /**< (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index Mask */ 2417 #define MCAN_RXF1A_F1AI(value) (MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos)) 2418 #define MCAN_RXF1A_MASK _U_(0x3F) /**< \deprecated (MCAN_RXF1A) Register MASK (Use MCAN_RXF1A_Msk instead) */ 2419 #define MCAN_RXF1A_Msk _U_(0x3F) /**< (MCAN_RXF1A) Register Mask */ 2420 2421 2422 /* -------- MCAN_RXESC : (MCAN Offset: 0xbc) (R/W 32) Receive Buffer / FIFO Element Size Configuration Register -------- */ 2423 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2424 #if COMPONENT_TYPEDEF_STYLE == 'N' 2425 typedef union { 2426 struct { 2427 uint32_t F0DS:3; /**< bit: 0..2 Receive FIFO 0 Data Field Size */ 2428 uint32_t :1; /**< bit: 3 Reserved */ 2429 uint32_t F1DS:3; /**< bit: 4..6 Receive FIFO 1 Data Field Size */ 2430 uint32_t :1; /**< bit: 7 Reserved */ 2431 uint32_t RBDS:3; /**< bit: 8..10 Receive Buffer Data Field Size */ 2432 uint32_t :21; /**< bit: 11..31 Reserved */ 2433 } bit; /**< Structure used for bit access */ 2434 uint32_t reg; /**< Type used for register access */ 2435 } MCAN_RXESC_Type; 2436 #endif 2437 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2438 2439 #define MCAN_RXESC_OFFSET (0xBC) /**< (MCAN_RXESC) Receive Buffer / FIFO Element Size Configuration Register Offset */ 2440 2441 #define MCAN_RXESC_F0DS_Pos 0 /**< (MCAN_RXESC) Receive FIFO 0 Data Field Size Position */ 2442 #define MCAN_RXESC_F0DS_Msk (_U_(0x7) << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) Receive FIFO 0 Data Field Size Mask */ 2443 #define MCAN_RXESC_F0DS(value) (MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos)) 2444 #define MCAN_RXESC_F0DS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ 2445 #define MCAN_RXESC_F0DS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ 2446 #define MCAN_RXESC_F0DS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ 2447 #define MCAN_RXESC_F0DS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ 2448 #define MCAN_RXESC_F0DS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ 2449 #define MCAN_RXESC_F0DS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ 2450 #define MCAN_RXESC_F0DS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ 2451 #define MCAN_RXESC_F0DS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ 2452 #define MCAN_RXESC_F0DS_8_BYTE (MCAN_RXESC_F0DS_8_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ 2453 #define MCAN_RXESC_F0DS_12_BYTE (MCAN_RXESC_F0DS_12_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ 2454 #define MCAN_RXESC_F0DS_16_BYTE (MCAN_RXESC_F0DS_16_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ 2455 #define MCAN_RXESC_F0DS_20_BYTE (MCAN_RXESC_F0DS_20_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ 2456 #define MCAN_RXESC_F0DS_24_BYTE (MCAN_RXESC_F0DS_24_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ 2457 #define MCAN_RXESC_F0DS_32_BYTE (MCAN_RXESC_F0DS_32_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ 2458 #define MCAN_RXESC_F0DS_48_BYTE (MCAN_RXESC_F0DS_48_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ 2459 #define MCAN_RXESC_F0DS_64_BYTE (MCAN_RXESC_F0DS_64_BYTE_Val << MCAN_RXESC_F0DS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ 2460 #define MCAN_RXESC_F1DS_Pos 4 /**< (MCAN_RXESC) Receive FIFO 1 Data Field Size Position */ 2461 #define MCAN_RXESC_F1DS_Msk (_U_(0x7) << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) Receive FIFO 1 Data Field Size Mask */ 2462 #define MCAN_RXESC_F1DS(value) (MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos)) 2463 #define MCAN_RXESC_F1DS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ 2464 #define MCAN_RXESC_F1DS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ 2465 #define MCAN_RXESC_F1DS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ 2466 #define MCAN_RXESC_F1DS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ 2467 #define MCAN_RXESC_F1DS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ 2468 #define MCAN_RXESC_F1DS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ 2469 #define MCAN_RXESC_F1DS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ 2470 #define MCAN_RXESC_F1DS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ 2471 #define MCAN_RXESC_F1DS_8_BYTE (MCAN_RXESC_F1DS_8_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ 2472 #define MCAN_RXESC_F1DS_12_BYTE (MCAN_RXESC_F1DS_12_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ 2473 #define MCAN_RXESC_F1DS_16_BYTE (MCAN_RXESC_F1DS_16_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ 2474 #define MCAN_RXESC_F1DS_20_BYTE (MCAN_RXESC_F1DS_20_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ 2475 #define MCAN_RXESC_F1DS_24_BYTE (MCAN_RXESC_F1DS_24_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ 2476 #define MCAN_RXESC_F1DS_32_BYTE (MCAN_RXESC_F1DS_32_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ 2477 #define MCAN_RXESC_F1DS_48_BYTE (MCAN_RXESC_F1DS_48_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ 2478 #define MCAN_RXESC_F1DS_64_BYTE (MCAN_RXESC_F1DS_64_BYTE_Val << MCAN_RXESC_F1DS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ 2479 #define MCAN_RXESC_RBDS_Pos 8 /**< (MCAN_RXESC) Receive Buffer Data Field Size Position */ 2480 #define MCAN_RXESC_RBDS_Msk (_U_(0x7) << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) Receive Buffer Data Field Size Mask */ 2481 #define MCAN_RXESC_RBDS(value) (MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos)) 2482 #define MCAN_RXESC_RBDS_8_BYTE_Val _U_(0x0) /**< (MCAN_RXESC) 8-byte data field */ 2483 #define MCAN_RXESC_RBDS_12_BYTE_Val _U_(0x1) /**< (MCAN_RXESC) 12-byte data field */ 2484 #define MCAN_RXESC_RBDS_16_BYTE_Val _U_(0x2) /**< (MCAN_RXESC) 16-byte data field */ 2485 #define MCAN_RXESC_RBDS_20_BYTE_Val _U_(0x3) /**< (MCAN_RXESC) 20-byte data field */ 2486 #define MCAN_RXESC_RBDS_24_BYTE_Val _U_(0x4) /**< (MCAN_RXESC) 24-byte data field */ 2487 #define MCAN_RXESC_RBDS_32_BYTE_Val _U_(0x5) /**< (MCAN_RXESC) 32-byte data field */ 2488 #define MCAN_RXESC_RBDS_48_BYTE_Val _U_(0x6) /**< (MCAN_RXESC) 48-byte data field */ 2489 #define MCAN_RXESC_RBDS_64_BYTE_Val _U_(0x7) /**< (MCAN_RXESC) 64-byte data field */ 2490 #define MCAN_RXESC_RBDS_8_BYTE (MCAN_RXESC_RBDS_8_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 8-byte data field Position */ 2491 #define MCAN_RXESC_RBDS_12_BYTE (MCAN_RXESC_RBDS_12_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 12-byte data field Position */ 2492 #define MCAN_RXESC_RBDS_16_BYTE (MCAN_RXESC_RBDS_16_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 16-byte data field Position */ 2493 #define MCAN_RXESC_RBDS_20_BYTE (MCAN_RXESC_RBDS_20_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 20-byte data field Position */ 2494 #define MCAN_RXESC_RBDS_24_BYTE (MCAN_RXESC_RBDS_24_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 24-byte data field Position */ 2495 #define MCAN_RXESC_RBDS_32_BYTE (MCAN_RXESC_RBDS_32_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 32-byte data field Position */ 2496 #define MCAN_RXESC_RBDS_48_BYTE (MCAN_RXESC_RBDS_48_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 48-byte data field Position */ 2497 #define MCAN_RXESC_RBDS_64_BYTE (MCAN_RXESC_RBDS_64_BYTE_Val << MCAN_RXESC_RBDS_Pos) /**< (MCAN_RXESC) 64-byte data field Position */ 2498 #define MCAN_RXESC_MASK _U_(0x777) /**< \deprecated (MCAN_RXESC) Register MASK (Use MCAN_RXESC_Msk instead) */ 2499 #define MCAN_RXESC_Msk _U_(0x777) /**< (MCAN_RXESC) Register Mask */ 2500 2501 2502 /* -------- MCAN_TXBC : (MCAN Offset: 0xc0) (R/W 32) Transmit Buffer Configuration Register -------- */ 2503 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2504 #if COMPONENT_TYPEDEF_STYLE == 'N' 2505 typedef union { 2506 struct { 2507 uint32_t :2; /**< bit: 0..1 Reserved */ 2508 uint32_t TBSA:14; /**< bit: 2..15 Tx Buffers Start Address */ 2509 uint32_t NDTB:6; /**< bit: 16..21 Number of Dedicated Transmit Buffers */ 2510 uint32_t :2; /**< bit: 22..23 Reserved */ 2511 uint32_t TFQS:6; /**< bit: 24..29 Transmit FIFO/Queue Size */ 2512 uint32_t TFQM:1; /**< bit: 30 Tx FIFO/Queue Mode */ 2513 uint32_t :1; /**< bit: 31 Reserved */ 2514 } bit; /**< Structure used for bit access */ 2515 uint32_t reg; /**< Type used for register access */ 2516 } MCAN_TXBC_Type; 2517 #endif 2518 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2519 2520 #define MCAN_TXBC_OFFSET (0xC0) /**< (MCAN_TXBC) Transmit Buffer Configuration Register Offset */ 2521 2522 #define MCAN_TXBC_TBSA_Pos 2 /**< (MCAN_TXBC) Tx Buffers Start Address Position */ 2523 #define MCAN_TXBC_TBSA_Msk (_U_(0x3FFF) << MCAN_TXBC_TBSA_Pos) /**< (MCAN_TXBC) Tx Buffers Start Address Mask */ 2524 #define MCAN_TXBC_TBSA(value) (MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos)) 2525 #define MCAN_TXBC_NDTB_Pos 16 /**< (MCAN_TXBC) Number of Dedicated Transmit Buffers Position */ 2526 #define MCAN_TXBC_NDTB_Msk (_U_(0x3F) << MCAN_TXBC_NDTB_Pos) /**< (MCAN_TXBC) Number of Dedicated Transmit Buffers Mask */ 2527 #define MCAN_TXBC_NDTB(value) (MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos)) 2528 #define MCAN_TXBC_TFQS_Pos 24 /**< (MCAN_TXBC) Transmit FIFO/Queue Size Position */ 2529 #define MCAN_TXBC_TFQS_Msk (_U_(0x3F) << MCAN_TXBC_TFQS_Pos) /**< (MCAN_TXBC) Transmit FIFO/Queue Size Mask */ 2530 #define MCAN_TXBC_TFQS(value) (MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos)) 2531 #define MCAN_TXBC_TFQM_Pos 30 /**< (MCAN_TXBC) Tx FIFO/Queue Mode Position */ 2532 #define MCAN_TXBC_TFQM_Msk (_U_(0x1) << MCAN_TXBC_TFQM_Pos) /**< (MCAN_TXBC) Tx FIFO/Queue Mode Mask */ 2533 #define MCAN_TXBC_TFQM MCAN_TXBC_TFQM_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBC_TFQM_Msk instead */ 2534 #define MCAN_TXBC_MASK _U_(0x7F3FFFFC) /**< \deprecated (MCAN_TXBC) Register MASK (Use MCAN_TXBC_Msk instead) */ 2535 #define MCAN_TXBC_Msk _U_(0x7F3FFFFC) /**< (MCAN_TXBC) Register Mask */ 2536 2537 2538 /* -------- MCAN_TXFQS : (MCAN Offset: 0xc4) (R/ 32) Transmit FIFO/Queue Status Register -------- */ 2539 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2540 #if COMPONENT_TYPEDEF_STYLE == 'N' 2541 typedef union { 2542 struct { 2543 uint32_t TFFL:6; /**< bit: 0..5 Tx FIFO Free Level */ 2544 uint32_t :2; /**< bit: 6..7 Reserved */ 2545 uint32_t TFGI:5; /**< bit: 8..12 Tx FIFO Get Index */ 2546 uint32_t :3; /**< bit: 13..15 Reserved */ 2547 uint32_t TFQPI:5; /**< bit: 16..20 Tx FIFO/Queue Put Index */ 2548 uint32_t TFQF:1; /**< bit: 21 Tx FIFO/Queue Full */ 2549 uint32_t :10; /**< bit: 22..31 Reserved */ 2550 } bit; /**< Structure used for bit access */ 2551 uint32_t reg; /**< Type used for register access */ 2552 } MCAN_TXFQS_Type; 2553 #endif 2554 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2555 2556 #define MCAN_TXFQS_OFFSET (0xC4) /**< (MCAN_TXFQS) Transmit FIFO/Queue Status Register Offset */ 2557 2558 #define MCAN_TXFQS_TFFL_Pos 0 /**< (MCAN_TXFQS) Tx FIFO Free Level Position */ 2559 #define MCAN_TXFQS_TFFL_Msk (_U_(0x3F) << MCAN_TXFQS_TFFL_Pos) /**< (MCAN_TXFQS) Tx FIFO Free Level Mask */ 2560 #define MCAN_TXFQS_TFFL(value) (MCAN_TXFQS_TFFL_Msk & ((value) << MCAN_TXFQS_TFFL_Pos)) 2561 #define MCAN_TXFQS_TFGI_Pos 8 /**< (MCAN_TXFQS) Tx FIFO Get Index Position */ 2562 #define MCAN_TXFQS_TFGI_Msk (_U_(0x1F) << MCAN_TXFQS_TFGI_Pos) /**< (MCAN_TXFQS) Tx FIFO Get Index Mask */ 2563 #define MCAN_TXFQS_TFGI(value) (MCAN_TXFQS_TFGI_Msk & ((value) << MCAN_TXFQS_TFGI_Pos)) 2564 #define MCAN_TXFQS_TFQPI_Pos 16 /**< (MCAN_TXFQS) Tx FIFO/Queue Put Index Position */ 2565 #define MCAN_TXFQS_TFQPI_Msk (_U_(0x1F) << MCAN_TXFQS_TFQPI_Pos) /**< (MCAN_TXFQS) Tx FIFO/Queue Put Index Mask */ 2566 #define MCAN_TXFQS_TFQPI(value) (MCAN_TXFQS_TFQPI_Msk & ((value) << MCAN_TXFQS_TFQPI_Pos)) 2567 #define MCAN_TXFQS_TFQF_Pos 21 /**< (MCAN_TXFQS) Tx FIFO/Queue Full Position */ 2568 #define MCAN_TXFQS_TFQF_Msk (_U_(0x1) << MCAN_TXFQS_TFQF_Pos) /**< (MCAN_TXFQS) Tx FIFO/Queue Full Mask */ 2569 #define MCAN_TXFQS_TFQF MCAN_TXFQS_TFQF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXFQS_TFQF_Msk instead */ 2570 #define MCAN_TXFQS_MASK _U_(0x3F1F3F) /**< \deprecated (MCAN_TXFQS) Register MASK (Use MCAN_TXFQS_Msk instead) */ 2571 #define MCAN_TXFQS_Msk _U_(0x3F1F3F) /**< (MCAN_TXFQS) Register Mask */ 2572 2573 2574 /* -------- MCAN_TXESC : (MCAN Offset: 0xc8) (R/W 32) Transmit Buffer Element Size Configuration Register -------- */ 2575 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2576 #if COMPONENT_TYPEDEF_STYLE == 'N' 2577 typedef union { 2578 struct { 2579 uint32_t TBDS:3; /**< bit: 0..2 Tx Buffer Data Field Size */ 2580 uint32_t :29; /**< bit: 3..31 Reserved */ 2581 } bit; /**< Structure used for bit access */ 2582 uint32_t reg; /**< Type used for register access */ 2583 } MCAN_TXESC_Type; 2584 #endif 2585 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2586 2587 #define MCAN_TXESC_OFFSET (0xC8) /**< (MCAN_TXESC) Transmit Buffer Element Size Configuration Register Offset */ 2588 2589 #define MCAN_TXESC_TBDS_Pos 0 /**< (MCAN_TXESC) Tx Buffer Data Field Size Position */ 2590 #define MCAN_TXESC_TBDS_Msk (_U_(0x7) << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) Tx Buffer Data Field Size Mask */ 2591 #define MCAN_TXESC_TBDS(value) (MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos)) 2592 #define MCAN_TXESC_TBDS_8_BYTE_Val _U_(0x0) /**< (MCAN_TXESC) 8-byte data field */ 2593 #define MCAN_TXESC_TBDS_12_BYTE_Val _U_(0x1) /**< (MCAN_TXESC) 12-byte data field */ 2594 #define MCAN_TXESC_TBDS_16_BYTE_Val _U_(0x2) /**< (MCAN_TXESC) 16-byte data field */ 2595 #define MCAN_TXESC_TBDS_20_BYTE_Val _U_(0x3) /**< (MCAN_TXESC) 20-byte data field */ 2596 #define MCAN_TXESC_TBDS_24_BYTE_Val _U_(0x4) /**< (MCAN_TXESC) 24-byte data field */ 2597 #define MCAN_TXESC_TBDS_32_BYTE_Val _U_(0x5) /**< (MCAN_TXESC) 32-byte data field */ 2598 #define MCAN_TXESC_TBDS_48_BYTE_Val _U_(0x6) /**< (MCAN_TXESC) 48-byte data field */ 2599 #define MCAN_TXESC_TBDS_64_BYTE_Val _U_(0x7) /**< (MCAN_TXESC) 64-byte data field */ 2600 #define MCAN_TXESC_TBDS_8_BYTE (MCAN_TXESC_TBDS_8_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 8-byte data field Position */ 2601 #define MCAN_TXESC_TBDS_12_BYTE (MCAN_TXESC_TBDS_12_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 12-byte data field Position */ 2602 #define MCAN_TXESC_TBDS_16_BYTE (MCAN_TXESC_TBDS_16_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 16-byte data field Position */ 2603 #define MCAN_TXESC_TBDS_20_BYTE (MCAN_TXESC_TBDS_20_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 20-byte data field Position */ 2604 #define MCAN_TXESC_TBDS_24_BYTE (MCAN_TXESC_TBDS_24_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 24-byte data field Position */ 2605 #define MCAN_TXESC_TBDS_32_BYTE (MCAN_TXESC_TBDS_32_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 32-byte data field Position */ 2606 #define MCAN_TXESC_TBDS_48_BYTE (MCAN_TXESC_TBDS_48_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 48-byte data field Position */ 2607 #define MCAN_TXESC_TBDS_64_BYTE (MCAN_TXESC_TBDS_64_BYTE_Val << MCAN_TXESC_TBDS_Pos) /**< (MCAN_TXESC) 64-byte data field Position */ 2608 #define MCAN_TXESC_MASK _U_(0x07) /**< \deprecated (MCAN_TXESC) Register MASK (Use MCAN_TXESC_Msk instead) */ 2609 #define MCAN_TXESC_Msk _U_(0x07) /**< (MCAN_TXESC) Register Mask */ 2610 2611 2612 /* -------- MCAN_TXBRP : (MCAN Offset: 0xcc) (R/ 32) Transmit Buffer Request Pending Register -------- */ 2613 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2614 #if COMPONENT_TYPEDEF_STYLE == 'N' 2615 typedef union { 2616 struct { 2617 uint32_t TRP0:1; /**< bit: 0 Transmission Request Pending for Buffer 0 */ 2618 uint32_t TRP1:1; /**< bit: 1 Transmission Request Pending for Buffer 1 */ 2619 uint32_t TRP2:1; /**< bit: 2 Transmission Request Pending for Buffer 2 */ 2620 uint32_t TRP3:1; /**< bit: 3 Transmission Request Pending for Buffer 3 */ 2621 uint32_t TRP4:1; /**< bit: 4 Transmission Request Pending for Buffer 4 */ 2622 uint32_t TRP5:1; /**< bit: 5 Transmission Request Pending for Buffer 5 */ 2623 uint32_t TRP6:1; /**< bit: 6 Transmission Request Pending for Buffer 6 */ 2624 uint32_t TRP7:1; /**< bit: 7 Transmission Request Pending for Buffer 7 */ 2625 uint32_t TRP8:1; /**< bit: 8 Transmission Request Pending for Buffer 8 */ 2626 uint32_t TRP9:1; /**< bit: 9 Transmission Request Pending for Buffer 9 */ 2627 uint32_t TRP10:1; /**< bit: 10 Transmission Request Pending for Buffer 10 */ 2628 uint32_t TRP11:1; /**< bit: 11 Transmission Request Pending for Buffer 11 */ 2629 uint32_t TRP12:1; /**< bit: 12 Transmission Request Pending for Buffer 12 */ 2630 uint32_t TRP13:1; /**< bit: 13 Transmission Request Pending for Buffer 13 */ 2631 uint32_t TRP14:1; /**< bit: 14 Transmission Request Pending for Buffer 14 */ 2632 uint32_t TRP15:1; /**< bit: 15 Transmission Request Pending for Buffer 15 */ 2633 uint32_t TRP16:1; /**< bit: 16 Transmission Request Pending for Buffer 16 */ 2634 uint32_t TRP17:1; /**< bit: 17 Transmission Request Pending for Buffer 17 */ 2635 uint32_t TRP18:1; /**< bit: 18 Transmission Request Pending for Buffer 18 */ 2636 uint32_t TRP19:1; /**< bit: 19 Transmission Request Pending for Buffer 19 */ 2637 uint32_t TRP20:1; /**< bit: 20 Transmission Request Pending for Buffer 20 */ 2638 uint32_t TRP21:1; /**< bit: 21 Transmission Request Pending for Buffer 21 */ 2639 uint32_t TRP22:1; /**< bit: 22 Transmission Request Pending for Buffer 22 */ 2640 uint32_t TRP23:1; /**< bit: 23 Transmission Request Pending for Buffer 23 */ 2641 uint32_t TRP24:1; /**< bit: 24 Transmission Request Pending for Buffer 24 */ 2642 uint32_t TRP25:1; /**< bit: 25 Transmission Request Pending for Buffer 25 */ 2643 uint32_t TRP26:1; /**< bit: 26 Transmission Request Pending for Buffer 26 */ 2644 uint32_t TRP27:1; /**< bit: 27 Transmission Request Pending for Buffer 27 */ 2645 uint32_t TRP28:1; /**< bit: 28 Transmission Request Pending for Buffer 28 */ 2646 uint32_t TRP29:1; /**< bit: 29 Transmission Request Pending for Buffer 29 */ 2647 uint32_t TRP30:1; /**< bit: 30 Transmission Request Pending for Buffer 30 */ 2648 uint32_t TRP31:1; /**< bit: 31 Transmission Request Pending for Buffer 31 */ 2649 } bit; /**< Structure used for bit access */ 2650 struct { 2651 uint32_t TRP:32; /**< bit: 0..31 Transmission Request Pending for Buffer 3x */ 2652 } vec; /**< Structure used for vec access */ 2653 uint32_t reg; /**< Type used for register access */ 2654 } MCAN_TXBRP_Type; 2655 #endif 2656 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2657 2658 #define MCAN_TXBRP_OFFSET (0xCC) /**< (MCAN_TXBRP) Transmit Buffer Request Pending Register Offset */ 2659 2660 #define MCAN_TXBRP_TRP0_Pos 0 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 0 Position */ 2661 #define MCAN_TXBRP_TRP0_Msk (_U_(0x1) << MCAN_TXBRP_TRP0_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 0 Mask */ 2662 #define MCAN_TXBRP_TRP0 MCAN_TXBRP_TRP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP0_Msk instead */ 2663 #define MCAN_TXBRP_TRP1_Pos 1 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 1 Position */ 2664 #define MCAN_TXBRP_TRP1_Msk (_U_(0x1) << MCAN_TXBRP_TRP1_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 1 Mask */ 2665 #define MCAN_TXBRP_TRP1 MCAN_TXBRP_TRP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP1_Msk instead */ 2666 #define MCAN_TXBRP_TRP2_Pos 2 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 2 Position */ 2667 #define MCAN_TXBRP_TRP2_Msk (_U_(0x1) << MCAN_TXBRP_TRP2_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 2 Mask */ 2668 #define MCAN_TXBRP_TRP2 MCAN_TXBRP_TRP2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP2_Msk instead */ 2669 #define MCAN_TXBRP_TRP3_Pos 3 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 3 Position */ 2670 #define MCAN_TXBRP_TRP3_Msk (_U_(0x1) << MCAN_TXBRP_TRP3_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 3 Mask */ 2671 #define MCAN_TXBRP_TRP3 MCAN_TXBRP_TRP3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP3_Msk instead */ 2672 #define MCAN_TXBRP_TRP4_Pos 4 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 4 Position */ 2673 #define MCAN_TXBRP_TRP4_Msk (_U_(0x1) << MCAN_TXBRP_TRP4_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 4 Mask */ 2674 #define MCAN_TXBRP_TRP4 MCAN_TXBRP_TRP4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP4_Msk instead */ 2675 #define MCAN_TXBRP_TRP5_Pos 5 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 5 Position */ 2676 #define MCAN_TXBRP_TRP5_Msk (_U_(0x1) << MCAN_TXBRP_TRP5_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 5 Mask */ 2677 #define MCAN_TXBRP_TRP5 MCAN_TXBRP_TRP5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP5_Msk instead */ 2678 #define MCAN_TXBRP_TRP6_Pos 6 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 6 Position */ 2679 #define MCAN_TXBRP_TRP6_Msk (_U_(0x1) << MCAN_TXBRP_TRP6_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 6 Mask */ 2680 #define MCAN_TXBRP_TRP6 MCAN_TXBRP_TRP6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP6_Msk instead */ 2681 #define MCAN_TXBRP_TRP7_Pos 7 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 7 Position */ 2682 #define MCAN_TXBRP_TRP7_Msk (_U_(0x1) << MCAN_TXBRP_TRP7_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 7 Mask */ 2683 #define MCAN_TXBRP_TRP7 MCAN_TXBRP_TRP7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP7_Msk instead */ 2684 #define MCAN_TXBRP_TRP8_Pos 8 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 8 Position */ 2685 #define MCAN_TXBRP_TRP8_Msk (_U_(0x1) << MCAN_TXBRP_TRP8_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 8 Mask */ 2686 #define MCAN_TXBRP_TRP8 MCAN_TXBRP_TRP8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP8_Msk instead */ 2687 #define MCAN_TXBRP_TRP9_Pos 9 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 9 Position */ 2688 #define MCAN_TXBRP_TRP9_Msk (_U_(0x1) << MCAN_TXBRP_TRP9_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 9 Mask */ 2689 #define MCAN_TXBRP_TRP9 MCAN_TXBRP_TRP9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP9_Msk instead */ 2690 #define MCAN_TXBRP_TRP10_Pos 10 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 10 Position */ 2691 #define MCAN_TXBRP_TRP10_Msk (_U_(0x1) << MCAN_TXBRP_TRP10_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 10 Mask */ 2692 #define MCAN_TXBRP_TRP10 MCAN_TXBRP_TRP10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP10_Msk instead */ 2693 #define MCAN_TXBRP_TRP11_Pos 11 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 11 Position */ 2694 #define MCAN_TXBRP_TRP11_Msk (_U_(0x1) << MCAN_TXBRP_TRP11_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 11 Mask */ 2695 #define MCAN_TXBRP_TRP11 MCAN_TXBRP_TRP11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP11_Msk instead */ 2696 #define MCAN_TXBRP_TRP12_Pos 12 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 12 Position */ 2697 #define MCAN_TXBRP_TRP12_Msk (_U_(0x1) << MCAN_TXBRP_TRP12_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 12 Mask */ 2698 #define MCAN_TXBRP_TRP12 MCAN_TXBRP_TRP12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP12_Msk instead */ 2699 #define MCAN_TXBRP_TRP13_Pos 13 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 13 Position */ 2700 #define MCAN_TXBRP_TRP13_Msk (_U_(0x1) << MCAN_TXBRP_TRP13_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 13 Mask */ 2701 #define MCAN_TXBRP_TRP13 MCAN_TXBRP_TRP13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP13_Msk instead */ 2702 #define MCAN_TXBRP_TRP14_Pos 14 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 14 Position */ 2703 #define MCAN_TXBRP_TRP14_Msk (_U_(0x1) << MCAN_TXBRP_TRP14_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 14 Mask */ 2704 #define MCAN_TXBRP_TRP14 MCAN_TXBRP_TRP14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP14_Msk instead */ 2705 #define MCAN_TXBRP_TRP15_Pos 15 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 15 Position */ 2706 #define MCAN_TXBRP_TRP15_Msk (_U_(0x1) << MCAN_TXBRP_TRP15_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 15 Mask */ 2707 #define MCAN_TXBRP_TRP15 MCAN_TXBRP_TRP15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP15_Msk instead */ 2708 #define MCAN_TXBRP_TRP16_Pos 16 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 16 Position */ 2709 #define MCAN_TXBRP_TRP16_Msk (_U_(0x1) << MCAN_TXBRP_TRP16_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 16 Mask */ 2710 #define MCAN_TXBRP_TRP16 MCAN_TXBRP_TRP16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP16_Msk instead */ 2711 #define MCAN_TXBRP_TRP17_Pos 17 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 17 Position */ 2712 #define MCAN_TXBRP_TRP17_Msk (_U_(0x1) << MCAN_TXBRP_TRP17_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 17 Mask */ 2713 #define MCAN_TXBRP_TRP17 MCAN_TXBRP_TRP17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP17_Msk instead */ 2714 #define MCAN_TXBRP_TRP18_Pos 18 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 18 Position */ 2715 #define MCAN_TXBRP_TRP18_Msk (_U_(0x1) << MCAN_TXBRP_TRP18_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 18 Mask */ 2716 #define MCAN_TXBRP_TRP18 MCAN_TXBRP_TRP18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP18_Msk instead */ 2717 #define MCAN_TXBRP_TRP19_Pos 19 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 19 Position */ 2718 #define MCAN_TXBRP_TRP19_Msk (_U_(0x1) << MCAN_TXBRP_TRP19_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 19 Mask */ 2719 #define MCAN_TXBRP_TRP19 MCAN_TXBRP_TRP19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP19_Msk instead */ 2720 #define MCAN_TXBRP_TRP20_Pos 20 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 20 Position */ 2721 #define MCAN_TXBRP_TRP20_Msk (_U_(0x1) << MCAN_TXBRP_TRP20_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 20 Mask */ 2722 #define MCAN_TXBRP_TRP20 MCAN_TXBRP_TRP20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP20_Msk instead */ 2723 #define MCAN_TXBRP_TRP21_Pos 21 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 21 Position */ 2724 #define MCAN_TXBRP_TRP21_Msk (_U_(0x1) << MCAN_TXBRP_TRP21_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 21 Mask */ 2725 #define MCAN_TXBRP_TRP21 MCAN_TXBRP_TRP21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP21_Msk instead */ 2726 #define MCAN_TXBRP_TRP22_Pos 22 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 22 Position */ 2727 #define MCAN_TXBRP_TRP22_Msk (_U_(0x1) << MCAN_TXBRP_TRP22_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 22 Mask */ 2728 #define MCAN_TXBRP_TRP22 MCAN_TXBRP_TRP22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP22_Msk instead */ 2729 #define MCAN_TXBRP_TRP23_Pos 23 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 23 Position */ 2730 #define MCAN_TXBRP_TRP23_Msk (_U_(0x1) << MCAN_TXBRP_TRP23_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 23 Mask */ 2731 #define MCAN_TXBRP_TRP23 MCAN_TXBRP_TRP23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP23_Msk instead */ 2732 #define MCAN_TXBRP_TRP24_Pos 24 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 24 Position */ 2733 #define MCAN_TXBRP_TRP24_Msk (_U_(0x1) << MCAN_TXBRP_TRP24_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 24 Mask */ 2734 #define MCAN_TXBRP_TRP24 MCAN_TXBRP_TRP24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP24_Msk instead */ 2735 #define MCAN_TXBRP_TRP25_Pos 25 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 25 Position */ 2736 #define MCAN_TXBRP_TRP25_Msk (_U_(0x1) << MCAN_TXBRP_TRP25_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 25 Mask */ 2737 #define MCAN_TXBRP_TRP25 MCAN_TXBRP_TRP25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP25_Msk instead */ 2738 #define MCAN_TXBRP_TRP26_Pos 26 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 26 Position */ 2739 #define MCAN_TXBRP_TRP26_Msk (_U_(0x1) << MCAN_TXBRP_TRP26_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 26 Mask */ 2740 #define MCAN_TXBRP_TRP26 MCAN_TXBRP_TRP26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP26_Msk instead */ 2741 #define MCAN_TXBRP_TRP27_Pos 27 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 27 Position */ 2742 #define MCAN_TXBRP_TRP27_Msk (_U_(0x1) << MCAN_TXBRP_TRP27_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 27 Mask */ 2743 #define MCAN_TXBRP_TRP27 MCAN_TXBRP_TRP27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP27_Msk instead */ 2744 #define MCAN_TXBRP_TRP28_Pos 28 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 28 Position */ 2745 #define MCAN_TXBRP_TRP28_Msk (_U_(0x1) << MCAN_TXBRP_TRP28_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 28 Mask */ 2746 #define MCAN_TXBRP_TRP28 MCAN_TXBRP_TRP28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP28_Msk instead */ 2747 #define MCAN_TXBRP_TRP29_Pos 29 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 29 Position */ 2748 #define MCAN_TXBRP_TRP29_Msk (_U_(0x1) << MCAN_TXBRP_TRP29_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 29 Mask */ 2749 #define MCAN_TXBRP_TRP29 MCAN_TXBRP_TRP29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP29_Msk instead */ 2750 #define MCAN_TXBRP_TRP30_Pos 30 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 30 Position */ 2751 #define MCAN_TXBRP_TRP30_Msk (_U_(0x1) << MCAN_TXBRP_TRP30_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 30 Mask */ 2752 #define MCAN_TXBRP_TRP30 MCAN_TXBRP_TRP30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP30_Msk instead */ 2753 #define MCAN_TXBRP_TRP31_Pos 31 /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 31 Position */ 2754 #define MCAN_TXBRP_TRP31_Msk (_U_(0x1) << MCAN_TXBRP_TRP31_Pos) /**< (MCAN_TXBRP) Transmission Request Pending for Buffer 31 Mask */ 2755 #define MCAN_TXBRP_TRP31 MCAN_TXBRP_TRP31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBRP_TRP31_Msk instead */ 2756 #define MCAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBRP) Register MASK (Use MCAN_TXBRP_Msk instead) */ 2757 #define MCAN_TXBRP_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBRP) Register Mask */ 2758 2759 #define MCAN_TXBRP_TRP_Pos 0 /**< (MCAN_TXBRP Position) Transmission Request Pending for Buffer 3x */ 2760 #define MCAN_TXBRP_TRP_Msk (_U_(0xFFFFFFFF) << MCAN_TXBRP_TRP_Pos) /**< (MCAN_TXBRP Mask) TRP */ 2761 #define MCAN_TXBRP_TRP(value) (MCAN_TXBRP_TRP_Msk & ((value) << MCAN_TXBRP_TRP_Pos)) 2762 2763 /* -------- MCAN_TXBAR : (MCAN Offset: 0xd0) (R/W 32) Transmit Buffer Add Request Register -------- */ 2764 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2765 #if COMPONENT_TYPEDEF_STYLE == 'N' 2766 typedef union { 2767 struct { 2768 uint32_t AR0:1; /**< bit: 0 Add Request for Transmit Buffer 0 */ 2769 uint32_t AR1:1; /**< bit: 1 Add Request for Transmit Buffer 1 */ 2770 uint32_t AR2:1; /**< bit: 2 Add Request for Transmit Buffer 2 */ 2771 uint32_t AR3:1; /**< bit: 3 Add Request for Transmit Buffer 3 */ 2772 uint32_t AR4:1; /**< bit: 4 Add Request for Transmit Buffer 4 */ 2773 uint32_t AR5:1; /**< bit: 5 Add Request for Transmit Buffer 5 */ 2774 uint32_t AR6:1; /**< bit: 6 Add Request for Transmit Buffer 6 */ 2775 uint32_t AR7:1; /**< bit: 7 Add Request for Transmit Buffer 7 */ 2776 uint32_t AR8:1; /**< bit: 8 Add Request for Transmit Buffer 8 */ 2777 uint32_t AR9:1; /**< bit: 9 Add Request for Transmit Buffer 9 */ 2778 uint32_t AR10:1; /**< bit: 10 Add Request for Transmit Buffer 10 */ 2779 uint32_t AR11:1; /**< bit: 11 Add Request for Transmit Buffer 11 */ 2780 uint32_t AR12:1; /**< bit: 12 Add Request for Transmit Buffer 12 */ 2781 uint32_t AR13:1; /**< bit: 13 Add Request for Transmit Buffer 13 */ 2782 uint32_t AR14:1; /**< bit: 14 Add Request for Transmit Buffer 14 */ 2783 uint32_t AR15:1; /**< bit: 15 Add Request for Transmit Buffer 15 */ 2784 uint32_t AR16:1; /**< bit: 16 Add Request for Transmit Buffer 16 */ 2785 uint32_t AR17:1; /**< bit: 17 Add Request for Transmit Buffer 17 */ 2786 uint32_t AR18:1; /**< bit: 18 Add Request for Transmit Buffer 18 */ 2787 uint32_t AR19:1; /**< bit: 19 Add Request for Transmit Buffer 19 */ 2788 uint32_t AR20:1; /**< bit: 20 Add Request for Transmit Buffer 20 */ 2789 uint32_t AR21:1; /**< bit: 21 Add Request for Transmit Buffer 21 */ 2790 uint32_t AR22:1; /**< bit: 22 Add Request for Transmit Buffer 22 */ 2791 uint32_t AR23:1; /**< bit: 23 Add Request for Transmit Buffer 23 */ 2792 uint32_t AR24:1; /**< bit: 24 Add Request for Transmit Buffer 24 */ 2793 uint32_t AR25:1; /**< bit: 25 Add Request for Transmit Buffer 25 */ 2794 uint32_t AR26:1; /**< bit: 26 Add Request for Transmit Buffer 26 */ 2795 uint32_t AR27:1; /**< bit: 27 Add Request for Transmit Buffer 27 */ 2796 uint32_t AR28:1; /**< bit: 28 Add Request for Transmit Buffer 28 */ 2797 uint32_t AR29:1; /**< bit: 29 Add Request for Transmit Buffer 29 */ 2798 uint32_t AR30:1; /**< bit: 30 Add Request for Transmit Buffer 30 */ 2799 uint32_t AR31:1; /**< bit: 31 Add Request for Transmit Buffer 31 */ 2800 } bit; /**< Structure used for bit access */ 2801 struct { 2802 uint32_t AR:32; /**< bit: 0..31 Add Request for Transmit Buffer 3x */ 2803 } vec; /**< Structure used for vec access */ 2804 uint32_t reg; /**< Type used for register access */ 2805 } MCAN_TXBAR_Type; 2806 #endif 2807 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2808 2809 #define MCAN_TXBAR_OFFSET (0xD0) /**< (MCAN_TXBAR) Transmit Buffer Add Request Register Offset */ 2810 2811 #define MCAN_TXBAR_AR0_Pos 0 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 0 Position */ 2812 #define MCAN_TXBAR_AR0_Msk (_U_(0x1) << MCAN_TXBAR_AR0_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 0 Mask */ 2813 #define MCAN_TXBAR_AR0 MCAN_TXBAR_AR0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR0_Msk instead */ 2814 #define MCAN_TXBAR_AR1_Pos 1 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 1 Position */ 2815 #define MCAN_TXBAR_AR1_Msk (_U_(0x1) << MCAN_TXBAR_AR1_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 1 Mask */ 2816 #define MCAN_TXBAR_AR1 MCAN_TXBAR_AR1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR1_Msk instead */ 2817 #define MCAN_TXBAR_AR2_Pos 2 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 2 Position */ 2818 #define MCAN_TXBAR_AR2_Msk (_U_(0x1) << MCAN_TXBAR_AR2_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 2 Mask */ 2819 #define MCAN_TXBAR_AR2 MCAN_TXBAR_AR2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR2_Msk instead */ 2820 #define MCAN_TXBAR_AR3_Pos 3 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 3 Position */ 2821 #define MCAN_TXBAR_AR3_Msk (_U_(0x1) << MCAN_TXBAR_AR3_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 3 Mask */ 2822 #define MCAN_TXBAR_AR3 MCAN_TXBAR_AR3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR3_Msk instead */ 2823 #define MCAN_TXBAR_AR4_Pos 4 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 4 Position */ 2824 #define MCAN_TXBAR_AR4_Msk (_U_(0x1) << MCAN_TXBAR_AR4_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 4 Mask */ 2825 #define MCAN_TXBAR_AR4 MCAN_TXBAR_AR4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR4_Msk instead */ 2826 #define MCAN_TXBAR_AR5_Pos 5 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 5 Position */ 2827 #define MCAN_TXBAR_AR5_Msk (_U_(0x1) << MCAN_TXBAR_AR5_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 5 Mask */ 2828 #define MCAN_TXBAR_AR5 MCAN_TXBAR_AR5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR5_Msk instead */ 2829 #define MCAN_TXBAR_AR6_Pos 6 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 6 Position */ 2830 #define MCAN_TXBAR_AR6_Msk (_U_(0x1) << MCAN_TXBAR_AR6_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 6 Mask */ 2831 #define MCAN_TXBAR_AR6 MCAN_TXBAR_AR6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR6_Msk instead */ 2832 #define MCAN_TXBAR_AR7_Pos 7 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 7 Position */ 2833 #define MCAN_TXBAR_AR7_Msk (_U_(0x1) << MCAN_TXBAR_AR7_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 7 Mask */ 2834 #define MCAN_TXBAR_AR7 MCAN_TXBAR_AR7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR7_Msk instead */ 2835 #define MCAN_TXBAR_AR8_Pos 8 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 8 Position */ 2836 #define MCAN_TXBAR_AR8_Msk (_U_(0x1) << MCAN_TXBAR_AR8_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 8 Mask */ 2837 #define MCAN_TXBAR_AR8 MCAN_TXBAR_AR8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR8_Msk instead */ 2838 #define MCAN_TXBAR_AR9_Pos 9 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 9 Position */ 2839 #define MCAN_TXBAR_AR9_Msk (_U_(0x1) << MCAN_TXBAR_AR9_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 9 Mask */ 2840 #define MCAN_TXBAR_AR9 MCAN_TXBAR_AR9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR9_Msk instead */ 2841 #define MCAN_TXBAR_AR10_Pos 10 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 10 Position */ 2842 #define MCAN_TXBAR_AR10_Msk (_U_(0x1) << MCAN_TXBAR_AR10_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 10 Mask */ 2843 #define MCAN_TXBAR_AR10 MCAN_TXBAR_AR10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR10_Msk instead */ 2844 #define MCAN_TXBAR_AR11_Pos 11 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 11 Position */ 2845 #define MCAN_TXBAR_AR11_Msk (_U_(0x1) << MCAN_TXBAR_AR11_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 11 Mask */ 2846 #define MCAN_TXBAR_AR11 MCAN_TXBAR_AR11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR11_Msk instead */ 2847 #define MCAN_TXBAR_AR12_Pos 12 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 12 Position */ 2848 #define MCAN_TXBAR_AR12_Msk (_U_(0x1) << MCAN_TXBAR_AR12_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 12 Mask */ 2849 #define MCAN_TXBAR_AR12 MCAN_TXBAR_AR12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR12_Msk instead */ 2850 #define MCAN_TXBAR_AR13_Pos 13 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 13 Position */ 2851 #define MCAN_TXBAR_AR13_Msk (_U_(0x1) << MCAN_TXBAR_AR13_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 13 Mask */ 2852 #define MCAN_TXBAR_AR13 MCAN_TXBAR_AR13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR13_Msk instead */ 2853 #define MCAN_TXBAR_AR14_Pos 14 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 14 Position */ 2854 #define MCAN_TXBAR_AR14_Msk (_U_(0x1) << MCAN_TXBAR_AR14_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 14 Mask */ 2855 #define MCAN_TXBAR_AR14 MCAN_TXBAR_AR14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR14_Msk instead */ 2856 #define MCAN_TXBAR_AR15_Pos 15 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 15 Position */ 2857 #define MCAN_TXBAR_AR15_Msk (_U_(0x1) << MCAN_TXBAR_AR15_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 15 Mask */ 2858 #define MCAN_TXBAR_AR15 MCAN_TXBAR_AR15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR15_Msk instead */ 2859 #define MCAN_TXBAR_AR16_Pos 16 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 16 Position */ 2860 #define MCAN_TXBAR_AR16_Msk (_U_(0x1) << MCAN_TXBAR_AR16_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 16 Mask */ 2861 #define MCAN_TXBAR_AR16 MCAN_TXBAR_AR16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR16_Msk instead */ 2862 #define MCAN_TXBAR_AR17_Pos 17 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 17 Position */ 2863 #define MCAN_TXBAR_AR17_Msk (_U_(0x1) << MCAN_TXBAR_AR17_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 17 Mask */ 2864 #define MCAN_TXBAR_AR17 MCAN_TXBAR_AR17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR17_Msk instead */ 2865 #define MCAN_TXBAR_AR18_Pos 18 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 18 Position */ 2866 #define MCAN_TXBAR_AR18_Msk (_U_(0x1) << MCAN_TXBAR_AR18_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 18 Mask */ 2867 #define MCAN_TXBAR_AR18 MCAN_TXBAR_AR18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR18_Msk instead */ 2868 #define MCAN_TXBAR_AR19_Pos 19 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 19 Position */ 2869 #define MCAN_TXBAR_AR19_Msk (_U_(0x1) << MCAN_TXBAR_AR19_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 19 Mask */ 2870 #define MCAN_TXBAR_AR19 MCAN_TXBAR_AR19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR19_Msk instead */ 2871 #define MCAN_TXBAR_AR20_Pos 20 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 20 Position */ 2872 #define MCAN_TXBAR_AR20_Msk (_U_(0x1) << MCAN_TXBAR_AR20_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 20 Mask */ 2873 #define MCAN_TXBAR_AR20 MCAN_TXBAR_AR20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR20_Msk instead */ 2874 #define MCAN_TXBAR_AR21_Pos 21 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 21 Position */ 2875 #define MCAN_TXBAR_AR21_Msk (_U_(0x1) << MCAN_TXBAR_AR21_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 21 Mask */ 2876 #define MCAN_TXBAR_AR21 MCAN_TXBAR_AR21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR21_Msk instead */ 2877 #define MCAN_TXBAR_AR22_Pos 22 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 22 Position */ 2878 #define MCAN_TXBAR_AR22_Msk (_U_(0x1) << MCAN_TXBAR_AR22_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 22 Mask */ 2879 #define MCAN_TXBAR_AR22 MCAN_TXBAR_AR22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR22_Msk instead */ 2880 #define MCAN_TXBAR_AR23_Pos 23 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 23 Position */ 2881 #define MCAN_TXBAR_AR23_Msk (_U_(0x1) << MCAN_TXBAR_AR23_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 23 Mask */ 2882 #define MCAN_TXBAR_AR23 MCAN_TXBAR_AR23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR23_Msk instead */ 2883 #define MCAN_TXBAR_AR24_Pos 24 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 24 Position */ 2884 #define MCAN_TXBAR_AR24_Msk (_U_(0x1) << MCAN_TXBAR_AR24_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 24 Mask */ 2885 #define MCAN_TXBAR_AR24 MCAN_TXBAR_AR24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR24_Msk instead */ 2886 #define MCAN_TXBAR_AR25_Pos 25 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 25 Position */ 2887 #define MCAN_TXBAR_AR25_Msk (_U_(0x1) << MCAN_TXBAR_AR25_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 25 Mask */ 2888 #define MCAN_TXBAR_AR25 MCAN_TXBAR_AR25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR25_Msk instead */ 2889 #define MCAN_TXBAR_AR26_Pos 26 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 26 Position */ 2890 #define MCAN_TXBAR_AR26_Msk (_U_(0x1) << MCAN_TXBAR_AR26_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 26 Mask */ 2891 #define MCAN_TXBAR_AR26 MCAN_TXBAR_AR26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR26_Msk instead */ 2892 #define MCAN_TXBAR_AR27_Pos 27 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 27 Position */ 2893 #define MCAN_TXBAR_AR27_Msk (_U_(0x1) << MCAN_TXBAR_AR27_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 27 Mask */ 2894 #define MCAN_TXBAR_AR27 MCAN_TXBAR_AR27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR27_Msk instead */ 2895 #define MCAN_TXBAR_AR28_Pos 28 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 28 Position */ 2896 #define MCAN_TXBAR_AR28_Msk (_U_(0x1) << MCAN_TXBAR_AR28_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 28 Mask */ 2897 #define MCAN_TXBAR_AR28 MCAN_TXBAR_AR28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR28_Msk instead */ 2898 #define MCAN_TXBAR_AR29_Pos 29 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 29 Position */ 2899 #define MCAN_TXBAR_AR29_Msk (_U_(0x1) << MCAN_TXBAR_AR29_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 29 Mask */ 2900 #define MCAN_TXBAR_AR29 MCAN_TXBAR_AR29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR29_Msk instead */ 2901 #define MCAN_TXBAR_AR30_Pos 30 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 30 Position */ 2902 #define MCAN_TXBAR_AR30_Msk (_U_(0x1) << MCAN_TXBAR_AR30_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 30 Mask */ 2903 #define MCAN_TXBAR_AR30 MCAN_TXBAR_AR30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR30_Msk instead */ 2904 #define MCAN_TXBAR_AR31_Pos 31 /**< (MCAN_TXBAR) Add Request for Transmit Buffer 31 Position */ 2905 #define MCAN_TXBAR_AR31_Msk (_U_(0x1) << MCAN_TXBAR_AR31_Pos) /**< (MCAN_TXBAR) Add Request for Transmit Buffer 31 Mask */ 2906 #define MCAN_TXBAR_AR31 MCAN_TXBAR_AR31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBAR_AR31_Msk instead */ 2907 #define MCAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBAR) Register MASK (Use MCAN_TXBAR_Msk instead) */ 2908 #define MCAN_TXBAR_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBAR) Register Mask */ 2909 2910 #define MCAN_TXBAR_AR_Pos 0 /**< (MCAN_TXBAR Position) Add Request for Transmit Buffer 3x */ 2911 #define MCAN_TXBAR_AR_Msk (_U_(0xFFFFFFFF) << MCAN_TXBAR_AR_Pos) /**< (MCAN_TXBAR Mask) AR */ 2912 #define MCAN_TXBAR_AR(value) (MCAN_TXBAR_AR_Msk & ((value) << MCAN_TXBAR_AR_Pos)) 2913 2914 /* -------- MCAN_TXBCR : (MCAN Offset: 0xd4) (R/W 32) Transmit Buffer Cancellation Request Register -------- */ 2915 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 2916 #if COMPONENT_TYPEDEF_STYLE == 'N' 2917 typedef union { 2918 struct { 2919 uint32_t CR0:1; /**< bit: 0 Cancellation Request for Transmit Buffer 0 */ 2920 uint32_t CR1:1; /**< bit: 1 Cancellation Request for Transmit Buffer 1 */ 2921 uint32_t CR2:1; /**< bit: 2 Cancellation Request for Transmit Buffer 2 */ 2922 uint32_t CR3:1; /**< bit: 3 Cancellation Request for Transmit Buffer 3 */ 2923 uint32_t CR4:1; /**< bit: 4 Cancellation Request for Transmit Buffer 4 */ 2924 uint32_t CR5:1; /**< bit: 5 Cancellation Request for Transmit Buffer 5 */ 2925 uint32_t CR6:1; /**< bit: 6 Cancellation Request for Transmit Buffer 6 */ 2926 uint32_t CR7:1; /**< bit: 7 Cancellation Request for Transmit Buffer 7 */ 2927 uint32_t CR8:1; /**< bit: 8 Cancellation Request for Transmit Buffer 8 */ 2928 uint32_t CR9:1; /**< bit: 9 Cancellation Request for Transmit Buffer 9 */ 2929 uint32_t CR10:1; /**< bit: 10 Cancellation Request for Transmit Buffer 10 */ 2930 uint32_t CR11:1; /**< bit: 11 Cancellation Request for Transmit Buffer 11 */ 2931 uint32_t CR12:1; /**< bit: 12 Cancellation Request for Transmit Buffer 12 */ 2932 uint32_t CR13:1; /**< bit: 13 Cancellation Request for Transmit Buffer 13 */ 2933 uint32_t CR14:1; /**< bit: 14 Cancellation Request for Transmit Buffer 14 */ 2934 uint32_t CR15:1; /**< bit: 15 Cancellation Request for Transmit Buffer 15 */ 2935 uint32_t CR16:1; /**< bit: 16 Cancellation Request for Transmit Buffer 16 */ 2936 uint32_t CR17:1; /**< bit: 17 Cancellation Request for Transmit Buffer 17 */ 2937 uint32_t CR18:1; /**< bit: 18 Cancellation Request for Transmit Buffer 18 */ 2938 uint32_t CR19:1; /**< bit: 19 Cancellation Request for Transmit Buffer 19 */ 2939 uint32_t CR20:1; /**< bit: 20 Cancellation Request for Transmit Buffer 20 */ 2940 uint32_t CR21:1; /**< bit: 21 Cancellation Request for Transmit Buffer 21 */ 2941 uint32_t CR22:1; /**< bit: 22 Cancellation Request for Transmit Buffer 22 */ 2942 uint32_t CR23:1; /**< bit: 23 Cancellation Request for Transmit Buffer 23 */ 2943 uint32_t CR24:1; /**< bit: 24 Cancellation Request for Transmit Buffer 24 */ 2944 uint32_t CR25:1; /**< bit: 25 Cancellation Request for Transmit Buffer 25 */ 2945 uint32_t CR26:1; /**< bit: 26 Cancellation Request for Transmit Buffer 26 */ 2946 uint32_t CR27:1; /**< bit: 27 Cancellation Request for Transmit Buffer 27 */ 2947 uint32_t CR28:1; /**< bit: 28 Cancellation Request for Transmit Buffer 28 */ 2948 uint32_t CR29:1; /**< bit: 29 Cancellation Request for Transmit Buffer 29 */ 2949 uint32_t CR30:1; /**< bit: 30 Cancellation Request for Transmit Buffer 30 */ 2950 uint32_t CR31:1; /**< bit: 31 Cancellation Request for Transmit Buffer 31 */ 2951 } bit; /**< Structure used for bit access */ 2952 struct { 2953 uint32_t CR:32; /**< bit: 0..31 Cancellation Request for Transmit Buffer 3x */ 2954 } vec; /**< Structure used for vec access */ 2955 uint32_t reg; /**< Type used for register access */ 2956 } MCAN_TXBCR_Type; 2957 #endif 2958 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 2959 2960 #define MCAN_TXBCR_OFFSET (0xD4) /**< (MCAN_TXBCR) Transmit Buffer Cancellation Request Register Offset */ 2961 2962 #define MCAN_TXBCR_CR0_Pos 0 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 Position */ 2963 #define MCAN_TXBCR_CR0_Msk (_U_(0x1) << MCAN_TXBCR_CR0_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 Mask */ 2964 #define MCAN_TXBCR_CR0 MCAN_TXBCR_CR0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR0_Msk instead */ 2965 #define MCAN_TXBCR_CR1_Pos 1 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 Position */ 2966 #define MCAN_TXBCR_CR1_Msk (_U_(0x1) << MCAN_TXBCR_CR1_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 Mask */ 2967 #define MCAN_TXBCR_CR1 MCAN_TXBCR_CR1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR1_Msk instead */ 2968 #define MCAN_TXBCR_CR2_Pos 2 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 Position */ 2969 #define MCAN_TXBCR_CR2_Msk (_U_(0x1) << MCAN_TXBCR_CR2_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 Mask */ 2970 #define MCAN_TXBCR_CR2 MCAN_TXBCR_CR2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR2_Msk instead */ 2971 #define MCAN_TXBCR_CR3_Pos 3 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 Position */ 2972 #define MCAN_TXBCR_CR3_Msk (_U_(0x1) << MCAN_TXBCR_CR3_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 Mask */ 2973 #define MCAN_TXBCR_CR3 MCAN_TXBCR_CR3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR3_Msk instead */ 2974 #define MCAN_TXBCR_CR4_Pos 4 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 Position */ 2975 #define MCAN_TXBCR_CR4_Msk (_U_(0x1) << MCAN_TXBCR_CR4_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 Mask */ 2976 #define MCAN_TXBCR_CR4 MCAN_TXBCR_CR4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR4_Msk instead */ 2977 #define MCAN_TXBCR_CR5_Pos 5 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 Position */ 2978 #define MCAN_TXBCR_CR5_Msk (_U_(0x1) << MCAN_TXBCR_CR5_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 Mask */ 2979 #define MCAN_TXBCR_CR5 MCAN_TXBCR_CR5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR5_Msk instead */ 2980 #define MCAN_TXBCR_CR6_Pos 6 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 Position */ 2981 #define MCAN_TXBCR_CR6_Msk (_U_(0x1) << MCAN_TXBCR_CR6_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 Mask */ 2982 #define MCAN_TXBCR_CR6 MCAN_TXBCR_CR6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR6_Msk instead */ 2983 #define MCAN_TXBCR_CR7_Pos 7 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 Position */ 2984 #define MCAN_TXBCR_CR7_Msk (_U_(0x1) << MCAN_TXBCR_CR7_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 Mask */ 2985 #define MCAN_TXBCR_CR7 MCAN_TXBCR_CR7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR7_Msk instead */ 2986 #define MCAN_TXBCR_CR8_Pos 8 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 Position */ 2987 #define MCAN_TXBCR_CR8_Msk (_U_(0x1) << MCAN_TXBCR_CR8_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 Mask */ 2988 #define MCAN_TXBCR_CR8 MCAN_TXBCR_CR8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR8_Msk instead */ 2989 #define MCAN_TXBCR_CR9_Pos 9 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 Position */ 2990 #define MCAN_TXBCR_CR9_Msk (_U_(0x1) << MCAN_TXBCR_CR9_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 Mask */ 2991 #define MCAN_TXBCR_CR9 MCAN_TXBCR_CR9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR9_Msk instead */ 2992 #define MCAN_TXBCR_CR10_Pos 10 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 Position */ 2993 #define MCAN_TXBCR_CR10_Msk (_U_(0x1) << MCAN_TXBCR_CR10_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 Mask */ 2994 #define MCAN_TXBCR_CR10 MCAN_TXBCR_CR10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR10_Msk instead */ 2995 #define MCAN_TXBCR_CR11_Pos 11 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 Position */ 2996 #define MCAN_TXBCR_CR11_Msk (_U_(0x1) << MCAN_TXBCR_CR11_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 Mask */ 2997 #define MCAN_TXBCR_CR11 MCAN_TXBCR_CR11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR11_Msk instead */ 2998 #define MCAN_TXBCR_CR12_Pos 12 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 Position */ 2999 #define MCAN_TXBCR_CR12_Msk (_U_(0x1) << MCAN_TXBCR_CR12_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 Mask */ 3000 #define MCAN_TXBCR_CR12 MCAN_TXBCR_CR12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR12_Msk instead */ 3001 #define MCAN_TXBCR_CR13_Pos 13 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 Position */ 3002 #define MCAN_TXBCR_CR13_Msk (_U_(0x1) << MCAN_TXBCR_CR13_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 Mask */ 3003 #define MCAN_TXBCR_CR13 MCAN_TXBCR_CR13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR13_Msk instead */ 3004 #define MCAN_TXBCR_CR14_Pos 14 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 Position */ 3005 #define MCAN_TXBCR_CR14_Msk (_U_(0x1) << MCAN_TXBCR_CR14_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 Mask */ 3006 #define MCAN_TXBCR_CR14 MCAN_TXBCR_CR14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR14_Msk instead */ 3007 #define MCAN_TXBCR_CR15_Pos 15 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 Position */ 3008 #define MCAN_TXBCR_CR15_Msk (_U_(0x1) << MCAN_TXBCR_CR15_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 Mask */ 3009 #define MCAN_TXBCR_CR15 MCAN_TXBCR_CR15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR15_Msk instead */ 3010 #define MCAN_TXBCR_CR16_Pos 16 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 Position */ 3011 #define MCAN_TXBCR_CR16_Msk (_U_(0x1) << MCAN_TXBCR_CR16_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 Mask */ 3012 #define MCAN_TXBCR_CR16 MCAN_TXBCR_CR16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR16_Msk instead */ 3013 #define MCAN_TXBCR_CR17_Pos 17 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 Position */ 3014 #define MCAN_TXBCR_CR17_Msk (_U_(0x1) << MCAN_TXBCR_CR17_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 Mask */ 3015 #define MCAN_TXBCR_CR17 MCAN_TXBCR_CR17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR17_Msk instead */ 3016 #define MCAN_TXBCR_CR18_Pos 18 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 Position */ 3017 #define MCAN_TXBCR_CR18_Msk (_U_(0x1) << MCAN_TXBCR_CR18_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 Mask */ 3018 #define MCAN_TXBCR_CR18 MCAN_TXBCR_CR18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR18_Msk instead */ 3019 #define MCAN_TXBCR_CR19_Pos 19 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 Position */ 3020 #define MCAN_TXBCR_CR19_Msk (_U_(0x1) << MCAN_TXBCR_CR19_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 Mask */ 3021 #define MCAN_TXBCR_CR19 MCAN_TXBCR_CR19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR19_Msk instead */ 3022 #define MCAN_TXBCR_CR20_Pos 20 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 Position */ 3023 #define MCAN_TXBCR_CR20_Msk (_U_(0x1) << MCAN_TXBCR_CR20_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 Mask */ 3024 #define MCAN_TXBCR_CR20 MCAN_TXBCR_CR20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR20_Msk instead */ 3025 #define MCAN_TXBCR_CR21_Pos 21 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 Position */ 3026 #define MCAN_TXBCR_CR21_Msk (_U_(0x1) << MCAN_TXBCR_CR21_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 Mask */ 3027 #define MCAN_TXBCR_CR21 MCAN_TXBCR_CR21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR21_Msk instead */ 3028 #define MCAN_TXBCR_CR22_Pos 22 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 Position */ 3029 #define MCAN_TXBCR_CR22_Msk (_U_(0x1) << MCAN_TXBCR_CR22_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 Mask */ 3030 #define MCAN_TXBCR_CR22 MCAN_TXBCR_CR22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR22_Msk instead */ 3031 #define MCAN_TXBCR_CR23_Pos 23 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 Position */ 3032 #define MCAN_TXBCR_CR23_Msk (_U_(0x1) << MCAN_TXBCR_CR23_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 Mask */ 3033 #define MCAN_TXBCR_CR23 MCAN_TXBCR_CR23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR23_Msk instead */ 3034 #define MCAN_TXBCR_CR24_Pos 24 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 Position */ 3035 #define MCAN_TXBCR_CR24_Msk (_U_(0x1) << MCAN_TXBCR_CR24_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 Mask */ 3036 #define MCAN_TXBCR_CR24 MCAN_TXBCR_CR24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR24_Msk instead */ 3037 #define MCAN_TXBCR_CR25_Pos 25 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 Position */ 3038 #define MCAN_TXBCR_CR25_Msk (_U_(0x1) << MCAN_TXBCR_CR25_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 Mask */ 3039 #define MCAN_TXBCR_CR25 MCAN_TXBCR_CR25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR25_Msk instead */ 3040 #define MCAN_TXBCR_CR26_Pos 26 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 Position */ 3041 #define MCAN_TXBCR_CR26_Msk (_U_(0x1) << MCAN_TXBCR_CR26_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 Mask */ 3042 #define MCAN_TXBCR_CR26 MCAN_TXBCR_CR26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR26_Msk instead */ 3043 #define MCAN_TXBCR_CR27_Pos 27 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 Position */ 3044 #define MCAN_TXBCR_CR27_Msk (_U_(0x1) << MCAN_TXBCR_CR27_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 Mask */ 3045 #define MCAN_TXBCR_CR27 MCAN_TXBCR_CR27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR27_Msk instead */ 3046 #define MCAN_TXBCR_CR28_Pos 28 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 Position */ 3047 #define MCAN_TXBCR_CR28_Msk (_U_(0x1) << MCAN_TXBCR_CR28_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 Mask */ 3048 #define MCAN_TXBCR_CR28 MCAN_TXBCR_CR28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR28_Msk instead */ 3049 #define MCAN_TXBCR_CR29_Pos 29 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 Position */ 3050 #define MCAN_TXBCR_CR29_Msk (_U_(0x1) << MCAN_TXBCR_CR29_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 Mask */ 3051 #define MCAN_TXBCR_CR29 MCAN_TXBCR_CR29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR29_Msk instead */ 3052 #define MCAN_TXBCR_CR30_Pos 30 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 Position */ 3053 #define MCAN_TXBCR_CR30_Msk (_U_(0x1) << MCAN_TXBCR_CR30_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 Mask */ 3054 #define MCAN_TXBCR_CR30 MCAN_TXBCR_CR30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR30_Msk instead */ 3055 #define MCAN_TXBCR_CR31_Pos 31 /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 Position */ 3056 #define MCAN_TXBCR_CR31_Msk (_U_(0x1) << MCAN_TXBCR_CR31_Pos) /**< (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 Mask */ 3057 #define MCAN_TXBCR_CR31 MCAN_TXBCR_CR31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCR_CR31_Msk instead */ 3058 #define MCAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBCR) Register MASK (Use MCAN_TXBCR_Msk instead) */ 3059 #define MCAN_TXBCR_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCR) Register Mask */ 3060 3061 #define MCAN_TXBCR_CR_Pos 0 /**< (MCAN_TXBCR Position) Cancellation Request for Transmit Buffer 3x */ 3062 #define MCAN_TXBCR_CR_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCR_CR_Pos) /**< (MCAN_TXBCR Mask) CR */ 3063 #define MCAN_TXBCR_CR(value) (MCAN_TXBCR_CR_Msk & ((value) << MCAN_TXBCR_CR_Pos)) 3064 3065 /* -------- MCAN_TXBTO : (MCAN Offset: 0xd8) (R/ 32) Transmit Buffer Transmission Occurred Register -------- */ 3066 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3067 #if COMPONENT_TYPEDEF_STYLE == 'N' 3068 typedef union { 3069 struct { 3070 uint32_t TO0:1; /**< bit: 0 Transmission Occurred for Buffer 0 */ 3071 uint32_t TO1:1; /**< bit: 1 Transmission Occurred for Buffer 1 */ 3072 uint32_t TO2:1; /**< bit: 2 Transmission Occurred for Buffer 2 */ 3073 uint32_t TO3:1; /**< bit: 3 Transmission Occurred for Buffer 3 */ 3074 uint32_t TO4:1; /**< bit: 4 Transmission Occurred for Buffer 4 */ 3075 uint32_t TO5:1; /**< bit: 5 Transmission Occurred for Buffer 5 */ 3076 uint32_t TO6:1; /**< bit: 6 Transmission Occurred for Buffer 6 */ 3077 uint32_t TO7:1; /**< bit: 7 Transmission Occurred for Buffer 7 */ 3078 uint32_t TO8:1; /**< bit: 8 Transmission Occurred for Buffer 8 */ 3079 uint32_t TO9:1; /**< bit: 9 Transmission Occurred for Buffer 9 */ 3080 uint32_t TO10:1; /**< bit: 10 Transmission Occurred for Buffer 10 */ 3081 uint32_t TO11:1; /**< bit: 11 Transmission Occurred for Buffer 11 */ 3082 uint32_t TO12:1; /**< bit: 12 Transmission Occurred for Buffer 12 */ 3083 uint32_t TO13:1; /**< bit: 13 Transmission Occurred for Buffer 13 */ 3084 uint32_t TO14:1; /**< bit: 14 Transmission Occurred for Buffer 14 */ 3085 uint32_t TO15:1; /**< bit: 15 Transmission Occurred for Buffer 15 */ 3086 uint32_t TO16:1; /**< bit: 16 Transmission Occurred for Buffer 16 */ 3087 uint32_t TO17:1; /**< bit: 17 Transmission Occurred for Buffer 17 */ 3088 uint32_t TO18:1; /**< bit: 18 Transmission Occurred for Buffer 18 */ 3089 uint32_t TO19:1; /**< bit: 19 Transmission Occurred for Buffer 19 */ 3090 uint32_t TO20:1; /**< bit: 20 Transmission Occurred for Buffer 20 */ 3091 uint32_t TO21:1; /**< bit: 21 Transmission Occurred for Buffer 21 */ 3092 uint32_t TO22:1; /**< bit: 22 Transmission Occurred for Buffer 22 */ 3093 uint32_t TO23:1; /**< bit: 23 Transmission Occurred for Buffer 23 */ 3094 uint32_t TO24:1; /**< bit: 24 Transmission Occurred for Buffer 24 */ 3095 uint32_t TO25:1; /**< bit: 25 Transmission Occurred for Buffer 25 */ 3096 uint32_t TO26:1; /**< bit: 26 Transmission Occurred for Buffer 26 */ 3097 uint32_t TO27:1; /**< bit: 27 Transmission Occurred for Buffer 27 */ 3098 uint32_t TO28:1; /**< bit: 28 Transmission Occurred for Buffer 28 */ 3099 uint32_t TO29:1; /**< bit: 29 Transmission Occurred for Buffer 29 */ 3100 uint32_t TO30:1; /**< bit: 30 Transmission Occurred for Buffer 30 */ 3101 uint32_t TO31:1; /**< bit: 31 Transmission Occurred for Buffer 31 */ 3102 } bit; /**< Structure used for bit access */ 3103 struct { 3104 uint32_t TO:32; /**< bit: 0..31 Transmission Occurred for Buffer 3x */ 3105 } vec; /**< Structure used for vec access */ 3106 uint32_t reg; /**< Type used for register access */ 3107 } MCAN_TXBTO_Type; 3108 #endif 3109 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3110 3111 #define MCAN_TXBTO_OFFSET (0xD8) /**< (MCAN_TXBTO) Transmit Buffer Transmission Occurred Register Offset */ 3112 3113 #define MCAN_TXBTO_TO0_Pos 0 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 0 Position */ 3114 #define MCAN_TXBTO_TO0_Msk (_U_(0x1) << MCAN_TXBTO_TO0_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 0 Mask */ 3115 #define MCAN_TXBTO_TO0 MCAN_TXBTO_TO0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO0_Msk instead */ 3116 #define MCAN_TXBTO_TO1_Pos 1 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 1 Position */ 3117 #define MCAN_TXBTO_TO1_Msk (_U_(0x1) << MCAN_TXBTO_TO1_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 1 Mask */ 3118 #define MCAN_TXBTO_TO1 MCAN_TXBTO_TO1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO1_Msk instead */ 3119 #define MCAN_TXBTO_TO2_Pos 2 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 2 Position */ 3120 #define MCAN_TXBTO_TO2_Msk (_U_(0x1) << MCAN_TXBTO_TO2_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 2 Mask */ 3121 #define MCAN_TXBTO_TO2 MCAN_TXBTO_TO2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO2_Msk instead */ 3122 #define MCAN_TXBTO_TO3_Pos 3 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 3 Position */ 3123 #define MCAN_TXBTO_TO3_Msk (_U_(0x1) << MCAN_TXBTO_TO3_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 3 Mask */ 3124 #define MCAN_TXBTO_TO3 MCAN_TXBTO_TO3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO3_Msk instead */ 3125 #define MCAN_TXBTO_TO4_Pos 4 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 4 Position */ 3126 #define MCAN_TXBTO_TO4_Msk (_U_(0x1) << MCAN_TXBTO_TO4_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 4 Mask */ 3127 #define MCAN_TXBTO_TO4 MCAN_TXBTO_TO4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO4_Msk instead */ 3128 #define MCAN_TXBTO_TO5_Pos 5 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 5 Position */ 3129 #define MCAN_TXBTO_TO5_Msk (_U_(0x1) << MCAN_TXBTO_TO5_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 5 Mask */ 3130 #define MCAN_TXBTO_TO5 MCAN_TXBTO_TO5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO5_Msk instead */ 3131 #define MCAN_TXBTO_TO6_Pos 6 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 6 Position */ 3132 #define MCAN_TXBTO_TO6_Msk (_U_(0x1) << MCAN_TXBTO_TO6_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 6 Mask */ 3133 #define MCAN_TXBTO_TO6 MCAN_TXBTO_TO6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO6_Msk instead */ 3134 #define MCAN_TXBTO_TO7_Pos 7 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 7 Position */ 3135 #define MCAN_TXBTO_TO7_Msk (_U_(0x1) << MCAN_TXBTO_TO7_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 7 Mask */ 3136 #define MCAN_TXBTO_TO7 MCAN_TXBTO_TO7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO7_Msk instead */ 3137 #define MCAN_TXBTO_TO8_Pos 8 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 8 Position */ 3138 #define MCAN_TXBTO_TO8_Msk (_U_(0x1) << MCAN_TXBTO_TO8_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 8 Mask */ 3139 #define MCAN_TXBTO_TO8 MCAN_TXBTO_TO8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO8_Msk instead */ 3140 #define MCAN_TXBTO_TO9_Pos 9 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 9 Position */ 3141 #define MCAN_TXBTO_TO9_Msk (_U_(0x1) << MCAN_TXBTO_TO9_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 9 Mask */ 3142 #define MCAN_TXBTO_TO9 MCAN_TXBTO_TO9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO9_Msk instead */ 3143 #define MCAN_TXBTO_TO10_Pos 10 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 10 Position */ 3144 #define MCAN_TXBTO_TO10_Msk (_U_(0x1) << MCAN_TXBTO_TO10_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 10 Mask */ 3145 #define MCAN_TXBTO_TO10 MCAN_TXBTO_TO10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO10_Msk instead */ 3146 #define MCAN_TXBTO_TO11_Pos 11 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 11 Position */ 3147 #define MCAN_TXBTO_TO11_Msk (_U_(0x1) << MCAN_TXBTO_TO11_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 11 Mask */ 3148 #define MCAN_TXBTO_TO11 MCAN_TXBTO_TO11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO11_Msk instead */ 3149 #define MCAN_TXBTO_TO12_Pos 12 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 12 Position */ 3150 #define MCAN_TXBTO_TO12_Msk (_U_(0x1) << MCAN_TXBTO_TO12_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 12 Mask */ 3151 #define MCAN_TXBTO_TO12 MCAN_TXBTO_TO12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO12_Msk instead */ 3152 #define MCAN_TXBTO_TO13_Pos 13 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 13 Position */ 3153 #define MCAN_TXBTO_TO13_Msk (_U_(0x1) << MCAN_TXBTO_TO13_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 13 Mask */ 3154 #define MCAN_TXBTO_TO13 MCAN_TXBTO_TO13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO13_Msk instead */ 3155 #define MCAN_TXBTO_TO14_Pos 14 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 14 Position */ 3156 #define MCAN_TXBTO_TO14_Msk (_U_(0x1) << MCAN_TXBTO_TO14_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 14 Mask */ 3157 #define MCAN_TXBTO_TO14 MCAN_TXBTO_TO14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO14_Msk instead */ 3158 #define MCAN_TXBTO_TO15_Pos 15 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 15 Position */ 3159 #define MCAN_TXBTO_TO15_Msk (_U_(0x1) << MCAN_TXBTO_TO15_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 15 Mask */ 3160 #define MCAN_TXBTO_TO15 MCAN_TXBTO_TO15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO15_Msk instead */ 3161 #define MCAN_TXBTO_TO16_Pos 16 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 16 Position */ 3162 #define MCAN_TXBTO_TO16_Msk (_U_(0x1) << MCAN_TXBTO_TO16_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 16 Mask */ 3163 #define MCAN_TXBTO_TO16 MCAN_TXBTO_TO16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO16_Msk instead */ 3164 #define MCAN_TXBTO_TO17_Pos 17 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 17 Position */ 3165 #define MCAN_TXBTO_TO17_Msk (_U_(0x1) << MCAN_TXBTO_TO17_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 17 Mask */ 3166 #define MCAN_TXBTO_TO17 MCAN_TXBTO_TO17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO17_Msk instead */ 3167 #define MCAN_TXBTO_TO18_Pos 18 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 18 Position */ 3168 #define MCAN_TXBTO_TO18_Msk (_U_(0x1) << MCAN_TXBTO_TO18_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 18 Mask */ 3169 #define MCAN_TXBTO_TO18 MCAN_TXBTO_TO18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO18_Msk instead */ 3170 #define MCAN_TXBTO_TO19_Pos 19 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 19 Position */ 3171 #define MCAN_TXBTO_TO19_Msk (_U_(0x1) << MCAN_TXBTO_TO19_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 19 Mask */ 3172 #define MCAN_TXBTO_TO19 MCAN_TXBTO_TO19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO19_Msk instead */ 3173 #define MCAN_TXBTO_TO20_Pos 20 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 20 Position */ 3174 #define MCAN_TXBTO_TO20_Msk (_U_(0x1) << MCAN_TXBTO_TO20_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 20 Mask */ 3175 #define MCAN_TXBTO_TO20 MCAN_TXBTO_TO20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO20_Msk instead */ 3176 #define MCAN_TXBTO_TO21_Pos 21 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 21 Position */ 3177 #define MCAN_TXBTO_TO21_Msk (_U_(0x1) << MCAN_TXBTO_TO21_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 21 Mask */ 3178 #define MCAN_TXBTO_TO21 MCAN_TXBTO_TO21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO21_Msk instead */ 3179 #define MCAN_TXBTO_TO22_Pos 22 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 22 Position */ 3180 #define MCAN_TXBTO_TO22_Msk (_U_(0x1) << MCAN_TXBTO_TO22_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 22 Mask */ 3181 #define MCAN_TXBTO_TO22 MCAN_TXBTO_TO22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO22_Msk instead */ 3182 #define MCAN_TXBTO_TO23_Pos 23 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 23 Position */ 3183 #define MCAN_TXBTO_TO23_Msk (_U_(0x1) << MCAN_TXBTO_TO23_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 23 Mask */ 3184 #define MCAN_TXBTO_TO23 MCAN_TXBTO_TO23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO23_Msk instead */ 3185 #define MCAN_TXBTO_TO24_Pos 24 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 24 Position */ 3186 #define MCAN_TXBTO_TO24_Msk (_U_(0x1) << MCAN_TXBTO_TO24_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 24 Mask */ 3187 #define MCAN_TXBTO_TO24 MCAN_TXBTO_TO24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO24_Msk instead */ 3188 #define MCAN_TXBTO_TO25_Pos 25 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 25 Position */ 3189 #define MCAN_TXBTO_TO25_Msk (_U_(0x1) << MCAN_TXBTO_TO25_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 25 Mask */ 3190 #define MCAN_TXBTO_TO25 MCAN_TXBTO_TO25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO25_Msk instead */ 3191 #define MCAN_TXBTO_TO26_Pos 26 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 26 Position */ 3192 #define MCAN_TXBTO_TO26_Msk (_U_(0x1) << MCAN_TXBTO_TO26_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 26 Mask */ 3193 #define MCAN_TXBTO_TO26 MCAN_TXBTO_TO26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO26_Msk instead */ 3194 #define MCAN_TXBTO_TO27_Pos 27 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 27 Position */ 3195 #define MCAN_TXBTO_TO27_Msk (_U_(0x1) << MCAN_TXBTO_TO27_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 27 Mask */ 3196 #define MCAN_TXBTO_TO27 MCAN_TXBTO_TO27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO27_Msk instead */ 3197 #define MCAN_TXBTO_TO28_Pos 28 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 28 Position */ 3198 #define MCAN_TXBTO_TO28_Msk (_U_(0x1) << MCAN_TXBTO_TO28_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 28 Mask */ 3199 #define MCAN_TXBTO_TO28 MCAN_TXBTO_TO28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO28_Msk instead */ 3200 #define MCAN_TXBTO_TO29_Pos 29 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 29 Position */ 3201 #define MCAN_TXBTO_TO29_Msk (_U_(0x1) << MCAN_TXBTO_TO29_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 29 Mask */ 3202 #define MCAN_TXBTO_TO29 MCAN_TXBTO_TO29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO29_Msk instead */ 3203 #define MCAN_TXBTO_TO30_Pos 30 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 30 Position */ 3204 #define MCAN_TXBTO_TO30_Msk (_U_(0x1) << MCAN_TXBTO_TO30_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 30 Mask */ 3205 #define MCAN_TXBTO_TO30 MCAN_TXBTO_TO30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO30_Msk instead */ 3206 #define MCAN_TXBTO_TO31_Pos 31 /**< (MCAN_TXBTO) Transmission Occurred for Buffer 31 Position */ 3207 #define MCAN_TXBTO_TO31_Msk (_U_(0x1) << MCAN_TXBTO_TO31_Pos) /**< (MCAN_TXBTO) Transmission Occurred for Buffer 31 Mask */ 3208 #define MCAN_TXBTO_TO31 MCAN_TXBTO_TO31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTO_TO31_Msk instead */ 3209 #define MCAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBTO) Register MASK (Use MCAN_TXBTO_Msk instead) */ 3210 #define MCAN_TXBTO_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBTO) Register Mask */ 3211 3212 #define MCAN_TXBTO_TO_Pos 0 /**< (MCAN_TXBTO Position) Transmission Occurred for Buffer 3x */ 3213 #define MCAN_TXBTO_TO_Msk (_U_(0xFFFFFFFF) << MCAN_TXBTO_TO_Pos) /**< (MCAN_TXBTO Mask) TO */ 3214 #define MCAN_TXBTO_TO(value) (MCAN_TXBTO_TO_Msk & ((value) << MCAN_TXBTO_TO_Pos)) 3215 3216 /* -------- MCAN_TXBCF : (MCAN Offset: 0xdc) (R/ 32) Transmit Buffer Cancellation Finished Register -------- */ 3217 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3218 #if COMPONENT_TYPEDEF_STYLE == 'N' 3219 typedef union { 3220 struct { 3221 uint32_t CF0:1; /**< bit: 0 Cancellation Finished for Transmit Buffer 0 */ 3222 uint32_t CF1:1; /**< bit: 1 Cancellation Finished for Transmit Buffer 1 */ 3223 uint32_t CF2:1; /**< bit: 2 Cancellation Finished for Transmit Buffer 2 */ 3224 uint32_t CF3:1; /**< bit: 3 Cancellation Finished for Transmit Buffer 3 */ 3225 uint32_t CF4:1; /**< bit: 4 Cancellation Finished for Transmit Buffer 4 */ 3226 uint32_t CF5:1; /**< bit: 5 Cancellation Finished for Transmit Buffer 5 */ 3227 uint32_t CF6:1; /**< bit: 6 Cancellation Finished for Transmit Buffer 6 */ 3228 uint32_t CF7:1; /**< bit: 7 Cancellation Finished for Transmit Buffer 7 */ 3229 uint32_t CF8:1; /**< bit: 8 Cancellation Finished for Transmit Buffer 8 */ 3230 uint32_t CF9:1; /**< bit: 9 Cancellation Finished for Transmit Buffer 9 */ 3231 uint32_t CF10:1; /**< bit: 10 Cancellation Finished for Transmit Buffer 10 */ 3232 uint32_t CF11:1; /**< bit: 11 Cancellation Finished for Transmit Buffer 11 */ 3233 uint32_t CF12:1; /**< bit: 12 Cancellation Finished for Transmit Buffer 12 */ 3234 uint32_t CF13:1; /**< bit: 13 Cancellation Finished for Transmit Buffer 13 */ 3235 uint32_t CF14:1; /**< bit: 14 Cancellation Finished for Transmit Buffer 14 */ 3236 uint32_t CF15:1; /**< bit: 15 Cancellation Finished for Transmit Buffer 15 */ 3237 uint32_t CF16:1; /**< bit: 16 Cancellation Finished for Transmit Buffer 16 */ 3238 uint32_t CF17:1; /**< bit: 17 Cancellation Finished for Transmit Buffer 17 */ 3239 uint32_t CF18:1; /**< bit: 18 Cancellation Finished for Transmit Buffer 18 */ 3240 uint32_t CF19:1; /**< bit: 19 Cancellation Finished for Transmit Buffer 19 */ 3241 uint32_t CF20:1; /**< bit: 20 Cancellation Finished for Transmit Buffer 20 */ 3242 uint32_t CF21:1; /**< bit: 21 Cancellation Finished for Transmit Buffer 21 */ 3243 uint32_t CF22:1; /**< bit: 22 Cancellation Finished for Transmit Buffer 22 */ 3244 uint32_t CF23:1; /**< bit: 23 Cancellation Finished for Transmit Buffer 23 */ 3245 uint32_t CF24:1; /**< bit: 24 Cancellation Finished for Transmit Buffer 24 */ 3246 uint32_t CF25:1; /**< bit: 25 Cancellation Finished for Transmit Buffer 25 */ 3247 uint32_t CF26:1; /**< bit: 26 Cancellation Finished for Transmit Buffer 26 */ 3248 uint32_t CF27:1; /**< bit: 27 Cancellation Finished for Transmit Buffer 27 */ 3249 uint32_t CF28:1; /**< bit: 28 Cancellation Finished for Transmit Buffer 28 */ 3250 uint32_t CF29:1; /**< bit: 29 Cancellation Finished for Transmit Buffer 29 */ 3251 uint32_t CF30:1; /**< bit: 30 Cancellation Finished for Transmit Buffer 30 */ 3252 uint32_t CF31:1; /**< bit: 31 Cancellation Finished for Transmit Buffer 31 */ 3253 } bit; /**< Structure used for bit access */ 3254 struct { 3255 uint32_t CF:32; /**< bit: 0..31 Cancellation Finished for Transmit Buffer 3x */ 3256 } vec; /**< Structure used for vec access */ 3257 uint32_t reg; /**< Type used for register access */ 3258 } MCAN_TXBCF_Type; 3259 #endif 3260 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3261 3262 #define MCAN_TXBCF_OFFSET (0xDC) /**< (MCAN_TXBCF) Transmit Buffer Cancellation Finished Register Offset */ 3263 3264 #define MCAN_TXBCF_CF0_Pos 0 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 Position */ 3265 #define MCAN_TXBCF_CF0_Msk (_U_(0x1) << MCAN_TXBCF_CF0_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 Mask */ 3266 #define MCAN_TXBCF_CF0 MCAN_TXBCF_CF0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF0_Msk instead */ 3267 #define MCAN_TXBCF_CF1_Pos 1 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 Position */ 3268 #define MCAN_TXBCF_CF1_Msk (_U_(0x1) << MCAN_TXBCF_CF1_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 Mask */ 3269 #define MCAN_TXBCF_CF1 MCAN_TXBCF_CF1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF1_Msk instead */ 3270 #define MCAN_TXBCF_CF2_Pos 2 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 Position */ 3271 #define MCAN_TXBCF_CF2_Msk (_U_(0x1) << MCAN_TXBCF_CF2_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 Mask */ 3272 #define MCAN_TXBCF_CF2 MCAN_TXBCF_CF2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF2_Msk instead */ 3273 #define MCAN_TXBCF_CF3_Pos 3 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 Position */ 3274 #define MCAN_TXBCF_CF3_Msk (_U_(0x1) << MCAN_TXBCF_CF3_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 Mask */ 3275 #define MCAN_TXBCF_CF3 MCAN_TXBCF_CF3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF3_Msk instead */ 3276 #define MCAN_TXBCF_CF4_Pos 4 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 Position */ 3277 #define MCAN_TXBCF_CF4_Msk (_U_(0x1) << MCAN_TXBCF_CF4_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 Mask */ 3278 #define MCAN_TXBCF_CF4 MCAN_TXBCF_CF4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF4_Msk instead */ 3279 #define MCAN_TXBCF_CF5_Pos 5 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 Position */ 3280 #define MCAN_TXBCF_CF5_Msk (_U_(0x1) << MCAN_TXBCF_CF5_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 Mask */ 3281 #define MCAN_TXBCF_CF5 MCAN_TXBCF_CF5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF5_Msk instead */ 3282 #define MCAN_TXBCF_CF6_Pos 6 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 Position */ 3283 #define MCAN_TXBCF_CF6_Msk (_U_(0x1) << MCAN_TXBCF_CF6_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 Mask */ 3284 #define MCAN_TXBCF_CF6 MCAN_TXBCF_CF6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF6_Msk instead */ 3285 #define MCAN_TXBCF_CF7_Pos 7 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 Position */ 3286 #define MCAN_TXBCF_CF7_Msk (_U_(0x1) << MCAN_TXBCF_CF7_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 Mask */ 3287 #define MCAN_TXBCF_CF7 MCAN_TXBCF_CF7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF7_Msk instead */ 3288 #define MCAN_TXBCF_CF8_Pos 8 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 Position */ 3289 #define MCAN_TXBCF_CF8_Msk (_U_(0x1) << MCAN_TXBCF_CF8_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 Mask */ 3290 #define MCAN_TXBCF_CF8 MCAN_TXBCF_CF8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF8_Msk instead */ 3291 #define MCAN_TXBCF_CF9_Pos 9 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 Position */ 3292 #define MCAN_TXBCF_CF9_Msk (_U_(0x1) << MCAN_TXBCF_CF9_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 Mask */ 3293 #define MCAN_TXBCF_CF9 MCAN_TXBCF_CF9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF9_Msk instead */ 3294 #define MCAN_TXBCF_CF10_Pos 10 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 Position */ 3295 #define MCAN_TXBCF_CF10_Msk (_U_(0x1) << MCAN_TXBCF_CF10_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 Mask */ 3296 #define MCAN_TXBCF_CF10 MCAN_TXBCF_CF10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF10_Msk instead */ 3297 #define MCAN_TXBCF_CF11_Pos 11 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 Position */ 3298 #define MCAN_TXBCF_CF11_Msk (_U_(0x1) << MCAN_TXBCF_CF11_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 Mask */ 3299 #define MCAN_TXBCF_CF11 MCAN_TXBCF_CF11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF11_Msk instead */ 3300 #define MCAN_TXBCF_CF12_Pos 12 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 Position */ 3301 #define MCAN_TXBCF_CF12_Msk (_U_(0x1) << MCAN_TXBCF_CF12_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 Mask */ 3302 #define MCAN_TXBCF_CF12 MCAN_TXBCF_CF12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF12_Msk instead */ 3303 #define MCAN_TXBCF_CF13_Pos 13 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 Position */ 3304 #define MCAN_TXBCF_CF13_Msk (_U_(0x1) << MCAN_TXBCF_CF13_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 Mask */ 3305 #define MCAN_TXBCF_CF13 MCAN_TXBCF_CF13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF13_Msk instead */ 3306 #define MCAN_TXBCF_CF14_Pos 14 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 Position */ 3307 #define MCAN_TXBCF_CF14_Msk (_U_(0x1) << MCAN_TXBCF_CF14_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 Mask */ 3308 #define MCAN_TXBCF_CF14 MCAN_TXBCF_CF14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF14_Msk instead */ 3309 #define MCAN_TXBCF_CF15_Pos 15 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 Position */ 3310 #define MCAN_TXBCF_CF15_Msk (_U_(0x1) << MCAN_TXBCF_CF15_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 Mask */ 3311 #define MCAN_TXBCF_CF15 MCAN_TXBCF_CF15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF15_Msk instead */ 3312 #define MCAN_TXBCF_CF16_Pos 16 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 Position */ 3313 #define MCAN_TXBCF_CF16_Msk (_U_(0x1) << MCAN_TXBCF_CF16_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 Mask */ 3314 #define MCAN_TXBCF_CF16 MCAN_TXBCF_CF16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF16_Msk instead */ 3315 #define MCAN_TXBCF_CF17_Pos 17 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 Position */ 3316 #define MCAN_TXBCF_CF17_Msk (_U_(0x1) << MCAN_TXBCF_CF17_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 Mask */ 3317 #define MCAN_TXBCF_CF17 MCAN_TXBCF_CF17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF17_Msk instead */ 3318 #define MCAN_TXBCF_CF18_Pos 18 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 Position */ 3319 #define MCAN_TXBCF_CF18_Msk (_U_(0x1) << MCAN_TXBCF_CF18_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 Mask */ 3320 #define MCAN_TXBCF_CF18 MCAN_TXBCF_CF18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF18_Msk instead */ 3321 #define MCAN_TXBCF_CF19_Pos 19 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 Position */ 3322 #define MCAN_TXBCF_CF19_Msk (_U_(0x1) << MCAN_TXBCF_CF19_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 Mask */ 3323 #define MCAN_TXBCF_CF19 MCAN_TXBCF_CF19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF19_Msk instead */ 3324 #define MCAN_TXBCF_CF20_Pos 20 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 Position */ 3325 #define MCAN_TXBCF_CF20_Msk (_U_(0x1) << MCAN_TXBCF_CF20_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 Mask */ 3326 #define MCAN_TXBCF_CF20 MCAN_TXBCF_CF20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF20_Msk instead */ 3327 #define MCAN_TXBCF_CF21_Pos 21 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 Position */ 3328 #define MCAN_TXBCF_CF21_Msk (_U_(0x1) << MCAN_TXBCF_CF21_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 Mask */ 3329 #define MCAN_TXBCF_CF21 MCAN_TXBCF_CF21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF21_Msk instead */ 3330 #define MCAN_TXBCF_CF22_Pos 22 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 Position */ 3331 #define MCAN_TXBCF_CF22_Msk (_U_(0x1) << MCAN_TXBCF_CF22_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 Mask */ 3332 #define MCAN_TXBCF_CF22 MCAN_TXBCF_CF22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF22_Msk instead */ 3333 #define MCAN_TXBCF_CF23_Pos 23 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 Position */ 3334 #define MCAN_TXBCF_CF23_Msk (_U_(0x1) << MCAN_TXBCF_CF23_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 Mask */ 3335 #define MCAN_TXBCF_CF23 MCAN_TXBCF_CF23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF23_Msk instead */ 3336 #define MCAN_TXBCF_CF24_Pos 24 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 Position */ 3337 #define MCAN_TXBCF_CF24_Msk (_U_(0x1) << MCAN_TXBCF_CF24_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 Mask */ 3338 #define MCAN_TXBCF_CF24 MCAN_TXBCF_CF24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF24_Msk instead */ 3339 #define MCAN_TXBCF_CF25_Pos 25 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 Position */ 3340 #define MCAN_TXBCF_CF25_Msk (_U_(0x1) << MCAN_TXBCF_CF25_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 Mask */ 3341 #define MCAN_TXBCF_CF25 MCAN_TXBCF_CF25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF25_Msk instead */ 3342 #define MCAN_TXBCF_CF26_Pos 26 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 Position */ 3343 #define MCAN_TXBCF_CF26_Msk (_U_(0x1) << MCAN_TXBCF_CF26_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 Mask */ 3344 #define MCAN_TXBCF_CF26 MCAN_TXBCF_CF26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF26_Msk instead */ 3345 #define MCAN_TXBCF_CF27_Pos 27 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 Position */ 3346 #define MCAN_TXBCF_CF27_Msk (_U_(0x1) << MCAN_TXBCF_CF27_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 Mask */ 3347 #define MCAN_TXBCF_CF27 MCAN_TXBCF_CF27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF27_Msk instead */ 3348 #define MCAN_TXBCF_CF28_Pos 28 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 Position */ 3349 #define MCAN_TXBCF_CF28_Msk (_U_(0x1) << MCAN_TXBCF_CF28_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 Mask */ 3350 #define MCAN_TXBCF_CF28 MCAN_TXBCF_CF28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF28_Msk instead */ 3351 #define MCAN_TXBCF_CF29_Pos 29 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 Position */ 3352 #define MCAN_TXBCF_CF29_Msk (_U_(0x1) << MCAN_TXBCF_CF29_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 Mask */ 3353 #define MCAN_TXBCF_CF29 MCAN_TXBCF_CF29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF29_Msk instead */ 3354 #define MCAN_TXBCF_CF30_Pos 30 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 Position */ 3355 #define MCAN_TXBCF_CF30_Msk (_U_(0x1) << MCAN_TXBCF_CF30_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 Mask */ 3356 #define MCAN_TXBCF_CF30 MCAN_TXBCF_CF30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF30_Msk instead */ 3357 #define MCAN_TXBCF_CF31_Pos 31 /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 Position */ 3358 #define MCAN_TXBCF_CF31_Msk (_U_(0x1) << MCAN_TXBCF_CF31_Pos) /**< (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 Mask */ 3359 #define MCAN_TXBCF_CF31 MCAN_TXBCF_CF31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCF_CF31_Msk instead */ 3360 #define MCAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBCF) Register MASK (Use MCAN_TXBCF_Msk instead) */ 3361 #define MCAN_TXBCF_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCF) Register Mask */ 3362 3363 #define MCAN_TXBCF_CF_Pos 0 /**< (MCAN_TXBCF Position) Cancellation Finished for Transmit Buffer 3x */ 3364 #define MCAN_TXBCF_CF_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCF_CF_Pos) /**< (MCAN_TXBCF Mask) CF */ 3365 #define MCAN_TXBCF_CF(value) (MCAN_TXBCF_CF_Msk & ((value) << MCAN_TXBCF_CF_Pos)) 3366 3367 /* -------- MCAN_TXBTIE : (MCAN Offset: 0xe0) (R/W 32) Transmit Buffer Transmission Interrupt Enable Register -------- */ 3368 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3369 #if COMPONENT_TYPEDEF_STYLE == 'N' 3370 typedef union { 3371 struct { 3372 uint32_t TIE0:1; /**< bit: 0 Transmission Interrupt Enable for Buffer 0 */ 3373 uint32_t TIE1:1; /**< bit: 1 Transmission Interrupt Enable for Buffer 1 */ 3374 uint32_t TIE2:1; /**< bit: 2 Transmission Interrupt Enable for Buffer 2 */ 3375 uint32_t TIE3:1; /**< bit: 3 Transmission Interrupt Enable for Buffer 3 */ 3376 uint32_t TIE4:1; /**< bit: 4 Transmission Interrupt Enable for Buffer 4 */ 3377 uint32_t TIE5:1; /**< bit: 5 Transmission Interrupt Enable for Buffer 5 */ 3378 uint32_t TIE6:1; /**< bit: 6 Transmission Interrupt Enable for Buffer 6 */ 3379 uint32_t TIE7:1; /**< bit: 7 Transmission Interrupt Enable for Buffer 7 */ 3380 uint32_t TIE8:1; /**< bit: 8 Transmission Interrupt Enable for Buffer 8 */ 3381 uint32_t TIE9:1; /**< bit: 9 Transmission Interrupt Enable for Buffer 9 */ 3382 uint32_t TIE10:1; /**< bit: 10 Transmission Interrupt Enable for Buffer 10 */ 3383 uint32_t TIE11:1; /**< bit: 11 Transmission Interrupt Enable for Buffer 11 */ 3384 uint32_t TIE12:1; /**< bit: 12 Transmission Interrupt Enable for Buffer 12 */ 3385 uint32_t TIE13:1; /**< bit: 13 Transmission Interrupt Enable for Buffer 13 */ 3386 uint32_t TIE14:1; /**< bit: 14 Transmission Interrupt Enable for Buffer 14 */ 3387 uint32_t TIE15:1; /**< bit: 15 Transmission Interrupt Enable for Buffer 15 */ 3388 uint32_t TIE16:1; /**< bit: 16 Transmission Interrupt Enable for Buffer 16 */ 3389 uint32_t TIE17:1; /**< bit: 17 Transmission Interrupt Enable for Buffer 17 */ 3390 uint32_t TIE18:1; /**< bit: 18 Transmission Interrupt Enable for Buffer 18 */ 3391 uint32_t TIE19:1; /**< bit: 19 Transmission Interrupt Enable for Buffer 19 */ 3392 uint32_t TIE20:1; /**< bit: 20 Transmission Interrupt Enable for Buffer 20 */ 3393 uint32_t TIE21:1; /**< bit: 21 Transmission Interrupt Enable for Buffer 21 */ 3394 uint32_t TIE22:1; /**< bit: 22 Transmission Interrupt Enable for Buffer 22 */ 3395 uint32_t TIE23:1; /**< bit: 23 Transmission Interrupt Enable for Buffer 23 */ 3396 uint32_t TIE24:1; /**< bit: 24 Transmission Interrupt Enable for Buffer 24 */ 3397 uint32_t TIE25:1; /**< bit: 25 Transmission Interrupt Enable for Buffer 25 */ 3398 uint32_t TIE26:1; /**< bit: 26 Transmission Interrupt Enable for Buffer 26 */ 3399 uint32_t TIE27:1; /**< bit: 27 Transmission Interrupt Enable for Buffer 27 */ 3400 uint32_t TIE28:1; /**< bit: 28 Transmission Interrupt Enable for Buffer 28 */ 3401 uint32_t TIE29:1; /**< bit: 29 Transmission Interrupt Enable for Buffer 29 */ 3402 uint32_t TIE30:1; /**< bit: 30 Transmission Interrupt Enable for Buffer 30 */ 3403 uint32_t TIE31:1; /**< bit: 31 Transmission Interrupt Enable for Buffer 31 */ 3404 } bit; /**< Structure used for bit access */ 3405 struct { 3406 uint32_t TIE:32; /**< bit: 0..31 Transmission Interrupt Enable for Buffer 3x */ 3407 } vec; /**< Structure used for vec access */ 3408 uint32_t reg; /**< Type used for register access */ 3409 } MCAN_TXBTIE_Type; 3410 #endif 3411 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3412 3413 #define MCAN_TXBTIE_OFFSET (0xE0) /**< (MCAN_TXBTIE) Transmit Buffer Transmission Interrupt Enable Register Offset */ 3414 3415 #define MCAN_TXBTIE_TIE0_Pos 0 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 Position */ 3416 #define MCAN_TXBTIE_TIE0_Msk (_U_(0x1) << MCAN_TXBTIE_TIE0_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 Mask */ 3417 #define MCAN_TXBTIE_TIE0 MCAN_TXBTIE_TIE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE0_Msk instead */ 3418 #define MCAN_TXBTIE_TIE1_Pos 1 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 Position */ 3419 #define MCAN_TXBTIE_TIE1_Msk (_U_(0x1) << MCAN_TXBTIE_TIE1_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 Mask */ 3420 #define MCAN_TXBTIE_TIE1 MCAN_TXBTIE_TIE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE1_Msk instead */ 3421 #define MCAN_TXBTIE_TIE2_Pos 2 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 Position */ 3422 #define MCAN_TXBTIE_TIE2_Msk (_U_(0x1) << MCAN_TXBTIE_TIE2_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 Mask */ 3423 #define MCAN_TXBTIE_TIE2 MCAN_TXBTIE_TIE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE2_Msk instead */ 3424 #define MCAN_TXBTIE_TIE3_Pos 3 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 Position */ 3425 #define MCAN_TXBTIE_TIE3_Msk (_U_(0x1) << MCAN_TXBTIE_TIE3_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 Mask */ 3426 #define MCAN_TXBTIE_TIE3 MCAN_TXBTIE_TIE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE3_Msk instead */ 3427 #define MCAN_TXBTIE_TIE4_Pos 4 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 Position */ 3428 #define MCAN_TXBTIE_TIE4_Msk (_U_(0x1) << MCAN_TXBTIE_TIE4_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 Mask */ 3429 #define MCAN_TXBTIE_TIE4 MCAN_TXBTIE_TIE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE4_Msk instead */ 3430 #define MCAN_TXBTIE_TIE5_Pos 5 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 Position */ 3431 #define MCAN_TXBTIE_TIE5_Msk (_U_(0x1) << MCAN_TXBTIE_TIE5_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 Mask */ 3432 #define MCAN_TXBTIE_TIE5 MCAN_TXBTIE_TIE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE5_Msk instead */ 3433 #define MCAN_TXBTIE_TIE6_Pos 6 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 Position */ 3434 #define MCAN_TXBTIE_TIE6_Msk (_U_(0x1) << MCAN_TXBTIE_TIE6_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 Mask */ 3435 #define MCAN_TXBTIE_TIE6 MCAN_TXBTIE_TIE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE6_Msk instead */ 3436 #define MCAN_TXBTIE_TIE7_Pos 7 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 Position */ 3437 #define MCAN_TXBTIE_TIE7_Msk (_U_(0x1) << MCAN_TXBTIE_TIE7_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 Mask */ 3438 #define MCAN_TXBTIE_TIE7 MCAN_TXBTIE_TIE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE7_Msk instead */ 3439 #define MCAN_TXBTIE_TIE8_Pos 8 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 Position */ 3440 #define MCAN_TXBTIE_TIE8_Msk (_U_(0x1) << MCAN_TXBTIE_TIE8_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 Mask */ 3441 #define MCAN_TXBTIE_TIE8 MCAN_TXBTIE_TIE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE8_Msk instead */ 3442 #define MCAN_TXBTIE_TIE9_Pos 9 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 Position */ 3443 #define MCAN_TXBTIE_TIE9_Msk (_U_(0x1) << MCAN_TXBTIE_TIE9_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 Mask */ 3444 #define MCAN_TXBTIE_TIE9 MCAN_TXBTIE_TIE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE9_Msk instead */ 3445 #define MCAN_TXBTIE_TIE10_Pos 10 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 Position */ 3446 #define MCAN_TXBTIE_TIE10_Msk (_U_(0x1) << MCAN_TXBTIE_TIE10_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 Mask */ 3447 #define MCAN_TXBTIE_TIE10 MCAN_TXBTIE_TIE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE10_Msk instead */ 3448 #define MCAN_TXBTIE_TIE11_Pos 11 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 Position */ 3449 #define MCAN_TXBTIE_TIE11_Msk (_U_(0x1) << MCAN_TXBTIE_TIE11_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 Mask */ 3450 #define MCAN_TXBTIE_TIE11 MCAN_TXBTIE_TIE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE11_Msk instead */ 3451 #define MCAN_TXBTIE_TIE12_Pos 12 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 Position */ 3452 #define MCAN_TXBTIE_TIE12_Msk (_U_(0x1) << MCAN_TXBTIE_TIE12_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 Mask */ 3453 #define MCAN_TXBTIE_TIE12 MCAN_TXBTIE_TIE12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE12_Msk instead */ 3454 #define MCAN_TXBTIE_TIE13_Pos 13 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 Position */ 3455 #define MCAN_TXBTIE_TIE13_Msk (_U_(0x1) << MCAN_TXBTIE_TIE13_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 Mask */ 3456 #define MCAN_TXBTIE_TIE13 MCAN_TXBTIE_TIE13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE13_Msk instead */ 3457 #define MCAN_TXBTIE_TIE14_Pos 14 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 Position */ 3458 #define MCAN_TXBTIE_TIE14_Msk (_U_(0x1) << MCAN_TXBTIE_TIE14_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 Mask */ 3459 #define MCAN_TXBTIE_TIE14 MCAN_TXBTIE_TIE14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE14_Msk instead */ 3460 #define MCAN_TXBTIE_TIE15_Pos 15 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 Position */ 3461 #define MCAN_TXBTIE_TIE15_Msk (_U_(0x1) << MCAN_TXBTIE_TIE15_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 Mask */ 3462 #define MCAN_TXBTIE_TIE15 MCAN_TXBTIE_TIE15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE15_Msk instead */ 3463 #define MCAN_TXBTIE_TIE16_Pos 16 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 Position */ 3464 #define MCAN_TXBTIE_TIE16_Msk (_U_(0x1) << MCAN_TXBTIE_TIE16_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 Mask */ 3465 #define MCAN_TXBTIE_TIE16 MCAN_TXBTIE_TIE16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE16_Msk instead */ 3466 #define MCAN_TXBTIE_TIE17_Pos 17 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 Position */ 3467 #define MCAN_TXBTIE_TIE17_Msk (_U_(0x1) << MCAN_TXBTIE_TIE17_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 Mask */ 3468 #define MCAN_TXBTIE_TIE17 MCAN_TXBTIE_TIE17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE17_Msk instead */ 3469 #define MCAN_TXBTIE_TIE18_Pos 18 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 Position */ 3470 #define MCAN_TXBTIE_TIE18_Msk (_U_(0x1) << MCAN_TXBTIE_TIE18_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 Mask */ 3471 #define MCAN_TXBTIE_TIE18 MCAN_TXBTIE_TIE18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE18_Msk instead */ 3472 #define MCAN_TXBTIE_TIE19_Pos 19 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 Position */ 3473 #define MCAN_TXBTIE_TIE19_Msk (_U_(0x1) << MCAN_TXBTIE_TIE19_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 Mask */ 3474 #define MCAN_TXBTIE_TIE19 MCAN_TXBTIE_TIE19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE19_Msk instead */ 3475 #define MCAN_TXBTIE_TIE20_Pos 20 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 Position */ 3476 #define MCAN_TXBTIE_TIE20_Msk (_U_(0x1) << MCAN_TXBTIE_TIE20_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 Mask */ 3477 #define MCAN_TXBTIE_TIE20 MCAN_TXBTIE_TIE20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE20_Msk instead */ 3478 #define MCAN_TXBTIE_TIE21_Pos 21 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 Position */ 3479 #define MCAN_TXBTIE_TIE21_Msk (_U_(0x1) << MCAN_TXBTIE_TIE21_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 Mask */ 3480 #define MCAN_TXBTIE_TIE21 MCAN_TXBTIE_TIE21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE21_Msk instead */ 3481 #define MCAN_TXBTIE_TIE22_Pos 22 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 Position */ 3482 #define MCAN_TXBTIE_TIE22_Msk (_U_(0x1) << MCAN_TXBTIE_TIE22_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 Mask */ 3483 #define MCAN_TXBTIE_TIE22 MCAN_TXBTIE_TIE22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE22_Msk instead */ 3484 #define MCAN_TXBTIE_TIE23_Pos 23 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 Position */ 3485 #define MCAN_TXBTIE_TIE23_Msk (_U_(0x1) << MCAN_TXBTIE_TIE23_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 Mask */ 3486 #define MCAN_TXBTIE_TIE23 MCAN_TXBTIE_TIE23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE23_Msk instead */ 3487 #define MCAN_TXBTIE_TIE24_Pos 24 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 Position */ 3488 #define MCAN_TXBTIE_TIE24_Msk (_U_(0x1) << MCAN_TXBTIE_TIE24_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 Mask */ 3489 #define MCAN_TXBTIE_TIE24 MCAN_TXBTIE_TIE24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE24_Msk instead */ 3490 #define MCAN_TXBTIE_TIE25_Pos 25 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 Position */ 3491 #define MCAN_TXBTIE_TIE25_Msk (_U_(0x1) << MCAN_TXBTIE_TIE25_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 Mask */ 3492 #define MCAN_TXBTIE_TIE25 MCAN_TXBTIE_TIE25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE25_Msk instead */ 3493 #define MCAN_TXBTIE_TIE26_Pos 26 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 Position */ 3494 #define MCAN_TXBTIE_TIE26_Msk (_U_(0x1) << MCAN_TXBTIE_TIE26_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 Mask */ 3495 #define MCAN_TXBTIE_TIE26 MCAN_TXBTIE_TIE26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE26_Msk instead */ 3496 #define MCAN_TXBTIE_TIE27_Pos 27 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 Position */ 3497 #define MCAN_TXBTIE_TIE27_Msk (_U_(0x1) << MCAN_TXBTIE_TIE27_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 Mask */ 3498 #define MCAN_TXBTIE_TIE27 MCAN_TXBTIE_TIE27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE27_Msk instead */ 3499 #define MCAN_TXBTIE_TIE28_Pos 28 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 Position */ 3500 #define MCAN_TXBTIE_TIE28_Msk (_U_(0x1) << MCAN_TXBTIE_TIE28_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 Mask */ 3501 #define MCAN_TXBTIE_TIE28 MCAN_TXBTIE_TIE28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE28_Msk instead */ 3502 #define MCAN_TXBTIE_TIE29_Pos 29 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 Position */ 3503 #define MCAN_TXBTIE_TIE29_Msk (_U_(0x1) << MCAN_TXBTIE_TIE29_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 Mask */ 3504 #define MCAN_TXBTIE_TIE29 MCAN_TXBTIE_TIE29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE29_Msk instead */ 3505 #define MCAN_TXBTIE_TIE30_Pos 30 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 Position */ 3506 #define MCAN_TXBTIE_TIE30_Msk (_U_(0x1) << MCAN_TXBTIE_TIE30_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 Mask */ 3507 #define MCAN_TXBTIE_TIE30 MCAN_TXBTIE_TIE30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE30_Msk instead */ 3508 #define MCAN_TXBTIE_TIE31_Pos 31 /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 Position */ 3509 #define MCAN_TXBTIE_TIE31_Msk (_U_(0x1) << MCAN_TXBTIE_TIE31_Pos) /**< (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 Mask */ 3510 #define MCAN_TXBTIE_TIE31 MCAN_TXBTIE_TIE31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBTIE_TIE31_Msk instead */ 3511 #define MCAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBTIE) Register MASK (Use MCAN_TXBTIE_Msk instead) */ 3512 #define MCAN_TXBTIE_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBTIE) Register Mask */ 3513 3514 #define MCAN_TXBTIE_TIE_Pos 0 /**< (MCAN_TXBTIE Position) Transmission Interrupt Enable for Buffer 3x */ 3515 #define MCAN_TXBTIE_TIE_Msk (_U_(0xFFFFFFFF) << MCAN_TXBTIE_TIE_Pos) /**< (MCAN_TXBTIE Mask) TIE */ 3516 #define MCAN_TXBTIE_TIE(value) (MCAN_TXBTIE_TIE_Msk & ((value) << MCAN_TXBTIE_TIE_Pos)) 3517 3518 /* -------- MCAN_TXBCIE : (MCAN Offset: 0xe4) (R/W 32) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ 3519 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3520 #if COMPONENT_TYPEDEF_STYLE == 'N' 3521 typedef union { 3522 struct { 3523 uint32_t CFIE0:1; /**< bit: 0 Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ 3524 uint32_t CFIE1:1; /**< bit: 1 Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ 3525 uint32_t CFIE2:1; /**< bit: 2 Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ 3526 uint32_t CFIE3:1; /**< bit: 3 Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ 3527 uint32_t CFIE4:1; /**< bit: 4 Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ 3528 uint32_t CFIE5:1; /**< bit: 5 Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ 3529 uint32_t CFIE6:1; /**< bit: 6 Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ 3530 uint32_t CFIE7:1; /**< bit: 7 Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ 3531 uint32_t CFIE8:1; /**< bit: 8 Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ 3532 uint32_t CFIE9:1; /**< bit: 9 Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ 3533 uint32_t CFIE10:1; /**< bit: 10 Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ 3534 uint32_t CFIE11:1; /**< bit: 11 Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ 3535 uint32_t CFIE12:1; /**< bit: 12 Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ 3536 uint32_t CFIE13:1; /**< bit: 13 Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ 3537 uint32_t CFIE14:1; /**< bit: 14 Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ 3538 uint32_t CFIE15:1; /**< bit: 15 Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ 3539 uint32_t CFIE16:1; /**< bit: 16 Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ 3540 uint32_t CFIE17:1; /**< bit: 17 Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ 3541 uint32_t CFIE18:1; /**< bit: 18 Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ 3542 uint32_t CFIE19:1; /**< bit: 19 Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ 3543 uint32_t CFIE20:1; /**< bit: 20 Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ 3544 uint32_t CFIE21:1; /**< bit: 21 Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ 3545 uint32_t CFIE22:1; /**< bit: 22 Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ 3546 uint32_t CFIE23:1; /**< bit: 23 Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ 3547 uint32_t CFIE24:1; /**< bit: 24 Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ 3548 uint32_t CFIE25:1; /**< bit: 25 Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ 3549 uint32_t CFIE26:1; /**< bit: 26 Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ 3550 uint32_t CFIE27:1; /**< bit: 27 Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ 3551 uint32_t CFIE28:1; /**< bit: 28 Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ 3552 uint32_t CFIE29:1; /**< bit: 29 Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ 3553 uint32_t CFIE30:1; /**< bit: 30 Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ 3554 uint32_t CFIE31:1; /**< bit: 31 Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ 3555 } bit; /**< Structure used for bit access */ 3556 struct { 3557 uint32_t CFIE:32; /**< bit: 0..31 Cancellation Finished Interrupt Enable for Transmit Buffer 3x */ 3558 } vec; /**< Structure used for vec access */ 3559 uint32_t reg; /**< Type used for register access */ 3560 } MCAN_TXBCIE_Type; 3561 #endif 3562 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3563 3564 #define MCAN_TXBCIE_OFFSET (0xE4) /**< (MCAN_TXBCIE) Transmit Buffer Cancellation Finished Interrupt Enable Register Offset */ 3565 3566 #define MCAN_TXBCIE_CFIE0_Pos 0 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 Position */ 3567 #define MCAN_TXBCIE_CFIE0_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE0_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 Mask */ 3568 #define MCAN_TXBCIE_CFIE0 MCAN_TXBCIE_CFIE0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE0_Msk instead */ 3569 #define MCAN_TXBCIE_CFIE1_Pos 1 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 Position */ 3570 #define MCAN_TXBCIE_CFIE1_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE1_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 Mask */ 3571 #define MCAN_TXBCIE_CFIE1 MCAN_TXBCIE_CFIE1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE1_Msk instead */ 3572 #define MCAN_TXBCIE_CFIE2_Pos 2 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 Position */ 3573 #define MCAN_TXBCIE_CFIE2_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE2_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 Mask */ 3574 #define MCAN_TXBCIE_CFIE2 MCAN_TXBCIE_CFIE2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE2_Msk instead */ 3575 #define MCAN_TXBCIE_CFIE3_Pos 3 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 Position */ 3576 #define MCAN_TXBCIE_CFIE3_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE3_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 Mask */ 3577 #define MCAN_TXBCIE_CFIE3 MCAN_TXBCIE_CFIE3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE3_Msk instead */ 3578 #define MCAN_TXBCIE_CFIE4_Pos 4 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 Position */ 3579 #define MCAN_TXBCIE_CFIE4_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE4_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 Mask */ 3580 #define MCAN_TXBCIE_CFIE4 MCAN_TXBCIE_CFIE4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE4_Msk instead */ 3581 #define MCAN_TXBCIE_CFIE5_Pos 5 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 Position */ 3582 #define MCAN_TXBCIE_CFIE5_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE5_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 Mask */ 3583 #define MCAN_TXBCIE_CFIE5 MCAN_TXBCIE_CFIE5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE5_Msk instead */ 3584 #define MCAN_TXBCIE_CFIE6_Pos 6 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 Position */ 3585 #define MCAN_TXBCIE_CFIE6_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE6_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 Mask */ 3586 #define MCAN_TXBCIE_CFIE6 MCAN_TXBCIE_CFIE6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE6_Msk instead */ 3587 #define MCAN_TXBCIE_CFIE7_Pos 7 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 Position */ 3588 #define MCAN_TXBCIE_CFIE7_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE7_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 Mask */ 3589 #define MCAN_TXBCIE_CFIE7 MCAN_TXBCIE_CFIE7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE7_Msk instead */ 3590 #define MCAN_TXBCIE_CFIE8_Pos 8 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 Position */ 3591 #define MCAN_TXBCIE_CFIE8_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE8_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 Mask */ 3592 #define MCAN_TXBCIE_CFIE8 MCAN_TXBCIE_CFIE8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE8_Msk instead */ 3593 #define MCAN_TXBCIE_CFIE9_Pos 9 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 Position */ 3594 #define MCAN_TXBCIE_CFIE9_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE9_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 Mask */ 3595 #define MCAN_TXBCIE_CFIE9 MCAN_TXBCIE_CFIE9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE9_Msk instead */ 3596 #define MCAN_TXBCIE_CFIE10_Pos 10 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 Position */ 3597 #define MCAN_TXBCIE_CFIE10_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE10_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 Mask */ 3598 #define MCAN_TXBCIE_CFIE10 MCAN_TXBCIE_CFIE10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE10_Msk instead */ 3599 #define MCAN_TXBCIE_CFIE11_Pos 11 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 Position */ 3600 #define MCAN_TXBCIE_CFIE11_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE11_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 Mask */ 3601 #define MCAN_TXBCIE_CFIE11 MCAN_TXBCIE_CFIE11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE11_Msk instead */ 3602 #define MCAN_TXBCIE_CFIE12_Pos 12 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 Position */ 3603 #define MCAN_TXBCIE_CFIE12_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE12_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 Mask */ 3604 #define MCAN_TXBCIE_CFIE12 MCAN_TXBCIE_CFIE12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE12_Msk instead */ 3605 #define MCAN_TXBCIE_CFIE13_Pos 13 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 Position */ 3606 #define MCAN_TXBCIE_CFIE13_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE13_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 Mask */ 3607 #define MCAN_TXBCIE_CFIE13 MCAN_TXBCIE_CFIE13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE13_Msk instead */ 3608 #define MCAN_TXBCIE_CFIE14_Pos 14 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 Position */ 3609 #define MCAN_TXBCIE_CFIE14_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE14_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 Mask */ 3610 #define MCAN_TXBCIE_CFIE14 MCAN_TXBCIE_CFIE14_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE14_Msk instead */ 3611 #define MCAN_TXBCIE_CFIE15_Pos 15 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 Position */ 3612 #define MCAN_TXBCIE_CFIE15_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE15_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 Mask */ 3613 #define MCAN_TXBCIE_CFIE15 MCAN_TXBCIE_CFIE15_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE15_Msk instead */ 3614 #define MCAN_TXBCIE_CFIE16_Pos 16 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 Position */ 3615 #define MCAN_TXBCIE_CFIE16_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE16_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 Mask */ 3616 #define MCAN_TXBCIE_CFIE16 MCAN_TXBCIE_CFIE16_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE16_Msk instead */ 3617 #define MCAN_TXBCIE_CFIE17_Pos 17 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 Position */ 3618 #define MCAN_TXBCIE_CFIE17_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE17_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 Mask */ 3619 #define MCAN_TXBCIE_CFIE17 MCAN_TXBCIE_CFIE17_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE17_Msk instead */ 3620 #define MCAN_TXBCIE_CFIE18_Pos 18 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 Position */ 3621 #define MCAN_TXBCIE_CFIE18_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE18_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 Mask */ 3622 #define MCAN_TXBCIE_CFIE18 MCAN_TXBCIE_CFIE18_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE18_Msk instead */ 3623 #define MCAN_TXBCIE_CFIE19_Pos 19 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 Position */ 3624 #define MCAN_TXBCIE_CFIE19_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE19_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 Mask */ 3625 #define MCAN_TXBCIE_CFIE19 MCAN_TXBCIE_CFIE19_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE19_Msk instead */ 3626 #define MCAN_TXBCIE_CFIE20_Pos 20 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 Position */ 3627 #define MCAN_TXBCIE_CFIE20_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE20_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 Mask */ 3628 #define MCAN_TXBCIE_CFIE20 MCAN_TXBCIE_CFIE20_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE20_Msk instead */ 3629 #define MCAN_TXBCIE_CFIE21_Pos 21 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 Position */ 3630 #define MCAN_TXBCIE_CFIE21_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE21_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 Mask */ 3631 #define MCAN_TXBCIE_CFIE21 MCAN_TXBCIE_CFIE21_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE21_Msk instead */ 3632 #define MCAN_TXBCIE_CFIE22_Pos 22 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 Position */ 3633 #define MCAN_TXBCIE_CFIE22_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE22_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 Mask */ 3634 #define MCAN_TXBCIE_CFIE22 MCAN_TXBCIE_CFIE22_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE22_Msk instead */ 3635 #define MCAN_TXBCIE_CFIE23_Pos 23 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 Position */ 3636 #define MCAN_TXBCIE_CFIE23_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE23_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 Mask */ 3637 #define MCAN_TXBCIE_CFIE23 MCAN_TXBCIE_CFIE23_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE23_Msk instead */ 3638 #define MCAN_TXBCIE_CFIE24_Pos 24 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 Position */ 3639 #define MCAN_TXBCIE_CFIE24_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE24_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 Mask */ 3640 #define MCAN_TXBCIE_CFIE24 MCAN_TXBCIE_CFIE24_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE24_Msk instead */ 3641 #define MCAN_TXBCIE_CFIE25_Pos 25 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 Position */ 3642 #define MCAN_TXBCIE_CFIE25_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE25_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 Mask */ 3643 #define MCAN_TXBCIE_CFIE25 MCAN_TXBCIE_CFIE25_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE25_Msk instead */ 3644 #define MCAN_TXBCIE_CFIE26_Pos 26 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 Position */ 3645 #define MCAN_TXBCIE_CFIE26_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE26_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 Mask */ 3646 #define MCAN_TXBCIE_CFIE26 MCAN_TXBCIE_CFIE26_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE26_Msk instead */ 3647 #define MCAN_TXBCIE_CFIE27_Pos 27 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 Position */ 3648 #define MCAN_TXBCIE_CFIE27_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE27_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 Mask */ 3649 #define MCAN_TXBCIE_CFIE27 MCAN_TXBCIE_CFIE27_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE27_Msk instead */ 3650 #define MCAN_TXBCIE_CFIE28_Pos 28 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 Position */ 3651 #define MCAN_TXBCIE_CFIE28_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE28_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 Mask */ 3652 #define MCAN_TXBCIE_CFIE28 MCAN_TXBCIE_CFIE28_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE28_Msk instead */ 3653 #define MCAN_TXBCIE_CFIE29_Pos 29 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 Position */ 3654 #define MCAN_TXBCIE_CFIE29_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE29_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 Mask */ 3655 #define MCAN_TXBCIE_CFIE29 MCAN_TXBCIE_CFIE29_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE29_Msk instead */ 3656 #define MCAN_TXBCIE_CFIE30_Pos 30 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 Position */ 3657 #define MCAN_TXBCIE_CFIE30_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE30_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 Mask */ 3658 #define MCAN_TXBCIE_CFIE30 MCAN_TXBCIE_CFIE30_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE30_Msk instead */ 3659 #define MCAN_TXBCIE_CFIE31_Pos 31 /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 Position */ 3660 #define MCAN_TXBCIE_CFIE31_Msk (_U_(0x1) << MCAN_TXBCIE_CFIE31_Pos) /**< (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 Mask */ 3661 #define MCAN_TXBCIE_CFIE31 MCAN_TXBCIE_CFIE31_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXBCIE_CFIE31_Msk instead */ 3662 #define MCAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \deprecated (MCAN_TXBCIE) Register MASK (Use MCAN_TXBCIE_Msk instead) */ 3663 #define MCAN_TXBCIE_Msk _U_(0xFFFFFFFF) /**< (MCAN_TXBCIE) Register Mask */ 3664 3665 #define MCAN_TXBCIE_CFIE_Pos 0 /**< (MCAN_TXBCIE Position) Cancellation Finished Interrupt Enable for Transmit Buffer 3x */ 3666 #define MCAN_TXBCIE_CFIE_Msk (_U_(0xFFFFFFFF) << MCAN_TXBCIE_CFIE_Pos) /**< (MCAN_TXBCIE Mask) CFIE */ 3667 #define MCAN_TXBCIE_CFIE(value) (MCAN_TXBCIE_CFIE_Msk & ((value) << MCAN_TXBCIE_CFIE_Pos)) 3668 3669 /* -------- MCAN_TXEFC : (MCAN Offset: 0xf0) (R/W 32) Transmit Event FIFO Configuration Register -------- */ 3670 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3671 #if COMPONENT_TYPEDEF_STYLE == 'N' 3672 typedef union { 3673 struct { 3674 uint32_t :2; /**< bit: 0..1 Reserved */ 3675 uint32_t EFSA:14; /**< bit: 2..15 Event FIFO Start Address */ 3676 uint32_t EFS:6; /**< bit: 16..21 Event FIFO Size */ 3677 uint32_t :2; /**< bit: 22..23 Reserved */ 3678 uint32_t EFWM:6; /**< bit: 24..29 Event FIFO Watermark */ 3679 uint32_t :2; /**< bit: 30..31 Reserved */ 3680 } bit; /**< Structure used for bit access */ 3681 uint32_t reg; /**< Type used for register access */ 3682 } MCAN_TXEFC_Type; 3683 #endif 3684 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3685 3686 #define MCAN_TXEFC_OFFSET (0xF0) /**< (MCAN_TXEFC) Transmit Event FIFO Configuration Register Offset */ 3687 3688 #define MCAN_TXEFC_EFSA_Pos 2 /**< (MCAN_TXEFC) Event FIFO Start Address Position */ 3689 #define MCAN_TXEFC_EFSA_Msk (_U_(0x3FFF) << MCAN_TXEFC_EFSA_Pos) /**< (MCAN_TXEFC) Event FIFO Start Address Mask */ 3690 #define MCAN_TXEFC_EFSA(value) (MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos)) 3691 #define MCAN_TXEFC_EFS_Pos 16 /**< (MCAN_TXEFC) Event FIFO Size Position */ 3692 #define MCAN_TXEFC_EFS_Msk (_U_(0x3F) << MCAN_TXEFC_EFS_Pos) /**< (MCAN_TXEFC) Event FIFO Size Mask */ 3693 #define MCAN_TXEFC_EFS(value) (MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos)) 3694 #define MCAN_TXEFC_EFWM_Pos 24 /**< (MCAN_TXEFC) Event FIFO Watermark Position */ 3695 #define MCAN_TXEFC_EFWM_Msk (_U_(0x3F) << MCAN_TXEFC_EFWM_Pos) /**< (MCAN_TXEFC) Event FIFO Watermark Mask */ 3696 #define MCAN_TXEFC_EFWM(value) (MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos)) 3697 #define MCAN_TXEFC_MASK _U_(0x3F3FFFFC) /**< \deprecated (MCAN_TXEFC) Register MASK (Use MCAN_TXEFC_Msk instead) */ 3698 #define MCAN_TXEFC_Msk _U_(0x3F3FFFFC) /**< (MCAN_TXEFC) Register Mask */ 3699 3700 3701 /* -------- MCAN_TXEFS : (MCAN Offset: 0xf4) (R/ 32) Transmit Event FIFO Status Register -------- */ 3702 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3703 #if COMPONENT_TYPEDEF_STYLE == 'N' 3704 typedef union { 3705 struct { 3706 uint32_t EFFL:6; /**< bit: 0..5 Event FIFO Fill Level */ 3707 uint32_t :2; /**< bit: 6..7 Reserved */ 3708 uint32_t EFGI:5; /**< bit: 8..12 Event FIFO Get Index */ 3709 uint32_t :3; /**< bit: 13..15 Reserved */ 3710 uint32_t EFPI:5; /**< bit: 16..20 Event FIFO Put Index */ 3711 uint32_t :3; /**< bit: 21..23 Reserved */ 3712 uint32_t EFF:1; /**< bit: 24 Event FIFO Full */ 3713 uint32_t TEFL:1; /**< bit: 25 Tx Event FIFO Element Lost */ 3714 uint32_t :6; /**< bit: 26..31 Reserved */ 3715 } bit; /**< Structure used for bit access */ 3716 uint32_t reg; /**< Type used for register access */ 3717 } MCAN_TXEFS_Type; 3718 #endif 3719 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3720 3721 #define MCAN_TXEFS_OFFSET (0xF4) /**< (MCAN_TXEFS) Transmit Event FIFO Status Register Offset */ 3722 3723 #define MCAN_TXEFS_EFFL_Pos 0 /**< (MCAN_TXEFS) Event FIFO Fill Level Position */ 3724 #define MCAN_TXEFS_EFFL_Msk (_U_(0x3F) << MCAN_TXEFS_EFFL_Pos) /**< (MCAN_TXEFS) Event FIFO Fill Level Mask */ 3725 #define MCAN_TXEFS_EFFL(value) (MCAN_TXEFS_EFFL_Msk & ((value) << MCAN_TXEFS_EFFL_Pos)) 3726 #define MCAN_TXEFS_EFGI_Pos 8 /**< (MCAN_TXEFS) Event FIFO Get Index Position */ 3727 #define MCAN_TXEFS_EFGI_Msk (_U_(0x1F) << MCAN_TXEFS_EFGI_Pos) /**< (MCAN_TXEFS) Event FIFO Get Index Mask */ 3728 #define MCAN_TXEFS_EFGI(value) (MCAN_TXEFS_EFGI_Msk & ((value) << MCAN_TXEFS_EFGI_Pos)) 3729 #define MCAN_TXEFS_EFPI_Pos 16 /**< (MCAN_TXEFS) Event FIFO Put Index Position */ 3730 #define MCAN_TXEFS_EFPI_Msk (_U_(0x1F) << MCAN_TXEFS_EFPI_Pos) /**< (MCAN_TXEFS) Event FIFO Put Index Mask */ 3731 #define MCAN_TXEFS_EFPI(value) (MCAN_TXEFS_EFPI_Msk & ((value) << MCAN_TXEFS_EFPI_Pos)) 3732 #define MCAN_TXEFS_EFF_Pos 24 /**< (MCAN_TXEFS) Event FIFO Full Position */ 3733 #define MCAN_TXEFS_EFF_Msk (_U_(0x1) << MCAN_TXEFS_EFF_Pos) /**< (MCAN_TXEFS) Event FIFO Full Mask */ 3734 #define MCAN_TXEFS_EFF MCAN_TXEFS_EFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFS_EFF_Msk instead */ 3735 #define MCAN_TXEFS_TEFL_Pos 25 /**< (MCAN_TXEFS) Tx Event FIFO Element Lost Position */ 3736 #define MCAN_TXEFS_TEFL_Msk (_U_(0x1) << MCAN_TXEFS_TEFL_Pos) /**< (MCAN_TXEFS) Tx Event FIFO Element Lost Mask */ 3737 #define MCAN_TXEFS_TEFL MCAN_TXEFS_TEFL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use MCAN_TXEFS_TEFL_Msk instead */ 3738 #define MCAN_TXEFS_MASK _U_(0x31F1F3F) /**< \deprecated (MCAN_TXEFS) Register MASK (Use MCAN_TXEFS_Msk instead) */ 3739 #define MCAN_TXEFS_Msk _U_(0x31F1F3F) /**< (MCAN_TXEFS) Register Mask */ 3740 3741 3742 /* -------- MCAN_TXEFA : (MCAN Offset: 0xf8) (R/W 32) Transmit Event FIFO Acknowledge Register -------- */ 3743 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3744 #if COMPONENT_TYPEDEF_STYLE == 'N' 3745 typedef union { 3746 struct { 3747 uint32_t EFAI:5; /**< bit: 0..4 Event FIFO Acknowledge Index */ 3748 uint32_t :27; /**< bit: 5..31 Reserved */ 3749 } bit; /**< Structure used for bit access */ 3750 uint32_t reg; /**< Type used for register access */ 3751 } MCAN_TXEFA_Type; 3752 #endif 3753 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 3754 3755 #define MCAN_TXEFA_OFFSET (0xF8) /**< (MCAN_TXEFA) Transmit Event FIFO Acknowledge Register Offset */ 3756 3757 #define MCAN_TXEFA_EFAI_Pos 0 /**< (MCAN_TXEFA) Event FIFO Acknowledge Index Position */ 3758 #define MCAN_TXEFA_EFAI_Msk (_U_(0x1F) << MCAN_TXEFA_EFAI_Pos) /**< (MCAN_TXEFA) Event FIFO Acknowledge Index Mask */ 3759 #define MCAN_TXEFA_EFAI(value) (MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos)) 3760 #define MCAN_TXEFA_MASK _U_(0x1F) /**< \deprecated (MCAN_TXEFA) Register MASK (Use MCAN_TXEFA_Msk instead) */ 3761 #define MCAN_TXEFA_Msk _U_(0x1F) /**< (MCAN_TXEFA) Register Mask */ 3762 3763 3764 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 3765 #if COMPONENT_TYPEDEF_STYLE == 'R' 3766 /** \brief MCAN_RXBE hardware registers */ 3767 typedef struct { /* Rx Buffer Element */ 3768 __IO uint32_t MCAN_RXBE_0; /**< (MCAN_RXBE Offset: 0x00) Rx Buffer Element 0 */ 3769 __IO uint32_t MCAN_RXBE_1; /**< (MCAN_RXBE Offset: 0x04) Rx Buffer Element 1 */ 3770 __IO uint32_t MCAN_RXBE_DATA; /**< (MCAN_RXBE Offset: 0x08) Rx Buffer Element Data */ 3771 } McanRxbe 3772 #ifdef __GNUC__ 3773 __attribute__ ((aligned (4))) 3774 #endif 3775 ; 3776 3777 /** \brief MCAN_RXF0E hardware registers */ 3778 typedef struct { /* Rx FIFO 0 Element */ 3779 __IO uint32_t MCAN_RXF0E_0; /**< (MCAN_RXF0E Offset: 0x00) Rx FIFO 0 Element 0 */ 3780 __IO uint32_t MCAN_RXF0E_1; /**< (MCAN_RXF0E Offset: 0x04) Rx FIFO 0 Element 1 */ 3781 __IO uint32_t MCAN_RXF0E_DATA; /**< (MCAN_RXF0E Offset: 0x08) Rx FIFO 0 Element Data */ 3782 } McanRxf0e 3783 #ifdef __GNUC__ 3784 __attribute__ ((aligned (4))) 3785 #endif 3786 ; 3787 3788 /** \brief MCAN_RXF1E hardware registers */ 3789 typedef struct { /* Rx FIFO 1 Element */ 3790 __IO uint32_t MCAN_RXF1E_0; /**< (MCAN_RXF1E Offset: 0x00) Rx FIFO 1 Element 0 */ 3791 __IO uint32_t MCAN_RXF1E_1; /**< (MCAN_RXF1E Offset: 0x04) Rx FIFO 1 Element 1 */ 3792 __IO uint32_t MCAN_RXF1E_DATA; /**< (MCAN_RXF1E Offset: 0x08) Rx FIFO 1 Element Data */ 3793 } McanRxf1e 3794 #ifdef __GNUC__ 3795 __attribute__ ((aligned (4))) 3796 #endif 3797 ; 3798 3799 /** \brief MCAN_TXBE hardware registers */ 3800 typedef struct { /* Tx Buffer Element */ 3801 __IO uint32_t MCAN_TXBE_0; /**< (MCAN_TXBE Offset: 0x00) Tx Buffer Element 0 */ 3802 __IO uint32_t MCAN_TXBE_1; /**< (MCAN_TXBE Offset: 0x04) Tx Buffer Element 1 */ 3803 __IO uint32_t MCAN_TXBE_DATA; /**< (MCAN_TXBE Offset: 0x08) Tx Buffer Element Data */ 3804 } McanTxbe 3805 #ifdef __GNUC__ 3806 __attribute__ ((aligned (4))) 3807 #endif 3808 ; 3809 3810 /** \brief MCAN_TXEFE hardware registers */ 3811 typedef struct { /* Tx Event FIFO Element */ 3812 __IO uint32_t MCAN_TXEFE_0; /**< (MCAN_TXEFE Offset: 0x00) Tx Event FIFO Element 0 */ 3813 __IO uint32_t MCAN_TXEFE_1; /**< (MCAN_TXEFE Offset: 0x04) Tx Event FIFO Element 1 */ 3814 } McanTxefe 3815 #ifdef __GNUC__ 3816 __attribute__ ((aligned (4))) 3817 #endif 3818 ; 3819 3820 /** \brief MCAN_SIDFE hardware registers */ 3821 typedef struct { /* Standard Message ID Filter Element */ 3822 __IO uint32_t MCAN_SIDFE_0; /**< (MCAN_SIDFE Offset: 0x00) Standard Message ID Filter Element 0 */ 3823 } McanSidfe 3824 #ifdef __GNUC__ 3825 __attribute__ ((aligned (4))) 3826 #endif 3827 ; 3828 3829 /** \brief MCAN_XIDFE hardware registers */ 3830 typedef struct { /* Extended Message ID Filter Element */ 3831 __IO uint32_t MCAN_XIDFE_0; /**< (MCAN_XIDFE Offset: 0x00) Extended Message ID Filter Element 0 */ 3832 __IO uint32_t MCAN_XIDFE_1; /**< (MCAN_XIDFE Offset: 0x04) Extended Message ID Filter Element 1 */ 3833 } McanXidfe 3834 #ifdef __GNUC__ 3835 __attribute__ ((aligned (4))) 3836 #endif 3837 ; 3838 3839 /** \brief MCAN hardware registers */ 3840 typedef struct { 3841 __I uint32_t MCAN_CREL; /**< (MCAN Offset: 0x00) Core Release Register */ 3842 __I uint32_t MCAN_ENDN; /**< (MCAN Offset: 0x04) Endian Register */ 3843 __IO uint32_t MCAN_CUST; /**< (MCAN Offset: 0x08) Customer Register */ 3844 __IO uint32_t MCAN_DBTP; /**< (MCAN Offset: 0x0C) Data Bit Timing and Prescaler Register */ 3845 __IO uint32_t MCAN_TEST; /**< (MCAN Offset: 0x10) Test Register */ 3846 __IO uint32_t MCAN_RWD; /**< (MCAN Offset: 0x14) RAM Watchdog Register */ 3847 __IO uint32_t MCAN_CCCR; /**< (MCAN Offset: 0x18) CC Control Register */ 3848 __IO uint32_t MCAN_NBTP; /**< (MCAN Offset: 0x1C) Nominal Bit Timing and Prescaler Register */ 3849 __IO uint32_t MCAN_TSCC; /**< (MCAN Offset: 0x20) Timestamp Counter Configuration Register */ 3850 __IO uint32_t MCAN_TSCV; /**< (MCAN Offset: 0x24) Timestamp Counter Value Register */ 3851 __IO uint32_t MCAN_TOCC; /**< (MCAN Offset: 0x28) Timeout Counter Configuration Register */ 3852 __IO uint32_t MCAN_TOCV; /**< (MCAN Offset: 0x2C) Timeout Counter Value Register */ 3853 __I uint8_t Reserved1[16]; 3854 __I uint32_t MCAN_ECR; /**< (MCAN Offset: 0x40) Error Counter Register */ 3855 __I uint32_t MCAN_PSR; /**< (MCAN Offset: 0x44) Protocol Status Register */ 3856 __IO uint32_t MCAN_TDCR; /**< (MCAN Offset: 0x48) Transmit Delay Compensation Register */ 3857 __I uint8_t Reserved2[4]; 3858 __IO uint32_t MCAN_IR; /**< (MCAN Offset: 0x50) Interrupt Register */ 3859 __IO uint32_t MCAN_IE; /**< (MCAN Offset: 0x54) Interrupt Enable Register */ 3860 __IO uint32_t MCAN_ILS; /**< (MCAN Offset: 0x58) Interrupt Line Select Register */ 3861 __IO uint32_t MCAN_ILE; /**< (MCAN Offset: 0x5C) Interrupt Line Enable Register */ 3862 __I uint8_t Reserved3[32]; 3863 __IO uint32_t MCAN_GFC; /**< (MCAN Offset: 0x80) Global Filter Configuration Register */ 3864 __IO uint32_t MCAN_SIDFC; /**< (MCAN Offset: 0x84) Standard ID Filter Configuration Register */ 3865 __IO uint32_t MCAN_XIDFC; /**< (MCAN Offset: 0x88) Extended ID Filter Configuration Register */ 3866 __I uint8_t Reserved4[4]; 3867 __IO uint32_t MCAN_XIDAM; /**< (MCAN Offset: 0x90) Extended ID AND Mask Register */ 3868 __I uint32_t MCAN_HPMS; /**< (MCAN Offset: 0x94) High Priority Message Status Register */ 3869 __IO uint32_t MCAN_NDAT1; /**< (MCAN Offset: 0x98) New Data 1 Register */ 3870 __IO uint32_t MCAN_NDAT2; /**< (MCAN Offset: 0x9C) New Data 2 Register */ 3871 __IO uint32_t MCAN_RXF0C; /**< (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register */ 3872 __I uint32_t MCAN_RXF0S; /**< (MCAN Offset: 0xA4) Receive FIFO 0 Status Register */ 3873 __IO uint32_t MCAN_RXF0A; /**< (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ 3874 __IO uint32_t MCAN_RXBC; /**< (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register */ 3875 __IO uint32_t MCAN_RXF1C; /**< (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register */ 3876 __I uint32_t MCAN_RXF1S; /**< (MCAN Offset: 0xB4) Receive FIFO 1 Status Register */ 3877 __IO uint32_t MCAN_RXF1A; /**< (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ 3878 __IO uint32_t MCAN_RXESC; /**< (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ 3879 __IO uint32_t MCAN_TXBC; /**< (MCAN Offset: 0xC0) Transmit Buffer Configuration Register */ 3880 __I uint32_t MCAN_TXFQS; /**< (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register */ 3881 __IO uint32_t MCAN_TXESC; /**< (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ 3882 __I uint32_t MCAN_TXBRP; /**< (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register */ 3883 __IO uint32_t MCAN_TXBAR; /**< (MCAN Offset: 0xD0) Transmit Buffer Add Request Register */ 3884 __IO uint32_t MCAN_TXBCR; /**< (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register */ 3885 __I uint32_t MCAN_TXBTO; /**< (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ 3886 __I uint32_t MCAN_TXBCF; /**< (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ 3887 __IO uint32_t MCAN_TXBTIE; /**< (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ 3888 __IO uint32_t MCAN_TXBCIE; /**< (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ 3889 __I uint8_t Reserved5[8]; 3890 __IO uint32_t MCAN_TXEFC; /**< (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register */ 3891 __I uint32_t MCAN_TXEFS; /**< (MCAN Offset: 0xF4) Transmit Event FIFO Status Register */ 3892 __IO uint32_t MCAN_TXEFA; /**< (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ 3893 } Mcan; 3894 3895 #elif COMPONENT_TYPEDEF_STYLE == 'N' 3896 /** \brief MCAN_RXBE hardware registers */ 3897 typedef struct { /* Rx Buffer Element */ 3898 __IO MCAN_RXBE_0_Type MCAN_RXBE_0; /**< Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ 3899 __IO MCAN_RXBE_1_Type MCAN_RXBE_1; /**< Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ 3900 __IO MCAN_RXBE_DATA_Type MCAN_RXBE_DATA; /**< Offset: 0x08 (R/W 32) Rx Buffer Element Data */ 3901 } McanRxbe 3902 #ifdef __GNUC__ 3903 __attribute__ ((aligned (4))) 3904 #endif 3905 ; 3906 3907 /** \brief MCAN_RXF0E hardware registers */ 3908 typedef struct { /* Rx FIFO 0 Element */ 3909 __IO MCAN_RXF0E_0_Type MCAN_RXF0E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ 3910 __IO MCAN_RXF0E_1_Type MCAN_RXF0E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ 3911 __IO MCAN_RXF0E_DATA_Type MCAN_RXF0E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ 3912 } McanRxf0e 3913 #ifdef __GNUC__ 3914 __attribute__ ((aligned (4))) 3915 #endif 3916 ; 3917 3918 /** \brief MCAN_RXF1E hardware registers */ 3919 typedef struct { /* Rx FIFO 1 Element */ 3920 __IO MCAN_RXF1E_0_Type MCAN_RXF1E_0; /**< Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ 3921 __IO MCAN_RXF1E_1_Type MCAN_RXF1E_1; /**< Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ 3922 __IO MCAN_RXF1E_DATA_Type MCAN_RXF1E_DATA; /**< Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ 3923 } McanRxf1e 3924 #ifdef __GNUC__ 3925 __attribute__ ((aligned (4))) 3926 #endif 3927 ; 3928 3929 /** \brief MCAN_TXBE hardware registers */ 3930 typedef struct { /* Tx Buffer Element */ 3931 __IO MCAN_TXBE_0_Type MCAN_TXBE_0; /**< Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ 3932 __IO MCAN_TXBE_1_Type MCAN_TXBE_1; /**< Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ 3933 __IO MCAN_TXBE_DATA_Type MCAN_TXBE_DATA; /**< Offset: 0x08 (R/W 32) Tx Buffer Element Data */ 3934 } McanTxbe 3935 #ifdef __GNUC__ 3936 __attribute__ ((aligned (4))) 3937 #endif 3938 ; 3939 3940 /** \brief MCAN_TXEFE hardware registers */ 3941 typedef struct { /* Tx Event FIFO Element */ 3942 __IO MCAN_TXEFE_0_Type MCAN_TXEFE_0; /**< Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ 3943 __IO MCAN_TXEFE_1_Type MCAN_TXEFE_1; /**< Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ 3944 } McanTxefe 3945 #ifdef __GNUC__ 3946 __attribute__ ((aligned (4))) 3947 #endif 3948 ; 3949 3950 /** \brief MCAN_SIDFE hardware registers */ 3951 typedef struct { /* Standard Message ID Filter Element */ 3952 __IO MCAN_SIDFE_0_Type MCAN_SIDFE_0; /**< Offset: 0x00 (R/W 32) Standard Message ID Filter Element 0 */ 3953 } McanSidfe 3954 #ifdef __GNUC__ 3955 __attribute__ ((aligned (4))) 3956 #endif 3957 ; 3958 3959 /** \brief MCAN_XIDFE hardware registers */ 3960 typedef struct { /* Extended Message ID Filter Element */ 3961 __IO MCAN_XIDFE_0_Type MCAN_XIDFE_0; /**< Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ 3962 __IO MCAN_XIDFE_1_Type MCAN_XIDFE_1; /**< Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ 3963 } McanXidfe 3964 #ifdef __GNUC__ 3965 __attribute__ ((aligned (4))) 3966 #endif 3967 ; 3968 3969 /** \brief MCAN hardware registers */ 3970 typedef struct { 3971 __I MCAN_CREL_Type MCAN_CREL; /**< Offset: 0x00 (R/ 32) Core Release Register */ 3972 __I MCAN_ENDN_Type MCAN_ENDN; /**< Offset: 0x04 (R/ 32) Endian Register */ 3973 __IO MCAN_CUST_Type MCAN_CUST; /**< Offset: 0x08 (R/W 32) Customer Register */ 3974 __IO MCAN_DBTP_Type MCAN_DBTP; /**< Offset: 0x0C (R/W 32) Data Bit Timing and Prescaler Register */ 3975 __IO MCAN_TEST_Type MCAN_TEST; /**< Offset: 0x10 (R/W 32) Test Register */ 3976 __IO MCAN_RWD_Type MCAN_RWD; /**< Offset: 0x14 (R/W 32) RAM Watchdog Register */ 3977 __IO MCAN_CCCR_Type MCAN_CCCR; /**< Offset: 0x18 (R/W 32) CC Control Register */ 3978 __IO MCAN_NBTP_Type MCAN_NBTP; /**< Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler Register */ 3979 __IO MCAN_TSCC_Type MCAN_TSCC; /**< Offset: 0x20 (R/W 32) Timestamp Counter Configuration Register */ 3980 __IO MCAN_TSCV_Type MCAN_TSCV; /**< Offset: 0x24 (R/W 32) Timestamp Counter Value Register */ 3981 __IO MCAN_TOCC_Type MCAN_TOCC; /**< Offset: 0x28 (R/W 32) Timeout Counter Configuration Register */ 3982 __IO MCAN_TOCV_Type MCAN_TOCV; /**< Offset: 0x2C (R/W 32) Timeout Counter Value Register */ 3983 __I uint8_t Reserved1[16]; 3984 __I MCAN_ECR_Type MCAN_ECR; /**< Offset: 0x40 (R/ 32) Error Counter Register */ 3985 __I MCAN_PSR_Type MCAN_PSR; /**< Offset: 0x44 (R/ 32) Protocol Status Register */ 3986 __IO MCAN_TDCR_Type MCAN_TDCR; /**< Offset: 0x48 (R/W 32) Transmit Delay Compensation Register */ 3987 __I uint8_t Reserved2[4]; 3988 __IO MCAN_IR_Type MCAN_IR; /**< Offset: 0x50 (R/W 32) Interrupt Register */ 3989 __IO MCAN_IE_Type MCAN_IE; /**< Offset: 0x54 (R/W 32) Interrupt Enable Register */ 3990 __IO MCAN_ILS_Type MCAN_ILS; /**< Offset: 0x58 (R/W 32) Interrupt Line Select Register */ 3991 __IO MCAN_ILE_Type MCAN_ILE; /**< Offset: 0x5C (R/W 32) Interrupt Line Enable Register */ 3992 __I uint8_t Reserved3[32]; 3993 __IO MCAN_GFC_Type MCAN_GFC; /**< Offset: 0x80 (R/W 32) Global Filter Configuration Register */ 3994 __IO MCAN_SIDFC_Type MCAN_SIDFC; /**< Offset: 0x84 (R/W 32) Standard ID Filter Configuration Register */ 3995 __IO MCAN_XIDFC_Type MCAN_XIDFC; /**< Offset: 0x88 (R/W 32) Extended ID Filter Configuration Register */ 3996 __I uint8_t Reserved4[4]; 3997 __IO MCAN_XIDAM_Type MCAN_XIDAM; /**< Offset: 0x90 (R/W 32) Extended ID AND Mask Register */ 3998 __I MCAN_HPMS_Type MCAN_HPMS; /**< Offset: 0x94 (R/ 32) High Priority Message Status Register */ 3999 __IO MCAN_NDAT1_Type MCAN_NDAT1; /**< Offset: 0x98 (R/W 32) New Data 1 Register */ 4000 __IO MCAN_NDAT2_Type MCAN_NDAT2; /**< Offset: 0x9C (R/W 32) New Data 2 Register */ 4001 __IO MCAN_RXF0C_Type MCAN_RXF0C; /**< Offset: 0xA0 (R/W 32) Receive FIFO 0 Configuration Register */ 4002 __I MCAN_RXF0S_Type MCAN_RXF0S; /**< Offset: 0xA4 (R/ 32) Receive FIFO 0 Status Register */ 4003 __IO MCAN_RXF0A_Type MCAN_RXF0A; /**< Offset: 0xA8 (R/W 32) Receive FIFO 0 Acknowledge Register */ 4004 __IO MCAN_RXBC_Type MCAN_RXBC; /**< Offset: 0xAC (R/W 32) Receive Rx Buffer Configuration Register */ 4005 __IO MCAN_RXF1C_Type MCAN_RXF1C; /**< Offset: 0xB0 (R/W 32) Receive FIFO 1 Configuration Register */ 4006 __I MCAN_RXF1S_Type MCAN_RXF1S; /**< Offset: 0xB4 (R/ 32) Receive FIFO 1 Status Register */ 4007 __IO MCAN_RXF1A_Type MCAN_RXF1A; /**< Offset: 0xB8 (R/W 32) Receive FIFO 1 Acknowledge Register */ 4008 __IO MCAN_RXESC_Type MCAN_RXESC; /**< Offset: 0xBC (R/W 32) Receive Buffer / FIFO Element Size Configuration Register */ 4009 __IO MCAN_TXBC_Type MCAN_TXBC; /**< Offset: 0xC0 (R/W 32) Transmit Buffer Configuration Register */ 4010 __I MCAN_TXFQS_Type MCAN_TXFQS; /**< Offset: 0xC4 (R/ 32) Transmit FIFO/Queue Status Register */ 4011 __IO MCAN_TXESC_Type MCAN_TXESC; /**< Offset: 0xC8 (R/W 32) Transmit Buffer Element Size Configuration Register */ 4012 __I MCAN_TXBRP_Type MCAN_TXBRP; /**< Offset: 0xCC (R/ 32) Transmit Buffer Request Pending Register */ 4013 __IO MCAN_TXBAR_Type MCAN_TXBAR; /**< Offset: 0xD0 (R/W 32) Transmit Buffer Add Request Register */ 4014 __IO MCAN_TXBCR_Type MCAN_TXBCR; /**< Offset: 0xD4 (R/W 32) Transmit Buffer Cancellation Request Register */ 4015 __I MCAN_TXBTO_Type MCAN_TXBTO; /**< Offset: 0xD8 (R/ 32) Transmit Buffer Transmission Occurred Register */ 4016 __I MCAN_TXBCF_Type MCAN_TXBCF; /**< Offset: 0xDC (R/ 32) Transmit Buffer Cancellation Finished Register */ 4017 __IO MCAN_TXBTIE_Type MCAN_TXBTIE; /**< Offset: 0xE0 (R/W 32) Transmit Buffer Transmission Interrupt Enable Register */ 4018 __IO MCAN_TXBCIE_Type MCAN_TXBCIE; /**< Offset: 0xE4 (R/W 32) Transmit Buffer Cancellation Finished Interrupt Enable Register */ 4019 __I uint8_t Reserved5[8]; 4020 __IO MCAN_TXEFC_Type MCAN_TXEFC; /**< Offset: 0xF0 (R/W 32) Transmit Event FIFO Configuration Register */ 4021 __I MCAN_TXEFS_Type MCAN_TXEFS; /**< Offset: 0xF4 (R/ 32) Transmit Event FIFO Status Register */ 4022 __IO MCAN_TXEFA_Type MCAN_TXEFA; /**< Offset: 0xF8 (R/W 32) Transmit Event FIFO Acknowledge Register */ 4023 } Mcan; 4024 4025 #else /* COMPONENT_TYPEDEF_STYLE */ 4026 #error Unknown component typedef style 4027 #endif /* COMPONENT_TYPEDEF_STYLE */ 4028 4029 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 4030 /** @} end of Controller Area Network */ 4031 4032 #endif /* _SAMV71_MCAN_COMPONENT_H_ */ 4033
