1 /** 2 * \file 3 * 4 * \brief Component description for ICM 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:21:15Z */ 31 #ifndef _SAMV71_ICM_COMPONENT_H_ 32 #define _SAMV71_ICM_COMPONENT_H_ 33 #define _SAMV71_ICM_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Integrity Check Monitor 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR ICM */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define ICM_11105 /**< (ICM) Module ID */ 46 #define REV_ICM H /**< (ICM) Module revision */ 47 48 /* -------- ICM_CFG : (ICM Offset: 0x00) (R/W 32) Configuration Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t WBDIS:1; /**< bit: 0 Write Back Disable */ 54 uint32_t EOMDIS:1; /**< bit: 1 End of Monitoring Disable */ 55 uint32_t SLBDIS:1; /**< bit: 2 Secondary List Branching Disable */ 56 uint32_t :1; /**< bit: 3 Reserved */ 57 uint32_t BBC:4; /**< bit: 4..7 Bus Burden Control */ 58 uint32_t ASCD:1; /**< bit: 8 Automatic Switch To Compare Digest */ 59 uint32_t DUALBUFF:1; /**< bit: 9 Dual Input Buffer */ 60 uint32_t :2; /**< bit: 10..11 Reserved */ 61 uint32_t UIHASH:1; /**< bit: 12 User Initial Hash Value */ 62 uint32_t UALGO:3; /**< bit: 13..15 User SHA Algorithm */ 63 uint32_t :16; /**< bit: 16..31 Reserved */ 64 } bit; /**< Structure used for bit access */ 65 uint32_t reg; /**< Type used for register access */ 66 } ICM_CFG_Type; 67 #endif 68 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 #define ICM_CFG_OFFSET (0x00) /**< (ICM_CFG) Configuration Register Offset */ 71 72 #define ICM_CFG_WBDIS_Pos 0 /**< (ICM_CFG) Write Back Disable Position */ 73 #define ICM_CFG_WBDIS_Msk (_U_(0x1) << ICM_CFG_WBDIS_Pos) /**< (ICM_CFG) Write Back Disable Mask */ 74 #define ICM_CFG_WBDIS ICM_CFG_WBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_WBDIS_Msk instead */ 75 #define ICM_CFG_EOMDIS_Pos 1 /**< (ICM_CFG) End of Monitoring Disable Position */ 76 #define ICM_CFG_EOMDIS_Msk (_U_(0x1) << ICM_CFG_EOMDIS_Pos) /**< (ICM_CFG) End of Monitoring Disable Mask */ 77 #define ICM_CFG_EOMDIS ICM_CFG_EOMDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_EOMDIS_Msk instead */ 78 #define ICM_CFG_SLBDIS_Pos 2 /**< (ICM_CFG) Secondary List Branching Disable Position */ 79 #define ICM_CFG_SLBDIS_Msk (_U_(0x1) << ICM_CFG_SLBDIS_Pos) /**< (ICM_CFG) Secondary List Branching Disable Mask */ 80 #define ICM_CFG_SLBDIS ICM_CFG_SLBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_SLBDIS_Msk instead */ 81 #define ICM_CFG_BBC_Pos 4 /**< (ICM_CFG) Bus Burden Control Position */ 82 #define ICM_CFG_BBC_Msk (_U_(0xF) << ICM_CFG_BBC_Pos) /**< (ICM_CFG) Bus Burden Control Mask */ 83 #define ICM_CFG_BBC(value) (ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos)) 84 #define ICM_CFG_ASCD_Pos 8 /**< (ICM_CFG) Automatic Switch To Compare Digest Position */ 85 #define ICM_CFG_ASCD_Msk (_U_(0x1) << ICM_CFG_ASCD_Pos) /**< (ICM_CFG) Automatic Switch To Compare Digest Mask */ 86 #define ICM_CFG_ASCD ICM_CFG_ASCD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_ASCD_Msk instead */ 87 #define ICM_CFG_DUALBUFF_Pos 9 /**< (ICM_CFG) Dual Input Buffer Position */ 88 #define ICM_CFG_DUALBUFF_Msk (_U_(0x1) << ICM_CFG_DUALBUFF_Pos) /**< (ICM_CFG) Dual Input Buffer Mask */ 89 #define ICM_CFG_DUALBUFF ICM_CFG_DUALBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_DUALBUFF_Msk instead */ 90 #define ICM_CFG_UIHASH_Pos 12 /**< (ICM_CFG) User Initial Hash Value Position */ 91 #define ICM_CFG_UIHASH_Msk (_U_(0x1) << ICM_CFG_UIHASH_Pos) /**< (ICM_CFG) User Initial Hash Value Mask */ 92 #define ICM_CFG_UIHASH ICM_CFG_UIHASH_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CFG_UIHASH_Msk instead */ 93 #define ICM_CFG_UALGO_Pos 13 /**< (ICM_CFG) User SHA Algorithm Position */ 94 #define ICM_CFG_UALGO_Msk (_U_(0x7) << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) User SHA Algorithm Mask */ 95 #define ICM_CFG_UALGO(value) (ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos)) 96 #define ICM_CFG_UALGO_SHA1_Val _U_(0x0) /**< (ICM_CFG) SHA1 algorithm processed */ 97 #define ICM_CFG_UALGO_SHA256_Val _U_(0x1) /**< (ICM_CFG) SHA256 algorithm processed */ 98 #define ICM_CFG_UALGO_SHA224_Val _U_(0x4) /**< (ICM_CFG) SHA224 algorithm processed */ 99 #define ICM_CFG_UALGO_SHA1 (ICM_CFG_UALGO_SHA1_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA1 algorithm processed Position */ 100 #define ICM_CFG_UALGO_SHA256 (ICM_CFG_UALGO_SHA256_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA256 algorithm processed Position */ 101 #define ICM_CFG_UALGO_SHA224 (ICM_CFG_UALGO_SHA224_Val << ICM_CFG_UALGO_Pos) /**< (ICM_CFG) SHA224 algorithm processed Position */ 102 #define ICM_CFG_MASK _U_(0xF3F7) /**< \deprecated (ICM_CFG) Register MASK (Use ICM_CFG_Msk instead) */ 103 #define ICM_CFG_Msk _U_(0xF3F7) /**< (ICM_CFG) Register Mask */ 104 105 106 /* -------- ICM_CTRL : (ICM Offset: 0x04) (/W 32) Control Register -------- */ 107 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 108 #if COMPONENT_TYPEDEF_STYLE == 'N' 109 typedef union { 110 struct { 111 uint32_t ENABLE:1; /**< bit: 0 ICM Enable */ 112 uint32_t DISABLE:1; /**< bit: 1 ICM Disable Register */ 113 uint32_t SWRST:1; /**< bit: 2 Software Reset */ 114 uint32_t :1; /**< bit: 3 Reserved */ 115 uint32_t REHASH:4; /**< bit: 4..7 Recompute Internal Hash */ 116 uint32_t RMDIS:4; /**< bit: 8..11 Region Monitoring Disable */ 117 uint32_t RMEN:4; /**< bit: 12..15 Region Monitoring Enable */ 118 uint32_t :16; /**< bit: 16..31 Reserved */ 119 } bit; /**< Structure used for bit access */ 120 uint32_t reg; /**< Type used for register access */ 121 } ICM_CTRL_Type; 122 #endif 123 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 124 125 #define ICM_CTRL_OFFSET (0x04) /**< (ICM_CTRL) Control Register Offset */ 126 127 #define ICM_CTRL_ENABLE_Pos 0 /**< (ICM_CTRL) ICM Enable Position */ 128 #define ICM_CTRL_ENABLE_Msk (_U_(0x1) << ICM_CTRL_ENABLE_Pos) /**< (ICM_CTRL) ICM Enable Mask */ 129 #define ICM_CTRL_ENABLE ICM_CTRL_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CTRL_ENABLE_Msk instead */ 130 #define ICM_CTRL_DISABLE_Pos 1 /**< (ICM_CTRL) ICM Disable Register Position */ 131 #define ICM_CTRL_DISABLE_Msk (_U_(0x1) << ICM_CTRL_DISABLE_Pos) /**< (ICM_CTRL) ICM Disable Register Mask */ 132 #define ICM_CTRL_DISABLE ICM_CTRL_DISABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CTRL_DISABLE_Msk instead */ 133 #define ICM_CTRL_SWRST_Pos 2 /**< (ICM_CTRL) Software Reset Position */ 134 #define ICM_CTRL_SWRST_Msk (_U_(0x1) << ICM_CTRL_SWRST_Pos) /**< (ICM_CTRL) Software Reset Mask */ 135 #define ICM_CTRL_SWRST ICM_CTRL_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_CTRL_SWRST_Msk instead */ 136 #define ICM_CTRL_REHASH_Pos 4 /**< (ICM_CTRL) Recompute Internal Hash Position */ 137 #define ICM_CTRL_REHASH_Msk (_U_(0xF) << ICM_CTRL_REHASH_Pos) /**< (ICM_CTRL) Recompute Internal Hash Mask */ 138 #define ICM_CTRL_REHASH(value) (ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos)) 139 #define ICM_CTRL_RMDIS_Pos 8 /**< (ICM_CTRL) Region Monitoring Disable Position */ 140 #define ICM_CTRL_RMDIS_Msk (_U_(0xF) << ICM_CTRL_RMDIS_Pos) /**< (ICM_CTRL) Region Monitoring Disable Mask */ 141 #define ICM_CTRL_RMDIS(value) (ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos)) 142 #define ICM_CTRL_RMEN_Pos 12 /**< (ICM_CTRL) Region Monitoring Enable Position */ 143 #define ICM_CTRL_RMEN_Msk (_U_(0xF) << ICM_CTRL_RMEN_Pos) /**< (ICM_CTRL) Region Monitoring Enable Mask */ 144 #define ICM_CTRL_RMEN(value) (ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos)) 145 #define ICM_CTRL_MASK _U_(0xFFF7) /**< \deprecated (ICM_CTRL) Register MASK (Use ICM_CTRL_Msk instead) */ 146 #define ICM_CTRL_Msk _U_(0xFFF7) /**< (ICM_CTRL) Register Mask */ 147 148 149 /* -------- ICM_SR : (ICM Offset: 0x08) (R/ 32) Status Register -------- */ 150 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 151 #if COMPONENT_TYPEDEF_STYLE == 'N' 152 typedef union { 153 struct { 154 uint32_t ENABLE:1; /**< bit: 0 ICM Controller Enable Register */ 155 uint32_t :7; /**< bit: 1..7 Reserved */ 156 uint32_t RAWRMDIS:4; /**< bit: 8..11 Region Monitoring Disabled Raw Status */ 157 uint32_t RMDIS:4; /**< bit: 12..15 Region Monitoring Disabled Status */ 158 uint32_t :16; /**< bit: 16..31 Reserved */ 159 } bit; /**< Structure used for bit access */ 160 uint32_t reg; /**< Type used for register access */ 161 } ICM_SR_Type; 162 #endif 163 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 164 165 #define ICM_SR_OFFSET (0x08) /**< (ICM_SR) Status Register Offset */ 166 167 #define ICM_SR_ENABLE_Pos 0 /**< (ICM_SR) ICM Controller Enable Register Position */ 168 #define ICM_SR_ENABLE_Msk (_U_(0x1) << ICM_SR_ENABLE_Pos) /**< (ICM_SR) ICM Controller Enable Register Mask */ 169 #define ICM_SR_ENABLE ICM_SR_ENABLE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_SR_ENABLE_Msk instead */ 170 #define ICM_SR_RAWRMDIS_Pos 8 /**< (ICM_SR) Region Monitoring Disabled Raw Status Position */ 171 #define ICM_SR_RAWRMDIS_Msk (_U_(0xF) << ICM_SR_RAWRMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Raw Status Mask */ 172 #define ICM_SR_RAWRMDIS(value) (ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos)) 173 #define ICM_SR_RMDIS_Pos 12 /**< (ICM_SR) Region Monitoring Disabled Status Position */ 174 #define ICM_SR_RMDIS_Msk (_U_(0xF) << ICM_SR_RMDIS_Pos) /**< (ICM_SR) Region Monitoring Disabled Status Mask */ 175 #define ICM_SR_RMDIS(value) (ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos)) 176 #define ICM_SR_MASK _U_(0xFF01) /**< \deprecated (ICM_SR) Register MASK (Use ICM_SR_Msk instead) */ 177 #define ICM_SR_Msk _U_(0xFF01) /**< (ICM_SR) Register Mask */ 178 179 180 /* -------- ICM_IER : (ICM Offset: 0x10) (/W 32) Interrupt Enable Register -------- */ 181 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 182 #if COMPONENT_TYPEDEF_STYLE == 'N' 183 typedef union { 184 struct { 185 uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed Interrupt Enable */ 186 uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch Interrupt Enable */ 187 uint32_t RBE:4; /**< bit: 8..11 Region Bus Error Interrupt Enable */ 188 uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition detected Interrupt Enable */ 189 uint32_t REC:4; /**< bit: 16..19 Region End bit Condition Detected Interrupt Enable */ 190 uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Interrupt Disable */ 191 uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Interrupt Enable */ 192 uint32_t :7; /**< bit: 25..31 Reserved */ 193 } bit; /**< Structure used for bit access */ 194 uint32_t reg; /**< Type used for register access */ 195 } ICM_IER_Type; 196 #endif 197 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 198 199 #define ICM_IER_OFFSET (0x10) /**< (ICM_IER) Interrupt Enable Register Offset */ 200 201 #define ICM_IER_RHC_Pos 0 /**< (ICM_IER) Region Hash Completed Interrupt Enable Position */ 202 #define ICM_IER_RHC_Msk (_U_(0xF) << ICM_IER_RHC_Pos) /**< (ICM_IER) Region Hash Completed Interrupt Enable Mask */ 203 #define ICM_IER_RHC(value) (ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos)) 204 #define ICM_IER_RDM_Pos 4 /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Position */ 205 #define ICM_IER_RDM_Msk (_U_(0xF) << ICM_IER_RDM_Pos) /**< (ICM_IER) Region Digest Mismatch Interrupt Enable Mask */ 206 #define ICM_IER_RDM(value) (ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos)) 207 #define ICM_IER_RBE_Pos 8 /**< (ICM_IER) Region Bus Error Interrupt Enable Position */ 208 #define ICM_IER_RBE_Msk (_U_(0xF) << ICM_IER_RBE_Pos) /**< (ICM_IER) Region Bus Error Interrupt Enable Mask */ 209 #define ICM_IER_RBE(value) (ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos)) 210 #define ICM_IER_RWC_Pos 12 /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Position */ 211 #define ICM_IER_RWC_Msk (_U_(0xF) << ICM_IER_RWC_Pos) /**< (ICM_IER) Region Wrap Condition detected Interrupt Enable Mask */ 212 #define ICM_IER_RWC(value) (ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos)) 213 #define ICM_IER_REC_Pos 16 /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Position */ 214 #define ICM_IER_REC_Msk (_U_(0xF) << ICM_IER_REC_Pos) /**< (ICM_IER) Region End bit Condition Detected Interrupt Enable Mask */ 215 #define ICM_IER_REC(value) (ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos)) 216 #define ICM_IER_RSU_Pos 20 /**< (ICM_IER) Region Status Updated Interrupt Disable Position */ 217 #define ICM_IER_RSU_Msk (_U_(0xF) << ICM_IER_RSU_Pos) /**< (ICM_IER) Region Status Updated Interrupt Disable Mask */ 218 #define ICM_IER_RSU(value) (ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos)) 219 #define ICM_IER_URAD_Pos 24 /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Position */ 220 #define ICM_IER_URAD_Msk (_U_(0x1) << ICM_IER_URAD_Pos) /**< (ICM_IER) Undefined Register Access Detection Interrupt Enable Mask */ 221 #define ICM_IER_URAD ICM_IER_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_IER_URAD_Msk instead */ 222 #define ICM_IER_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_IER) Register MASK (Use ICM_IER_Msk instead) */ 223 #define ICM_IER_Msk _U_(0x1FFFFFF) /**< (ICM_IER) Register Mask */ 224 225 226 /* -------- ICM_IDR : (ICM Offset: 0x14) (/W 32) Interrupt Disable Register -------- */ 227 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 228 #if COMPONENT_TYPEDEF_STYLE == 'N' 229 typedef union { 230 struct { 231 uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed Interrupt Disable */ 232 uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch Interrupt Disable */ 233 uint32_t RBE:4; /**< bit: 8..11 Region Bus Error Interrupt Disable */ 234 uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition Detected Interrupt Disable */ 235 uint32_t REC:4; /**< bit: 16..19 Region End bit Condition detected Interrupt Disable */ 236 uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Interrupt Disable */ 237 uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Interrupt Disable */ 238 uint32_t :7; /**< bit: 25..31 Reserved */ 239 } bit; /**< Structure used for bit access */ 240 uint32_t reg; /**< Type used for register access */ 241 } ICM_IDR_Type; 242 #endif 243 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 244 245 #define ICM_IDR_OFFSET (0x14) /**< (ICM_IDR) Interrupt Disable Register Offset */ 246 247 #define ICM_IDR_RHC_Pos 0 /**< (ICM_IDR) Region Hash Completed Interrupt Disable Position */ 248 #define ICM_IDR_RHC_Msk (_U_(0xF) << ICM_IDR_RHC_Pos) /**< (ICM_IDR) Region Hash Completed Interrupt Disable Mask */ 249 #define ICM_IDR_RHC(value) (ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos)) 250 #define ICM_IDR_RDM_Pos 4 /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Position */ 251 #define ICM_IDR_RDM_Msk (_U_(0xF) << ICM_IDR_RDM_Pos) /**< (ICM_IDR) Region Digest Mismatch Interrupt Disable Mask */ 252 #define ICM_IDR_RDM(value) (ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos)) 253 #define ICM_IDR_RBE_Pos 8 /**< (ICM_IDR) Region Bus Error Interrupt Disable Position */ 254 #define ICM_IDR_RBE_Msk (_U_(0xF) << ICM_IDR_RBE_Pos) /**< (ICM_IDR) Region Bus Error Interrupt Disable Mask */ 255 #define ICM_IDR_RBE(value) (ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos)) 256 #define ICM_IDR_RWC_Pos 12 /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Position */ 257 #define ICM_IDR_RWC_Msk (_U_(0xF) << ICM_IDR_RWC_Pos) /**< (ICM_IDR) Region Wrap Condition Detected Interrupt Disable Mask */ 258 #define ICM_IDR_RWC(value) (ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos)) 259 #define ICM_IDR_REC_Pos 16 /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Position */ 260 #define ICM_IDR_REC_Msk (_U_(0xF) << ICM_IDR_REC_Pos) /**< (ICM_IDR) Region End bit Condition detected Interrupt Disable Mask */ 261 #define ICM_IDR_REC(value) (ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos)) 262 #define ICM_IDR_RSU_Pos 20 /**< (ICM_IDR) Region Status Updated Interrupt Disable Position */ 263 #define ICM_IDR_RSU_Msk (_U_(0xF) << ICM_IDR_RSU_Pos) /**< (ICM_IDR) Region Status Updated Interrupt Disable Mask */ 264 #define ICM_IDR_RSU(value) (ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos)) 265 #define ICM_IDR_URAD_Pos 24 /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Position */ 266 #define ICM_IDR_URAD_Msk (_U_(0x1) << ICM_IDR_URAD_Pos) /**< (ICM_IDR) Undefined Register Access Detection Interrupt Disable Mask */ 267 #define ICM_IDR_URAD ICM_IDR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_IDR_URAD_Msk instead */ 268 #define ICM_IDR_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_IDR) Register MASK (Use ICM_IDR_Msk instead) */ 269 #define ICM_IDR_Msk _U_(0x1FFFFFF) /**< (ICM_IDR) Register Mask */ 270 271 272 /* -------- ICM_IMR : (ICM Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ 273 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 274 #if COMPONENT_TYPEDEF_STYLE == 'N' 275 typedef union { 276 struct { 277 uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed Interrupt Mask */ 278 uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch Interrupt Mask */ 279 uint32_t RBE:4; /**< bit: 8..11 Region Bus Error Interrupt Mask */ 280 uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition Detected Interrupt Mask */ 281 uint32_t REC:4; /**< bit: 16..19 Region End bit Condition Detected Interrupt Mask */ 282 uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Interrupt Mask */ 283 uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Interrupt Mask */ 284 uint32_t :7; /**< bit: 25..31 Reserved */ 285 } bit; /**< Structure used for bit access */ 286 uint32_t reg; /**< Type used for register access */ 287 } ICM_IMR_Type; 288 #endif 289 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 290 291 #define ICM_IMR_OFFSET (0x18) /**< (ICM_IMR) Interrupt Mask Register Offset */ 292 293 #define ICM_IMR_RHC_Pos 0 /**< (ICM_IMR) Region Hash Completed Interrupt Mask Position */ 294 #define ICM_IMR_RHC_Msk (_U_(0xF) << ICM_IMR_RHC_Pos) /**< (ICM_IMR) Region Hash Completed Interrupt Mask Mask */ 295 #define ICM_IMR_RHC(value) (ICM_IMR_RHC_Msk & ((value) << ICM_IMR_RHC_Pos)) 296 #define ICM_IMR_RDM_Pos 4 /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Position */ 297 #define ICM_IMR_RDM_Msk (_U_(0xF) << ICM_IMR_RDM_Pos) /**< (ICM_IMR) Region Digest Mismatch Interrupt Mask Mask */ 298 #define ICM_IMR_RDM(value) (ICM_IMR_RDM_Msk & ((value) << ICM_IMR_RDM_Pos)) 299 #define ICM_IMR_RBE_Pos 8 /**< (ICM_IMR) Region Bus Error Interrupt Mask Position */ 300 #define ICM_IMR_RBE_Msk (_U_(0xF) << ICM_IMR_RBE_Pos) /**< (ICM_IMR) Region Bus Error Interrupt Mask Mask */ 301 #define ICM_IMR_RBE(value) (ICM_IMR_RBE_Msk & ((value) << ICM_IMR_RBE_Pos)) 302 #define ICM_IMR_RWC_Pos 12 /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Position */ 303 #define ICM_IMR_RWC_Msk (_U_(0xF) << ICM_IMR_RWC_Pos) /**< (ICM_IMR) Region Wrap Condition Detected Interrupt Mask Mask */ 304 #define ICM_IMR_RWC(value) (ICM_IMR_RWC_Msk & ((value) << ICM_IMR_RWC_Pos)) 305 #define ICM_IMR_REC_Pos 16 /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Position */ 306 #define ICM_IMR_REC_Msk (_U_(0xF) << ICM_IMR_REC_Pos) /**< (ICM_IMR) Region End bit Condition Detected Interrupt Mask Mask */ 307 #define ICM_IMR_REC(value) (ICM_IMR_REC_Msk & ((value) << ICM_IMR_REC_Pos)) 308 #define ICM_IMR_RSU_Pos 20 /**< (ICM_IMR) Region Status Updated Interrupt Mask Position */ 309 #define ICM_IMR_RSU_Msk (_U_(0xF) << ICM_IMR_RSU_Pos) /**< (ICM_IMR) Region Status Updated Interrupt Mask Mask */ 310 #define ICM_IMR_RSU(value) (ICM_IMR_RSU_Msk & ((value) << ICM_IMR_RSU_Pos)) 311 #define ICM_IMR_URAD_Pos 24 /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Position */ 312 #define ICM_IMR_URAD_Msk (_U_(0x1) << ICM_IMR_URAD_Pos) /**< (ICM_IMR) Undefined Register Access Detection Interrupt Mask Mask */ 313 #define ICM_IMR_URAD ICM_IMR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_IMR_URAD_Msk instead */ 314 #define ICM_IMR_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_IMR) Register MASK (Use ICM_IMR_Msk instead) */ 315 #define ICM_IMR_Msk _U_(0x1FFFFFF) /**< (ICM_IMR) Register Mask */ 316 317 318 /* -------- ICM_ISR : (ICM Offset: 0x1c) (R/ 32) Interrupt Status Register -------- */ 319 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 320 #if COMPONENT_TYPEDEF_STYLE == 'N' 321 typedef union { 322 struct { 323 uint32_t RHC:4; /**< bit: 0..3 Region Hash Completed */ 324 uint32_t RDM:4; /**< bit: 4..7 Region Digest Mismatch */ 325 uint32_t RBE:4; /**< bit: 8..11 Region Bus Error */ 326 uint32_t RWC:4; /**< bit: 12..15 Region Wrap Condition Detected */ 327 uint32_t REC:4; /**< bit: 16..19 Region End bit Condition Detected */ 328 uint32_t RSU:4; /**< bit: 20..23 Region Status Updated Detected */ 329 uint32_t URAD:1; /**< bit: 24 Undefined Register Access Detection Status */ 330 uint32_t :7; /**< bit: 25..31 Reserved */ 331 } bit; /**< Structure used for bit access */ 332 uint32_t reg; /**< Type used for register access */ 333 } ICM_ISR_Type; 334 #endif 335 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 336 337 #define ICM_ISR_OFFSET (0x1C) /**< (ICM_ISR) Interrupt Status Register Offset */ 338 339 #define ICM_ISR_RHC_Pos 0 /**< (ICM_ISR) Region Hash Completed Position */ 340 #define ICM_ISR_RHC_Msk (_U_(0xF) << ICM_ISR_RHC_Pos) /**< (ICM_ISR) Region Hash Completed Mask */ 341 #define ICM_ISR_RHC(value) (ICM_ISR_RHC_Msk & ((value) << ICM_ISR_RHC_Pos)) 342 #define ICM_ISR_RDM_Pos 4 /**< (ICM_ISR) Region Digest Mismatch Position */ 343 #define ICM_ISR_RDM_Msk (_U_(0xF) << ICM_ISR_RDM_Pos) /**< (ICM_ISR) Region Digest Mismatch Mask */ 344 #define ICM_ISR_RDM(value) (ICM_ISR_RDM_Msk & ((value) << ICM_ISR_RDM_Pos)) 345 #define ICM_ISR_RBE_Pos 8 /**< (ICM_ISR) Region Bus Error Position */ 346 #define ICM_ISR_RBE_Msk (_U_(0xF) << ICM_ISR_RBE_Pos) /**< (ICM_ISR) Region Bus Error Mask */ 347 #define ICM_ISR_RBE(value) (ICM_ISR_RBE_Msk & ((value) << ICM_ISR_RBE_Pos)) 348 #define ICM_ISR_RWC_Pos 12 /**< (ICM_ISR) Region Wrap Condition Detected Position */ 349 #define ICM_ISR_RWC_Msk (_U_(0xF) << ICM_ISR_RWC_Pos) /**< (ICM_ISR) Region Wrap Condition Detected Mask */ 350 #define ICM_ISR_RWC(value) (ICM_ISR_RWC_Msk & ((value) << ICM_ISR_RWC_Pos)) 351 #define ICM_ISR_REC_Pos 16 /**< (ICM_ISR) Region End bit Condition Detected Position */ 352 #define ICM_ISR_REC_Msk (_U_(0xF) << ICM_ISR_REC_Pos) /**< (ICM_ISR) Region End bit Condition Detected Mask */ 353 #define ICM_ISR_REC(value) (ICM_ISR_REC_Msk & ((value) << ICM_ISR_REC_Pos)) 354 #define ICM_ISR_RSU_Pos 20 /**< (ICM_ISR) Region Status Updated Detected Position */ 355 #define ICM_ISR_RSU_Msk (_U_(0xF) << ICM_ISR_RSU_Pos) /**< (ICM_ISR) Region Status Updated Detected Mask */ 356 #define ICM_ISR_RSU(value) (ICM_ISR_RSU_Msk & ((value) << ICM_ISR_RSU_Pos)) 357 #define ICM_ISR_URAD_Pos 24 /**< (ICM_ISR) Undefined Register Access Detection Status Position */ 358 #define ICM_ISR_URAD_Msk (_U_(0x1) << ICM_ISR_URAD_Pos) /**< (ICM_ISR) Undefined Register Access Detection Status Mask */ 359 #define ICM_ISR_URAD ICM_ISR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use ICM_ISR_URAD_Msk instead */ 360 #define ICM_ISR_MASK _U_(0x1FFFFFF) /**< \deprecated (ICM_ISR) Register MASK (Use ICM_ISR_Msk instead) */ 361 #define ICM_ISR_Msk _U_(0x1FFFFFF) /**< (ICM_ISR) Register Mask */ 362 363 364 /* -------- ICM_UASR : (ICM Offset: 0x20) (R/ 32) Undefined Access Status Register -------- */ 365 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 366 #if COMPONENT_TYPEDEF_STYLE == 'N' 367 typedef union { 368 struct { 369 uint32_t URAT:3; /**< bit: 0..2 Undefined Register Access Trace */ 370 uint32_t :29; /**< bit: 3..31 Reserved */ 371 } bit; /**< Structure used for bit access */ 372 uint32_t reg; /**< Type used for register access */ 373 } ICM_UASR_Type; 374 #endif 375 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 376 377 #define ICM_UASR_OFFSET (0x20) /**< (ICM_UASR) Undefined Access Status Register Offset */ 378 379 #define ICM_UASR_URAT_Pos 0 /**< (ICM_UASR) Undefined Register Access Trace Position */ 380 #define ICM_UASR_URAT_Msk (_U_(0x7) << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Undefined Register Access Trace Mask */ 381 #define ICM_UASR_URAT(value) (ICM_UASR_URAT_Msk & ((value) << ICM_UASR_URAT_Pos)) 382 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val _U_(0x0) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ 383 #define ICM_UASR_URAT_ICM_CFG_MODIFIED_Val _U_(0x1) /**< (ICM_UASR) ICM_CFG modified during active monitoring. */ 384 #define ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val _U_(0x2) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. */ 385 #define ICM_UASR_URAT_ICM_HASH_MODIFIED_Val _U_(0x3) /**< (ICM_UASR) ICM_HASH modified during active monitoring */ 386 #define ICM_UASR_URAT_READ_ACCESS_Val _U_(0x4) /**< (ICM_UASR) Write-only register read access */ 387 #define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. Position */ 388 #define ICM_UASR_URAT_ICM_CFG_MODIFIED (ICM_UASR_URAT_ICM_CFG_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_CFG modified during active monitoring. Position */ 389 #define ICM_UASR_URAT_ICM_DSCR_MODIFIED (ICM_UASR_URAT_ICM_DSCR_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_DSCR modified during active monitoring. Position */ 390 #define ICM_UASR_URAT_ICM_HASH_MODIFIED (ICM_UASR_URAT_ICM_HASH_MODIFIED_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) ICM_HASH modified during active monitoring Position */ 391 #define ICM_UASR_URAT_READ_ACCESS (ICM_UASR_URAT_READ_ACCESS_Val << ICM_UASR_URAT_Pos) /**< (ICM_UASR) Write-only register read access Position */ 392 #define ICM_UASR_MASK _U_(0x07) /**< \deprecated (ICM_UASR) Register MASK (Use ICM_UASR_Msk instead) */ 393 #define ICM_UASR_Msk _U_(0x07) /**< (ICM_UASR) Register Mask */ 394 395 396 /* -------- ICM_DSCR : (ICM Offset: 0x30) (R/W 32) Region Descriptor Area Start Address Register -------- */ 397 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 398 #if COMPONENT_TYPEDEF_STYLE == 'N' 399 typedef union { 400 struct { 401 uint32_t :6; /**< bit: 0..5 Reserved */ 402 uint32_t DASA:26; /**< bit: 6..31 Descriptor Area Start Address */ 403 } bit; /**< Structure used for bit access */ 404 uint32_t reg; /**< Type used for register access */ 405 } ICM_DSCR_Type; 406 #endif 407 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 408 409 #define ICM_DSCR_OFFSET (0x30) /**< (ICM_DSCR) Region Descriptor Area Start Address Register Offset */ 410 411 #define ICM_DSCR_DASA_Pos 6 /**< (ICM_DSCR) Descriptor Area Start Address Position */ 412 #define ICM_DSCR_DASA_Msk (_U_(0x3FFFFFF) << ICM_DSCR_DASA_Pos) /**< (ICM_DSCR) Descriptor Area Start Address Mask */ 413 #define ICM_DSCR_DASA(value) (ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos)) 414 #define ICM_DSCR_MASK _U_(0xFFFFFFC0) /**< \deprecated (ICM_DSCR) Register MASK (Use ICM_DSCR_Msk instead) */ 415 #define ICM_DSCR_Msk _U_(0xFFFFFFC0) /**< (ICM_DSCR) Register Mask */ 416 417 418 /* -------- ICM_HASH : (ICM Offset: 0x34) (R/W 32) Region Hash Area Start Address Register -------- */ 419 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 420 #if COMPONENT_TYPEDEF_STYLE == 'N' 421 typedef union { 422 struct { 423 uint32_t :7; /**< bit: 0..6 Reserved */ 424 uint32_t HASA:25; /**< bit: 7..31 Hash Area Start Address */ 425 } bit; /**< Structure used for bit access */ 426 uint32_t reg; /**< Type used for register access */ 427 } ICM_HASH_Type; 428 #endif 429 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 430 431 #define ICM_HASH_OFFSET (0x34) /**< (ICM_HASH) Region Hash Area Start Address Register Offset */ 432 433 #define ICM_HASH_HASA_Pos 7 /**< (ICM_HASH) Hash Area Start Address Position */ 434 #define ICM_HASH_HASA_Msk (_U_(0x1FFFFFF) << ICM_HASH_HASA_Pos) /**< (ICM_HASH) Hash Area Start Address Mask */ 435 #define ICM_HASH_HASA(value) (ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos)) 436 #define ICM_HASH_MASK _U_(0xFFFFFF80) /**< \deprecated (ICM_HASH) Register MASK (Use ICM_HASH_Msk instead) */ 437 #define ICM_HASH_Msk _U_(0xFFFFFF80) /**< (ICM_HASH) Register Mask */ 438 439 440 /* -------- ICM_UIHVAL : (ICM Offset: 0x38) (/W 32) User Initial Hash Value 0 Register 0 -------- */ 441 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 442 #if COMPONENT_TYPEDEF_STYLE == 'N' 443 typedef union { 444 struct { 445 uint32_t VAL:32; /**< bit: 0..31 Initial Hash Value */ 446 } bit; /**< Structure used for bit access */ 447 uint32_t reg; /**< Type used for register access */ 448 } ICM_UIHVAL_Type; 449 #endif 450 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 451 452 #define ICM_UIHVAL_OFFSET (0x38) /**< (ICM_UIHVAL) User Initial Hash Value 0 Register 0 Offset */ 453 454 #define ICM_UIHVAL_VAL_Pos 0 /**< (ICM_UIHVAL) Initial Hash Value Position */ 455 #define ICM_UIHVAL_VAL_Msk (_U_(0xFFFFFFFF) << ICM_UIHVAL_VAL_Pos) /**< (ICM_UIHVAL) Initial Hash Value Mask */ 456 #define ICM_UIHVAL_VAL(value) (ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos)) 457 #define ICM_UIHVAL_MASK _U_(0xFFFFFFFF) /**< \deprecated (ICM_UIHVAL) Register MASK (Use ICM_UIHVAL_Msk instead) */ 458 #define ICM_UIHVAL_Msk _U_(0xFFFFFFFF) /**< (ICM_UIHVAL) Register Mask */ 459 460 461 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 462 #if COMPONENT_TYPEDEF_STYLE == 'R' 463 /** \brief ICM hardware registers */ 464 typedef struct { 465 __IO uint32_t ICM_CFG; /**< (ICM Offset: 0x00) Configuration Register */ 466 __O uint32_t ICM_CTRL; /**< (ICM Offset: 0x04) Control Register */ 467 __I uint32_t ICM_SR; /**< (ICM Offset: 0x08) Status Register */ 468 __I uint8_t Reserved1[4]; 469 __O uint32_t ICM_IER; /**< (ICM Offset: 0x10) Interrupt Enable Register */ 470 __O uint32_t ICM_IDR; /**< (ICM Offset: 0x14) Interrupt Disable Register */ 471 __I uint32_t ICM_IMR; /**< (ICM Offset: 0x18) Interrupt Mask Register */ 472 __I uint32_t ICM_ISR; /**< (ICM Offset: 0x1C) Interrupt Status Register */ 473 __I uint32_t ICM_UASR; /**< (ICM Offset: 0x20) Undefined Access Status Register */ 474 __I uint8_t Reserved2[12]; 475 __IO uint32_t ICM_DSCR; /**< (ICM Offset: 0x30) Region Descriptor Area Start Address Register */ 476 __IO uint32_t ICM_HASH; /**< (ICM Offset: 0x34) Region Hash Area Start Address Register */ 477 __O uint32_t ICM_UIHVAL[8]; /**< (ICM Offset: 0x38) User Initial Hash Value 0 Register 0 */ 478 } Icm; 479 480 #elif COMPONENT_TYPEDEF_STYLE == 'N' 481 /** \brief ICM hardware registers */ 482 typedef struct { 483 __IO ICM_CFG_Type ICM_CFG; /**< Offset: 0x00 (R/W 32) Configuration Register */ 484 __O ICM_CTRL_Type ICM_CTRL; /**< Offset: 0x04 ( /W 32) Control Register */ 485 __I ICM_SR_Type ICM_SR; /**< Offset: 0x08 (R/ 32) Status Register */ 486 __I uint8_t Reserved1[4]; 487 __O ICM_IER_Type ICM_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ 488 __O ICM_IDR_Type ICM_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ 489 __I ICM_IMR_Type ICM_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ 490 __I ICM_ISR_Type ICM_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ 491 __I ICM_UASR_Type ICM_UASR; /**< Offset: 0x20 (R/ 32) Undefined Access Status Register */ 492 __I uint8_t Reserved2[12]; 493 __IO ICM_DSCR_Type ICM_DSCR; /**< Offset: 0x30 (R/W 32) Region Descriptor Area Start Address Register */ 494 __IO ICM_HASH_Type ICM_HASH; /**< Offset: 0x34 (R/W 32) Region Hash Area Start Address Register */ 495 __O ICM_UIHVAL_Type ICM_UIHVAL[8]; /**< Offset: 0x38 ( /W 32) User Initial Hash Value 0 Register 0 */ 496 } Icm; 497 498 #else /* COMPONENT_TYPEDEF_STYLE */ 499 #error Unknown component typedef style 500 #endif /* COMPONENT_TYPEDEF_STYLE */ 501 502 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 503 /** @} end of Integrity Check Monitor */ 504 505 #endif /* _SAMV71_ICM_COMPONENT_H_ */ 506
