1 /** 2 * \file 3 * 4 * \brief Header file for ATSAMV71J21 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71J21_H_ 32 #define _SAMV71J21_H_ 33 34 /** \addtogroup SAMV71J21_definitions SAMV71J21 definitions 35 This file defines all structures and symbols for SAMV71J21: 36 - registers and bitfields 37 - peripheral base address 38 - peripheral ID 39 - PIO definitions 40 * @{ 41 */ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 /** \defgroup Atmel_glob_defs Atmel Global Defines 48 49 <strong>IO Type Qualifiers</strong> are used 50 \li to specify the access to peripheral variables. 51 \li for automatic generation of peripheral register debug information. 52 53 \remark 54 CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint<size>_t' respective types. 55 Default the header files will follow the CMSIS core syntax. 56 * @{ 57 */ 58 59 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 60 #include <stdint.h> 61 62 /* IO definitions (access restrictions to peripheral registers) */ 63 #ifndef __cplusplus 64 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 65 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 66 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 67 #else 68 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 69 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 70 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 71 #endif 72 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 73 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 74 typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 75 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 76 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 77 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 78 79 #define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */ 80 #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ 81 #else /* Assembler */ 82 #define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */ 83 #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ 84 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 85 86 #if !defined(SKIP_INTEGER_LITERALS) 87 88 #if defined(_U_) || defined(_L_) || defined(_UL_) 89 #error "Integer Literals macros already defined elsewhere" 90 #endif 91 92 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 93 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */ 94 #define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ 95 #define _L_(x) x ## L /**< C code: Long integer literal constant value */ 96 #define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 97 98 #else /* Assembler */ 99 100 #define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ 101 #define _L_(x) x /**< Assembler: Long integer literal constant value */ 102 #define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ 103 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 104 105 #endif /* SKIP_INTEGER_LITERALS */ 106 /** @} end of Atmel Global Defines */ 107 108 /** \addtogroup SAMV71J21_cmsis CMSIS Definitions 109 * @{ 110 */ 111 /* ************************************************************************** */ 112 /* CMSIS DEFINITIONS FOR SAMV71J21 */ 113 /* ************************************************************************** */ 114 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 115 /** Interrupt Number Definition */ 116 typedef enum IRQn 117 { 118 /****** CORTEX-M7 Processor Exceptions Numbers ******************************/ 119 Reset_IRQn = -15, /**< 1 Reset Vector, invoked on Power up and warm reset */ 120 NonMaskableInt_IRQn = -14, /**< 2 Non maskable Interrupt, cannot be stopped or preempted */ 121 HardFault_IRQn = -13, /**< 3 Hard Fault, all classes of Fault */ 122 MemoryManagement_IRQn = -12, /**< 4 Memory Management, MPU mismatch, including Access Violation and No Match */ 123 BusFault_IRQn = -11, /**< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 124 UsageFault_IRQn = -10, /**< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 125 SVCall_IRQn = -5 , /**< 11 System Service Call via SVC instruction */ 126 DebugMonitor_IRQn = -4 , /**< 12 Debug Monitor */ 127 PendSV_IRQn = -2 , /**< 14 Pendable request for system service */ 128 SysTick_IRQn = -1 , /**< 15 System Tick Timer */ 129 /****** SAMV71J21 specific Interrupt Numbers ***********************************/ 130 SUPC_IRQn = 0 , /**< 0 SAMV71J21 Supply Controller (SUPC) */ 131 RSTC_IRQn = 1 , /**< 1 SAMV71J21 Reset Controller (RSTC) */ 132 RTC_IRQn = 2 , /**< 2 SAMV71J21 Real-time Clock (RTC) */ 133 RTT_IRQn = 3 , /**< 3 SAMV71J21 Real-time Timer (RTT) */ 134 WDT_IRQn = 4 , /**< 4 SAMV71J21 Watchdog Timer (WDT) */ 135 PMC_IRQn = 5 , /**< 5 SAMV71J21 Power Management Controller (PMC) */ 136 EFC_IRQn = 6 , /**< 6 SAMV71J21 Embedded Flash Controller (EFC) */ 137 UART0_IRQn = 7 , /**< 7 SAMV71J21 Universal Asynchronous Receiver Transmitter (UART0) */ 138 UART1_IRQn = 8 , /**< 8 SAMV71J21 Universal Asynchronous Receiver Transmitter (UART1) */ 139 PIOA_IRQn = 10 , /**< 10 SAMV71J21 Parallel Input/Output Controller (PIOA) */ 140 PIOB_IRQn = 11 , /**< 11 SAMV71J21 Parallel Input/Output Controller (PIOB) */ 141 USART0_IRQn = 13 , /**< 13 SAMV71J21 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ 142 USART1_IRQn = 14 , /**< 14 SAMV71J21 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ 143 PIOD_IRQn = 16 , /**< 16 SAMV71J21 Parallel Input/Output Controller (PIOD) */ 144 HSMCI_IRQn = 18 , /**< 18 SAMV71J21 High Speed MultiMedia Card Interface (HSMCI) */ 145 TWIHS0_IRQn = 19 , /**< 19 SAMV71J21 Two-wire Interface High Speed (TWIHS0) */ 146 TWIHS1_IRQn = 20 , /**< 20 SAMV71J21 Two-wire Interface High Speed (TWIHS1) */ 147 SSC_IRQn = 22 , /**< 22 SAMV71J21 Synchronous Serial Controller (SSC) */ 148 TC0_IRQn = 23 , /**< 23 SAMV71J21 Timer Counter (TC0) */ 149 TC1_IRQn = 24 , /**< 24 SAMV71J21 Timer Counter (TC0) */ 150 TC2_IRQn = 25 , /**< 25 SAMV71J21 Timer Counter (TC0) */ 151 TC3_IRQn = 26 , /**< 26 SAMV71J21 Timer Counter (TC1) */ 152 TC4_IRQn = 27 , /**< 27 SAMV71J21 Timer Counter (TC1) */ 153 TC5_IRQn = 28 , /**< 28 SAMV71J21 Timer Counter (TC1) */ 154 AFEC0_IRQn = 29 , /**< 29 SAMV71J21 Analog Front-End Controller (AFEC0) */ 155 DACC_IRQn = 30 , /**< 30 SAMV71J21 Digital-to-Analog Converter Controller (DACC) */ 156 PWM0_IRQn = 31 , /**< 31 SAMV71J21 Pulse Width Modulation Controller (PWM0) */ 157 ICM_IRQn = 32 , /**< 32 SAMV71J21 Integrity Check Monitor (ICM) */ 158 ACC_IRQn = 33 , /**< 33 SAMV71J21 Analog Comparator Controller (ACC) */ 159 USBHS_IRQn = 34 , /**< 34 SAMV71J21 USB High-Speed Interface (USBHS) */ 160 MCAN0_INT0_IRQn = 35 , /**< 35 SAMV71J21 Controller Area Network (MCAN0) */ 161 MCAN0_INT1_IRQn = 36 , /**< 36 SAMV71J21 Controller Area Network (MCAN0) */ 162 GMAC_IRQn = 39 , /**< 39 SAMV71J21 Gigabit Ethernet MAC (GMAC) */ 163 AFEC1_IRQn = 40 , /**< 40 SAMV71J21 Analog Front-End Controller (AFEC1) */ 164 QSPI_IRQn = 43 , /**< 43 SAMV71J21 Quad Serial Peripheral Interface (QSPI) */ 165 UART2_IRQn = 44 , /**< 44 SAMV71J21 Universal Asynchronous Receiver Transmitter (UART2) */ 166 TC6_IRQn = 47 , /**< 47 SAMV71J21 Timer Counter (TC2) */ 167 TC7_IRQn = 48 , /**< 48 SAMV71J21 Timer Counter (TC2) */ 168 TC8_IRQn = 49 , /**< 49 SAMV71J21 Timer Counter (TC2) */ 169 TC9_IRQn = 50 , /**< 50 SAMV71J21 Timer Counter (TC3) */ 170 TC10_IRQn = 51 , /**< 51 SAMV71J21 Timer Counter (TC3) */ 171 TC11_IRQn = 52 , /**< 52 SAMV71J21 Timer Counter (TC3) */ 172 MLB_IRQn = 53 , /**< 53 SAMV71J21 MediaLB (MLB) */ 173 AES_IRQn = 56 , /**< 56 SAMV71J21 Advanced Encryption Standard (AES) */ 174 TRNG_IRQn = 57 , /**< 57 SAMV71J21 True Random Number Generator (TRNG) */ 175 XDMAC_IRQn = 58 , /**< 58 SAMV71J21 Extensible DMA Controller (XDMAC) */ 176 ISI_IRQn = 59 , /**< 59 SAMV71J21 Image Sensor Interface (ISI) */ 177 PWM1_IRQn = 60 , /**< 60 SAMV71J21 Pulse Width Modulation Controller (PWM1) */ 178 FPU_IRQn = 61 , /**< 61 SAMV71J21 Floating Point Unit (FPU) */ 179 RSWDT_IRQn = 63 , /**< 63 SAMV71J21 Reinforced Safety Watchdog Timer (RSWDT) */ 180 GMAC_Q1_IRQn = 66 , /**< 66 SAMV71J21 Gigabit Ethernet MAC (GMAC) */ 181 GMAC_Q2_IRQn = 67 , /**< 67 SAMV71J21 Gigabit Ethernet MAC (GMAC) */ 182 IXC_IRQn = 68 , /**< 68 SAMV71J21 Floating Point Unit (FPU) */ 183 184 PERIPH_COUNT_IRQn = 69 /**< Number of peripheral IDs */ 185 } IRQn_Type; 186 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 187 188 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 189 typedef struct _DeviceVectors 190 { 191 /* Stack pointer */ 192 void* pvStack; 193 /* Cortex-M handlers */ 194 void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */ 195 void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */ 196 void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */ 197 void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */ 198 void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ 199 void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ 200 void* pvReservedC9; 201 void* pvReservedC8; 202 void* pvReservedC7; 203 void* pvReservedC6; 204 void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */ 205 void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */ 206 void* pvReservedC3; 207 void* pfnPendSV_Handler; /* -2 Pendable request for system service */ 208 void* pfnSysTick_Handler; /* -1 System Tick Timer */ 209 210 211 /* Peripheral handlers */ 212 void* pfnSUPC_Handler; /* 0 SAMV71J21 Supply Controller (SUPC) */ 213 void* pfnRSTC_Handler; /* 1 SAMV71J21 Reset Controller (RSTC) */ 214 void* pfnRTC_Handler; /* 2 SAMV71J21 Real-time Clock (RTC) */ 215 void* pfnRTT_Handler; /* 3 SAMV71J21 Real-time Timer (RTT) */ 216 void* pfnWDT_Handler; /* 4 SAMV71J21 Watchdog Timer (WDT) */ 217 void* pfnPMC_Handler; /* 5 SAMV71J21 Power Management Controller (PMC) */ 218 void* pfnEFC_Handler; /* 6 SAMV71J21 Embedded Flash Controller (EFC) */ 219 void* pfnUART0_Handler; /* 7 SAMV71J21 Universal Asynchronous Receiver Transmitter (UART0) */ 220 void* pfnUART1_Handler; /* 8 SAMV71J21 Universal Asynchronous Receiver Transmitter (UART1) */ 221 void* pvReserved9; 222 void* pfnPIOA_Handler; /* 10 SAMV71J21 Parallel Input/Output Controller (PIOA) */ 223 void* pfnPIOB_Handler; /* 11 SAMV71J21 Parallel Input/Output Controller (PIOB) */ 224 void* pvReserved12; 225 void* pfnUSART0_Handler; /* 13 SAMV71J21 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ 226 void* pfnUSART1_Handler; /* 14 SAMV71J21 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ 227 void* pvReserved15; 228 void* pfnPIOD_Handler; /* 16 SAMV71J21 Parallel Input/Output Controller (PIOD) */ 229 void* pvReserved17; 230 void* pfnHSMCI_Handler; /* 18 SAMV71J21 High Speed MultiMedia Card Interface (HSMCI) */ 231 void* pfnTWIHS0_Handler; /* 19 SAMV71J21 Two-wire Interface High Speed (TWIHS0) */ 232 void* pfnTWIHS1_Handler; /* 20 SAMV71J21 Two-wire Interface High Speed (TWIHS1) */ 233 void* pvReserved21; 234 void* pfnSSC_Handler; /* 22 SAMV71J21 Synchronous Serial Controller (SSC) */ 235 void* pfnTC0_Handler; /* 23 SAMV71J21 Timer Counter (TC0) */ 236 void* pfnTC1_Handler; /* 24 SAMV71J21 Timer Counter (TC0) */ 237 void* pfnTC2_Handler; /* 25 SAMV71J21 Timer Counter (TC0) */ 238 void* pfnTC3_Handler; /* 26 SAMV71J21 Timer Counter (TC1) */ 239 void* pfnTC4_Handler; /* 27 SAMV71J21 Timer Counter (TC1) */ 240 void* pfnTC5_Handler; /* 28 SAMV71J21 Timer Counter (TC1) */ 241 void* pfnAFEC0_Handler; /* 29 SAMV71J21 Analog Front-End Controller (AFEC0) */ 242 void* pfnDACC_Handler; /* 30 SAMV71J21 Digital-to-Analog Converter Controller (DACC) */ 243 void* pfnPWM0_Handler; /* 31 SAMV71J21 Pulse Width Modulation Controller (PWM0) */ 244 void* pfnICM_Handler; /* 32 SAMV71J21 Integrity Check Monitor (ICM) */ 245 void* pfnACC_Handler; /* 33 SAMV71J21 Analog Comparator Controller (ACC) */ 246 void* pfnUSBHS_Handler; /* 34 SAMV71J21 USB High-Speed Interface (USBHS) */ 247 void* pfnMCAN0_INT0_Handler; /* 35 SAMV71J21 Controller Area Network (MCAN0) */ 248 void* pfnMCAN0_INT1_Handler; /* 36 SAMV71J21 Controller Area Network (MCAN0) */ 249 void* pvReserved37; 250 void* pvReserved38; 251 void* pfnGMAC_Handler; /* 39 SAMV71J21 Gigabit Ethernet MAC (GMAC) */ 252 void* pfnAFEC1_Handler; /* 40 SAMV71J21 Analog Front-End Controller (AFEC1) */ 253 void* pvReserved41; 254 void* pvReserved42; 255 void* pfnQSPI_Handler; /* 43 SAMV71J21 Quad Serial Peripheral Interface (QSPI) */ 256 void* pfnUART2_Handler; /* 44 SAMV71J21 Universal Asynchronous Receiver Transmitter (UART2) */ 257 void* pvReserved45; 258 void* pvReserved46; 259 void* pfnTC6_Handler; /* 47 SAMV71J21 Timer Counter (TC2) */ 260 void* pfnTC7_Handler; /* 48 SAMV71J21 Timer Counter (TC2) */ 261 void* pfnTC8_Handler; /* 49 SAMV71J21 Timer Counter (TC2) */ 262 void* pfnTC9_Handler; /* 50 SAMV71J21 Timer Counter (TC3) */ 263 void* pfnTC10_Handler; /* 51 SAMV71J21 Timer Counter (TC3) */ 264 void* pfnTC11_Handler; /* 52 SAMV71J21 Timer Counter (TC3) */ 265 void* pfnMLB_Handler; /* 53 SAMV71J21 MediaLB (MLB) */ 266 void* pvReserved54; 267 void* pvReserved55; 268 void* pfnAES_Handler; /* 56 SAMV71J21 Advanced Encryption Standard (AES) */ 269 void* pfnTRNG_Handler; /* 57 SAMV71J21 True Random Number Generator (TRNG) */ 270 void* pfnXDMAC_Handler; /* 58 SAMV71J21 Extensible DMA Controller (XDMAC) */ 271 void* pfnISI_Handler; /* 59 SAMV71J21 Image Sensor Interface (ISI) */ 272 void* pfnPWM1_Handler; /* 60 SAMV71J21 Pulse Width Modulation Controller (PWM1) */ 273 void* pfnFPU_Handler; /* 61 SAMV71J21 Floating Point Unit (FPU) */ 274 void* pvReserved62; 275 void* pfnRSWDT_Handler; /* 63 SAMV71J21 Reinforced Safety Watchdog Timer (RSWDT) */ 276 void* pvReserved64; 277 void* pvReserved65; 278 void* pfnGMAC_Q1_Handler; /* 66 SAMV71J21 Gigabit Ethernet MAC (GMAC) */ 279 void* pfnGMAC_Q2_Handler; /* 67 SAMV71J21 Gigabit Ethernet MAC (GMAC) */ 280 void* pfnIXC_Handler; /* 68 SAMV71J21 Floating Point Unit (FPU) */ 281 } DeviceVectors; 282 283 /* Defines for Deprecated Interrupt and Exceptions handler names */ 284 #define pfnMemManage_Handler pfnMemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ 285 #define pfnDebugMon_Handler pfnDebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ 286 #define pfnNMI_Handler pfnNonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ 287 #define pfnSVC_Handler pfnSVCall_Handler /**< \deprecated Backward compatibility for ASF */ 288 289 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 290 291 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 292 #if !defined DONT_USE_PREDEFINED_CORE_HANDLERS 293 294 /* CORTEX-M7 core handlers */ 295 void Reset_Handler ( void ); 296 void NonMaskableInt_Handler ( void ); 297 void HardFault_Handler ( void ); 298 void MemoryManagement_Handler ( void ); 299 void BusFault_Handler ( void ); 300 void UsageFault_Handler ( void ); 301 void SVCall_Handler ( void ); 302 void DebugMonitor_Handler ( void ); 303 void PendSV_Handler ( void ); 304 void SysTick_Handler ( void ); 305 #endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */ 306 307 #if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS 308 309 /* Peripherals handlers */ 310 void ACC_Handler ( void ); 311 void AES_Handler ( void ); 312 void AFEC0_Handler ( void ); 313 void AFEC1_Handler ( void ); 314 void DACC_Handler ( void ); 315 void EFC_Handler ( void ); 316 void FPU_Handler ( void ); 317 void GMAC_Handler ( void ); 318 void GMAC_Q1_Handler ( void ); 319 void GMAC_Q2_Handler ( void ); 320 void HSMCI_Handler ( void ); 321 void ICM_Handler ( void ); 322 void ISI_Handler ( void ); 323 void IXC_Handler ( void ); 324 void MCAN0_INT0_Handler ( void ); 325 void MCAN0_INT1_Handler ( void ); 326 void MLB_Handler ( void ); 327 void PIOA_Handler ( void ); 328 void PIOB_Handler ( void ); 329 void PIOD_Handler ( void ); 330 void PMC_Handler ( void ); 331 void PWM0_Handler ( void ); 332 void PWM1_Handler ( void ); 333 void QSPI_Handler ( void ); 334 void RSTC_Handler ( void ); 335 void RSWDT_Handler ( void ); 336 void RTC_Handler ( void ); 337 void RTT_Handler ( void ); 338 void SSC_Handler ( void ); 339 void SUPC_Handler ( void ); 340 void TC0_Handler ( void ); 341 void TC10_Handler ( void ); 342 void TC11_Handler ( void ); 343 void TC1_Handler ( void ); 344 void TC2_Handler ( void ); 345 void TC3_Handler ( void ); 346 void TC4_Handler ( void ); 347 void TC5_Handler ( void ); 348 void TC6_Handler ( void ); 349 void TC7_Handler ( void ); 350 void TC8_Handler ( void ); 351 void TC9_Handler ( void ); 352 void TRNG_Handler ( void ); 353 void TWIHS0_Handler ( void ); 354 void TWIHS1_Handler ( void ); 355 void UART0_Handler ( void ); 356 void UART1_Handler ( void ); 357 void UART2_Handler ( void ); 358 void USART0_Handler ( void ); 359 void USART1_Handler ( void ); 360 void USBHS_Handler ( void ); 361 void WDT_Handler ( void ); 362 void XDMAC_Handler ( void ); 363 #endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */ 364 365 366 /* Defines for Deprecated Interrupt and Exceptions handler names */ 367 #define MemManage_Handler MemoryManagement_Handler /**< \deprecated Backward compatibility for ASF */ 368 #define DebugMon_Handler DebugMonitor_Handler /**< \deprecated Backward compatibility for ASF */ 369 #define NMI_Handler NonMaskableInt_Handler /**< \deprecated Backward compatibility for ASF */ 370 #define SVC_Handler SVCall_Handler /**< \deprecated Backward compatibility for ASF */ 371 372 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 373 374 375 /* 376 * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals 377 */ 378 379 #define __CM7_REV 0x0101 /**< CM7 Core Revision */ 380 #define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */ 381 #define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ 382 #define __MPU_PRESENT 1 /**< MPU present or not */ 383 #define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */ 384 #define __FPU_PRESENT 1 /**< FPU present or not */ 385 #define __FPU_DP 1 /**< Double Precision FPU */ 386 #define __ICACHE_PRESENT 1 /**< Instruction Cache present */ 387 #define __DCACHE_PRESENT 1 /**< Data Cache present */ 388 #define __ITCM_PRESENT 1 /**< Instruction TCM present */ 389 #define __DTCM_PRESENT 1 /**< Data TCM present */ 390 #define __DEBUG_LVL 1 391 #define __TRACE_LVL 1 392 #define __ARCH_ARM 1 393 #define __ARCH_ARM_CORTEX_M 1 394 #define __DEVICE_IS_SAM 1 395 396 /* 397 * \brief CMSIS includes 398 */ 399 #include <core_cm7.h> 400 #if !defined DONT_USE_CMSIS_INIT 401 #include "system_samv71.h" 402 #endif /* DONT_USE_CMSIS_INIT */ 403 404 /** @} end of SAMV71J21_cmsis CMSIS Definitions */ 405 406 /** \defgroup SAMV71J21_api Peripheral Software API 407 * @{ 408 */ 409 410 /* ************************************************************************** */ 411 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J21 */ 412 /* ************************************************************************** */ 413 #include "component/acc.h" 414 #include "component/aes.h" 415 #include "component/afec.h" 416 #include "component/chipid.h" 417 #include "component/dacc.h" 418 #include "component/efc.h" 419 #include "component/gmac.h" 420 #include "component/gpbr.h" 421 #include "component/hsmci.h" 422 #include "component/icm.h" 423 #include "component/isi.h" 424 #include "component/matrix.h" 425 #include "component/mcan.h" 426 #include "component/mlb.h" 427 #include "component/pio.h" 428 #include "component/pmc.h" 429 #include "component/pwm.h" 430 #include "component/qspi.h" 431 #include "component/rstc.h" 432 #include "component/rswdt.h" 433 #include "component/rtc.h" 434 #include "component/rtt.h" 435 #include "component/spi.h" 436 #include "component/ssc.h" 437 #include "component/supc.h" 438 #include "component/tc.h" 439 #include "component/trng.h" 440 #include "component/twihs.h" 441 #include "component/uart.h" 442 #include "component/usart.h" 443 #include "component/usbhs.h" 444 #include "component/utmi.h" 445 #include "component/wdt.h" 446 #include "component/xdmac.h" 447 /** @} end of Peripheral Software API */ 448 449 /** \defgroup SAMV71J21_reg Registers Access Definitions 450 * @{ 451 */ 452 453 /* ************************************************************************** */ 454 /* REGISTER ACCESS DEFINITIONS FOR SAMV71J21 */ 455 /* ************************************************************************** */ 456 #include "instance/acc.h" 457 #include "instance/aes.h" 458 #include "instance/afec0.h" 459 #include "instance/afec1.h" 460 #include "instance/chipid.h" 461 #include "instance/dacc.h" 462 #include "instance/efc.h" 463 #include "instance/gmac.h" 464 #include "instance/gpbr.h" 465 #include "instance/hsmci.h" 466 #include "instance/icm.h" 467 #include "instance/isi.h" 468 #include "instance/matrix.h" 469 #include "instance/mcan0.h" 470 #include "instance/mlb.h" 471 #include "instance/pioa.h" 472 #include "instance/piob.h" 473 #include "instance/piod.h" 474 #include "instance/pmc.h" 475 #include "instance/pwm0.h" 476 #include "instance/pwm1.h" 477 #include "instance/qspi.h" 478 #include "instance/rstc.h" 479 #include "instance/rswdt.h" 480 #include "instance/rtc.h" 481 #include "instance/rtt.h" 482 #include "instance/ssc.h" 483 #include "instance/supc.h" 484 #include "instance/tc0.h" 485 #include "instance/tc1.h" 486 #include "instance/tc2.h" 487 #include "instance/tc3.h" 488 #include "instance/trng.h" 489 #include "instance/twihs0.h" 490 #include "instance/twihs1.h" 491 #include "instance/uart0.h" 492 #include "instance/uart1.h" 493 #include "instance/uart2.h" 494 #include "instance/usart0.h" 495 #include "instance/usart1.h" 496 #include "instance/usbhs.h" 497 #include "instance/utmi.h" 498 #include "instance/wdt.h" 499 #include "instance/xdmac.h" 500 /** @} end of Registers Access Definitions */ 501 502 /** \addtogroup SAMV71J21_id Peripheral Ids Definitions 503 * @{ 504 */ 505 506 /* ************************************************************************** */ 507 /* PERIPHERAL ID DEFINITIONS FOR SAMV71J21 */ 508 /* ************************************************************************** */ 509 #define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ 510 #define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ 511 #define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */ 512 #define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */ 513 #define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ 514 #define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ 515 #define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */ 516 #define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */ 517 #define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */ 518 #define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */ 519 #define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */ 520 #define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */ 521 #define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */ 522 #define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */ 523 #define ID_HSMCI ( 18) /**< \brief High Speed MultiMedia Card Interface (HSMCI) */ 524 #define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */ 525 #define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */ 526 #define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */ 527 #define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */ 528 #define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */ 529 #define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */ 530 #define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */ 531 #define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */ 532 #define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */ 533 #define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */ 534 #define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */ 535 #define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */ 536 #define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */ 537 #define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */ 538 #define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */ 539 #define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */ 540 #define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */ 541 #define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */ 542 #define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */ 543 #define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */ 544 #define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */ 545 #define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */ 546 #define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */ 547 #define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */ 548 #define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */ 549 #define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */ 550 #define ID_MLB ( 53) /**< \brief MediaLB (MLB) */ 551 #define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */ 552 #define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */ 553 #define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */ 554 #define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */ 555 #define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */ 556 #define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */ 557 558 #define ID_PERIPH_COUNT ( 64) /**< \brief Number of peripheral IDs */ 559 /** @} end of Peripheral Ids Definitions */ 560 561 /** \addtogroup legacy_SAMV71J21_id Legacy Peripheral Ids Definitions 562 * @{ 563 */ 564 565 /* ************************************************************************** */ 566 /* LEGACY PERIPHERAL ID DEFINITIONS FOR SAMV71J21 */ 567 /* ************************************************************************** */ 568 #define ID_TC0 TC0_INSTANCE_ID_CHANNEL0 569 #define ID_TC1 TC0_INSTANCE_ID_CHANNEL1 570 #define ID_TC2 TC0_INSTANCE_ID_CHANNEL2 571 #define ID_TC3 TC1_INSTANCE_ID_CHANNEL0 572 #define ID_TC4 TC1_INSTANCE_ID_CHANNEL1 573 #define ID_TC5 TC1_INSTANCE_ID_CHANNEL2 574 #define ID_TC6 TC2_INSTANCE_ID_CHANNEL0 575 #define ID_TC7 TC2_INSTANCE_ID_CHANNEL1 576 #define ID_TC8 TC2_INSTANCE_ID_CHANNEL2 577 #define ID_TC9 TC3_INSTANCE_ID_CHANNEL0 578 #define ID_TC10 TC3_INSTANCE_ID_CHANNEL1 579 #define ID_TC11 TC3_INSTANCE_ID_CHANNEL2 580 /** @} end of Legacy Peripheral Ids Definitions */ 581 582 /** \addtogroup SAMV71J21_base Peripheral Base Address Definitions 583 * @{ 584 */ 585 586 /* ************************************************************************** */ 587 /* BASE ADDRESS DEFINITIONS FOR SAMV71J21 */ 588 /* ************************************************************************** */ 589 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 590 #define ACC (0x40044000) /**< \brief (ACC ) Base Address */ 591 #define AES (0x4006C000) /**< \brief (AES ) Base Address */ 592 #define AFEC0 (0x4003C000) /**< \brief (AFEC0 ) Base Address */ 593 #define AFEC1 (0x40064000) /**< \brief (AFEC1 ) Base Address */ 594 #define CHIPID (0x400E0940) /**< \brief (CHIPID ) Base Address */ 595 #define DACC (0x40040000) /**< \brief (DACC ) Base Address */ 596 #define EFC (0x400E0C00) /**< \brief (EFC ) Base Address */ 597 #define GMAC (0x40050000) /**< \brief (GMAC ) Base Address */ 598 #define GPBR (0x400E1890) /**< \brief (GPBR ) Base Address */ 599 #define HSMCI (0x40000000) /**< \brief (HSMCI ) Base Address */ 600 #define ICM (0x40048000) /**< \brief (ICM ) Base Address */ 601 #define ISI (0x4004C000) /**< \brief (ISI ) Base Address */ 602 #define MATRIX (0x40088000) /**< \brief (MATRIX ) Base Address */ 603 #define MCAN0 (0x40030000) /**< \brief (MCAN0 ) Base Address */ 604 #define MLB (0x40068000) /**< \brief (MLB ) Base Address */ 605 #define PIOA (0x400E0E00) /**< \brief (PIOA ) Base Address */ 606 #define PIOB (0x400E1000) /**< \brief (PIOB ) Base Address */ 607 #define PIOD (0x400E1400) /**< \brief (PIOD ) Base Address */ 608 #define PMC (0x400E0600) /**< \brief (PMC ) Base Address */ 609 #define PWM0 (0x40020000) /**< \brief (PWM0 ) Base Address */ 610 #define PWM1 (0x4005C000) /**< \brief (PWM1 ) Base Address */ 611 #define QSPI (0x4007C000) /**< \brief (QSPI ) Base Address */ 612 #define RSTC (0x400E1800) /**< \brief (RSTC ) Base Address */ 613 #define RSWDT (0x400E1900) /**< \brief (RSWDT ) Base Address */ 614 #define RTC (0x400E1860) /**< \brief (RTC ) Base Address */ 615 #define RTT (0x400E1830) /**< \brief (RTT ) Base Address */ 616 #define SSC (0x40004000) /**< \brief (SSC ) Base Address */ 617 #define SUPC (0x400E1810) /**< \brief (SUPC ) Base Address */ 618 #define TC0 (0x4000C000) /**< \brief (TC0 ) Base Address */ 619 #define TC1 (0x40010000) /**< \brief (TC1 ) Base Address */ 620 #define TC2 (0x40014000) /**< \brief (TC2 ) Base Address */ 621 #define TC3 (0x40054000) /**< \brief (TC3 ) Base Address */ 622 #define TRNG (0x40070000) /**< \brief (TRNG ) Base Address */ 623 #define TWIHS0 (0x40018000) /**< \brief (TWIHS0 ) Base Address */ 624 #define TWIHS1 (0x4001C000) /**< \brief (TWIHS1 ) Base Address */ 625 #define UART0 (0x400E0800) /**< \brief (UART0 ) Base Address */ 626 #define UART1 (0x400E0A00) /**< \brief (UART1 ) Base Address */ 627 #define UART2 (0x400E1A00) /**< \brief (UART2 ) Base Address */ 628 #define USART0 (0x40024000) /**< \brief (USART0 ) Base Address */ 629 #define USART1 (0x40028000) /**< \brief (USART1 ) Base Address */ 630 #define USBHS (0x40038000) /**< \brief (USBHS ) Base Address */ 631 #define UTMI (0x400E0400) /**< \brief (UTMI ) Base Address */ 632 #define WDT (0x400E1850) /**< \brief (WDT ) Base Address */ 633 #define XDMAC (0x40078000) /**< \brief (XDMAC ) Base Address */ 634 635 #else /* For C/C++ compiler */ 636 637 #define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ 638 #define ACC_INST_NUM 1 /**< \brief (ACC ) Number of instances */ 639 #define ACC_INSTS { ACC } /**< \brief (ACC ) Instances List */ 640 641 #define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ 642 #define AES_INST_NUM 1 /**< \brief (AES ) Number of instances */ 643 #define AES_INSTS { AES } /**< \brief (AES ) Instances List */ 644 645 #define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ 646 #define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ 647 #define AFEC_INST_NUM 2 /**< \brief (AFEC ) Number of instances */ 648 #define AFEC_INSTS { AFEC0, AFEC1 } /**< \brief (AFEC ) Instances List */ 649 650 #define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID ) Base Address */ 651 #define CHIPID_INST_NUM 1 /**< \brief (CHIPID ) Number of instances */ 652 #define CHIPID_INSTS { CHIPID } /**< \brief (CHIPID ) Instances List */ 653 654 #define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ 655 #define DACC_INST_NUM 1 /**< \brief (DACC ) Number of instances */ 656 #define DACC_INSTS { DACC } /**< \brief (DACC ) Instances List */ 657 658 #define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ 659 #define EFC_INST_NUM 1 /**< \brief (EFC ) Number of instances */ 660 #define EFC_INSTS { EFC } /**< \brief (EFC ) Instances List */ 661 662 #define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ 663 #define GMAC_INST_NUM 1 /**< \brief (GMAC ) Number of instances */ 664 #define GMAC_INSTS { GMAC } /**< \brief (GMAC ) Instances List */ 665 666 #define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ 667 #define GPBR_INST_NUM 1 /**< \brief (GPBR ) Number of instances */ 668 #define GPBR_INSTS { GPBR } /**< \brief (GPBR ) Instances List */ 669 670 #define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ 671 #define HSMCI_INST_NUM 1 /**< \brief (HSMCI ) Number of instances */ 672 #define HSMCI_INSTS { HSMCI } /**< \brief (HSMCI ) Instances List */ 673 674 #define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ 675 #define ICM_INST_NUM 1 /**< \brief (ICM ) Number of instances */ 676 #define ICM_INSTS { ICM } /**< \brief (ICM ) Instances List */ 677 678 #define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ 679 #define ISI_INST_NUM 1 /**< \brief (ISI ) Number of instances */ 680 #define ISI_INSTS { ISI } /**< \brief (ISI ) Instances List */ 681 682 #define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX ) Base Address */ 683 #define MATRIX_INST_NUM 1 /**< \brief (MATRIX ) Number of instances */ 684 #define MATRIX_INSTS { MATRIX } /**< \brief (MATRIX ) Instances List */ 685 686 #define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ 687 #define MCAN_INST_NUM 1 /**< \brief (MCAN ) Number of instances */ 688 #define MCAN_INSTS { MCAN0 } /**< \brief (MCAN ) Instances List */ 689 690 #define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ 691 #define MLB_INST_NUM 1 /**< \brief (MLB ) Number of instances */ 692 #define MLB_INSTS { MLB } /**< \brief (MLB ) Instances List */ 693 694 #define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ 695 #define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ 696 #define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ 697 #define PIO_INST_NUM 3 /**< \brief (PIO ) Number of instances */ 698 #define PIO_INSTS { PIOA, PIOB, PIOD } /**< \brief (PIO ) Instances List */ 699 700 #define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ 701 #define PMC_INST_NUM 1 /**< \brief (PMC ) Number of instances */ 702 #define PMC_INSTS { PMC } /**< \brief (PMC ) Instances List */ 703 704 #define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ 705 #define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ 706 #define PWM_INST_NUM 2 /**< \brief (PWM ) Number of instances */ 707 #define PWM_INSTS { PWM0, PWM1 } /**< \brief (PWM ) Instances List */ 708 709 #define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ 710 #define QSPI_INST_NUM 1 /**< \brief (QSPI ) Number of instances */ 711 #define QSPI_INSTS { QSPI } /**< \brief (QSPI ) Instances List */ 712 713 #define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ 714 #define RSTC_INST_NUM 1 /**< \brief (RSTC ) Number of instances */ 715 #define RSTC_INSTS { RSTC } /**< \brief (RSTC ) Instances List */ 716 717 #define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ 718 #define RSWDT_INST_NUM 1 /**< \brief (RSWDT ) Number of instances */ 719 #define RSWDT_INSTS { RSWDT } /**< \brief (RSWDT ) Instances List */ 720 721 #define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ 722 #define RTC_INST_NUM 1 /**< \brief (RTC ) Number of instances */ 723 #define RTC_INSTS { RTC } /**< \brief (RTC ) Instances List */ 724 725 #define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ 726 #define RTT_INST_NUM 1 /**< \brief (RTT ) Number of instances */ 727 #define RTT_INSTS { RTT } /**< \brief (RTT ) Instances List */ 728 729 #define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ 730 #define SSC_INST_NUM 1 /**< \brief (SSC ) Number of instances */ 731 #define SSC_INSTS { SSC } /**< \brief (SSC ) Instances List */ 732 733 #define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ 734 #define SUPC_INST_NUM 1 /**< \brief (SUPC ) Number of instances */ 735 #define SUPC_INSTS { SUPC } /**< \brief (SUPC ) Instances List */ 736 737 #define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ 738 #define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ 739 #define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ 740 #define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ 741 #define TC_INST_NUM 4 /**< \brief (TC ) Number of instances */ 742 #define TC_INSTS { TC0, TC1, TC2, TC3 } /**< \brief (TC ) Instances List */ 743 744 #define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ 745 #define TRNG_INST_NUM 1 /**< \brief (TRNG ) Number of instances */ 746 #define TRNG_INSTS { TRNG } /**< \brief (TRNG ) Instances List */ 747 748 #define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0 ) Base Address */ 749 #define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1 ) Base Address */ 750 #define TWIHS_INST_NUM 2 /**< \brief (TWIHS ) Number of instances */ 751 #define TWIHS_INSTS { TWIHS0, TWIHS1 } /**< \brief (TWIHS ) Instances List */ 752 753 #define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ 754 #define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ 755 #define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ 756 #define UART_INST_NUM 3 /**< \brief (UART ) Number of instances */ 757 #define UART_INSTS { UART0, UART1, UART2 } /**< \brief (UART ) Instances List */ 758 759 #define USART0 ((Usart *)0x40024000U) /**< \brief (USART0 ) Base Address */ 760 #define USART1 ((Usart *)0x40028000U) /**< \brief (USART1 ) Base Address */ 761 #define USART_INST_NUM 2 /**< \brief (USART ) Number of instances */ 762 #define USART_INSTS { USART0, USART1 } /**< \brief (USART ) Instances List */ 763 764 #define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ 765 #define USBHS_INST_NUM 1 /**< \brief (USBHS ) Number of instances */ 766 #define USBHS_INSTS { USBHS } /**< \brief (USBHS ) Instances List */ 767 768 #define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ 769 #define UTMI_INST_NUM 1 /**< \brief (UTMI ) Number of instances */ 770 #define UTMI_INSTS { UTMI } /**< \brief (UTMI ) Instances List */ 771 772 #define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ 773 #define WDT_INST_NUM 1 /**< \brief (WDT ) Number of instances */ 774 #define WDT_INSTS { WDT } /**< \brief (WDT ) Instances List */ 775 776 #define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ 777 #define XDMAC_INST_NUM 1 /**< \brief (XDMAC ) Number of instances */ 778 #define XDMAC_INSTS { XDMAC } /**< \brief (XDMAC ) Instances List */ 779 780 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 781 /** @} end of Peripheral Base Address Definitions */ 782 783 /** \addtogroup SAMV71J21_pio Peripheral Pio Definitions 784 * @{ 785 */ 786 787 /* ************************************************************************** */ 788 /* PIO DEFINITIONS FOR SAMV71J21*/ 789 /* ************************************************************************** */ 790 #include "pio/samv71j21.h" 791 /** @} end of Peripheral Pio Definitions */ 792 793 /* ************************************************************************** */ 794 /* MEMORY MAPPING DEFINITIONS FOR SAMV71J21*/ 795 /* ************************************************************************** */ 796 797 #define PERIPHERALS_SIZE _U_(0x20000000) /* 524288kB Memory segment type: io */ 798 #define SYSTEM_SIZE _U_(0x10000000) /* 262144kB Memory segment type: io */ 799 #define QSPIMEM_SIZE _U_(0x20000000) /* 524288kB Memory segment type: other */ 800 #define AXIMX_SIZE _U_(0x00100000) /* 1024kB Memory segment type: other */ 801 #define ITCM_SIZE _U_(0x00200000) /* 2048kB Memory segment type: other */ 802 #define IFLASH_SIZE _U_(0x00200000) /* 2048kB Memory segment type: flash */ 803 #define IFLASH_PAGE_SIZE _U_( 512) 804 #define IFLASH_NB_OF_PAGES _U_( 4096) 805 806 #define IROM_SIZE _U_(0x00004000) /* 16kB Memory segment type: rom */ 807 #define DTCM_SIZE _U_(0x00020000) /* 128kB Memory segment type: other */ 808 #define IRAM_SIZE _U_(0x00060000) /* 384kB Memory segment type: ram */ 809 810 #define PERIPHERALS_ADDR _U_(0x40000000) /**< PERIPHERALS base address (type: io)*/ 811 #define SYSTEM_ADDR _U_(0xe0000000) /**< SYSTEM base address (type: io)*/ 812 #define QSPIMEM_ADDR _U_(0x80000000) /**< QSPIMEM base address (type: other)*/ 813 #define AXIMX_ADDR _U_(0xa0000000) /**< AXIMX base address (type: other)*/ 814 #define ITCM_ADDR _U_(0x00000000) /**< ITCM base address (type: other)*/ 815 #define IFLASH_ADDR _U_(0x00400000) /**< IFLASH base address (type: flash)*/ 816 #define IROM_ADDR _U_(0x00800000) /**< IROM base address (type: rom)*/ 817 #define DTCM_ADDR _U_(0x20000000) /**< DTCM base address (type: other)*/ 818 #define IRAM_ADDR _U_(0x20400000) /**< IRAM base address (type: ram)*/ 819 820 /* ************************************************************************** */ 821 /** DEVICE SIGNATURES FOR SAMV71J21 */ 822 /* ************************************************************************** */ 823 #define JTAGID _UL_(0X05B3D03F) 824 #define CHIP_JTAGID _UL_(0X05B3D03F) 825 #define CHIP_CIDR _UL_(0XA1220E00) 826 #define CHIP_EXID _UL_(0X00000000) 827 828 /* ************************************************************************** */ 829 /** ELECTRICAL DEFINITIONS FOR SAMV71J21 */ 830 /* ************************************************************************** */ 831 #define CHIP_FREQ_SLCK_RC_MIN _UL_(20000) 832 #define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency*/ 833 #define CHIP_FREQ_SLCK_RC_MAX _UL_(44000) 834 #define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000) 835 #define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000) 836 #define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000) 837 #define CHIP_FREQ_CPU_MAX _UL_(300000000) 838 #define CHIP_FREQ_XTAL_32K _UL_(32768) 839 #define CHIP_FREQ_XTAL_12M _UL_(12000000) 840 #define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0*/ 841 #define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1*/ 842 #define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2*/ 843 #define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3*/ 844 #define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/ 845 #define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/ 846 #define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/ 847 #define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges*/ 848 849 850 851 #ifdef __cplusplus 852 } 853 #endif 854 855 /** @} end of SAMV71J21 definitions */ 856 857 858 #endif /* _SAMV71J21_H_ */ 859
