1 /** 2 * \file 3 * 4 * \brief Component description for SUPC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_SUPC_COMPONENT_H_ 32 #define _SAMV71_SUPC_COMPONENT_H_ 33 #define _SAMV71_SUPC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Supply Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR SUPC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define SUPC_6452 /**< (SUPC) Module ID */ 46 #define REV_SUPC ZB /**< (SUPC) Module revision */ 47 48 /* -------- SUPC_CR : (SUPC Offset: 0x00) (/W 32) Supply Controller Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t :2; /**< bit: 0..1 Reserved */ 54 uint32_t VROFF:1; /**< bit: 2 Voltage Regulator Off */ 55 uint32_t XTALSEL:1; /**< bit: 3 Crystal Oscillator Select */ 56 uint32_t :20; /**< bit: 4..23 Reserved */ 57 uint32_t KEY:8; /**< bit: 24..31 Password */ 58 } bit; /**< Structure used for bit access */ 59 uint32_t reg; /**< Type used for register access */ 60 } SUPC_CR_Type; 61 #endif 62 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 63 64 #define SUPC_CR_OFFSET (0x00) /**< (SUPC_CR) Supply Controller Control Register Offset */ 65 66 #define SUPC_CR_VROFF_Pos 2 /**< (SUPC_CR) Voltage Regulator Off Position */ 67 #define SUPC_CR_VROFF_Msk (_U_(0x1) << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) Voltage Regulator Off Mask */ 68 #define SUPC_CR_VROFF SUPC_CR_VROFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_CR_VROFF_Msk instead */ 69 #define SUPC_CR_VROFF_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */ 70 #define SUPC_CR_VROFF_STOP_VREG_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ 71 #define SUPC_CR_VROFF_NO_EFFECT (SUPC_CR_VROFF_NO_EFFECT_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) No effect. Position */ 72 #define SUPC_CR_VROFF_STOP_VREG (SUPC_CR_VROFF_STOP_VREG_Val << SUPC_CR_VROFF_Pos) /**< (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. Position */ 73 #define SUPC_CR_XTALSEL_Pos 3 /**< (SUPC_CR) Crystal Oscillator Select Position */ 74 #define SUPC_CR_XTALSEL_Msk (_U_(0x1) << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) Crystal Oscillator Select Mask */ 75 #define SUPC_CR_XTALSEL SUPC_CR_XTALSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_CR_XTALSEL_Msk instead */ 76 #define SUPC_CR_XTALSEL_NO_EFFECT_Val _U_(0x0) /**< (SUPC_CR) No effect. */ 77 #define SUPC_CR_XTALSEL_CRYSTAL_SEL_Val _U_(0x1) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ 78 #define SUPC_CR_XTALSEL_NO_EFFECT (SUPC_CR_XTALSEL_NO_EFFECT_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) No effect. Position */ 79 #define SUPC_CR_XTALSEL_CRYSTAL_SEL (SUPC_CR_XTALSEL_CRYSTAL_SEL_Val << SUPC_CR_XTALSEL_Pos) /**< (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. Position */ 80 #define SUPC_CR_KEY_Pos 24 /**< (SUPC_CR) Password Position */ 81 #define SUPC_CR_KEY_Msk (_U_(0xFF) << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Password Mask */ 82 #define SUPC_CR_KEY(value) (SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos)) 83 #define SUPC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. */ 84 #define SUPC_CR_KEY_PASSWD (SUPC_CR_KEY_PASSWD_Val << SUPC_CR_KEY_Pos) /**< (SUPC_CR) Writing any other value in this field aborts the write operation. Position */ 85 #define SUPC_CR_MASK _U_(0xFF00000C) /**< \deprecated (SUPC_CR) Register MASK (Use SUPC_CR_Msk instead) */ 86 #define SUPC_CR_Msk _U_(0xFF00000C) /**< (SUPC_CR) Register Mask */ 87 88 89 /* -------- SUPC_SMMR : (SUPC Offset: 0x04) (R/W 32) Supply Controller Supply Monitor Mode Register -------- */ 90 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 91 #if COMPONENT_TYPEDEF_STYLE == 'N' 92 typedef union { 93 struct { 94 uint32_t SMTH:4; /**< bit: 0..3 Supply Monitor Threshold */ 95 uint32_t :4; /**< bit: 4..7 Reserved */ 96 uint32_t SMSMPL:3; /**< bit: 8..10 Supply Monitor Sampling Period */ 97 uint32_t :1; /**< bit: 11 Reserved */ 98 uint32_t SMRSTEN:1; /**< bit: 12 Supply Monitor Reset Enable */ 99 uint32_t SMIEN:1; /**< bit: 13 Supply Monitor Interrupt Enable */ 100 uint32_t :18; /**< bit: 14..31 Reserved */ 101 } bit; /**< Structure used for bit access */ 102 uint32_t reg; /**< Type used for register access */ 103 } SUPC_SMMR_Type; 104 #endif 105 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 106 107 #define SUPC_SMMR_OFFSET (0x04) /**< (SUPC_SMMR) Supply Controller Supply Monitor Mode Register Offset */ 108 109 #define SUPC_SMMR_SMTH_Pos 0 /**< (SUPC_SMMR) Supply Monitor Threshold Position */ 110 #define SUPC_SMMR_SMTH_Msk (_U_(0xF) << SUPC_SMMR_SMTH_Pos) /**< (SUPC_SMMR) Supply Monitor Threshold Mask */ 111 #define SUPC_SMMR_SMTH(value) (SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos)) 112 #define SUPC_SMMR_SMSMPL_Pos 8 /**< (SUPC_SMMR) Supply Monitor Sampling Period Position */ 113 #define SUPC_SMMR_SMSMPL_Msk (_U_(0x7) << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor Sampling Period Mask */ 114 #define SUPC_SMMR_SMSMPL(value) (SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos)) 115 #define SUPC_SMMR_SMSMPL_SMD_Val _U_(0x0) /**< (SUPC_SMMR) Supply Monitor disabled */ 116 #define SUPC_SMMR_SMSMPL_CSM_Val _U_(0x1) /**< (SUPC_SMMR) Continuous Supply Monitor */ 117 #define SUPC_SMMR_SMSMPL_32SLCK_Val _U_(0x2) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ 118 #define SUPC_SMMR_SMSMPL_256SLCK_Val _U_(0x3) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ 119 #define SUPC_SMMR_SMSMPL_2048SLCK_Val _U_(0x4) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ 120 #define SUPC_SMMR_SMSMPL_SMD (SUPC_SMMR_SMSMPL_SMD_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor disabled Position */ 121 #define SUPC_SMMR_SMSMPL_CSM (SUPC_SMMR_SMSMPL_CSM_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Continuous Supply Monitor Position */ 122 #define SUPC_SMMR_SMSMPL_32SLCK (SUPC_SMMR_SMSMPL_32SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods Position */ 123 #define SUPC_SMMR_SMSMPL_256SLCK (SUPC_SMMR_SMSMPL_256SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods Position */ 124 #define SUPC_SMMR_SMSMPL_2048SLCK (SUPC_SMMR_SMSMPL_2048SLCK_Val << SUPC_SMMR_SMSMPL_Pos) /**< (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods Position */ 125 #define SUPC_SMMR_SMRSTEN_Pos 12 /**< (SUPC_SMMR) Supply Monitor Reset Enable Position */ 126 #define SUPC_SMMR_SMRSTEN_Msk (_U_(0x1) << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) Supply Monitor Reset Enable Mask */ 127 #define SUPC_SMMR_SMRSTEN SUPC_SMMR_SMRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SMMR_SMRSTEN_Msk instead */ 128 #define SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ 129 #define SUPC_SMMR_SMRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ 130 #define SUPC_SMMR_SMRSTEN_NOT_ENABLE (SUPC_SMMR_SMRSTEN_NOT_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. Position */ 131 #define SUPC_SMMR_SMRSTEN_ENABLE (SUPC_SMMR_SMRSTEN_ENABLE_Val << SUPC_SMMR_SMRSTEN_Pos) /**< (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. Position */ 132 #define SUPC_SMMR_SMIEN_Pos 13 /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Position */ 133 #define SUPC_SMMR_SMIEN_Msk (_U_(0x1) << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) Supply Monitor Interrupt Enable Mask */ 134 #define SUPC_SMMR_SMIEN SUPC_SMMR_SMIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SMMR_SMIEN_Msk instead */ 135 #define SUPC_SMMR_SMIEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ 136 #define SUPC_SMMR_SMIEN_ENABLE_Val _U_(0x1) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ 137 #define SUPC_SMMR_SMIEN_NOT_ENABLE (SUPC_SMMR_SMIEN_NOT_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. Position */ 138 #define SUPC_SMMR_SMIEN_ENABLE (SUPC_SMMR_SMIEN_ENABLE_Val << SUPC_SMMR_SMIEN_Pos) /**< (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. Position */ 139 #define SUPC_SMMR_MASK _U_(0x370F) /**< \deprecated (SUPC_SMMR) Register MASK (Use SUPC_SMMR_Msk instead) */ 140 #define SUPC_SMMR_Msk _U_(0x370F) /**< (SUPC_SMMR) Register Mask */ 141 142 143 /* -------- SUPC_MR : (SUPC Offset: 0x08) (R/W 32) Supply Controller Mode Register -------- */ 144 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 145 #if COMPONENT_TYPEDEF_STYLE == 'N' 146 typedef union { 147 struct { 148 uint32_t :12; /**< bit: 0..11 Reserved */ 149 uint32_t BODRSTEN:1; /**< bit: 12 Brownout Detector Reset Enable */ 150 uint32_t BODDIS:1; /**< bit: 13 Brownout Detector Disable */ 151 uint32_t ONREG:1; /**< bit: 14 Voltage Regulator Enable */ 152 uint32_t :2; /**< bit: 15..16 Reserved */ 153 uint32_t BKUPRETON:1; /**< bit: 17 SRAM On In Backup Mode */ 154 uint32_t :2; /**< bit: 18..19 Reserved */ 155 uint32_t OSCBYPASS:1; /**< bit: 20 Oscillator Bypass */ 156 uint32_t :3; /**< bit: 21..23 Reserved */ 157 uint32_t KEY:8; /**< bit: 24..31 Password Key */ 158 } bit; /**< Structure used for bit access */ 159 uint32_t reg; /**< Type used for register access */ 160 } SUPC_MR_Type; 161 #endif 162 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 163 164 #define SUPC_MR_OFFSET (0x08) /**< (SUPC_MR) Supply Controller Mode Register Offset */ 165 166 #define SUPC_MR_BODRSTEN_Pos 12 /**< (SUPC_MR) Brownout Detector Reset Enable Position */ 167 #define SUPC_MR_BODRSTEN_Msk (_U_(0x1) << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) Brownout Detector Reset Enable Mask */ 168 #define SUPC_MR_BODRSTEN SUPC_MR_BODRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_BODRSTEN_Msk instead */ 169 #define SUPC_MR_BODRSTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ 170 #define SUPC_MR_BODRSTEN_ENABLE_Val _U_(0x1) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ 171 #define SUPC_MR_BODRSTEN_NOT_ENABLE (SUPC_MR_BODRSTEN_NOT_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. Position */ 172 #define SUPC_MR_BODRSTEN_ENABLE (SUPC_MR_BODRSTEN_ENABLE_Val << SUPC_MR_BODRSTEN_Pos) /**< (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. Position */ 173 #define SUPC_MR_BODDIS_Pos 13 /**< (SUPC_MR) Brownout Detector Disable Position */ 174 #define SUPC_MR_BODDIS_Msk (_U_(0x1) << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) Brownout Detector Disable Mask */ 175 #define SUPC_MR_BODDIS SUPC_MR_BODDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_BODDIS_Msk instead */ 176 #define SUPC_MR_BODDIS_ENABLE_Val _U_(0x0) /**< (SUPC_MR) The core brownout detector is enabled. */ 177 #define SUPC_MR_BODDIS_DISABLE_Val _U_(0x1) /**< (SUPC_MR) The core brownout detector is disabled. */ 178 #define SUPC_MR_BODDIS_ENABLE (SUPC_MR_BODDIS_ENABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is enabled. Position */ 179 #define SUPC_MR_BODDIS_DISABLE (SUPC_MR_BODDIS_DISABLE_Val << SUPC_MR_BODDIS_Pos) /**< (SUPC_MR) The core brownout detector is disabled. Position */ 180 #define SUPC_MR_ONREG_Pos 14 /**< (SUPC_MR) Voltage Regulator Enable Position */ 181 #define SUPC_MR_ONREG_Msk (_U_(0x1) << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Voltage Regulator Enable Mask */ 182 #define SUPC_MR_ONREG SUPC_MR_ONREG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_ONREG_Msk instead */ 183 #define SUPC_MR_ONREG_ONREG_UNUSED_Val _U_(0x0) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ 184 #define SUPC_MR_ONREG_ONREG_USED_Val _U_(0x1) /**< (SUPC_MR) Internal voltage regulator is used. */ 185 #define SUPC_MR_ONREG_ONREG_UNUSED (SUPC_MR_ONREG_ONREG_UNUSED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is not used (external power supply is used). Position */ 186 #define SUPC_MR_ONREG_ONREG_USED (SUPC_MR_ONREG_ONREG_USED_Val << SUPC_MR_ONREG_Pos) /**< (SUPC_MR) Internal voltage regulator is used. Position */ 187 #define SUPC_MR_BKUPRETON_Pos 17 /**< (SUPC_MR) SRAM On In Backup Mode Position */ 188 #define SUPC_MR_BKUPRETON_Msk (_U_(0x1) << SUPC_MR_BKUPRETON_Pos) /**< (SUPC_MR) SRAM On In Backup Mode Mask */ 189 #define SUPC_MR_BKUPRETON SUPC_MR_BKUPRETON_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_BKUPRETON_Msk instead */ 190 #define SUPC_MR_OSCBYPASS_Pos 20 /**< (SUPC_MR) Oscillator Bypass Position */ 191 #define SUPC_MR_OSCBYPASS_Msk (_U_(0x1) << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) Oscillator Bypass Mask */ 192 #define SUPC_MR_OSCBYPASS SUPC_MR_OSCBYPASS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_MR_OSCBYPASS_Msk instead */ 193 #define SUPC_MR_OSCBYPASS_NO_EFFECT_Val _U_(0x0) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ 194 #define SUPC_MR_OSCBYPASS_BYPASS_Val _U_(0x1) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ 195 #define SUPC_MR_OSCBYPASS_NO_EFFECT (SUPC_MR_OSCBYPASS_NO_EFFECT_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). Position */ 196 #define SUPC_MR_OSCBYPASS_BYPASS (SUPC_MR_OSCBYPASS_BYPASS_Val << SUPC_MR_OSCBYPASS_Pos) /**< (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. Position */ 197 #define SUPC_MR_KEY_Pos 24 /**< (SUPC_MR) Password Key Position */ 198 #define SUPC_MR_KEY_Msk (_U_(0xFF) << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Password Key Mask */ 199 #define SUPC_MR_KEY(value) (SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos)) 200 #define SUPC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. */ 201 #define SUPC_MR_KEY_PASSWD (SUPC_MR_KEY_PASSWD_Val << SUPC_MR_KEY_Pos) /**< (SUPC_MR) Writing any other value in this field aborts the write operation. Position */ 202 #define SUPC_MR_MASK _U_(0xFF127000) /**< \deprecated (SUPC_MR) Register MASK (Use SUPC_MR_Msk instead) */ 203 #define SUPC_MR_Msk _U_(0xFF127000) /**< (SUPC_MR) Register Mask */ 204 205 206 /* -------- SUPC_WUMR : (SUPC Offset: 0x0c) (R/W 32) Supply Controller Wakeup Mode Register -------- */ 207 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 208 #if COMPONENT_TYPEDEF_STYLE == 'N' 209 typedef union { 210 struct { 211 uint32_t :1; /**< bit: 0 Reserved */ 212 uint32_t SMEN:1; /**< bit: 1 Supply Monitor Wakeup Enable */ 213 uint32_t RTTEN:1; /**< bit: 2 Real-time Timer Wakeup Enable */ 214 uint32_t RTCEN:1; /**< bit: 3 Real-time Clock Wakeup Enable */ 215 uint32_t :1; /**< bit: 4 Reserved */ 216 uint32_t LPDBCEN0:1; /**< bit: 5 Low-power Debouncer Enable WKUP0 */ 217 uint32_t LPDBCEN1:1; /**< bit: 6 Low-power Debouncer Enable WKUP1 */ 218 uint32_t LPDBCCLR:1; /**< bit: 7 Low-power Debouncer Clear */ 219 uint32_t :4; /**< bit: 8..11 Reserved */ 220 uint32_t WKUPDBC:3; /**< bit: 12..14 Wakeup Inputs Debouncer Period */ 221 uint32_t :1; /**< bit: 15 Reserved */ 222 uint32_t LPDBC:3; /**< bit: 16..18 Low-power Debouncer Period */ 223 uint32_t :13; /**< bit: 19..31 Reserved */ 224 } bit; /**< Structure used for bit access */ 225 struct { 226 uint32_t :5; /**< bit: 0..4 Reserved */ 227 uint32_t LPDBCEN:2; /**< bit: 5..6 Low-power Debouncer Enable WKUPx */ 228 uint32_t :25; /**< bit: 7..31 Reserved */ 229 } vec; /**< Structure used for vec access */ 230 uint32_t reg; /**< Type used for register access */ 231 } SUPC_WUMR_Type; 232 #endif 233 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 234 235 #define SUPC_WUMR_OFFSET (0x0C) /**< (SUPC_WUMR) Supply Controller Wakeup Mode Register Offset */ 236 237 #define SUPC_WUMR_SMEN_Pos 1 /**< (SUPC_WUMR) Supply Monitor Wakeup Enable Position */ 238 #define SUPC_WUMR_SMEN_Msk (_U_(0x1) << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) Supply Monitor Wakeup Enable Mask */ 239 #define SUPC_WUMR_SMEN SUPC_WUMR_SMEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_SMEN_Msk instead */ 240 #define SUPC_WUMR_SMEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The supply monitor detection has no wakeup effect. */ 241 #define SUPC_WUMR_SMEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The supply monitor detection forces the wakeup of the core power supply. */ 242 #define SUPC_WUMR_SMEN_NOT_ENABLE (SUPC_WUMR_SMEN_NOT_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection has no wakeup effect. Position */ 243 #define SUPC_WUMR_SMEN_ENABLE (SUPC_WUMR_SMEN_ENABLE_Val << SUPC_WUMR_SMEN_Pos) /**< (SUPC_WUMR) The supply monitor detection forces the wakeup of the core power supply. Position */ 244 #define SUPC_WUMR_RTTEN_Pos 2 /**< (SUPC_WUMR) Real-time Timer Wakeup Enable Position */ 245 #define SUPC_WUMR_RTTEN_Msk (_U_(0x1) << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) Real-time Timer Wakeup Enable Mask */ 246 #define SUPC_WUMR_RTTEN SUPC_WUMR_RTTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_RTTEN_Msk instead */ 247 #define SUPC_WUMR_RTTEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTT alarm signal has no wakeup effect. */ 248 #define SUPC_WUMR_RTTEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTT alarm signal forces the wakeup of the core power supply. */ 249 #define SUPC_WUMR_RTTEN_NOT_ENABLE (SUPC_WUMR_RTTEN_NOT_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal has no wakeup effect. Position */ 250 #define SUPC_WUMR_RTTEN_ENABLE (SUPC_WUMR_RTTEN_ENABLE_Val << SUPC_WUMR_RTTEN_Pos) /**< (SUPC_WUMR) The RTT alarm signal forces the wakeup of the core power supply. Position */ 251 #define SUPC_WUMR_RTCEN_Pos 3 /**< (SUPC_WUMR) Real-time Clock Wakeup Enable Position */ 252 #define SUPC_WUMR_RTCEN_Msk (_U_(0x1) << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) Real-time Clock Wakeup Enable Mask */ 253 #define SUPC_WUMR_RTCEN SUPC_WUMR_RTCEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_RTCEN_Msk instead */ 254 #define SUPC_WUMR_RTCEN_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The RTC alarm signal has no wakeup effect. */ 255 #define SUPC_WUMR_RTCEN_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The RTC alarm signal forces the wakeup of the core power supply. */ 256 #define SUPC_WUMR_RTCEN_NOT_ENABLE (SUPC_WUMR_RTCEN_NOT_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal has no wakeup effect. Position */ 257 #define SUPC_WUMR_RTCEN_ENABLE (SUPC_WUMR_RTCEN_ENABLE_Val << SUPC_WUMR_RTCEN_Pos) /**< (SUPC_WUMR) The RTC alarm signal forces the wakeup of the core power supply. Position */ 258 #define SUPC_WUMR_LPDBCEN0_Pos 5 /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Position */ 259 #define SUPC_WUMR_LPDBCEN0_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP0 Mask */ 260 #define SUPC_WUMR_LPDBCEN0 SUPC_WUMR_LPDBCEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_LPDBCEN0_Msk instead */ 261 #define SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ 262 #define SUPC_WUMR_LPDBCEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wakeup. */ 263 #define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (SUPC_WUMR_LPDBCEN0_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. Position */ 264 #define SUPC_WUMR_LPDBCEN0_ENABLE (SUPC_WUMR_LPDBCEN0_ENABLE_Val << SUPC_WUMR_LPDBCEN0_Pos) /**< (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wakeup. Position */ 265 #define SUPC_WUMR_LPDBCEN1_Pos 6 /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Position */ 266 #define SUPC_WUMR_LPDBCEN1_Msk (_U_(0x1) << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) Low-power Debouncer Enable WKUP1 Mask */ 267 #define SUPC_WUMR_LPDBCEN1 SUPC_WUMR_LPDBCEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_LPDBCEN1_Msk instead */ 268 #define SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ 269 #define SUPC_WUMR_LPDBCEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wakeup. */ 270 #define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (SUPC_WUMR_LPDBCEN1_NOT_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. Position */ 271 #define SUPC_WUMR_LPDBCEN1_ENABLE (SUPC_WUMR_LPDBCEN1_ENABLE_Val << SUPC_WUMR_LPDBCEN1_Pos) /**< (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wakeup. Position */ 272 #define SUPC_WUMR_LPDBCCLR_Pos 7 /**< (SUPC_WUMR) Low-power Debouncer Clear Position */ 273 #define SUPC_WUMR_LPDBCCLR_Msk (_U_(0x1) << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) Low-power Debouncer Clear Mask */ 274 #define SUPC_WUMR_LPDBCCLR SUPC_WUMR_LPDBCCLR_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUMR_LPDBCCLR_Msk instead */ 275 #define SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val _U_(0x0) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ 276 #define SUPC_WUMR_LPDBCCLR_ENABLE_Val _U_(0x1) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ 277 #define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (SUPC_WUMR_LPDBCCLR_NOT_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. Position */ 278 #define SUPC_WUMR_LPDBCCLR_ENABLE (SUPC_WUMR_LPDBCCLR_ENABLE_Val << SUPC_WUMR_LPDBCCLR_Pos) /**< (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. Position */ 279 #define SUPC_WUMR_WKUPDBC_Pos 12 /**< (SUPC_WUMR) Wakeup Inputs Debouncer Period Position */ 280 #define SUPC_WUMR_WKUPDBC_Msk (_U_(0x7) << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Wakeup Inputs Debouncer Period Mask */ 281 #define SUPC_WUMR_WKUPDBC(value) (SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos)) 282 #define SUPC_WUMR_WKUPDBC_IMMEDIATE_Val _U_(0x0) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ 283 #define SUPC_WUMR_WKUPDBC_3_SLCK_Val _U_(0x1) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ 284 #define SUPC_WUMR_WKUPDBC_32_SLCK_Val _U_(0x2) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ 285 #define SUPC_WUMR_WKUPDBC_512_SLCK_Val _U_(0x3) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ 286 #define SUPC_WUMR_WKUPDBC_4096_SLCK_Val _U_(0x4) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ 287 #define SUPC_WUMR_WKUPDBC_32768_SLCK_Val _U_(0x5) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ 288 #define SUPC_WUMR_WKUPDBC_IMMEDIATE (SUPC_WUMR_WKUPDBC_IMMEDIATE_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. Position */ 289 #define SUPC_WUMR_WKUPDBC_3_SLCK (SUPC_WUMR_WKUPDBC_3_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods Position */ 290 #define SUPC_WUMR_WKUPDBC_32_SLCK (SUPC_WUMR_WKUPDBC_32_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods Position */ 291 #define SUPC_WUMR_WKUPDBC_512_SLCK (SUPC_WUMR_WKUPDBC_512_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods Position */ 292 #define SUPC_WUMR_WKUPDBC_4096_SLCK (SUPC_WUMR_WKUPDBC_4096_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods Position */ 293 #define SUPC_WUMR_WKUPDBC_32768_SLCK (SUPC_WUMR_WKUPDBC_32768_SLCK_Val << SUPC_WUMR_WKUPDBC_Pos) /**< (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods Position */ 294 #define SUPC_WUMR_LPDBC_Pos 16 /**< (SUPC_WUMR) Low-power Debouncer Period Position */ 295 #define SUPC_WUMR_LPDBC_Msk (_U_(0x7) << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Low-power Debouncer Period Mask */ 296 #define SUPC_WUMR_LPDBC(value) (SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos)) 297 #define SUPC_WUMR_LPDBC_DISABLE_Val _U_(0x0) /**< (SUPC_WUMR) Disables the low-power debouncers. */ 298 #define SUPC_WUMR_LPDBC_2_RTCOUT_Val _U_(0x1) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ 299 #define SUPC_WUMR_LPDBC_3_RTCOUT_Val _U_(0x2) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ 300 #define SUPC_WUMR_LPDBC_4_RTCOUT_Val _U_(0x3) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ 301 #define SUPC_WUMR_LPDBC_5_RTCOUT_Val _U_(0x4) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ 302 #define SUPC_WUMR_LPDBC_6_RTCOUT_Val _U_(0x5) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ 303 #define SUPC_WUMR_LPDBC_7_RTCOUT_Val _U_(0x6) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ 304 #define SUPC_WUMR_LPDBC_8_RTCOUT_Val _U_(0x7) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ 305 #define SUPC_WUMR_LPDBC_DISABLE (SUPC_WUMR_LPDBC_DISABLE_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) Disables the low-power debouncers. Position */ 306 #define SUPC_WUMR_LPDBC_2_RTCOUT (SUPC_WUMR_LPDBC_2_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods Position */ 307 #define SUPC_WUMR_LPDBC_3_RTCOUT (SUPC_WUMR_LPDBC_3_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods Position */ 308 #define SUPC_WUMR_LPDBC_4_RTCOUT (SUPC_WUMR_LPDBC_4_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods Position */ 309 #define SUPC_WUMR_LPDBC_5_RTCOUT (SUPC_WUMR_LPDBC_5_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods Position */ 310 #define SUPC_WUMR_LPDBC_6_RTCOUT (SUPC_WUMR_LPDBC_6_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods Position */ 311 #define SUPC_WUMR_LPDBC_7_RTCOUT (SUPC_WUMR_LPDBC_7_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods Position */ 312 #define SUPC_WUMR_LPDBC_8_RTCOUT (SUPC_WUMR_LPDBC_8_RTCOUT_Val << SUPC_WUMR_LPDBC_Pos) /**< (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods Position */ 313 #define SUPC_WUMR_MASK _U_(0x770EE) /**< \deprecated (SUPC_WUMR) Register MASK (Use SUPC_WUMR_Msk instead) */ 314 #define SUPC_WUMR_Msk _U_(0x770EE) /**< (SUPC_WUMR) Register Mask */ 315 316 #define SUPC_WUMR_LPDBCEN_Pos 5 /**< (SUPC_WUMR Position) Low-power Debouncer Enable WKUPx */ 317 #define SUPC_WUMR_LPDBCEN_Msk (_U_(0x3) << SUPC_WUMR_LPDBCEN_Pos) /**< (SUPC_WUMR Mask) LPDBCEN */ 318 #define SUPC_WUMR_LPDBCEN(value) (SUPC_WUMR_LPDBCEN_Msk & ((value) << SUPC_WUMR_LPDBCEN_Pos)) 319 320 /* -------- SUPC_WUIR : (SUPC Offset: 0x10) (R/W 32) Supply Controller Wakeup Inputs Register -------- */ 321 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 322 #if COMPONENT_TYPEDEF_STYLE == 'N' 323 typedef union { 324 struct { 325 uint32_t WKUPEN0:1; /**< bit: 0 Wakeup Input Enable 0 to 0 */ 326 uint32_t WKUPEN1:1; /**< bit: 1 Wakeup Input Enable 0 to 1 */ 327 uint32_t WKUPEN2:1; /**< bit: 2 Wakeup Input Enable 0 to 2 */ 328 uint32_t WKUPEN3:1; /**< bit: 3 Wakeup Input Enable 0 to 3 */ 329 uint32_t WKUPEN4:1; /**< bit: 4 Wakeup Input Enable 0 to 4 */ 330 uint32_t WKUPEN5:1; /**< bit: 5 Wakeup Input Enable 0 to 5 */ 331 uint32_t WKUPEN6:1; /**< bit: 6 Wakeup Input Enable 0 to 6 */ 332 uint32_t WKUPEN7:1; /**< bit: 7 Wakeup Input Enable 0 to 7 */ 333 uint32_t WKUPEN8:1; /**< bit: 8 Wakeup Input Enable 0 to 8 */ 334 uint32_t WKUPEN9:1; /**< bit: 9 Wakeup Input Enable 0 to 9 */ 335 uint32_t WKUPEN10:1; /**< bit: 10 Wakeup Input Enable 0 to 10 */ 336 uint32_t WKUPEN11:1; /**< bit: 11 Wakeup Input Enable 0 to 11 */ 337 uint32_t WKUPEN12:1; /**< bit: 12 Wakeup Input Enable 0 to 12 */ 338 uint32_t WKUPEN13:1; /**< bit: 13 Wakeup Input Enable 0 to 13 */ 339 uint32_t :2; /**< bit: 14..15 Reserved */ 340 uint32_t WKUPT0:1; /**< bit: 16 Wakeup Input Type 0 to 0 */ 341 uint32_t WKUPT1:1; /**< bit: 17 Wakeup Input Type 0 to 1 */ 342 uint32_t WKUPT2:1; /**< bit: 18 Wakeup Input Type 0 to 2 */ 343 uint32_t WKUPT3:1; /**< bit: 19 Wakeup Input Type 0 to 3 */ 344 uint32_t WKUPT4:1; /**< bit: 20 Wakeup Input Type 0 to 4 */ 345 uint32_t WKUPT5:1; /**< bit: 21 Wakeup Input Type 0 to 5 */ 346 uint32_t WKUPT6:1; /**< bit: 22 Wakeup Input Type 0 to 6 */ 347 uint32_t WKUPT7:1; /**< bit: 23 Wakeup Input Type 0 to 7 */ 348 uint32_t WKUPT8:1; /**< bit: 24 Wakeup Input Type 0 to 8 */ 349 uint32_t WKUPT9:1; /**< bit: 25 Wakeup Input Type 0 to 9 */ 350 uint32_t WKUPT10:1; /**< bit: 26 Wakeup Input Type 0 to 10 */ 351 uint32_t WKUPT11:1; /**< bit: 27 Wakeup Input Type 0 to 11 */ 352 uint32_t WKUPT12:1; /**< bit: 28 Wakeup Input Type 0 to 12 */ 353 uint32_t WKUPT13:1; /**< bit: 29 Wakeup Input Type 0 to 13 */ 354 uint32_t :2; /**< bit: 30..31 Reserved */ 355 } bit; /**< Structure used for bit access */ 356 struct { 357 uint32_t WKUPEN:14; /**< bit: 0..13 Wakeup Input Enable x to x */ 358 uint32_t :2; /**< bit: 14..15 Reserved */ 359 uint32_t WKUPT:14; /**< bit: 16..29 Wakeup Input Type x to x3 */ 360 uint32_t :2; /**< bit: 30..31 Reserved */ 361 } vec; /**< Structure used for vec access */ 362 uint32_t reg; /**< Type used for register access */ 363 } SUPC_WUIR_Type; 364 #endif 365 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 366 367 #define SUPC_WUIR_OFFSET (0x10) /**< (SUPC_WUIR) Supply Controller Wakeup Inputs Register Offset */ 368 369 #define SUPC_WUIR_WKUPEN0_Pos 0 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 0 Position */ 370 #define SUPC_WUIR_WKUPEN0_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 0 Mask */ 371 #define SUPC_WUIR_WKUPEN0 SUPC_WUIR_WKUPEN0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN0_Msk instead */ 372 #define SUPC_WUIR_WKUPEN0_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 373 #define SUPC_WUIR_WKUPEN0_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 374 #define SUPC_WUIR_WKUPEN0_DISABLE (SUPC_WUIR_WKUPEN0_DISABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 375 #define SUPC_WUIR_WKUPEN0_ENABLE (SUPC_WUIR_WKUPEN0_ENABLE_Val << SUPC_WUIR_WKUPEN0_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 376 #define SUPC_WUIR_WKUPEN1_Pos 1 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 1 Position */ 377 #define SUPC_WUIR_WKUPEN1_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 1 Mask */ 378 #define SUPC_WUIR_WKUPEN1 SUPC_WUIR_WKUPEN1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN1_Msk instead */ 379 #define SUPC_WUIR_WKUPEN1_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 380 #define SUPC_WUIR_WKUPEN1_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 381 #define SUPC_WUIR_WKUPEN1_DISABLE (SUPC_WUIR_WKUPEN1_DISABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 382 #define SUPC_WUIR_WKUPEN1_ENABLE (SUPC_WUIR_WKUPEN1_ENABLE_Val << SUPC_WUIR_WKUPEN1_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 383 #define SUPC_WUIR_WKUPEN2_Pos 2 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 2 Position */ 384 #define SUPC_WUIR_WKUPEN2_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 2 Mask */ 385 #define SUPC_WUIR_WKUPEN2 SUPC_WUIR_WKUPEN2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN2_Msk instead */ 386 #define SUPC_WUIR_WKUPEN2_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 387 #define SUPC_WUIR_WKUPEN2_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 388 #define SUPC_WUIR_WKUPEN2_DISABLE (SUPC_WUIR_WKUPEN2_DISABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 389 #define SUPC_WUIR_WKUPEN2_ENABLE (SUPC_WUIR_WKUPEN2_ENABLE_Val << SUPC_WUIR_WKUPEN2_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 390 #define SUPC_WUIR_WKUPEN3_Pos 3 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 3 Position */ 391 #define SUPC_WUIR_WKUPEN3_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 3 Mask */ 392 #define SUPC_WUIR_WKUPEN3 SUPC_WUIR_WKUPEN3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN3_Msk instead */ 393 #define SUPC_WUIR_WKUPEN3_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 394 #define SUPC_WUIR_WKUPEN3_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 395 #define SUPC_WUIR_WKUPEN3_DISABLE (SUPC_WUIR_WKUPEN3_DISABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 396 #define SUPC_WUIR_WKUPEN3_ENABLE (SUPC_WUIR_WKUPEN3_ENABLE_Val << SUPC_WUIR_WKUPEN3_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 397 #define SUPC_WUIR_WKUPEN4_Pos 4 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 4 Position */ 398 #define SUPC_WUIR_WKUPEN4_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 4 Mask */ 399 #define SUPC_WUIR_WKUPEN4 SUPC_WUIR_WKUPEN4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN4_Msk instead */ 400 #define SUPC_WUIR_WKUPEN4_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 401 #define SUPC_WUIR_WKUPEN4_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 402 #define SUPC_WUIR_WKUPEN4_DISABLE (SUPC_WUIR_WKUPEN4_DISABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 403 #define SUPC_WUIR_WKUPEN4_ENABLE (SUPC_WUIR_WKUPEN4_ENABLE_Val << SUPC_WUIR_WKUPEN4_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 404 #define SUPC_WUIR_WKUPEN5_Pos 5 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 5 Position */ 405 #define SUPC_WUIR_WKUPEN5_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 5 Mask */ 406 #define SUPC_WUIR_WKUPEN5 SUPC_WUIR_WKUPEN5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN5_Msk instead */ 407 #define SUPC_WUIR_WKUPEN5_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 408 #define SUPC_WUIR_WKUPEN5_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 409 #define SUPC_WUIR_WKUPEN5_DISABLE (SUPC_WUIR_WKUPEN5_DISABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 410 #define SUPC_WUIR_WKUPEN5_ENABLE (SUPC_WUIR_WKUPEN5_ENABLE_Val << SUPC_WUIR_WKUPEN5_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 411 #define SUPC_WUIR_WKUPEN6_Pos 6 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 6 Position */ 412 #define SUPC_WUIR_WKUPEN6_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 6 Mask */ 413 #define SUPC_WUIR_WKUPEN6 SUPC_WUIR_WKUPEN6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN6_Msk instead */ 414 #define SUPC_WUIR_WKUPEN6_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 415 #define SUPC_WUIR_WKUPEN6_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 416 #define SUPC_WUIR_WKUPEN6_DISABLE (SUPC_WUIR_WKUPEN6_DISABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 417 #define SUPC_WUIR_WKUPEN6_ENABLE (SUPC_WUIR_WKUPEN6_ENABLE_Val << SUPC_WUIR_WKUPEN6_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 418 #define SUPC_WUIR_WKUPEN7_Pos 7 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 7 Position */ 419 #define SUPC_WUIR_WKUPEN7_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 7 Mask */ 420 #define SUPC_WUIR_WKUPEN7 SUPC_WUIR_WKUPEN7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN7_Msk instead */ 421 #define SUPC_WUIR_WKUPEN7_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 422 #define SUPC_WUIR_WKUPEN7_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 423 #define SUPC_WUIR_WKUPEN7_DISABLE (SUPC_WUIR_WKUPEN7_DISABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 424 #define SUPC_WUIR_WKUPEN7_ENABLE (SUPC_WUIR_WKUPEN7_ENABLE_Val << SUPC_WUIR_WKUPEN7_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 425 #define SUPC_WUIR_WKUPEN8_Pos 8 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 8 Position */ 426 #define SUPC_WUIR_WKUPEN8_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 8 Mask */ 427 #define SUPC_WUIR_WKUPEN8 SUPC_WUIR_WKUPEN8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN8_Msk instead */ 428 #define SUPC_WUIR_WKUPEN8_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 429 #define SUPC_WUIR_WKUPEN8_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 430 #define SUPC_WUIR_WKUPEN8_DISABLE (SUPC_WUIR_WKUPEN8_DISABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 431 #define SUPC_WUIR_WKUPEN8_ENABLE (SUPC_WUIR_WKUPEN8_ENABLE_Val << SUPC_WUIR_WKUPEN8_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 432 #define SUPC_WUIR_WKUPEN9_Pos 9 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 9 Position */ 433 #define SUPC_WUIR_WKUPEN9_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 9 Mask */ 434 #define SUPC_WUIR_WKUPEN9 SUPC_WUIR_WKUPEN9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN9_Msk instead */ 435 #define SUPC_WUIR_WKUPEN9_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 436 #define SUPC_WUIR_WKUPEN9_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 437 #define SUPC_WUIR_WKUPEN9_DISABLE (SUPC_WUIR_WKUPEN9_DISABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 438 #define SUPC_WUIR_WKUPEN9_ENABLE (SUPC_WUIR_WKUPEN9_ENABLE_Val << SUPC_WUIR_WKUPEN9_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 439 #define SUPC_WUIR_WKUPEN10_Pos 10 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 10 Position */ 440 #define SUPC_WUIR_WKUPEN10_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 10 Mask */ 441 #define SUPC_WUIR_WKUPEN10 SUPC_WUIR_WKUPEN10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN10_Msk instead */ 442 #define SUPC_WUIR_WKUPEN10_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 443 #define SUPC_WUIR_WKUPEN10_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 444 #define SUPC_WUIR_WKUPEN10_DISABLE (SUPC_WUIR_WKUPEN10_DISABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 445 #define SUPC_WUIR_WKUPEN10_ENABLE (SUPC_WUIR_WKUPEN10_ENABLE_Val << SUPC_WUIR_WKUPEN10_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 446 #define SUPC_WUIR_WKUPEN11_Pos 11 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 11 Position */ 447 #define SUPC_WUIR_WKUPEN11_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 11 Mask */ 448 #define SUPC_WUIR_WKUPEN11 SUPC_WUIR_WKUPEN11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN11_Msk instead */ 449 #define SUPC_WUIR_WKUPEN11_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 450 #define SUPC_WUIR_WKUPEN11_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 451 #define SUPC_WUIR_WKUPEN11_DISABLE (SUPC_WUIR_WKUPEN11_DISABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 452 #define SUPC_WUIR_WKUPEN11_ENABLE (SUPC_WUIR_WKUPEN11_ENABLE_Val << SUPC_WUIR_WKUPEN11_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 453 #define SUPC_WUIR_WKUPEN12_Pos 12 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 12 Position */ 454 #define SUPC_WUIR_WKUPEN12_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 12 Mask */ 455 #define SUPC_WUIR_WKUPEN12 SUPC_WUIR_WKUPEN12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN12_Msk instead */ 456 #define SUPC_WUIR_WKUPEN12_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 457 #define SUPC_WUIR_WKUPEN12_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 458 #define SUPC_WUIR_WKUPEN12_DISABLE (SUPC_WUIR_WKUPEN12_DISABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 459 #define SUPC_WUIR_WKUPEN12_ENABLE (SUPC_WUIR_WKUPEN12_ENABLE_Val << SUPC_WUIR_WKUPEN12_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 460 #define SUPC_WUIR_WKUPEN13_Pos 13 /**< (SUPC_WUIR) Wakeup Input Enable 0 to 13 Position */ 461 #define SUPC_WUIR_WKUPEN13_Msk (_U_(0x1) << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) Wakeup Input Enable 0 to 13 Mask */ 462 #define SUPC_WUIR_WKUPEN13 SUPC_WUIR_WKUPEN13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPEN13_Msk instead */ 463 #define SUPC_WUIR_WKUPEN13_DISABLE_Val _U_(0x0) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. */ 464 #define SUPC_WUIR_WKUPEN13_ENABLE_Val _U_(0x1) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. */ 465 #define SUPC_WUIR_WKUPEN13_DISABLE (SUPC_WUIR_WKUPEN13_DISABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wakeup input has no wakeup effect. Position */ 466 #define SUPC_WUIR_WKUPEN13_ENABLE (SUPC_WUIR_WKUPEN13_ENABLE_Val << SUPC_WUIR_WKUPEN13_Pos) /**< (SUPC_WUIR) The corresponding wakeup input is enabled for a wakeup of the core power supply. Position */ 467 #define SUPC_WUIR_WKUPT0_Pos 16 /**< (SUPC_WUIR) Wakeup Input Type 0 to 0 Position */ 468 #define SUPC_WUIR_WKUPT0_Msk (_U_(0x1) << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 0 Mask */ 469 #define SUPC_WUIR_WKUPT0 SUPC_WUIR_WKUPT0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT0_Msk instead */ 470 #define SUPC_WUIR_WKUPT0_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 471 #define SUPC_WUIR_WKUPT0_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 472 #define SUPC_WUIR_WKUPT0_LOW (SUPC_WUIR_WKUPT0_LOW_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 473 #define SUPC_WUIR_WKUPT0_HIGH (SUPC_WUIR_WKUPT0_HIGH_Val << SUPC_WUIR_WKUPT0_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 474 #define SUPC_WUIR_WKUPT1_Pos 17 /**< (SUPC_WUIR) Wakeup Input Type 0 to 1 Position */ 475 #define SUPC_WUIR_WKUPT1_Msk (_U_(0x1) << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 1 Mask */ 476 #define SUPC_WUIR_WKUPT1 SUPC_WUIR_WKUPT1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT1_Msk instead */ 477 #define SUPC_WUIR_WKUPT1_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 478 #define SUPC_WUIR_WKUPT1_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 479 #define SUPC_WUIR_WKUPT1_LOW (SUPC_WUIR_WKUPT1_LOW_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 480 #define SUPC_WUIR_WKUPT1_HIGH (SUPC_WUIR_WKUPT1_HIGH_Val << SUPC_WUIR_WKUPT1_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 481 #define SUPC_WUIR_WKUPT2_Pos 18 /**< (SUPC_WUIR) Wakeup Input Type 0 to 2 Position */ 482 #define SUPC_WUIR_WKUPT2_Msk (_U_(0x1) << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 2 Mask */ 483 #define SUPC_WUIR_WKUPT2 SUPC_WUIR_WKUPT2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT2_Msk instead */ 484 #define SUPC_WUIR_WKUPT2_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 485 #define SUPC_WUIR_WKUPT2_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 486 #define SUPC_WUIR_WKUPT2_LOW (SUPC_WUIR_WKUPT2_LOW_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 487 #define SUPC_WUIR_WKUPT2_HIGH (SUPC_WUIR_WKUPT2_HIGH_Val << SUPC_WUIR_WKUPT2_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 488 #define SUPC_WUIR_WKUPT3_Pos 19 /**< (SUPC_WUIR) Wakeup Input Type 0 to 3 Position */ 489 #define SUPC_WUIR_WKUPT3_Msk (_U_(0x1) << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 3 Mask */ 490 #define SUPC_WUIR_WKUPT3 SUPC_WUIR_WKUPT3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT3_Msk instead */ 491 #define SUPC_WUIR_WKUPT3_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 492 #define SUPC_WUIR_WKUPT3_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 493 #define SUPC_WUIR_WKUPT3_LOW (SUPC_WUIR_WKUPT3_LOW_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 494 #define SUPC_WUIR_WKUPT3_HIGH (SUPC_WUIR_WKUPT3_HIGH_Val << SUPC_WUIR_WKUPT3_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 495 #define SUPC_WUIR_WKUPT4_Pos 20 /**< (SUPC_WUIR) Wakeup Input Type 0 to 4 Position */ 496 #define SUPC_WUIR_WKUPT4_Msk (_U_(0x1) << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 4 Mask */ 497 #define SUPC_WUIR_WKUPT4 SUPC_WUIR_WKUPT4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT4_Msk instead */ 498 #define SUPC_WUIR_WKUPT4_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 499 #define SUPC_WUIR_WKUPT4_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 500 #define SUPC_WUIR_WKUPT4_LOW (SUPC_WUIR_WKUPT4_LOW_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 501 #define SUPC_WUIR_WKUPT4_HIGH (SUPC_WUIR_WKUPT4_HIGH_Val << SUPC_WUIR_WKUPT4_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 502 #define SUPC_WUIR_WKUPT5_Pos 21 /**< (SUPC_WUIR) Wakeup Input Type 0 to 5 Position */ 503 #define SUPC_WUIR_WKUPT5_Msk (_U_(0x1) << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 5 Mask */ 504 #define SUPC_WUIR_WKUPT5 SUPC_WUIR_WKUPT5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT5_Msk instead */ 505 #define SUPC_WUIR_WKUPT5_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 506 #define SUPC_WUIR_WKUPT5_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 507 #define SUPC_WUIR_WKUPT5_LOW (SUPC_WUIR_WKUPT5_LOW_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 508 #define SUPC_WUIR_WKUPT5_HIGH (SUPC_WUIR_WKUPT5_HIGH_Val << SUPC_WUIR_WKUPT5_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 509 #define SUPC_WUIR_WKUPT6_Pos 22 /**< (SUPC_WUIR) Wakeup Input Type 0 to 6 Position */ 510 #define SUPC_WUIR_WKUPT6_Msk (_U_(0x1) << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 6 Mask */ 511 #define SUPC_WUIR_WKUPT6 SUPC_WUIR_WKUPT6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT6_Msk instead */ 512 #define SUPC_WUIR_WKUPT6_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 513 #define SUPC_WUIR_WKUPT6_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 514 #define SUPC_WUIR_WKUPT6_LOW (SUPC_WUIR_WKUPT6_LOW_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 515 #define SUPC_WUIR_WKUPT6_HIGH (SUPC_WUIR_WKUPT6_HIGH_Val << SUPC_WUIR_WKUPT6_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 516 #define SUPC_WUIR_WKUPT7_Pos 23 /**< (SUPC_WUIR) Wakeup Input Type 0 to 7 Position */ 517 #define SUPC_WUIR_WKUPT7_Msk (_U_(0x1) << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 7 Mask */ 518 #define SUPC_WUIR_WKUPT7 SUPC_WUIR_WKUPT7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT7_Msk instead */ 519 #define SUPC_WUIR_WKUPT7_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 520 #define SUPC_WUIR_WKUPT7_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 521 #define SUPC_WUIR_WKUPT7_LOW (SUPC_WUIR_WKUPT7_LOW_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 522 #define SUPC_WUIR_WKUPT7_HIGH (SUPC_WUIR_WKUPT7_HIGH_Val << SUPC_WUIR_WKUPT7_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 523 #define SUPC_WUIR_WKUPT8_Pos 24 /**< (SUPC_WUIR) Wakeup Input Type 0 to 8 Position */ 524 #define SUPC_WUIR_WKUPT8_Msk (_U_(0x1) << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 8 Mask */ 525 #define SUPC_WUIR_WKUPT8 SUPC_WUIR_WKUPT8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT8_Msk instead */ 526 #define SUPC_WUIR_WKUPT8_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 527 #define SUPC_WUIR_WKUPT8_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 528 #define SUPC_WUIR_WKUPT8_LOW (SUPC_WUIR_WKUPT8_LOW_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 529 #define SUPC_WUIR_WKUPT8_HIGH (SUPC_WUIR_WKUPT8_HIGH_Val << SUPC_WUIR_WKUPT8_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 530 #define SUPC_WUIR_WKUPT9_Pos 25 /**< (SUPC_WUIR) Wakeup Input Type 0 to 9 Position */ 531 #define SUPC_WUIR_WKUPT9_Msk (_U_(0x1) << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 9 Mask */ 532 #define SUPC_WUIR_WKUPT9 SUPC_WUIR_WKUPT9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT9_Msk instead */ 533 #define SUPC_WUIR_WKUPT9_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 534 #define SUPC_WUIR_WKUPT9_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 535 #define SUPC_WUIR_WKUPT9_LOW (SUPC_WUIR_WKUPT9_LOW_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 536 #define SUPC_WUIR_WKUPT9_HIGH (SUPC_WUIR_WKUPT9_HIGH_Val << SUPC_WUIR_WKUPT9_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 537 #define SUPC_WUIR_WKUPT10_Pos 26 /**< (SUPC_WUIR) Wakeup Input Type 0 to 10 Position */ 538 #define SUPC_WUIR_WKUPT10_Msk (_U_(0x1) << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 10 Mask */ 539 #define SUPC_WUIR_WKUPT10 SUPC_WUIR_WKUPT10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT10_Msk instead */ 540 #define SUPC_WUIR_WKUPT10_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 541 #define SUPC_WUIR_WKUPT10_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 542 #define SUPC_WUIR_WKUPT10_LOW (SUPC_WUIR_WKUPT10_LOW_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 543 #define SUPC_WUIR_WKUPT10_HIGH (SUPC_WUIR_WKUPT10_HIGH_Val << SUPC_WUIR_WKUPT10_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 544 #define SUPC_WUIR_WKUPT11_Pos 27 /**< (SUPC_WUIR) Wakeup Input Type 0 to 11 Position */ 545 #define SUPC_WUIR_WKUPT11_Msk (_U_(0x1) << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 11 Mask */ 546 #define SUPC_WUIR_WKUPT11 SUPC_WUIR_WKUPT11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT11_Msk instead */ 547 #define SUPC_WUIR_WKUPT11_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 548 #define SUPC_WUIR_WKUPT11_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 549 #define SUPC_WUIR_WKUPT11_LOW (SUPC_WUIR_WKUPT11_LOW_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 550 #define SUPC_WUIR_WKUPT11_HIGH (SUPC_WUIR_WKUPT11_HIGH_Val << SUPC_WUIR_WKUPT11_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 551 #define SUPC_WUIR_WKUPT12_Pos 28 /**< (SUPC_WUIR) Wakeup Input Type 0 to 12 Position */ 552 #define SUPC_WUIR_WKUPT12_Msk (_U_(0x1) << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 12 Mask */ 553 #define SUPC_WUIR_WKUPT12 SUPC_WUIR_WKUPT12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT12_Msk instead */ 554 #define SUPC_WUIR_WKUPT12_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 555 #define SUPC_WUIR_WKUPT12_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 556 #define SUPC_WUIR_WKUPT12_LOW (SUPC_WUIR_WKUPT12_LOW_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 557 #define SUPC_WUIR_WKUPT12_HIGH (SUPC_WUIR_WKUPT12_HIGH_Val << SUPC_WUIR_WKUPT12_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 558 #define SUPC_WUIR_WKUPT13_Pos 29 /**< (SUPC_WUIR) Wakeup Input Type 0 to 13 Position */ 559 #define SUPC_WUIR_WKUPT13_Msk (_U_(0x1) << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) Wakeup Input Type 0 to 13 Mask */ 560 #define SUPC_WUIR_WKUPT13 SUPC_WUIR_WKUPT13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_WUIR_WKUPT13_Msk instead */ 561 #define SUPC_WUIR_WKUPT13_LOW_Val _U_(0x0) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. */ 562 #define SUPC_WUIR_WKUPT13_HIGH_Val _U_(0x1) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. */ 563 #define SUPC_WUIR_WKUPT13_LOW (SUPC_WUIR_WKUPT13_LOW_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wakeup input forces the wakeup of the core power supply. Position */ 564 #define SUPC_WUIR_WKUPT13_HIGH (SUPC_WUIR_WKUPT13_HIGH_Val << SUPC_WUIR_WKUPT13_Pos) /**< (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wakeup input forces the wakeup of the core power supply. Position */ 565 #define SUPC_WUIR_MASK _U_(0x3FFF3FFF) /**< \deprecated (SUPC_WUIR) Register MASK (Use SUPC_WUIR_Msk instead) */ 566 #define SUPC_WUIR_Msk _U_(0x3FFF3FFF) /**< (SUPC_WUIR) Register Mask */ 567 568 #define SUPC_WUIR_WKUPEN_Pos 0 /**< (SUPC_WUIR Position) Wakeup Input Enable x to x */ 569 #define SUPC_WUIR_WKUPEN_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPEN_Pos) /**< (SUPC_WUIR Mask) WKUPEN */ 570 #define SUPC_WUIR_WKUPEN(value) (SUPC_WUIR_WKUPEN_Msk & ((value) << SUPC_WUIR_WKUPEN_Pos)) 571 #define SUPC_WUIR_WKUPT_Pos 16 /**< (SUPC_WUIR Position) Wakeup Input Type x to x3 */ 572 #define SUPC_WUIR_WKUPT_Msk (_U_(0x3FFF) << SUPC_WUIR_WKUPT_Pos) /**< (SUPC_WUIR Mask) WKUPT */ 573 #define SUPC_WUIR_WKUPT(value) (SUPC_WUIR_WKUPT_Msk & ((value) << SUPC_WUIR_WKUPT_Pos)) 574 575 /* -------- SUPC_SR : (SUPC Offset: 0x14) (R/ 32) Supply Controller Status Register -------- */ 576 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 577 #if COMPONENT_TYPEDEF_STYLE == 'N' 578 typedef union { 579 struct { 580 uint32_t :1; /**< bit: 0 Reserved */ 581 uint32_t WKUPS:1; /**< bit: 1 WKUP Wakeup Status (cleared on read) */ 582 uint32_t SMWS:1; /**< bit: 2 Supply Monitor Detection Wakeup Status (cleared on read) */ 583 uint32_t BODRSTS:1; /**< bit: 3 Brownout Detector Reset Status (cleared on read) */ 584 uint32_t SMRSTS:1; /**< bit: 4 Supply Monitor Reset Status (cleared on read) */ 585 uint32_t SMS:1; /**< bit: 5 Supply Monitor Status (cleared on read) */ 586 uint32_t SMOS:1; /**< bit: 6 Supply Monitor Output Status */ 587 uint32_t OSCSEL:1; /**< bit: 7 32-kHz Oscillator Selection Status */ 588 uint32_t :5; /**< bit: 8..12 Reserved */ 589 uint32_t LPDBCS0:1; /**< bit: 13 Low-power Debouncer Wakeup Status on WKUP0 (cleared on read) */ 590 uint32_t LPDBCS1:1; /**< bit: 14 Low-power Debouncer Wakeup Status on WKUP1 (cleared on read) */ 591 uint32_t :1; /**< bit: 15 Reserved */ 592 uint32_t WKUPIS0:1; /**< bit: 16 WKUPx Input Status (cleared on read) */ 593 uint32_t WKUPIS1:1; /**< bit: 17 WKUPx Input Status (cleared on read) */ 594 uint32_t WKUPIS2:1; /**< bit: 18 WKUPx Input Status (cleared on read) */ 595 uint32_t WKUPIS3:1; /**< bit: 19 WKUPx Input Status (cleared on read) */ 596 uint32_t WKUPIS4:1; /**< bit: 20 WKUPx Input Status (cleared on read) */ 597 uint32_t WKUPIS5:1; /**< bit: 21 WKUPx Input Status (cleared on read) */ 598 uint32_t WKUPIS6:1; /**< bit: 22 WKUPx Input Status (cleared on read) */ 599 uint32_t WKUPIS7:1; /**< bit: 23 WKUPx Input Status (cleared on read) */ 600 uint32_t WKUPIS8:1; /**< bit: 24 WKUPx Input Status (cleared on read) */ 601 uint32_t WKUPIS9:1; /**< bit: 25 WKUPx Input Status (cleared on read) */ 602 uint32_t WKUPIS10:1; /**< bit: 26 WKUPx Input Status (cleared on read) */ 603 uint32_t WKUPIS11:1; /**< bit: 27 WKUPx Input Status (cleared on read) */ 604 uint32_t WKUPIS12:1; /**< bit: 28 WKUPx Input Status (cleared on read) */ 605 uint32_t WKUPIS13:1; /**< bit: 29 WKUPx Input Status (cleared on read) */ 606 uint32_t :2; /**< bit: 30..31 Reserved */ 607 } bit; /**< Structure used for bit access */ 608 struct { 609 uint32_t :13; /**< bit: 0..12 Reserved */ 610 uint32_t LPDBCS:2; /**< bit: 13..14 Low-power Debouncer Wakeup Status on WKUPx (cleared on read) */ 611 uint32_t :1; /**< bit: 15 Reserved */ 612 uint32_t WKUPIS:14; /**< bit: 16..29 WKUPx Input Status (cleared on read) */ 613 uint32_t :2; /**< bit: 30..31 Reserved */ 614 } vec; /**< Structure used for vec access */ 615 uint32_t reg; /**< Type used for register access */ 616 } SUPC_SR_Type; 617 #endif 618 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 619 620 #define SUPC_SR_OFFSET (0x14) /**< (SUPC_SR) Supply Controller Status Register Offset */ 621 622 #define SUPC_SR_WKUPS_Pos 1 /**< (SUPC_SR) WKUP Wakeup Status (cleared on read) Position */ 623 #define SUPC_SR_WKUPS_Msk (_U_(0x1) << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) WKUP Wakeup Status (cleared on read) Mask */ 624 #define SUPC_SR_WKUPS SUPC_SR_WKUPS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPS_Msk instead */ 625 #define SUPC_SR_WKUPS_NO_Val _U_(0x0) /**< (SUPC_SR) No wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ 626 #define SUPC_SR_WKUPS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ 627 #define SUPC_SR_WKUPS_NO (SUPC_SR_WKUPS_NO_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) No wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */ 628 #define SUPC_SR_WKUPS_PRESENT (SUPC_SR_WKUPS_PRESENT_Val << SUPC_SR_WKUPS_Pos) /**< (SUPC_SR) At least one wakeup due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. Position */ 629 #define SUPC_SR_SMWS_Pos 2 /**< (SUPC_SR) Supply Monitor Detection Wakeup Status (cleared on read) Position */ 630 #define SUPC_SR_SMWS_Msk (_U_(0x1) << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) Supply Monitor Detection Wakeup Status (cleared on read) Mask */ 631 #define SUPC_SR_SMWS SUPC_SR_SMWS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMWS_Msk instead */ 632 #define SUPC_SR_SMWS_NO_Val _U_(0x0) /**< (SUPC_SR) No wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR. */ 633 #define SUPC_SR_SMWS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR. */ 634 #define SUPC_SR_SMWS_NO (SUPC_SR_SMWS_NO_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) No wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */ 635 #define SUPC_SR_SMWS_PRESENT (SUPC_SR_SMWS_PRESENT_Val << SUPC_SR_SMWS_Pos) /**< (SUPC_SR) At least one wakeup due to a supply monitor detection has occurred since the last read of SUPC_SR. Position */ 636 #define SUPC_SR_BODRSTS_Pos 3 /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Position */ 637 #define SUPC_SR_BODRSTS_Msk (_U_(0x1) << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) Brownout Detector Reset Status (cleared on read) Mask */ 638 #define SUPC_SR_BODRSTS SUPC_SR_BODRSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_BODRSTS_Msk instead */ 639 #define SUPC_SR_BODRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ 640 #define SUPC_SR_BODRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ 641 #define SUPC_SR_BODRSTS_NO (SUPC_SR_BODRSTS_NO_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. Position */ 642 #define SUPC_SR_BODRSTS_PRESENT (SUPC_SR_BODRSTS_PRESENT_Val << SUPC_SR_BODRSTS_Pos) /**< (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. Position */ 643 #define SUPC_SR_SMRSTS_Pos 4 /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Position */ 644 #define SUPC_SR_SMRSTS_Msk (_U_(0x1) << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) Supply Monitor Reset Status (cleared on read) Mask */ 645 #define SUPC_SR_SMRSTS SUPC_SR_SMRSTS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMRSTS_Msk instead */ 646 #define SUPC_SR_SMRSTS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ 647 #define SUPC_SR_SMRSTS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ 648 #define SUPC_SR_SMRSTS_NO (SUPC_SR_SMRSTS_NO_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */ 649 #define SUPC_SR_SMRSTS_PRESENT (SUPC_SR_SMRSTS_PRESENT_Val << SUPC_SR_SMRSTS_Pos) /**< (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. Position */ 650 #define SUPC_SR_SMS_Pos 5 /**< (SUPC_SR) Supply Monitor Status (cleared on read) Position */ 651 #define SUPC_SR_SMS_Msk (_U_(0x1) << SUPC_SR_SMS_Pos) /**< (SUPC_SR) Supply Monitor Status (cleared on read) Mask */ 652 #define SUPC_SR_SMS SUPC_SR_SMS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMS_Msk instead */ 653 #define SUPC_SR_SMS_NO_Val _U_(0x0) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ 654 #define SUPC_SR_SMS_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ 655 #define SUPC_SR_SMS_NO (SUPC_SR_SMS_NO_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. Position */ 656 #define SUPC_SR_SMS_PRESENT (SUPC_SR_SMS_PRESENT_Val << SUPC_SR_SMS_Pos) /**< (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. Position */ 657 #define SUPC_SR_SMOS_Pos 6 /**< (SUPC_SR) Supply Monitor Output Status Position */ 658 #define SUPC_SR_SMOS_Msk (_U_(0x1) << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) Supply Monitor Output Status Mask */ 659 #define SUPC_SR_SMOS SUPC_SR_SMOS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_SMOS_Msk instead */ 660 #define SUPC_SR_SMOS_HIGH_Val _U_(0x0) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ 661 #define SUPC_SR_SMOS_LOW_Val _U_(0x1) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ 662 #define SUPC_SR_SMOS_HIGH (SUPC_SR_SMOS_HIGH_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. Position */ 663 #define SUPC_SR_SMOS_LOW (SUPC_SR_SMOS_LOW_Val << SUPC_SR_SMOS_Pos) /**< (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. Position */ 664 #define SUPC_SR_OSCSEL_Pos 7 /**< (SUPC_SR) 32-kHz Oscillator Selection Status Position */ 665 #define SUPC_SR_OSCSEL_Msk (_U_(0x1) << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) 32-kHz Oscillator Selection Status Mask */ 666 #define SUPC_SR_OSCSEL SUPC_SR_OSCSEL_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_OSCSEL_Msk instead */ 667 #define SUPC_SR_OSCSEL_RC_Val _U_(0x0) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ 668 #define SUPC_SR_OSCSEL_CRYST_Val _U_(0x1) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ 669 #define SUPC_SR_OSCSEL_RC (SUPC_SR_OSCSEL_RC_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. Position */ 670 #define SUPC_SR_OSCSEL_CRYST (SUPC_SR_OSCSEL_CRYST_Val << SUPC_SR_OSCSEL_Pos) /**< (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. Position */ 671 #define SUPC_SR_LPDBCS0_Pos 13 /**< (SUPC_SR) Low-power Debouncer Wakeup Status on WKUP0 (cleared on read) Position */ 672 #define SUPC_SR_LPDBCS0_Msk (_U_(0x1) << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) Low-power Debouncer Wakeup Status on WKUP0 (cleared on read) Mask */ 673 #define SUPC_SR_LPDBCS0 SUPC_SR_LPDBCS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_LPDBCS0_Msk instead */ 674 #define SUPC_SR_LPDBCS0_NO_Val _U_(0x0) /**< (SUPC_SR) No wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ 675 #define SUPC_SR_LPDBCS0_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ 676 #define SUPC_SR_LPDBCS0_NO (SUPC_SR_LPDBCS0_NO_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) No wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */ 677 #define SUPC_SR_LPDBCS0_PRESENT (SUPC_SR_LPDBCS0_PRESENT_Val << SUPC_SR_LPDBCS0_Pos) /**< (SUPC_SR) At least one wakeup due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. Position */ 678 #define SUPC_SR_LPDBCS1_Pos 14 /**< (SUPC_SR) Low-power Debouncer Wakeup Status on WKUP1 (cleared on read) Position */ 679 #define SUPC_SR_LPDBCS1_Msk (_U_(0x1) << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) Low-power Debouncer Wakeup Status on WKUP1 (cleared on read) Mask */ 680 #define SUPC_SR_LPDBCS1 SUPC_SR_LPDBCS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_LPDBCS1_Msk instead */ 681 #define SUPC_SR_LPDBCS1_NO_Val _U_(0x0) /**< (SUPC_SR) No wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ 682 #define SUPC_SR_LPDBCS1_PRESENT_Val _U_(0x1) /**< (SUPC_SR) At least one wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ 683 #define SUPC_SR_LPDBCS1_NO (SUPC_SR_LPDBCS1_NO_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) No wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */ 684 #define SUPC_SR_LPDBCS1_PRESENT (SUPC_SR_LPDBCS1_PRESENT_Val << SUPC_SR_LPDBCS1_Pos) /**< (SUPC_SR) At least one wakeup due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. Position */ 685 #define SUPC_SR_WKUPIS0_Pos 16 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 686 #define SUPC_SR_WKUPIS0_Msk (_U_(0x1) << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 687 #define SUPC_SR_WKUPIS0 SUPC_SR_WKUPIS0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS0_Msk instead */ 688 #define SUPC_SR_WKUPIS0_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 689 #define SUPC_SR_WKUPIS0_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 690 #define SUPC_SR_WKUPIS0_DIS (SUPC_SR_WKUPIS0_DIS_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 691 #define SUPC_SR_WKUPIS0_EN (SUPC_SR_WKUPIS0_EN_Val << SUPC_SR_WKUPIS0_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 692 #define SUPC_SR_WKUPIS1_Pos 17 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 693 #define SUPC_SR_WKUPIS1_Msk (_U_(0x1) << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 694 #define SUPC_SR_WKUPIS1 SUPC_SR_WKUPIS1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS1_Msk instead */ 695 #define SUPC_SR_WKUPIS1_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 696 #define SUPC_SR_WKUPIS1_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 697 #define SUPC_SR_WKUPIS1_DIS (SUPC_SR_WKUPIS1_DIS_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 698 #define SUPC_SR_WKUPIS1_EN (SUPC_SR_WKUPIS1_EN_Val << SUPC_SR_WKUPIS1_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 699 #define SUPC_SR_WKUPIS2_Pos 18 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 700 #define SUPC_SR_WKUPIS2_Msk (_U_(0x1) << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 701 #define SUPC_SR_WKUPIS2 SUPC_SR_WKUPIS2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS2_Msk instead */ 702 #define SUPC_SR_WKUPIS2_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 703 #define SUPC_SR_WKUPIS2_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 704 #define SUPC_SR_WKUPIS2_DIS (SUPC_SR_WKUPIS2_DIS_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 705 #define SUPC_SR_WKUPIS2_EN (SUPC_SR_WKUPIS2_EN_Val << SUPC_SR_WKUPIS2_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 706 #define SUPC_SR_WKUPIS3_Pos 19 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 707 #define SUPC_SR_WKUPIS3_Msk (_U_(0x1) << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 708 #define SUPC_SR_WKUPIS3 SUPC_SR_WKUPIS3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS3_Msk instead */ 709 #define SUPC_SR_WKUPIS3_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 710 #define SUPC_SR_WKUPIS3_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 711 #define SUPC_SR_WKUPIS3_DIS (SUPC_SR_WKUPIS3_DIS_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 712 #define SUPC_SR_WKUPIS3_EN (SUPC_SR_WKUPIS3_EN_Val << SUPC_SR_WKUPIS3_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 713 #define SUPC_SR_WKUPIS4_Pos 20 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 714 #define SUPC_SR_WKUPIS4_Msk (_U_(0x1) << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 715 #define SUPC_SR_WKUPIS4 SUPC_SR_WKUPIS4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS4_Msk instead */ 716 #define SUPC_SR_WKUPIS4_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 717 #define SUPC_SR_WKUPIS4_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 718 #define SUPC_SR_WKUPIS4_DIS (SUPC_SR_WKUPIS4_DIS_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 719 #define SUPC_SR_WKUPIS4_EN (SUPC_SR_WKUPIS4_EN_Val << SUPC_SR_WKUPIS4_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 720 #define SUPC_SR_WKUPIS5_Pos 21 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 721 #define SUPC_SR_WKUPIS5_Msk (_U_(0x1) << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 722 #define SUPC_SR_WKUPIS5 SUPC_SR_WKUPIS5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS5_Msk instead */ 723 #define SUPC_SR_WKUPIS5_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 724 #define SUPC_SR_WKUPIS5_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 725 #define SUPC_SR_WKUPIS5_DIS (SUPC_SR_WKUPIS5_DIS_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 726 #define SUPC_SR_WKUPIS5_EN (SUPC_SR_WKUPIS5_EN_Val << SUPC_SR_WKUPIS5_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 727 #define SUPC_SR_WKUPIS6_Pos 22 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 728 #define SUPC_SR_WKUPIS6_Msk (_U_(0x1) << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 729 #define SUPC_SR_WKUPIS6 SUPC_SR_WKUPIS6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS6_Msk instead */ 730 #define SUPC_SR_WKUPIS6_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 731 #define SUPC_SR_WKUPIS6_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 732 #define SUPC_SR_WKUPIS6_DIS (SUPC_SR_WKUPIS6_DIS_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 733 #define SUPC_SR_WKUPIS6_EN (SUPC_SR_WKUPIS6_EN_Val << SUPC_SR_WKUPIS6_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 734 #define SUPC_SR_WKUPIS7_Pos 23 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 735 #define SUPC_SR_WKUPIS7_Msk (_U_(0x1) << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 736 #define SUPC_SR_WKUPIS7 SUPC_SR_WKUPIS7_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS7_Msk instead */ 737 #define SUPC_SR_WKUPIS7_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 738 #define SUPC_SR_WKUPIS7_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 739 #define SUPC_SR_WKUPIS7_DIS (SUPC_SR_WKUPIS7_DIS_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 740 #define SUPC_SR_WKUPIS7_EN (SUPC_SR_WKUPIS7_EN_Val << SUPC_SR_WKUPIS7_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 741 #define SUPC_SR_WKUPIS8_Pos 24 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 742 #define SUPC_SR_WKUPIS8_Msk (_U_(0x1) << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 743 #define SUPC_SR_WKUPIS8 SUPC_SR_WKUPIS8_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS8_Msk instead */ 744 #define SUPC_SR_WKUPIS8_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 745 #define SUPC_SR_WKUPIS8_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 746 #define SUPC_SR_WKUPIS8_DIS (SUPC_SR_WKUPIS8_DIS_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 747 #define SUPC_SR_WKUPIS8_EN (SUPC_SR_WKUPIS8_EN_Val << SUPC_SR_WKUPIS8_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 748 #define SUPC_SR_WKUPIS9_Pos 25 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 749 #define SUPC_SR_WKUPIS9_Msk (_U_(0x1) << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 750 #define SUPC_SR_WKUPIS9 SUPC_SR_WKUPIS9_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS9_Msk instead */ 751 #define SUPC_SR_WKUPIS9_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 752 #define SUPC_SR_WKUPIS9_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 753 #define SUPC_SR_WKUPIS9_DIS (SUPC_SR_WKUPIS9_DIS_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 754 #define SUPC_SR_WKUPIS9_EN (SUPC_SR_WKUPIS9_EN_Val << SUPC_SR_WKUPIS9_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 755 #define SUPC_SR_WKUPIS10_Pos 26 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 756 #define SUPC_SR_WKUPIS10_Msk (_U_(0x1) << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 757 #define SUPC_SR_WKUPIS10 SUPC_SR_WKUPIS10_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS10_Msk instead */ 758 #define SUPC_SR_WKUPIS10_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 759 #define SUPC_SR_WKUPIS10_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 760 #define SUPC_SR_WKUPIS10_DIS (SUPC_SR_WKUPIS10_DIS_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 761 #define SUPC_SR_WKUPIS10_EN (SUPC_SR_WKUPIS10_EN_Val << SUPC_SR_WKUPIS10_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 762 #define SUPC_SR_WKUPIS11_Pos 27 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 763 #define SUPC_SR_WKUPIS11_Msk (_U_(0x1) << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 764 #define SUPC_SR_WKUPIS11 SUPC_SR_WKUPIS11_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS11_Msk instead */ 765 #define SUPC_SR_WKUPIS11_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 766 #define SUPC_SR_WKUPIS11_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 767 #define SUPC_SR_WKUPIS11_DIS (SUPC_SR_WKUPIS11_DIS_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 768 #define SUPC_SR_WKUPIS11_EN (SUPC_SR_WKUPIS11_EN_Val << SUPC_SR_WKUPIS11_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 769 #define SUPC_SR_WKUPIS12_Pos 28 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 770 #define SUPC_SR_WKUPIS12_Msk (_U_(0x1) << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 771 #define SUPC_SR_WKUPIS12 SUPC_SR_WKUPIS12_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS12_Msk instead */ 772 #define SUPC_SR_WKUPIS12_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 773 #define SUPC_SR_WKUPIS12_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 774 #define SUPC_SR_WKUPIS12_DIS (SUPC_SR_WKUPIS12_DIS_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 775 #define SUPC_SR_WKUPIS12_EN (SUPC_SR_WKUPIS12_EN_Val << SUPC_SR_WKUPIS12_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 776 #define SUPC_SR_WKUPIS13_Pos 29 /**< (SUPC_SR) WKUPx Input Status (cleared on read) Position */ 777 #define SUPC_SR_WKUPIS13_Msk (_U_(0x1) << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) WKUPx Input Status (cleared on read) Mask */ 778 #define SUPC_SR_WKUPIS13 SUPC_SR_WKUPIS13_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SUPC_SR_WKUPIS13_Msk instead */ 779 #define SUPC_SR_WKUPIS13_DIS_Val _U_(0x0) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. */ 780 #define SUPC_SR_WKUPIS13_EN_Val _U_(0x1) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. */ 781 #define SUPC_SR_WKUPIS13_DIS (SUPC_SR_WKUPIS13_DIS_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wakeup input is disabled, or was inactive at the time the debouncer triggered a wakeup event. Position */ 782 #define SUPC_SR_WKUPIS13_EN (SUPC_SR_WKUPIS13_EN_Val << SUPC_SR_WKUPIS13_Pos) /**< (SUPC_SR) The corresponding wakeup input was active at the time the debouncer triggered a wakeup event since the last read of SUPC_SR. Position */ 783 #define SUPC_SR_MASK _U_(0x3FFF60FE) /**< \deprecated (SUPC_SR) Register MASK (Use SUPC_SR_Msk instead) */ 784 #define SUPC_SR_Msk _U_(0x3FFF60FE) /**< (SUPC_SR) Register Mask */ 785 786 #define SUPC_SR_LPDBCS_Pos 13 /**< (SUPC_SR Position) Low-power Debouncer Wakeup Status on WKUPx (cleared on read) */ 787 #define SUPC_SR_LPDBCS_Msk (_U_(0x3) << SUPC_SR_LPDBCS_Pos) /**< (SUPC_SR Mask) LPDBCS */ 788 #define SUPC_SR_LPDBCS(value) (SUPC_SR_LPDBCS_Msk & ((value) << SUPC_SR_LPDBCS_Pos)) 789 #define SUPC_SR_WKUPIS_Pos 16 /**< (SUPC_SR Position) WKUPx Input Status (cleared on read) */ 790 #define SUPC_SR_WKUPIS_Msk (_U_(0x3FFF) << SUPC_SR_WKUPIS_Pos) /**< (SUPC_SR Mask) WKUPIS */ 791 #define SUPC_SR_WKUPIS(value) (SUPC_SR_WKUPIS_Msk & ((value) << SUPC_SR_WKUPIS_Pos)) 792 793 /* -------- SYSC_VERSION : (SUPC Offset: 0xfc) (R/ 32) Version Register -------- */ 794 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 795 #if COMPONENT_TYPEDEF_STYLE == 'N' 796 typedef union { 797 struct { 798 uint32_t VERSION:12; /**< bit: 0..11 Version of the Hardware Module */ 799 uint32_t :4; /**< bit: 12..15 Reserved */ 800 uint32_t MFN:3; /**< bit: 16..18 Metal Fix Number */ 801 uint32_t :13; /**< bit: 19..31 Reserved */ 802 } bit; /**< Structure used for bit access */ 803 uint32_t reg; /**< Type used for register access */ 804 } SYSC_VERSION_Type; 805 #endif 806 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 807 808 #define SYSC_VERSION_OFFSET (0xFC) /**< (SYSC_VERSION) Version Register Offset */ 809 810 #define SYSC_VERSION_VERSION_Pos 0 /**< (SYSC_VERSION) Version of the Hardware Module Position */ 811 #define SYSC_VERSION_VERSION_Msk (_U_(0xFFF) << SYSC_VERSION_VERSION_Pos) /**< (SYSC_VERSION) Version of the Hardware Module Mask */ 812 #define SYSC_VERSION_VERSION(value) (SYSC_VERSION_VERSION_Msk & ((value) << SYSC_VERSION_VERSION_Pos)) 813 #define SYSC_VERSION_MFN_Pos 16 /**< (SYSC_VERSION) Metal Fix Number Position */ 814 #define SYSC_VERSION_MFN_Msk (_U_(0x7) << SYSC_VERSION_MFN_Pos) /**< (SYSC_VERSION) Metal Fix Number Mask */ 815 #define SYSC_VERSION_MFN(value) (SYSC_VERSION_MFN_Msk & ((value) << SYSC_VERSION_MFN_Pos)) 816 #define SYSC_VERSION_MASK _U_(0x70FFF) /**< \deprecated (SYSC_VERSION) Register MASK (Use SYSC_VERSION_Msk instead) */ 817 #define SYSC_VERSION_Msk _U_(0x70FFF) /**< (SYSC_VERSION) Register Mask */ 818 819 820 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 821 #if COMPONENT_TYPEDEF_STYLE == 'R' 822 /** \brief SUPC hardware registers */ 823 typedef struct { 824 __O uint32_t SUPC_CR; /**< (SUPC Offset: 0x00) Supply Controller Control Register */ 825 __IO uint32_t SUPC_SMMR; /**< (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register */ 826 __IO uint32_t SUPC_MR; /**< (SUPC Offset: 0x08) Supply Controller Mode Register */ 827 __IO uint32_t SUPC_WUMR; /**< (SUPC Offset: 0x0C) Supply Controller Wakeup Mode Register */ 828 __IO uint32_t SUPC_WUIR; /**< (SUPC Offset: 0x10) Supply Controller Wakeup Inputs Register */ 829 __I uint32_t SUPC_SR; /**< (SUPC Offset: 0x14) Supply Controller Status Register */ 830 __I uint8_t Reserved1[228]; 831 __I uint32_t SYSC_VERSION; /**< (SUPC Offset: 0xFC) Version Register */ 832 } Supc; 833 834 #elif COMPONENT_TYPEDEF_STYLE == 'N' 835 /** \brief SUPC hardware registers */ 836 typedef struct { 837 __O SUPC_CR_Type SUPC_CR; /**< Offset: 0x00 ( /W 32) Supply Controller Control Register */ 838 __IO SUPC_SMMR_Type SUPC_SMMR; /**< Offset: 0x04 (R/W 32) Supply Controller Supply Monitor Mode Register */ 839 __IO SUPC_MR_Type SUPC_MR; /**< Offset: 0x08 (R/W 32) Supply Controller Mode Register */ 840 __IO SUPC_WUMR_Type SUPC_WUMR; /**< Offset: 0x0C (R/W 32) Supply Controller Wakeup Mode Register */ 841 __IO SUPC_WUIR_Type SUPC_WUIR; /**< Offset: 0x10 (R/W 32) Supply Controller Wakeup Inputs Register */ 842 __I SUPC_SR_Type SUPC_SR; /**< Offset: 0x14 (R/ 32) Supply Controller Status Register */ 843 __I uint8_t Reserved1[228]; 844 __I SYSC_VERSION_Type SYSC_VERSION; /**< Offset: 0xFC (R/ 32) Version Register */ 845 } Supc; 846 847 #else /* COMPONENT_TYPEDEF_STYLE */ 848 #error Unknown component typedef style 849 #endif /* COMPONENT_TYPEDEF_STYLE */ 850 851 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 852 /** @} end of Supply Controller */ 853 854 #endif /* _SAMV71_SUPC_COMPONENT_H_ */ 855
