1 /** 2 * \file 3 * 4 * \brief Component description for RSWDT 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_RSWDT_COMPONENT_H_ 32 #define _SAMV71_RSWDT_COMPONENT_H_ 33 #define _SAMV71_RSWDT_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Reinforced Safety Watchdog Timer 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR RSWDT */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define RSWDT_11110 /**< (RSWDT) Module ID */ 46 #define REV_RSWDT E /**< (RSWDT) Module revision */ 47 48 /* -------- RSWDT_CR : (RSWDT Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t WDRSTT:1; /**< bit: 0 Watchdog Restart */ 54 uint32_t :23; /**< bit: 1..23 Reserved */ 55 uint32_t KEY:8; /**< bit: 24..31 Password */ 56 } bit; /**< Structure used for bit access */ 57 uint32_t reg; /**< Type used for register access */ 58 } RSWDT_CR_Type; 59 #endif 60 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 61 62 #define RSWDT_CR_OFFSET (0x00) /**< (RSWDT_CR) Control Register Offset */ 63 64 #define RSWDT_CR_WDRSTT_Pos 0 /**< (RSWDT_CR) Watchdog Restart Position */ 65 #define RSWDT_CR_WDRSTT_Msk (_U_(0x1) << RSWDT_CR_WDRSTT_Pos) /**< (RSWDT_CR) Watchdog Restart Mask */ 66 #define RSWDT_CR_WDRSTT RSWDT_CR_WDRSTT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_CR_WDRSTT_Msk instead */ 67 #define RSWDT_CR_KEY_Pos 24 /**< (RSWDT_CR) Password Position */ 68 #define RSWDT_CR_KEY_Msk (_U_(0xFF) << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Password Mask */ 69 #define RSWDT_CR_KEY(value) (RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos)) 70 #define RSWDT_CR_KEY_PASSWD_Val _U_(0xC4) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. */ 71 #define RSWDT_CR_KEY_PASSWD (RSWDT_CR_KEY_PASSWD_Val << RSWDT_CR_KEY_Pos) /**< (RSWDT_CR) Writing any other value in this field aborts the write operation. Position */ 72 #define RSWDT_CR_MASK _U_(0xFF000001) /**< \deprecated (RSWDT_CR) Register MASK (Use RSWDT_CR_Msk instead) */ 73 #define RSWDT_CR_Msk _U_(0xFF000001) /**< (RSWDT_CR) Register Mask */ 74 75 76 /* -------- RSWDT_MR : (RSWDT Offset: 0x04) (R/W 32) Mode Register -------- */ 77 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 78 #if COMPONENT_TYPEDEF_STYLE == 'N' 79 typedef union { 80 struct { 81 uint32_t WDV:12; /**< bit: 0..11 Watchdog Counter Value */ 82 uint32_t WDFIEN:1; /**< bit: 12 Watchdog Fault Interrupt Enable */ 83 uint32_t WDRSTEN:1; /**< bit: 13 Watchdog Reset Enable */ 84 uint32_t :1; /**< bit: 14 Reserved */ 85 uint32_t WDDIS:1; /**< bit: 15 Watchdog Disable */ 86 uint32_t ALLONES:12; /**< bit: 16..27 Must Always Be Written with 0xFFF */ 87 uint32_t WDDBGHLT:1; /**< bit: 28 Watchdog Debug Halt */ 88 uint32_t WDIDLEHLT:1; /**< bit: 29 Watchdog Idle Halt */ 89 uint32_t :2; /**< bit: 30..31 Reserved */ 90 } bit; /**< Structure used for bit access */ 91 uint32_t reg; /**< Type used for register access */ 92 } RSWDT_MR_Type; 93 #endif 94 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 96 #define RSWDT_MR_OFFSET (0x04) /**< (RSWDT_MR) Mode Register Offset */ 97 98 #define RSWDT_MR_WDV_Pos 0 /**< (RSWDT_MR) Watchdog Counter Value Position */ 99 #define RSWDT_MR_WDV_Msk (_U_(0xFFF) << RSWDT_MR_WDV_Pos) /**< (RSWDT_MR) Watchdog Counter Value Mask */ 100 #define RSWDT_MR_WDV(value) (RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos)) 101 #define RSWDT_MR_WDFIEN_Pos 12 /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Position */ 102 #define RSWDT_MR_WDFIEN_Msk (_U_(0x1) << RSWDT_MR_WDFIEN_Pos) /**< (RSWDT_MR) Watchdog Fault Interrupt Enable Mask */ 103 #define RSWDT_MR_WDFIEN RSWDT_MR_WDFIEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDFIEN_Msk instead */ 104 #define RSWDT_MR_WDRSTEN_Pos 13 /**< (RSWDT_MR) Watchdog Reset Enable Position */ 105 #define RSWDT_MR_WDRSTEN_Msk (_U_(0x1) << RSWDT_MR_WDRSTEN_Pos) /**< (RSWDT_MR) Watchdog Reset Enable Mask */ 106 #define RSWDT_MR_WDRSTEN RSWDT_MR_WDRSTEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDRSTEN_Msk instead */ 107 #define RSWDT_MR_WDDIS_Pos 15 /**< (RSWDT_MR) Watchdog Disable Position */ 108 #define RSWDT_MR_WDDIS_Msk (_U_(0x1) << RSWDT_MR_WDDIS_Pos) /**< (RSWDT_MR) Watchdog Disable Mask */ 109 #define RSWDT_MR_WDDIS RSWDT_MR_WDDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDDIS_Msk instead */ 110 #define RSWDT_MR_ALLONES_Pos 16 /**< (RSWDT_MR) Must Always Be Written with 0xFFF Position */ 111 #define RSWDT_MR_ALLONES_Msk (_U_(0xFFF) << RSWDT_MR_ALLONES_Pos) /**< (RSWDT_MR) Must Always Be Written with 0xFFF Mask */ 112 #define RSWDT_MR_ALLONES(value) (RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos)) 113 #define RSWDT_MR_WDDBGHLT_Pos 28 /**< (RSWDT_MR) Watchdog Debug Halt Position */ 114 #define RSWDT_MR_WDDBGHLT_Msk (_U_(0x1) << RSWDT_MR_WDDBGHLT_Pos) /**< (RSWDT_MR) Watchdog Debug Halt Mask */ 115 #define RSWDT_MR_WDDBGHLT RSWDT_MR_WDDBGHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDDBGHLT_Msk instead */ 116 #define RSWDT_MR_WDIDLEHLT_Pos 29 /**< (RSWDT_MR) Watchdog Idle Halt Position */ 117 #define RSWDT_MR_WDIDLEHLT_Msk (_U_(0x1) << RSWDT_MR_WDIDLEHLT_Pos) /**< (RSWDT_MR) Watchdog Idle Halt Mask */ 118 #define RSWDT_MR_WDIDLEHLT RSWDT_MR_WDIDLEHLT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_MR_WDIDLEHLT_Msk instead */ 119 #define RSWDT_MR_MASK _U_(0x3FFFBFFF) /**< \deprecated (RSWDT_MR) Register MASK (Use RSWDT_MR_Msk instead) */ 120 #define RSWDT_MR_Msk _U_(0x3FFFBFFF) /**< (RSWDT_MR) Register Mask */ 121 122 123 /* -------- RSWDT_SR : (RSWDT Offset: 0x08) (R/ 32) Status Register -------- */ 124 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 125 #if COMPONENT_TYPEDEF_STYLE == 'N' 126 typedef union { 127 struct { 128 uint32_t WDUNF:1; /**< bit: 0 Watchdog Underflow */ 129 uint32_t :31; /**< bit: 1..31 Reserved */ 130 } bit; /**< Structure used for bit access */ 131 uint32_t reg; /**< Type used for register access */ 132 } RSWDT_SR_Type; 133 #endif 134 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 135 136 #define RSWDT_SR_OFFSET (0x08) /**< (RSWDT_SR) Status Register Offset */ 137 138 #define RSWDT_SR_WDUNF_Pos 0 /**< (RSWDT_SR) Watchdog Underflow Position */ 139 #define RSWDT_SR_WDUNF_Msk (_U_(0x1) << RSWDT_SR_WDUNF_Pos) /**< (RSWDT_SR) Watchdog Underflow Mask */ 140 #define RSWDT_SR_WDUNF RSWDT_SR_WDUNF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use RSWDT_SR_WDUNF_Msk instead */ 141 #define RSWDT_SR_MASK _U_(0x01) /**< \deprecated (RSWDT_SR) Register MASK (Use RSWDT_SR_Msk instead) */ 142 #define RSWDT_SR_Msk _U_(0x01) /**< (RSWDT_SR) Register Mask */ 143 144 145 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 146 #if COMPONENT_TYPEDEF_STYLE == 'R' 147 /** \brief RSWDT hardware registers */ 148 typedef struct { 149 __O uint32_t RSWDT_CR; /**< (RSWDT Offset: 0x00) Control Register */ 150 __IO uint32_t RSWDT_MR; /**< (RSWDT Offset: 0x04) Mode Register */ 151 __I uint32_t RSWDT_SR; /**< (RSWDT Offset: 0x08) Status Register */ 152 } Rswdt; 153 154 #elif COMPONENT_TYPEDEF_STYLE == 'N' 155 /** \brief RSWDT hardware registers */ 156 typedef struct { 157 __O RSWDT_CR_Type RSWDT_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 158 __IO RSWDT_MR_Type RSWDT_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 159 __I RSWDT_SR_Type RSWDT_SR; /**< Offset: 0x08 (R/ 32) Status Register */ 160 } Rswdt; 161 162 #else /* COMPONENT_TYPEDEF_STYLE */ 163 #error Unknown component typedef style 164 #endif /* COMPONENT_TYPEDEF_STYLE */ 165 166 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 167 /** @} end of Reinforced Safety Watchdog Timer */ 168 169 #endif /* _SAMV71_RSWDT_COMPONENT_H_ */ 170
