1 /** 2 * \file 3 * 4 * \brief Component description for AES 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2017-01-08T14:00:00Z */ 31 #ifndef _SAMV71_AES_COMPONENT_H_ 32 #define _SAMV71_AES_COMPONENT_H_ 33 #define _SAMV71_AES_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAMV_SAMV71 Advanced Encryption Standard 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR AES */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define AES_6149 /**< (AES) Module ID */ 46 #define REV_AES U /**< (AES) Module revision */ 47 48 /* -------- AES_CR : (AES Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t START:1; /**< bit: 0 Start Processing */ 54 uint32_t :7; /**< bit: 1..7 Reserved */ 55 uint32_t SWRST:1; /**< bit: 8 Software Reset */ 56 uint32_t :7; /**< bit: 9..15 Reserved */ 57 uint32_t LOADSEED:1; /**< bit: 16 Random Number Generator Seed Loading */ 58 uint32_t :15; /**< bit: 17..31 Reserved */ 59 } bit; /**< Structure used for bit access */ 60 uint32_t reg; /**< Type used for register access */ 61 } AES_CR_Type; 62 #endif 63 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 #define AES_CR_OFFSET (0x00) /**< (AES_CR) Control Register Offset */ 66 67 #define AES_CR_START_Pos 0 /**< (AES_CR) Start Processing Position */ 68 #define AES_CR_START_Msk (_U_(0x1) << AES_CR_START_Pos) /**< (AES_CR) Start Processing Mask */ 69 #define AES_CR_START AES_CR_START_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_START_Msk instead */ 70 #define AES_CR_SWRST_Pos 8 /**< (AES_CR) Software Reset Position */ 71 #define AES_CR_SWRST_Msk (_U_(0x1) << AES_CR_SWRST_Pos) /**< (AES_CR) Software Reset Mask */ 72 #define AES_CR_SWRST AES_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_SWRST_Msk instead */ 73 #define AES_CR_LOADSEED_Pos 16 /**< (AES_CR) Random Number Generator Seed Loading Position */ 74 #define AES_CR_LOADSEED_Msk (_U_(0x1) << AES_CR_LOADSEED_Pos) /**< (AES_CR) Random Number Generator Seed Loading Mask */ 75 #define AES_CR_LOADSEED AES_CR_LOADSEED_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_CR_LOADSEED_Msk instead */ 76 #define AES_CR_MASK _U_(0x10101) /**< \deprecated (AES_CR) Register MASK (Use AES_CR_Msk instead) */ 77 #define AES_CR_Msk _U_(0x10101) /**< (AES_CR) Register Mask */ 78 79 80 /* -------- AES_MR : (AES Offset: 0x04) (R/W 32) Mode Register -------- */ 81 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 82 #if COMPONENT_TYPEDEF_STYLE == 'N' 83 typedef union { 84 struct { 85 uint32_t CIPHER:1; /**< bit: 0 Processing Mode */ 86 uint32_t GTAGEN:1; /**< bit: 1 GCM Automatic Tag Generation Enable */ 87 uint32_t :1; /**< bit: 2 Reserved */ 88 uint32_t DUALBUFF:1; /**< bit: 3 Dual Input Buffer */ 89 uint32_t PROCDLY:4; /**< bit: 4..7 Processing Delay */ 90 uint32_t SMOD:2; /**< bit: 8..9 Start Mode */ 91 uint32_t KEYSIZE:2; /**< bit: 10..11 Key Size */ 92 uint32_t OPMOD:3; /**< bit: 12..14 Operating Mode */ 93 uint32_t LOD:1; /**< bit: 15 Last Output Data Mode */ 94 uint32_t CFBS:3; /**< bit: 16..18 Cipher Feedback Data Size */ 95 uint32_t :1; /**< bit: 19 Reserved */ 96 uint32_t CKEY:4; /**< bit: 20..23 Countermeasure Key */ 97 uint32_t CMTYP1:1; /**< bit: 24 Countermeasure Type 1 */ 98 uint32_t CMTYP2:1; /**< bit: 25 Countermeasure Type 2 */ 99 uint32_t CMTYP3:1; /**< bit: 26 Countermeasure Type 3 */ 100 uint32_t CMTYP4:1; /**< bit: 27 Countermeasure Type 4 */ 101 uint32_t CMTYP5:1; /**< bit: 28 Countermeasure Type 5 */ 102 uint32_t CMTYP6:1; /**< bit: 29 Countermeasure Type 6 */ 103 uint32_t :2; /**< bit: 30..31 Reserved */ 104 } bit; /**< Structure used for bit access */ 105 struct { 106 uint32_t :24; /**< bit: 0..23 Reserved */ 107 uint32_t CMTYP:6; /**< bit: 24..29 Countermeasure Type 6 */ 108 uint32_t :2; /**< bit: 30..31 Reserved */ 109 } vec; /**< Structure used for vec access */ 110 uint32_t reg; /**< Type used for register access */ 111 } AES_MR_Type; 112 #endif 113 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 114 115 #define AES_MR_OFFSET (0x04) /**< (AES_MR) Mode Register Offset */ 116 117 #define AES_MR_CIPHER_Pos 0 /**< (AES_MR) Processing Mode Position */ 118 #define AES_MR_CIPHER_Msk (_U_(0x1) << AES_MR_CIPHER_Pos) /**< (AES_MR) Processing Mode Mask */ 119 #define AES_MR_CIPHER AES_MR_CIPHER_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CIPHER_Msk instead */ 120 #define AES_MR_GTAGEN_Pos 1 /**< (AES_MR) GCM Automatic Tag Generation Enable Position */ 121 #define AES_MR_GTAGEN_Msk (_U_(0x1) << AES_MR_GTAGEN_Pos) /**< (AES_MR) GCM Automatic Tag Generation Enable Mask */ 122 #define AES_MR_GTAGEN AES_MR_GTAGEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_GTAGEN_Msk instead */ 123 #define AES_MR_DUALBUFF_Pos 3 /**< (AES_MR) Dual Input Buffer Position */ 124 #define AES_MR_DUALBUFF_Msk (_U_(0x1) << AES_MR_DUALBUFF_Pos) /**< (AES_MR) Dual Input Buffer Mask */ 125 #define AES_MR_DUALBUFF AES_MR_DUALBUFF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_DUALBUFF_Msk instead */ 126 #define AES_MR_DUALBUFF_INACTIVE_Val _U_(0x0) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ 127 #define AES_MR_DUALBUFF_ACTIVE_Val _U_(0x1) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */ 128 #define AES_MR_DUALBUFF_INACTIVE (AES_MR_DUALBUFF_INACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. Position */ 129 #define AES_MR_DUALBUFF_ACTIVE (AES_MR_DUALBUFF_ACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. Position */ 130 #define AES_MR_PROCDLY_Pos 4 /**< (AES_MR) Processing Delay Position */ 131 #define AES_MR_PROCDLY_Msk (_U_(0xF) << AES_MR_PROCDLY_Pos) /**< (AES_MR) Processing Delay Mask */ 132 #define AES_MR_PROCDLY(value) (AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos)) 133 #define AES_MR_SMOD_Pos 8 /**< (AES_MR) Start Mode Position */ 134 #define AES_MR_SMOD_Msk (_U_(0x3) << AES_MR_SMOD_Pos) /**< (AES_MR) Start Mode Mask */ 135 #define AES_MR_SMOD(value) (AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos)) 136 #define AES_MR_SMOD_MANUAL_START_Val _U_(0x0) /**< (AES_MR) Manual Mode */ 137 #define AES_MR_SMOD_AUTO_START_Val _U_(0x1) /**< (AES_MR) Auto Mode */ 138 #define AES_MR_SMOD_IDATAR0_START_Val _U_(0x2) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ 139 #define AES_MR_SMOD_MANUAL_START (AES_MR_SMOD_MANUAL_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Manual Mode Position */ 140 #define AES_MR_SMOD_AUTO_START (AES_MR_SMOD_AUTO_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Auto Mode Position */ 141 #define AES_MR_SMOD_IDATAR0_START (AES_MR_SMOD_IDATAR0_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) Position */ 142 #define AES_MR_KEYSIZE_Pos 10 /**< (AES_MR) Key Size Position */ 143 #define AES_MR_KEYSIZE_Msk (_U_(0x3) << AES_MR_KEYSIZE_Pos) /**< (AES_MR) Key Size Mask */ 144 #define AES_MR_KEYSIZE(value) (AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos)) 145 #define AES_MR_KEYSIZE_AES128_Val _U_(0x0) /**< (AES_MR) AES Key Size is 128 bits */ 146 #define AES_MR_KEYSIZE_AES192_Val _U_(0x1) /**< (AES_MR) AES Key Size is 192 bits */ 147 #define AES_MR_KEYSIZE_AES256_Val _U_(0x2) /**< (AES_MR) AES Key Size is 256 bits */ 148 #define AES_MR_KEYSIZE_AES128 (AES_MR_KEYSIZE_AES128_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 128 bits Position */ 149 #define AES_MR_KEYSIZE_AES192 (AES_MR_KEYSIZE_AES192_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 192 bits Position */ 150 #define AES_MR_KEYSIZE_AES256 (AES_MR_KEYSIZE_AES256_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 256 bits Position */ 151 #define AES_MR_OPMOD_Pos 12 /**< (AES_MR) Operating Mode Position */ 152 #define AES_MR_OPMOD_Msk (_U_(0x7) << AES_MR_OPMOD_Pos) /**< (AES_MR) Operating Mode Mask */ 153 #define AES_MR_OPMOD(value) (AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos)) 154 #define AES_MR_OPMOD_ECB_Val _U_(0x0) /**< (AES_MR) ECB: Electronic Code Book mode */ 155 #define AES_MR_OPMOD_CBC_Val _U_(0x1) /**< (AES_MR) CBC: Cipher Block Chaining mode */ 156 #define AES_MR_OPMOD_OFB_Val _U_(0x2) /**< (AES_MR) OFB: Output Feedback mode */ 157 #define AES_MR_OPMOD_CFB_Val _U_(0x3) /**< (AES_MR) CFB: Cipher Feedback mode */ 158 #define AES_MR_OPMOD_CTR_Val _U_(0x4) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) */ 159 #define AES_MR_OPMOD_GCM_Val _U_(0x5) /**< (AES_MR) GCM: Galois/Counter mode */ 160 #define AES_MR_OPMOD_ECB (AES_MR_OPMOD_ECB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) ECB: Electronic Code Book mode Position */ 161 #define AES_MR_OPMOD_CBC (AES_MR_OPMOD_CBC_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CBC: Cipher Block Chaining mode Position */ 162 #define AES_MR_OPMOD_OFB (AES_MR_OPMOD_OFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) OFB: Output Feedback mode Position */ 163 #define AES_MR_OPMOD_CFB (AES_MR_OPMOD_CFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CFB: Cipher Feedback mode Position */ 164 #define AES_MR_OPMOD_CTR (AES_MR_OPMOD_CTR_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) Position */ 165 #define AES_MR_OPMOD_GCM (AES_MR_OPMOD_GCM_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) GCM: Galois/Counter mode Position */ 166 #define AES_MR_LOD_Pos 15 /**< (AES_MR) Last Output Data Mode Position */ 167 #define AES_MR_LOD_Msk (_U_(0x1) << AES_MR_LOD_Pos) /**< (AES_MR) Last Output Data Mode Mask */ 168 #define AES_MR_LOD AES_MR_LOD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_LOD_Msk instead */ 169 #define AES_MR_CFBS_Pos 16 /**< (AES_MR) Cipher Feedback Data Size Position */ 170 #define AES_MR_CFBS_Msk (_U_(0x7) << AES_MR_CFBS_Pos) /**< (AES_MR) Cipher Feedback Data Size Mask */ 171 #define AES_MR_CFBS(value) (AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos)) 172 #define AES_MR_CFBS_SIZE_128BIT_Val _U_(0x0) /**< (AES_MR) 128-bit */ 173 #define AES_MR_CFBS_SIZE_64BIT_Val _U_(0x1) /**< (AES_MR) 64-bit */ 174 #define AES_MR_CFBS_SIZE_32BIT_Val _U_(0x2) /**< (AES_MR) 32-bit */ 175 #define AES_MR_CFBS_SIZE_16BIT_Val _U_(0x3) /**< (AES_MR) 16-bit */ 176 #define AES_MR_CFBS_SIZE_8BIT_Val _U_(0x4) /**< (AES_MR) 8-bit */ 177 #define AES_MR_CFBS_SIZE_128BIT (AES_MR_CFBS_SIZE_128BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 128-bit Position */ 178 #define AES_MR_CFBS_SIZE_64BIT (AES_MR_CFBS_SIZE_64BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 64-bit Position */ 179 #define AES_MR_CFBS_SIZE_32BIT (AES_MR_CFBS_SIZE_32BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 32-bit Position */ 180 #define AES_MR_CFBS_SIZE_16BIT (AES_MR_CFBS_SIZE_16BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 16-bit Position */ 181 #define AES_MR_CFBS_SIZE_8BIT (AES_MR_CFBS_SIZE_8BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 8-bit Position */ 182 #define AES_MR_CKEY_Pos 20 /**< (AES_MR) Countermeasure Key Position */ 183 #define AES_MR_CKEY_Msk (_U_(0xF) << AES_MR_CKEY_Pos) /**< (AES_MR) Countermeasure Key Mask */ 184 #define AES_MR_CKEY(value) (AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos)) 185 #define AES_MR_CKEY_PASSWD_Val _U_(0xE) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */ 186 #define AES_MR_CKEY_PASSWD (AES_MR_CKEY_PASSWD_Val << AES_MR_CKEY_Pos) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. Position */ 187 #define AES_MR_CMTYP1_Pos 24 /**< (AES_MR) Countermeasure Type 1 Position */ 188 #define AES_MR_CMTYP1_Msk (_U_(0x1) << AES_MR_CMTYP1_Pos) /**< (AES_MR) Countermeasure Type 1 Mask */ 189 #define AES_MR_CMTYP1 AES_MR_CMTYP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CMTYP1_Msk instead */ 190 #define AES_MR_CMTYP1_NOPROT_EXTKEY_Val _U_(0x0) /**< (AES_MR) Countermeasure type 1 is disabled. */ 191 #define AES_MR_CMTYP1_PROT_EXTKEY_Val _U_(0x1) /**< (AES_MR) Countermeasure type 1 is enabled. */ 192 #define AES_MR_CMTYP1_NOPROT_EXTKEY (AES_MR_CMTYP1_NOPROT_EXTKEY_Val << AES_MR_CMTYP1_Pos) /**< (AES_MR) Countermeasure type 1 is disabled. Position */ 193 #define AES_MR_CMTYP1_PROT_EXTKEY (AES_MR_CMTYP1_PROT_EXTKEY_Val << AES_MR_CMTYP1_Pos) /**< (AES_MR) Countermeasure type 1 is enabled. Position */ 194 #define AES_MR_CMTYP2_Pos 25 /**< (AES_MR) Countermeasure Type 2 Position */ 195 #define AES_MR_CMTYP2_Msk (_U_(0x1) << AES_MR_CMTYP2_Pos) /**< (AES_MR) Countermeasure Type 2 Mask */ 196 #define AES_MR_CMTYP2 AES_MR_CMTYP2_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CMTYP2_Msk instead */ 197 #define AES_MR_CMTYP2_NO_PAUSE_Val _U_(0x0) /**< (AES_MR) Countermeasure type 2 is disabled. */ 198 #define AES_MR_CMTYP2_PAUSE_Val _U_(0x1) /**< (AES_MR) Countermeasure type 2 is enabled. */ 199 #define AES_MR_CMTYP2_NO_PAUSE (AES_MR_CMTYP2_NO_PAUSE_Val << AES_MR_CMTYP2_Pos) /**< (AES_MR) Countermeasure type 2 is disabled. Position */ 200 #define AES_MR_CMTYP2_PAUSE (AES_MR_CMTYP2_PAUSE_Val << AES_MR_CMTYP2_Pos) /**< (AES_MR) Countermeasure type 2 is enabled. Position */ 201 #define AES_MR_CMTYP3_Pos 26 /**< (AES_MR) Countermeasure Type 3 Position */ 202 #define AES_MR_CMTYP3_Msk (_U_(0x1) << AES_MR_CMTYP3_Pos) /**< (AES_MR) Countermeasure Type 3 Mask */ 203 #define AES_MR_CMTYP3 AES_MR_CMTYP3_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CMTYP3_Msk instead */ 204 #define AES_MR_CMTYP3_NO_DUMMY_Val _U_(0x0) /**< (AES_MR) Countermeasure type 3 is disabled. */ 205 #define AES_MR_CMTYP3_DUMMY_Val _U_(0x1) /**< (AES_MR) Countermeasure type 3 is enabled. */ 206 #define AES_MR_CMTYP3_NO_DUMMY (AES_MR_CMTYP3_NO_DUMMY_Val << AES_MR_CMTYP3_Pos) /**< (AES_MR) Countermeasure type 3 is disabled. Position */ 207 #define AES_MR_CMTYP3_DUMMY (AES_MR_CMTYP3_DUMMY_Val << AES_MR_CMTYP3_Pos) /**< (AES_MR) Countermeasure type 3 is enabled. Position */ 208 #define AES_MR_CMTYP4_Pos 27 /**< (AES_MR) Countermeasure Type 4 Position */ 209 #define AES_MR_CMTYP4_Msk (_U_(0x1) << AES_MR_CMTYP4_Pos) /**< (AES_MR) Countermeasure Type 4 Mask */ 210 #define AES_MR_CMTYP4 AES_MR_CMTYP4_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CMTYP4_Msk instead */ 211 #define AES_MR_CMTYP4_NO_RESTART_Val _U_(0x0) /**< (AES_MR) Countermeasure type 4 is disabled. */ 212 #define AES_MR_CMTYP4_RESTART_Val _U_(0x1) /**< (AES_MR) Countermeasure type 4 is enabled. */ 213 #define AES_MR_CMTYP4_NO_RESTART (AES_MR_CMTYP4_NO_RESTART_Val << AES_MR_CMTYP4_Pos) /**< (AES_MR) Countermeasure type 4 is disabled. Position */ 214 #define AES_MR_CMTYP4_RESTART (AES_MR_CMTYP4_RESTART_Val << AES_MR_CMTYP4_Pos) /**< (AES_MR) Countermeasure type 4 is enabled. Position */ 215 #define AES_MR_CMTYP5_Pos 28 /**< (AES_MR) Countermeasure Type 5 Position */ 216 #define AES_MR_CMTYP5_Msk (_U_(0x1) << AES_MR_CMTYP5_Pos) /**< (AES_MR) Countermeasure Type 5 Mask */ 217 #define AES_MR_CMTYP5 AES_MR_CMTYP5_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CMTYP5_Msk instead */ 218 #define AES_MR_CMTYP5_NO_ADDACCESS_Val _U_(0x0) /**< (AES_MR) Countermeasure type 5 is disabled. */ 219 #define AES_MR_CMTYP5_ADDACCESS_Val _U_(0x1) /**< (AES_MR) Countermeasure type 5 is enabled. */ 220 #define AES_MR_CMTYP5_NO_ADDACCESS (AES_MR_CMTYP5_NO_ADDACCESS_Val << AES_MR_CMTYP5_Pos) /**< (AES_MR) Countermeasure type 5 is disabled. Position */ 221 #define AES_MR_CMTYP5_ADDACCESS (AES_MR_CMTYP5_ADDACCESS_Val << AES_MR_CMTYP5_Pos) /**< (AES_MR) Countermeasure type 5 is enabled. Position */ 222 #define AES_MR_CMTYP6_Pos 29 /**< (AES_MR) Countermeasure Type 6 Position */ 223 #define AES_MR_CMTYP6_Msk (_U_(0x1) << AES_MR_CMTYP6_Pos) /**< (AES_MR) Countermeasure Type 6 Mask */ 224 #define AES_MR_CMTYP6 AES_MR_CMTYP6_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_MR_CMTYP6_Msk instead */ 225 #define AES_MR_CMTYP6_NO_IDLECURRENT_Val _U_(0x0) /**< (AES_MR) Countermeasure type 6 is disabled. */ 226 #define AES_MR_CMTYP6_IDLECURRENT_Val _U_(0x1) /**< (AES_MR) Countermeasure type 6 is enabled. */ 227 #define AES_MR_CMTYP6_NO_IDLECURRENT (AES_MR_CMTYP6_NO_IDLECURRENT_Val << AES_MR_CMTYP6_Pos) /**< (AES_MR) Countermeasure type 6 is disabled. Position */ 228 #define AES_MR_CMTYP6_IDLECURRENT (AES_MR_CMTYP6_IDLECURRENT_Val << AES_MR_CMTYP6_Pos) /**< (AES_MR) Countermeasure type 6 is enabled. Position */ 229 #define AES_MR_MASK _U_(0x3FF7FFFB) /**< \deprecated (AES_MR) Register MASK (Use AES_MR_Msk instead) */ 230 #define AES_MR_Msk _U_(0x3FF7FFFB) /**< (AES_MR) Register Mask */ 231 232 #define AES_MR_CMTYP_Pos 24 /**< (AES_MR Position) Countermeasure Type 6 */ 233 #define AES_MR_CMTYP_Msk (_U_(0x3F) << AES_MR_CMTYP_Pos) /**< (AES_MR Mask) CMTYP */ 234 #define AES_MR_CMTYP(value) (AES_MR_CMTYP_Msk & ((value) << AES_MR_CMTYP_Pos)) 235 236 /* -------- AES_IER : (AES Offset: 0x10) (/W 32) Interrupt Enable Register -------- */ 237 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 238 #if COMPONENT_TYPEDEF_STYLE == 'N' 239 typedef union { 240 struct { 241 uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Enable */ 242 uint32_t :7; /**< bit: 1..7 Reserved */ 243 uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Enable */ 244 uint32_t :7; /**< bit: 9..15 Reserved */ 245 uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Enable */ 246 uint32_t :15; /**< bit: 17..31 Reserved */ 247 } bit; /**< Structure used for bit access */ 248 uint32_t reg; /**< Type used for register access */ 249 } AES_IER_Type; 250 #endif 251 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 252 253 #define AES_IER_OFFSET (0x10) /**< (AES_IER) Interrupt Enable Register Offset */ 254 255 #define AES_IER_DATRDY_Pos 0 /**< (AES_IER) Data Ready Interrupt Enable Position */ 256 #define AES_IER_DATRDY_Msk (_U_(0x1) << AES_IER_DATRDY_Pos) /**< (AES_IER) Data Ready Interrupt Enable Mask */ 257 #define AES_IER_DATRDY AES_IER_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_DATRDY_Msk instead */ 258 #define AES_IER_URAD_Pos 8 /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Position */ 259 #define AES_IER_URAD_Msk (_U_(0x1) << AES_IER_URAD_Pos) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Mask */ 260 #define AES_IER_URAD AES_IER_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_URAD_Msk instead */ 261 #define AES_IER_TAGRDY_Pos 16 /**< (AES_IER) GCM Tag Ready Interrupt Enable Position */ 262 #define AES_IER_TAGRDY_Msk (_U_(0x1) << AES_IER_TAGRDY_Pos) /**< (AES_IER) GCM Tag Ready Interrupt Enable Mask */ 263 #define AES_IER_TAGRDY AES_IER_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IER_TAGRDY_Msk instead */ 264 #define AES_IER_MASK _U_(0x10101) /**< \deprecated (AES_IER) Register MASK (Use AES_IER_Msk instead) */ 265 #define AES_IER_Msk _U_(0x10101) /**< (AES_IER) Register Mask */ 266 267 268 /* -------- AES_IDR : (AES Offset: 0x14) (/W 32) Interrupt Disable Register -------- */ 269 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 270 #if COMPONENT_TYPEDEF_STYLE == 'N' 271 typedef union { 272 struct { 273 uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Disable */ 274 uint32_t :7; /**< bit: 1..7 Reserved */ 275 uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Disable */ 276 uint32_t :7; /**< bit: 9..15 Reserved */ 277 uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Disable */ 278 uint32_t :15; /**< bit: 17..31 Reserved */ 279 } bit; /**< Structure used for bit access */ 280 uint32_t reg; /**< Type used for register access */ 281 } AES_IDR_Type; 282 #endif 283 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 284 285 #define AES_IDR_OFFSET (0x14) /**< (AES_IDR) Interrupt Disable Register Offset */ 286 287 #define AES_IDR_DATRDY_Pos 0 /**< (AES_IDR) Data Ready Interrupt Disable Position */ 288 #define AES_IDR_DATRDY_Msk (_U_(0x1) << AES_IDR_DATRDY_Pos) /**< (AES_IDR) Data Ready Interrupt Disable Mask */ 289 #define AES_IDR_DATRDY AES_IDR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_DATRDY_Msk instead */ 290 #define AES_IDR_URAD_Pos 8 /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Position */ 291 #define AES_IDR_URAD_Msk (_U_(0x1) << AES_IDR_URAD_Pos) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Mask */ 292 #define AES_IDR_URAD AES_IDR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_URAD_Msk instead */ 293 #define AES_IDR_TAGRDY_Pos 16 /**< (AES_IDR) GCM Tag Ready Interrupt Disable Position */ 294 #define AES_IDR_TAGRDY_Msk (_U_(0x1) << AES_IDR_TAGRDY_Pos) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Mask */ 295 #define AES_IDR_TAGRDY AES_IDR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IDR_TAGRDY_Msk instead */ 296 #define AES_IDR_MASK _U_(0x10101) /**< \deprecated (AES_IDR) Register MASK (Use AES_IDR_Msk instead) */ 297 #define AES_IDR_Msk _U_(0x10101) /**< (AES_IDR) Register Mask */ 298 299 300 /* -------- AES_IMR : (AES Offset: 0x18) (R/ 32) Interrupt Mask Register -------- */ 301 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 302 #if COMPONENT_TYPEDEF_STYLE == 'N' 303 typedef union { 304 struct { 305 uint32_t DATRDY:1; /**< bit: 0 Data Ready Interrupt Mask */ 306 uint32_t :7; /**< bit: 1..7 Reserved */ 307 uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Interrupt Mask */ 308 uint32_t :7; /**< bit: 9..15 Reserved */ 309 uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready Interrupt Mask */ 310 uint32_t :15; /**< bit: 17..31 Reserved */ 311 } bit; /**< Structure used for bit access */ 312 uint32_t reg; /**< Type used for register access */ 313 } AES_IMR_Type; 314 #endif 315 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 316 317 #define AES_IMR_OFFSET (0x18) /**< (AES_IMR) Interrupt Mask Register Offset */ 318 319 #define AES_IMR_DATRDY_Pos 0 /**< (AES_IMR) Data Ready Interrupt Mask Position */ 320 #define AES_IMR_DATRDY_Msk (_U_(0x1) << AES_IMR_DATRDY_Pos) /**< (AES_IMR) Data Ready Interrupt Mask Mask */ 321 #define AES_IMR_DATRDY AES_IMR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_DATRDY_Msk instead */ 322 #define AES_IMR_URAD_Pos 8 /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Position */ 323 #define AES_IMR_URAD_Msk (_U_(0x1) << AES_IMR_URAD_Pos) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Mask */ 324 #define AES_IMR_URAD AES_IMR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_URAD_Msk instead */ 325 #define AES_IMR_TAGRDY_Pos 16 /**< (AES_IMR) GCM Tag Ready Interrupt Mask Position */ 326 #define AES_IMR_TAGRDY_Msk (_U_(0x1) << AES_IMR_TAGRDY_Pos) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Mask */ 327 #define AES_IMR_TAGRDY AES_IMR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_IMR_TAGRDY_Msk instead */ 328 #define AES_IMR_MASK _U_(0x10101) /**< \deprecated (AES_IMR) Register MASK (Use AES_IMR_Msk instead) */ 329 #define AES_IMR_Msk _U_(0x10101) /**< (AES_IMR) Register Mask */ 330 331 332 /* -------- AES_ISR : (AES Offset: 0x1c) (R/ 32) Interrupt Status Register -------- */ 333 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 334 #if COMPONENT_TYPEDEF_STYLE == 'N' 335 typedef union { 336 struct { 337 uint32_t DATRDY:1; /**< bit: 0 Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ 338 uint32_t :7; /**< bit: 1..7 Reserved */ 339 uint32_t URAD:1; /**< bit: 8 Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ 340 uint32_t :3; /**< bit: 9..11 Reserved */ 341 uint32_t URAT:4; /**< bit: 12..15 Unspecified Register Access (cleared by writing SWRST in AES_CR) */ 342 uint32_t TAGRDY:1; /**< bit: 16 GCM Tag Ready */ 343 uint32_t :15; /**< bit: 17..31 Reserved */ 344 } bit; /**< Structure used for bit access */ 345 uint32_t reg; /**< Type used for register access */ 346 } AES_ISR_Type; 347 #endif 348 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 349 350 #define AES_ISR_OFFSET (0x1C) /**< (AES_ISR) Interrupt Status Register Offset */ 351 352 #define AES_ISR_DATRDY_Pos 0 /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Position */ 353 #define AES_ISR_DATRDY_Msk (_U_(0x1) << AES_ISR_DATRDY_Pos) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Mask */ 354 #define AES_ISR_DATRDY AES_ISR_DATRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_DATRDY_Msk instead */ 355 #define AES_ISR_URAD_Pos 8 /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Position */ 356 #define AES_ISR_URAD_Msk (_U_(0x1) << AES_ISR_URAD_Pos) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Mask */ 357 #define AES_ISR_URAD AES_ISR_URAD_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_URAD_Msk instead */ 358 #define AES_ISR_URAT_Pos 12 /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Position */ 359 #define AES_ISR_URAT_Msk (_U_(0xF) << AES_ISR_URAT_Pos) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Mask */ 360 #define AES_ISR_URAT(value) (AES_ISR_URAT_Msk & ((value) << AES_ISR_URAT_Pos)) 361 #define AES_ISR_URAT_IDR_WR_PROCESSING_Val _U_(0x0) /**< (AES_ISR) Input Data register written during the data processing when SMOD = 0x2 mode. */ 362 #define AES_ISR_URAT_ODR_RD_PROCESSING_Val _U_(0x1) /**< (AES_ISR) Output Data register read during the data processing. */ 363 #define AES_ISR_URAT_MR_WR_PROCESSING_Val _U_(0x2) /**< (AES_ISR) Mode register written during the data processing. */ 364 #define AES_ISR_URAT_ODR_RD_SUBKGEN_Val _U_(0x3) /**< (AES_ISR) Output Data register read during the sub-keys generation. */ 365 #define AES_ISR_URAT_MR_WR_SUBKGEN_Val _U_(0x4) /**< (AES_ISR) Mode register written during the sub-keys generation. */ 366 #define AES_ISR_URAT_WOR_RD_ACCESS_Val _U_(0x5) /**< (AES_ISR) Write-only register read access. */ 367 #define AES_ISR_URAT_IDR_WR_PROCESSING (AES_ISR_URAT_IDR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Input Data register written during the data processing when SMOD = 0x2 mode. Position */ 368 #define AES_ISR_URAT_ODR_RD_PROCESSING (AES_ISR_URAT_ODR_RD_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data register read during the data processing. Position */ 369 #define AES_ISR_URAT_MR_WR_PROCESSING (AES_ISR_URAT_MR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode register written during the data processing. Position */ 370 #define AES_ISR_URAT_ODR_RD_SUBKGEN (AES_ISR_URAT_ODR_RD_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data register read during the sub-keys generation. Position */ 371 #define AES_ISR_URAT_MR_WR_SUBKGEN (AES_ISR_URAT_MR_WR_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode register written during the sub-keys generation. Position */ 372 #define AES_ISR_URAT_WOR_RD_ACCESS (AES_ISR_URAT_WOR_RD_ACCESS_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Write-only register read access. Position */ 373 #define AES_ISR_TAGRDY_Pos 16 /**< (AES_ISR) GCM Tag Ready Position */ 374 #define AES_ISR_TAGRDY_Msk (_U_(0x1) << AES_ISR_TAGRDY_Pos) /**< (AES_ISR) GCM Tag Ready Mask */ 375 #define AES_ISR_TAGRDY AES_ISR_TAGRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use AES_ISR_TAGRDY_Msk instead */ 376 #define AES_ISR_MASK _U_(0x1F101) /**< \deprecated (AES_ISR) Register MASK (Use AES_ISR_Msk instead) */ 377 #define AES_ISR_Msk _U_(0x1F101) /**< (AES_ISR) Register Mask */ 378 379 380 /* -------- AES_KEYWR : (AES Offset: 0x20) (/W 32) Key Word Register 0 -------- */ 381 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 382 #if COMPONENT_TYPEDEF_STYLE == 'N' 383 typedef union { 384 struct { 385 uint32_t KEYW:32; /**< bit: 0..31 Key Word */ 386 } bit; /**< Structure used for bit access */ 387 uint32_t reg; /**< Type used for register access */ 388 } AES_KEYWR_Type; 389 #endif 390 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 391 392 #define AES_KEYWR_OFFSET (0x20) /**< (AES_KEYWR) Key Word Register 0 Offset */ 393 394 #define AES_KEYWR_KEYW_Pos 0 /**< (AES_KEYWR) Key Word Position */ 395 #define AES_KEYWR_KEYW_Msk (_U_(0xFFFFFFFF) << AES_KEYWR_KEYW_Pos) /**< (AES_KEYWR) Key Word Mask */ 396 #define AES_KEYWR_KEYW(value) (AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos)) 397 #define AES_KEYWR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_KEYWR) Register MASK (Use AES_KEYWR_Msk instead) */ 398 #define AES_KEYWR_Msk _U_(0xFFFFFFFF) /**< (AES_KEYWR) Register Mask */ 399 400 401 /* -------- AES_IDATAR : (AES Offset: 0x40) (/W 32) Input Data Register 0 -------- */ 402 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 403 #if COMPONENT_TYPEDEF_STYLE == 'N' 404 typedef union { 405 struct { 406 uint32_t IDATA:32; /**< bit: 0..31 Input Data Word */ 407 } bit; /**< Structure used for bit access */ 408 uint32_t reg; /**< Type used for register access */ 409 } AES_IDATAR_Type; 410 #endif 411 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 412 413 #define AES_IDATAR_OFFSET (0x40) /**< (AES_IDATAR) Input Data Register 0 Offset */ 414 415 #define AES_IDATAR_IDATA_Pos 0 /**< (AES_IDATAR) Input Data Word Position */ 416 #define AES_IDATAR_IDATA_Msk (_U_(0xFFFFFFFF) << AES_IDATAR_IDATA_Pos) /**< (AES_IDATAR) Input Data Word Mask */ 417 #define AES_IDATAR_IDATA(value) (AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos)) 418 #define AES_IDATAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_IDATAR) Register MASK (Use AES_IDATAR_Msk instead) */ 419 #define AES_IDATAR_Msk _U_(0xFFFFFFFF) /**< (AES_IDATAR) Register Mask */ 420 421 422 /* -------- AES_ODATAR : (AES Offset: 0x50) (R/ 32) Output Data Register 0 -------- */ 423 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 424 #if COMPONENT_TYPEDEF_STYLE == 'N' 425 typedef union { 426 struct { 427 uint32_t ODATA:32; /**< bit: 0..31 Output Data */ 428 } bit; /**< Structure used for bit access */ 429 uint32_t reg; /**< Type used for register access */ 430 } AES_ODATAR_Type; 431 #endif 432 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 433 434 #define AES_ODATAR_OFFSET (0x50) /**< (AES_ODATAR) Output Data Register 0 Offset */ 435 436 #define AES_ODATAR_ODATA_Pos 0 /**< (AES_ODATAR) Output Data Position */ 437 #define AES_ODATAR_ODATA_Msk (_U_(0xFFFFFFFF) << AES_ODATAR_ODATA_Pos) /**< (AES_ODATAR) Output Data Mask */ 438 #define AES_ODATAR_ODATA(value) (AES_ODATAR_ODATA_Msk & ((value) << AES_ODATAR_ODATA_Pos)) 439 #define AES_ODATAR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_ODATAR) Register MASK (Use AES_ODATAR_Msk instead) */ 440 #define AES_ODATAR_Msk _U_(0xFFFFFFFF) /**< (AES_ODATAR) Register Mask */ 441 442 443 /* -------- AES_IVR : (AES Offset: 0x60) (/W 32) Initialization Vector Register 0 -------- */ 444 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 445 #if COMPONENT_TYPEDEF_STYLE == 'N' 446 typedef union { 447 struct { 448 uint32_t IV:32; /**< bit: 0..31 Initialization Vector */ 449 } bit; /**< Structure used for bit access */ 450 uint32_t reg; /**< Type used for register access */ 451 } AES_IVR_Type; 452 #endif 453 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 454 455 #define AES_IVR_OFFSET (0x60) /**< (AES_IVR) Initialization Vector Register 0 Offset */ 456 457 #define AES_IVR_IV_Pos 0 /**< (AES_IVR) Initialization Vector Position */ 458 #define AES_IVR_IV_Msk (_U_(0xFFFFFFFF) << AES_IVR_IV_Pos) /**< (AES_IVR) Initialization Vector Mask */ 459 #define AES_IVR_IV(value) (AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos)) 460 #define AES_IVR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_IVR) Register MASK (Use AES_IVR_Msk instead) */ 461 #define AES_IVR_Msk _U_(0xFFFFFFFF) /**< (AES_IVR) Register Mask */ 462 463 464 /* -------- AES_AADLENR : (AES Offset: 0x70) (R/W 32) Additional Authenticated Data Length Register -------- */ 465 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 466 #if COMPONENT_TYPEDEF_STYLE == 'N' 467 typedef union { 468 struct { 469 uint32_t AADLEN:32; /**< bit: 0..31 Additional Authenticated Data Length */ 470 } bit; /**< Structure used for bit access */ 471 uint32_t reg; /**< Type used for register access */ 472 } AES_AADLENR_Type; 473 #endif 474 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 475 476 #define AES_AADLENR_OFFSET (0x70) /**< (AES_AADLENR) Additional Authenticated Data Length Register Offset */ 477 478 #define AES_AADLENR_AADLEN_Pos 0 /**< (AES_AADLENR) Additional Authenticated Data Length Position */ 479 #define AES_AADLENR_AADLEN_Msk (_U_(0xFFFFFFFF) << AES_AADLENR_AADLEN_Pos) /**< (AES_AADLENR) Additional Authenticated Data Length Mask */ 480 #define AES_AADLENR_AADLEN(value) (AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos)) 481 #define AES_AADLENR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_AADLENR) Register MASK (Use AES_AADLENR_Msk instead) */ 482 #define AES_AADLENR_Msk _U_(0xFFFFFFFF) /**< (AES_AADLENR) Register Mask */ 483 484 485 /* -------- AES_CLENR : (AES Offset: 0x74) (R/W 32) Plaintext/Ciphertext Length Register -------- */ 486 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 487 #if COMPONENT_TYPEDEF_STYLE == 'N' 488 typedef union { 489 struct { 490 uint32_t CLEN:32; /**< bit: 0..31 Plaintext/Ciphertext Length */ 491 } bit; /**< Structure used for bit access */ 492 uint32_t reg; /**< Type used for register access */ 493 } AES_CLENR_Type; 494 #endif 495 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 496 497 #define AES_CLENR_OFFSET (0x74) /**< (AES_CLENR) Plaintext/Ciphertext Length Register Offset */ 498 499 #define AES_CLENR_CLEN_Pos 0 /**< (AES_CLENR) Plaintext/Ciphertext Length Position */ 500 #define AES_CLENR_CLEN_Msk (_U_(0xFFFFFFFF) << AES_CLENR_CLEN_Pos) /**< (AES_CLENR) Plaintext/Ciphertext Length Mask */ 501 #define AES_CLENR_CLEN(value) (AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos)) 502 #define AES_CLENR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_CLENR) Register MASK (Use AES_CLENR_Msk instead) */ 503 #define AES_CLENR_Msk _U_(0xFFFFFFFF) /**< (AES_CLENR) Register Mask */ 504 505 506 /* -------- AES_GHASHR : (AES Offset: 0x78) (R/W 32) GCM Intermediate Hash Word Register 0 -------- */ 507 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 508 #if COMPONENT_TYPEDEF_STYLE == 'N' 509 typedef union { 510 struct { 511 uint32_t GHASH:32; /**< bit: 0..31 Intermediate GCM Hash Word x */ 512 } bit; /**< Structure used for bit access */ 513 uint32_t reg; /**< Type used for register access */ 514 } AES_GHASHR_Type; 515 #endif 516 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 517 518 #define AES_GHASHR_OFFSET (0x78) /**< (AES_GHASHR) GCM Intermediate Hash Word Register 0 Offset */ 519 520 #define AES_GHASHR_GHASH_Pos 0 /**< (AES_GHASHR) Intermediate GCM Hash Word x Position */ 521 #define AES_GHASHR_GHASH_Msk (_U_(0xFFFFFFFF) << AES_GHASHR_GHASH_Pos) /**< (AES_GHASHR) Intermediate GCM Hash Word x Mask */ 522 #define AES_GHASHR_GHASH(value) (AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos)) 523 #define AES_GHASHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_GHASHR) Register MASK (Use AES_GHASHR_Msk instead) */ 524 #define AES_GHASHR_Msk _U_(0xFFFFFFFF) /**< (AES_GHASHR) Register Mask */ 525 526 527 /* -------- AES_TAGR : (AES Offset: 0x88) (R/ 32) GCM Authentication Tag Word Register 0 -------- */ 528 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 529 #if COMPONENT_TYPEDEF_STYLE == 'N' 530 typedef union { 531 struct { 532 uint32_t TAG:32; /**< bit: 0..31 GCM Authentication Tag x */ 533 } bit; /**< Structure used for bit access */ 534 uint32_t reg; /**< Type used for register access */ 535 } AES_TAGR_Type; 536 #endif 537 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 538 539 #define AES_TAGR_OFFSET (0x88) /**< (AES_TAGR) GCM Authentication Tag Word Register 0 Offset */ 540 541 #define AES_TAGR_TAG_Pos 0 /**< (AES_TAGR) GCM Authentication Tag x Position */ 542 #define AES_TAGR_TAG_Msk (_U_(0xFFFFFFFF) << AES_TAGR_TAG_Pos) /**< (AES_TAGR) GCM Authentication Tag x Mask */ 543 #define AES_TAGR_TAG(value) (AES_TAGR_TAG_Msk & ((value) << AES_TAGR_TAG_Pos)) 544 #define AES_TAGR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_TAGR) Register MASK (Use AES_TAGR_Msk instead) */ 545 #define AES_TAGR_Msk _U_(0xFFFFFFFF) /**< (AES_TAGR) Register Mask */ 546 547 548 /* -------- AES_CTRR : (AES Offset: 0x98) (R/ 32) GCM Encryption Counter Value Register -------- */ 549 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 550 #if COMPONENT_TYPEDEF_STYLE == 'N' 551 typedef union { 552 struct { 553 uint32_t CTR:32; /**< bit: 0..31 GCM Encryption Counter */ 554 } bit; /**< Structure used for bit access */ 555 uint32_t reg; /**< Type used for register access */ 556 } AES_CTRR_Type; 557 #endif 558 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 559 560 #define AES_CTRR_OFFSET (0x98) /**< (AES_CTRR) GCM Encryption Counter Value Register Offset */ 561 562 #define AES_CTRR_CTR_Pos 0 /**< (AES_CTRR) GCM Encryption Counter Position */ 563 #define AES_CTRR_CTR_Msk (_U_(0xFFFFFFFF) << AES_CTRR_CTR_Pos) /**< (AES_CTRR) GCM Encryption Counter Mask */ 564 #define AES_CTRR_CTR(value) (AES_CTRR_CTR_Msk & ((value) << AES_CTRR_CTR_Pos)) 565 #define AES_CTRR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_CTRR) Register MASK (Use AES_CTRR_Msk instead) */ 566 #define AES_CTRR_Msk _U_(0xFFFFFFFF) /**< (AES_CTRR) Register Mask */ 567 568 569 /* -------- AES_GCMHR : (AES Offset: 0x9c) (R/W 32) GCM H Word Register 0 -------- */ 570 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 571 #if COMPONENT_TYPEDEF_STYLE == 'N' 572 typedef union { 573 struct { 574 uint32_t H:32; /**< bit: 0..31 GCM H Word x */ 575 } bit; /**< Structure used for bit access */ 576 uint32_t reg; /**< Type used for register access */ 577 } AES_GCMHR_Type; 578 #endif 579 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 580 581 #define AES_GCMHR_OFFSET (0x9C) /**< (AES_GCMHR) GCM H Word Register 0 Offset */ 582 583 #define AES_GCMHR_H_Pos 0 /**< (AES_GCMHR) GCM H Word x Position */ 584 #define AES_GCMHR_H_Msk (_U_(0xFFFFFFFF) << AES_GCMHR_H_Pos) /**< (AES_GCMHR) GCM H Word x Mask */ 585 #define AES_GCMHR_H(value) (AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos)) 586 #define AES_GCMHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (AES_GCMHR) Register MASK (Use AES_GCMHR_Msk instead) */ 587 #define AES_GCMHR_Msk _U_(0xFFFFFFFF) /**< (AES_GCMHR) Register Mask */ 588 589 590 /* -------- AES_VERSION : (AES Offset: 0xfc) (R/ 32) Version Register -------- */ 591 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 592 #if COMPONENT_TYPEDEF_STYLE == 'N' 593 typedef union { 594 struct { 595 uint32_t VERSION:12; /**< bit: 0..11 Version of the Hardware Module */ 596 uint32_t :4; /**< bit: 12..15 Reserved */ 597 uint32_t MFN:3; /**< bit: 16..18 Metal Fix Number */ 598 uint32_t :13; /**< bit: 19..31 Reserved */ 599 } bit; /**< Structure used for bit access */ 600 uint32_t reg; /**< Type used for register access */ 601 } AES_VERSION_Type; 602 #endif 603 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 604 605 #define AES_VERSION_OFFSET (0xFC) /**< (AES_VERSION) Version Register Offset */ 606 607 #define AES_VERSION_VERSION_Pos 0 /**< (AES_VERSION) Version of the Hardware Module Position */ 608 #define AES_VERSION_VERSION_Msk (_U_(0xFFF) << AES_VERSION_VERSION_Pos) /**< (AES_VERSION) Version of the Hardware Module Mask */ 609 #define AES_VERSION_VERSION(value) (AES_VERSION_VERSION_Msk & ((value) << AES_VERSION_VERSION_Pos)) 610 #define AES_VERSION_MFN_Pos 16 /**< (AES_VERSION) Metal Fix Number Position */ 611 #define AES_VERSION_MFN_Msk (_U_(0x7) << AES_VERSION_MFN_Pos) /**< (AES_VERSION) Metal Fix Number Mask */ 612 #define AES_VERSION_MFN(value) (AES_VERSION_MFN_Msk & ((value) << AES_VERSION_MFN_Pos)) 613 #define AES_VERSION_MASK _U_(0x70FFF) /**< \deprecated (AES_VERSION) Register MASK (Use AES_VERSION_Msk instead) */ 614 #define AES_VERSION_Msk _U_(0x70FFF) /**< (AES_VERSION) Register Mask */ 615 616 617 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 618 #if COMPONENT_TYPEDEF_STYLE == 'R' 619 /** \brief AES hardware registers */ 620 typedef struct { 621 __O uint32_t AES_CR; /**< (AES Offset: 0x00) Control Register */ 622 __IO uint32_t AES_MR; /**< (AES Offset: 0x04) Mode Register */ 623 __I uint8_t Reserved1[8]; 624 __O uint32_t AES_IER; /**< (AES Offset: 0x10) Interrupt Enable Register */ 625 __O uint32_t AES_IDR; /**< (AES Offset: 0x14) Interrupt Disable Register */ 626 __I uint32_t AES_IMR; /**< (AES Offset: 0x18) Interrupt Mask Register */ 627 __I uint32_t AES_ISR; /**< (AES Offset: 0x1C) Interrupt Status Register */ 628 __O uint32_t AES_KEYWR[8]; /**< (AES Offset: 0x20) Key Word Register 0 */ 629 __O uint32_t AES_IDATAR[4]; /**< (AES Offset: 0x40) Input Data Register 0 */ 630 __I uint32_t AES_ODATAR[4]; /**< (AES Offset: 0x50) Output Data Register 0 */ 631 __O uint32_t AES_IVR[4]; /**< (AES Offset: 0x60) Initialization Vector Register 0 */ 632 __IO uint32_t AES_AADLENR; /**< (AES Offset: 0x70) Additional Authenticated Data Length Register */ 633 __IO uint32_t AES_CLENR; /**< (AES Offset: 0x74) Plaintext/Ciphertext Length Register */ 634 __IO uint32_t AES_GHASHR[4]; /**< (AES Offset: 0x78) GCM Intermediate Hash Word Register 0 */ 635 __I uint32_t AES_TAGR[4]; /**< (AES Offset: 0x88) GCM Authentication Tag Word Register 0 */ 636 __I uint32_t AES_CTRR; /**< (AES Offset: 0x98) GCM Encryption Counter Value Register */ 637 __IO uint32_t AES_GCMHR[4]; /**< (AES Offset: 0x9C) GCM H Word Register 0 */ 638 __I uint8_t Reserved2[80]; 639 __I uint32_t AES_VERSION; /**< (AES Offset: 0xFC) Version Register */ 640 } Aes; 641 642 #elif COMPONENT_TYPEDEF_STYLE == 'N' 643 /** \brief AES hardware registers */ 644 typedef struct { 645 __O AES_CR_Type AES_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 646 __IO AES_MR_Type AES_MR; /**< Offset: 0x04 (R/W 32) Mode Register */ 647 __I uint8_t Reserved1[8]; 648 __O AES_IER_Type AES_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */ 649 __O AES_IDR_Type AES_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */ 650 __I AES_IMR_Type AES_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */ 651 __I AES_ISR_Type AES_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */ 652 __O AES_KEYWR_Type AES_KEYWR[8]; /**< Offset: 0x20 ( /W 32) Key Word Register 0 */ 653 __O AES_IDATAR_Type AES_IDATAR[4]; /**< Offset: 0x40 ( /W 32) Input Data Register 0 */ 654 __I AES_ODATAR_Type AES_ODATAR[4]; /**< Offset: 0x50 (R/ 32) Output Data Register 0 */ 655 __O AES_IVR_Type AES_IVR[4]; /**< Offset: 0x60 ( /W 32) Initialization Vector Register 0 */ 656 __IO AES_AADLENR_Type AES_AADLENR; /**< Offset: 0x70 (R/W 32) Additional Authenticated Data Length Register */ 657 __IO AES_CLENR_Type AES_CLENR; /**< Offset: 0x74 (R/W 32) Plaintext/Ciphertext Length Register */ 658 __IO AES_GHASHR_Type AES_GHASHR[4]; /**< Offset: 0x78 (R/W 32) GCM Intermediate Hash Word Register 0 */ 659 __I AES_TAGR_Type AES_TAGR[4]; /**< Offset: 0x88 (R/ 32) GCM Authentication Tag Word Register 0 */ 660 __I AES_CTRR_Type AES_CTRR; /**< Offset: 0x98 (R/ 32) GCM Encryption Counter Value Register */ 661 __IO AES_GCMHR_Type AES_GCMHR[4]; /**< Offset: 0x9C (R/W 32) GCM H Word Register 0 */ 662 __I uint8_t Reserved2[80]; 663 __I AES_VERSION_Type AES_VERSION; /**< Offset: 0xFC (R/ 32) Version Register */ 664 } Aes; 665 666 #else /* COMPONENT_TYPEDEF_STYLE */ 667 #error Unknown component typedef style 668 #endif /* COMPONENT_TYPEDEF_STYLE */ 669 670 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 671 /** @} end of Advanced Encryption Standard */ 672 673 #endif /* _SAMV71_AES_COMPONENT_H_ */ 674
