1 /**
2  * \file
3  *
4  * \brief Header file for ATSAME70J19B
5  *
6  * Copyright (c) 2019 Microchip Technology Inc.
7  *
8  * \license_start
9  *
10  * \page License
11  *
12  * SPDX-License-Identifier: Apache-2.0
13  *
14  * Licensed under the Apache License, Version 2.0 (the "License");
15  * you may not use this file except in compliance with the License.
16  * You may obtain a copy of the License at
17  *
18  *   http://www.apache.org/licenses/LICENSE-2.0
19  *
20  * Unless required by applicable law or agreed to in writing, software
21  * distributed under the License is distributed on an "AS IS" BASIS,
22  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23  * See the License for the specific language governing permissions and
24  * limitations under the License.
25  *
26  * \license_stop
27  *
28  */
29 
30 /* file generated from device description version 2019-01-18T21:19:37Z */
31 #ifndef _SAME70J19B_H_
32 #define _SAME70J19B_H_
33 
34 /** \addtogroup SAME70J19B_definitions SAME70J19B definitions
35   This file defines all structures and symbols for SAME70J19B:
36     - registers and bitfields
37     - peripheral base address
38     - peripheral ID
39     - PIO definitions
40  *  @{
41  */
42 
43 #ifdef __cplusplus
44  extern "C" {
45 #endif
46 
47 /** \defgroup Atmel_glob_defs Atmel Global Defines
48 
49     <strong>IO Type Qualifiers</strong> are used
50     \li to specify the access to peripheral variables.
51     \li for automatic generation of peripheral register debug information.
52 
53     \remark
54     CMSIS core has a syntax that differs from this using i.e. __I, __O, or __IO followed by 'uint<size>_t' respective types.
55     Default the header files will follow the CMSIS core syntax.
56  *  @{
57  */
58 
59 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
60 #include <stdint.h>
61 
62 /* IO definitions (access restrictions to peripheral registers) */
63 #ifndef __cplusplus
64 typedef volatile const uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
65 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
66 typedef volatile const uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
67 #else
68 typedef volatile       uint32_t RoReg;   /**< Read only 32-bit register (volatile const unsigned int) */
69 typedef volatile       uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */
70 typedef volatile       uint8_t  RoReg8;  /**< Read only  8-bit register (volatile const unsigned int) */
71 #endif
72 typedef volatile       uint32_t WoReg;   /**< Write only 32-bit register (volatile unsigned int) */
73 typedef volatile       uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */
74 typedef volatile       uint8_t  WoReg8;  /**< Write only  8-bit register (volatile unsigned int) */
75 typedef volatile       uint32_t RwReg;   /**< Read-Write 32-bit register (volatile unsigned int) */
76 typedef volatile       uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */
77 typedef volatile       uint8_t  RwReg8;  /**< Read-Write  8-bit register (volatile unsigned int) */
78 
79 #define CAST(type, value) ((type *)(value)) /**< Pointer Type Conversion Macro for C/C++ */
80 #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */
81 #else /* Assembler */
82 #define CAST(type, value) (value) /**< Pointer Type Conversion Macro for Assembler */
83 #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */
84 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
85 
86 #if !defined(SKIP_INTEGER_LITERALS)
87 
88 #if defined(_U_) || defined(_L_) || defined(_UL_)
89   #error "Integer Literals macros already defined elsewhere"
90 #endif
91 
92 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
93 /* Macros that deal with adding suffixes to integer literal constants for C/C++ */
94 #define _U_(x) x ## U    /**< C code: Unsigned integer literal constant value */
95 #define _L_(x) x ## L    /**< C code: Long integer literal constant value */
96 #define _UL_(x) x ## UL  /**< C code: Unsigned Long integer literal constant value */
97 
98 #else /* Assembler */
99 
100 #define _U_(x) x    /**< Assembler: Unsigned integer literal constant value */
101 #define _L_(x) x    /**< Assembler: Long integer literal constant value */
102 #define _UL_(x) x   /**< Assembler: Unsigned Long integer literal constant value */
103 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
104 
105 #endif /* SKIP_INTEGER_LITERALS */
106 /** @}  end of Atmel Global Defines */
107 
108 /** \addtogroup SAME70J19B_cmsis CMSIS Definitions
109  *  @{
110  */
111 /* ************************************************************************** */
112 /*   CMSIS DEFINITIONS FOR SAME70J19B */
113 /* ************************************************************************** */
114 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
115 /** Interrupt Number Definition */
116 typedef enum IRQn
117 {
118 /******  CORTEX-M7 Processor Exceptions Numbers ******************************/
119   Reset_IRQn                = -15, /**< 1   Reset Vector, invoked on Power up and warm reset  */
120   NonMaskableInt_IRQn       = -14, /**< 2   Non maskable Interrupt, cannot be stopped or preempted  */
121   HardFault_IRQn            = -13, /**< 3   Hard Fault, all classes of Fault     */
122   MemoryManagement_IRQn     = -12, /**< 4   Memory Management, MPU mismatch, including Access Violation and No Match  */
123   BusFault_IRQn             = -11, /**< 5   Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault  */
124   UsageFault_IRQn           = -10, /**< 6   Usage Fault, i.e. Undef Instruction, Illegal State Transition  */
125   SVCall_IRQn               = -5 , /**< 11  System Service Call via SVC instruction  */
126   DebugMonitor_IRQn         = -4 , /**< 12  Debug Monitor                        */
127   PendSV_IRQn               = -2 , /**< 14  Pendable request for system service  */
128   SysTick_IRQn              = -1 , /**< 15  System Tick Timer                    */
129 /******  SAME70J19B specific Interrupt Numbers ***********************************/
130   SUPC_IRQn                 = 0  , /**< 0   SAME70J19B Supply Controller (SUPC) */
131   RSTC_IRQn                 = 1  , /**< 1   SAME70J19B Reset Controller (RSTC)  */
132   RTC_IRQn                  = 2  , /**< 2   SAME70J19B Real-time Clock (RTC)    */
133   RTT_IRQn                  = 3  , /**< 3   SAME70J19B Real-time Timer (RTT)    */
134   WDT_IRQn                  = 4  , /**< 4   SAME70J19B Watchdog Timer (WDT)     */
135   PMC_IRQn                  = 5  , /**< 5   SAME70J19B Power Management Controller (PMC) */
136   EFC_IRQn                  = 6  , /**< 6   SAME70J19B Embedded Flash Controller (EFC) */
137   UART0_IRQn                = 7  , /**< 7   SAME70J19B Universal Asynchronous Receiver Transmitter (UART0) */
138   UART1_IRQn                = 8  , /**< 8   SAME70J19B Universal Asynchronous Receiver Transmitter (UART1) */
139   PIOA_IRQn                 = 10 , /**< 10  SAME70J19B Parallel Input/Output Controller (PIOA) */
140   PIOB_IRQn                 = 11 , /**< 11  SAME70J19B Parallel Input/Output Controller (PIOB) */
141   USART0_IRQn               = 13 , /**< 13  SAME70J19B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */
142   USART1_IRQn               = 14 , /**< 14  SAME70J19B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */
143   PIOD_IRQn                 = 16 , /**< 16  SAME70J19B Parallel Input/Output Controller (PIOD) */
144   TWIHS0_IRQn               = 19 , /**< 19  SAME70J19B Two-wire Interface High Speed (TWIHS0) */
145   TWIHS1_IRQn               = 20 , /**< 20  SAME70J19B Two-wire Interface High Speed (TWIHS1) */
146   SSC_IRQn                  = 22 , /**< 22  SAME70J19B Synchronous Serial Controller (SSC) */
147   TC0_IRQn                  = 23 , /**< 23  SAME70J19B Timer Counter (TC0)      */
148   TC1_IRQn                  = 24 , /**< 24  SAME70J19B Timer Counter (TC0)      */
149   TC2_IRQn                  = 25 , /**< 25  SAME70J19B Timer Counter (TC0)      */
150   TC3_IRQn                  = 26 , /**< 26  SAME70J19B Timer Counter (TC1)      */
151   TC4_IRQn                  = 27 , /**< 27  SAME70J19B Timer Counter (TC1)      */
152   TC5_IRQn                  = 28 , /**< 28  SAME70J19B Timer Counter (TC1)      */
153   AFEC0_IRQn                = 29 , /**< 29  SAME70J19B Analog Front-End Controller (AFEC0) */
154   DACC_IRQn                 = 30 , /**< 30  SAME70J19B Digital-to-Analog Converter Controller (DACC) */
155   PWM0_IRQn                 = 31 , /**< 31  SAME70J19B Pulse Width Modulation Controller (PWM0) */
156   ICM_IRQn                  = 32 , /**< 32  SAME70J19B Integrity Check Monitor (ICM) */
157   ACC_IRQn                  = 33 , /**< 33  SAME70J19B Analog Comparator Controller (ACC) */
158   USBHS_IRQn                = 34 , /**< 34  SAME70J19B USB High-Speed Interface (USBHS) */
159   MCAN0_INT0_IRQn           = 35 , /**< 35  SAME70J19B Controller Area Network (MCAN0) */
160   MCAN0_INT1_IRQn           = 36 , /**< 36  SAME70J19B Controller Area Network (MCAN0) */
161   GMAC_IRQn                 = 39 , /**< 39  SAME70J19B Gigabit Ethernet MAC (GMAC) */
162   AFEC1_IRQn                = 40 , /**< 40  SAME70J19B Analog Front-End Controller (AFEC1) */
163   QSPI_IRQn                 = 43 , /**< 43  SAME70J19B Quad Serial Peripheral Interface (QSPI) */
164   UART2_IRQn                = 44 , /**< 44  SAME70J19B Universal Asynchronous Receiver Transmitter (UART2) */
165   TC6_IRQn                  = 47 , /**< 47  SAME70J19B Timer Counter (TC2)      */
166   TC7_IRQn                  = 48 , /**< 48  SAME70J19B Timer Counter (TC2)      */
167   TC8_IRQn                  = 49 , /**< 49  SAME70J19B Timer Counter (TC2)      */
168   TC9_IRQn                  = 50 , /**< 50  SAME70J19B Timer Counter (TC3)      */
169   TC10_IRQn                 = 51 , /**< 51  SAME70J19B Timer Counter (TC3)      */
170   TC11_IRQn                 = 52 , /**< 52  SAME70J19B Timer Counter (TC3)      */
171   AES_IRQn                  = 56 , /**< 56  SAME70J19B Advanced Encryption Standard (AES) */
172   TRNG_IRQn                 = 57 , /**< 57  SAME70J19B True Random Number Generator (TRNG) */
173   XDMAC_IRQn                = 58 , /**< 58  SAME70J19B Extensible DMA Controller (XDMAC) */
174   ISI_IRQn                  = 59 , /**< 59  SAME70J19B Image Sensor Interface (ISI) */
175   PWM1_IRQn                 = 60 , /**< 60  SAME70J19B Pulse Width Modulation Controller (PWM1) */
176   FPU_IRQn                  = 61 , /**< 61  SAME70J19B Floating Point Unit (FPU) */
177   RSWDT_IRQn                = 63 , /**< 63  SAME70J19B Reinforced Safety Watchdog Timer (RSWDT) */
178   CCW_IRQn                  = 64 , /**< 64  SAME70J19B System Control Block (SCB) */
179   CCF_IRQn                  = 65 , /**< 65  SAME70J19B System Control Block (SCB) */
180   GMAC_Q1_IRQn              = 66 , /**< 66  SAME70J19B Gigabit Ethernet MAC (GMAC) */
181   GMAC_Q2_IRQn              = 67 , /**< 67  SAME70J19B Gigabit Ethernet MAC (GMAC) */
182   IXC_IRQn                  = 68 , /**< 68  SAME70J19B Floating Point Unit (FPU) */
183   GMAC_Q3_IRQn              = 71 , /**< 71  SAME70J19B Gigabit Ethernet MAC (GMAC) */
184   GMAC_Q4_IRQn              = 72 , /**< 72  SAME70J19B Gigabit Ethernet MAC (GMAC) */
185   GMAC_Q5_IRQn              = 73 , /**< 73  SAME70J19B Gigabit Ethernet MAC (GMAC) */
186 
187   PERIPH_COUNT_IRQn        = 74  /**< Number of peripheral IDs */
188 } IRQn_Type;
189 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
190 
191 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
192 typedef struct _DeviceVectors
193 {
194   /* Stack pointer */
195   void* pvStack;
196   /* Cortex-M handlers */
197   void* pfnReset_Handler;                        /* -15 Reset Vector, invoked on Power up and warm reset  */
198   void* pfnNonMaskableInt_Handler;               /* -14 Non maskable Interrupt, cannot be stopped or preempted  */
199   void* pfnHardFault_Handler;                    /* -13 Hard Fault, all classes of Fault     */
200   void* pfnMemoryManagement_Handler;             /* -12 Memory Management, MPU mismatch, including Access Violation and No Match  */
201   void* pfnBusFault_Handler;                     /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault  */
202   void* pfnUsageFault_Handler;                   /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition  */
203   void* pvReservedC9;
204   void* pvReservedC8;
205   void* pvReservedC7;
206   void* pvReservedC6;
207   void* pfnSVCall_Handler;                       /*  -5 System Service Call via SVC instruction  */
208   void* pfnDebugMonitor_Handler;                 /*  -4 Debug Monitor                        */
209   void* pvReservedC3;
210   void* pfnPendSV_Handler;                       /*  -2 Pendable request for system service  */
211   void* pfnSysTick_Handler;                      /*  -1 System Tick Timer                    */
212 
213 
214   /* Peripheral handlers */
215   void* pfnSUPC_Handler;                         /* 0   SAME70J19B Supply Controller (SUPC) */
216   void* pfnRSTC_Handler;                         /* 1   SAME70J19B Reset Controller (RSTC) */
217   void* pfnRTC_Handler;                          /* 2   SAME70J19B Real-time Clock (RTC) */
218   void* pfnRTT_Handler;                          /* 3   SAME70J19B Real-time Timer (RTT) */
219   void* pfnWDT_Handler;                          /* 4   SAME70J19B Watchdog Timer (WDT) */
220   void* pfnPMC_Handler;                          /* 5   SAME70J19B Power Management Controller (PMC) */
221   void* pfnEFC_Handler;                          /* 6   SAME70J19B Embedded Flash Controller (EFC) */
222   void* pfnUART0_Handler;                        /* 7   SAME70J19B Universal Asynchronous Receiver Transmitter (UART0) */
223   void* pfnUART1_Handler;                        /* 8   SAME70J19B Universal Asynchronous Receiver Transmitter (UART1) */
224   void* pvReserved9;
225   void* pfnPIOA_Handler;                         /* 10  SAME70J19B Parallel Input/Output Controller (PIOA) */
226   void* pfnPIOB_Handler;                         /* 11  SAME70J19B Parallel Input/Output Controller (PIOB) */
227   void* pvReserved12;
228   void* pfnUSART0_Handler;                       /* 13  SAME70J19B Universal Synchronous Asynchronous Receiver Transmitter (USART0) */
229   void* pfnUSART1_Handler;                       /* 14  SAME70J19B Universal Synchronous Asynchronous Receiver Transmitter (USART1) */
230   void* pvReserved15;
231   void* pfnPIOD_Handler;                         /* 16  SAME70J19B Parallel Input/Output Controller (PIOD) */
232   void* pvReserved17;
233   void* pvReserved18;
234   void* pfnTWIHS0_Handler;                       /* 19  SAME70J19B Two-wire Interface High Speed (TWIHS0) */
235   void* pfnTWIHS1_Handler;                       /* 20  SAME70J19B Two-wire Interface High Speed (TWIHS1) */
236   void* pvReserved21;
237   void* pfnSSC_Handler;                          /* 22  SAME70J19B Synchronous Serial Controller (SSC) */
238   void* pfnTC0_Handler;                          /* 23  SAME70J19B Timer Counter (TC0) */
239   void* pfnTC1_Handler;                          /* 24  SAME70J19B Timer Counter (TC0) */
240   void* pfnTC2_Handler;                          /* 25  SAME70J19B Timer Counter (TC0) */
241   void* pfnTC3_Handler;                          /* 26  SAME70J19B Timer Counter (TC1) */
242   void* pfnTC4_Handler;                          /* 27  SAME70J19B Timer Counter (TC1) */
243   void* pfnTC5_Handler;                          /* 28  SAME70J19B Timer Counter (TC1) */
244   void* pfnAFEC0_Handler;                        /* 29  SAME70J19B Analog Front-End Controller (AFEC0) */
245   void* pfnDACC_Handler;                         /* 30  SAME70J19B Digital-to-Analog Converter Controller (DACC) */
246   void* pfnPWM0_Handler;                         /* 31  SAME70J19B Pulse Width Modulation Controller (PWM0) */
247   void* pfnICM_Handler;                          /* 32  SAME70J19B Integrity Check Monitor (ICM) */
248   void* pfnACC_Handler;                          /* 33  SAME70J19B Analog Comparator Controller (ACC) */
249   void* pfnUSBHS_Handler;                        /* 34  SAME70J19B USB High-Speed Interface (USBHS) */
250   void* pfnMCAN0_INT0_Handler;                   /* 35  SAME70J19B Controller Area Network (MCAN0) */
251   void* pfnMCAN0_INT1_Handler;                   /* 36  SAME70J19B Controller Area Network (MCAN0) */
252   void* pvReserved37;
253   void* pvReserved38;
254   void* pfnGMAC_Handler;                         /* 39  SAME70J19B Gigabit Ethernet MAC (GMAC) */
255   void* pfnAFEC1_Handler;                        /* 40  SAME70J19B Analog Front-End Controller (AFEC1) */
256   void* pvReserved41;
257   void* pvReserved42;
258   void* pfnQSPI_Handler;                         /* 43  SAME70J19B Quad Serial Peripheral Interface (QSPI) */
259   void* pfnUART2_Handler;                        /* 44  SAME70J19B Universal Asynchronous Receiver Transmitter (UART2) */
260   void* pvReserved45;
261   void* pvReserved46;
262   void* pfnTC6_Handler;                          /* 47  SAME70J19B Timer Counter (TC2) */
263   void* pfnTC7_Handler;                          /* 48  SAME70J19B Timer Counter (TC2) */
264   void* pfnTC8_Handler;                          /* 49  SAME70J19B Timer Counter (TC2) */
265   void* pfnTC9_Handler;                          /* 50  SAME70J19B Timer Counter (TC3) */
266   void* pfnTC10_Handler;                         /* 51  SAME70J19B Timer Counter (TC3) */
267   void* pfnTC11_Handler;                         /* 52  SAME70J19B Timer Counter (TC3) */
268   void* pvReserved53;
269   void* pvReserved54;
270   void* pvReserved55;
271   void* pfnAES_Handler;                          /* 56  SAME70J19B Advanced Encryption Standard (AES) */
272   void* pfnTRNG_Handler;                         /* 57  SAME70J19B True Random Number Generator (TRNG) */
273   void* pfnXDMAC_Handler;                        /* 58  SAME70J19B Extensible DMA Controller (XDMAC) */
274   void* pfnISI_Handler;                          /* 59  SAME70J19B Image Sensor Interface (ISI) */
275   void* pfnPWM1_Handler;                         /* 60  SAME70J19B Pulse Width Modulation Controller (PWM1) */
276   void* pfnFPU_Handler;                          /* 61  SAME70J19B Floating Point Unit (FPU) */
277   void* pvReserved62;
278   void* pfnRSWDT_Handler;                        /* 63  SAME70J19B Reinforced Safety Watchdog Timer (RSWDT) */
279   void* pfnCCW_Handler;                          /* 64  SAME70J19B System Control Block (SCB) */
280   void* pfnCCF_Handler;                          /* 65  SAME70J19B System Control Block (SCB) */
281   void* pfnGMAC_Q1_Handler;                      /* 66  SAME70J19B Gigabit Ethernet MAC (GMAC) */
282   void* pfnGMAC_Q2_Handler;                      /* 67  SAME70J19B Gigabit Ethernet MAC (GMAC) */
283   void* pfnIXC_Handler;                          /* 68  SAME70J19B Floating Point Unit (FPU) */
284   void* pvReserved69;
285   void* pvReserved70;
286   void* pfnGMAC_Q3_Handler;                      /* 71  SAME70J19B Gigabit Ethernet MAC (GMAC) */
287   void* pfnGMAC_Q4_Handler;                      /* 72  SAME70J19B Gigabit Ethernet MAC (GMAC) */
288   void* pfnGMAC_Q5_Handler;                      /* 73  SAME70J19B Gigabit Ethernet MAC (GMAC) */
289 } DeviceVectors;
290 
291 /* Defines for Deprecated Interrupt and Exceptions handler names */
292 #define pfnMemManage_Handler      pfnMemoryManagement_Handler     /**< \deprecated  Backward compatibility for ASF */
293 #define pfnDebugMon_Handler       pfnDebugMonitor_Handler         /**< \deprecated  Backward compatibility for ASF */
294 #define pfnNMI_Handler            pfnNonMaskableInt_Handler       /**< \deprecated  Backward compatibility for ASF */
295 #define pfnSVC_Handler            pfnSVCall_Handler               /**< \deprecated  Backward compatibility for ASF */
296 
297 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
298 
299 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
300 #if !defined DONT_USE_PREDEFINED_CORE_HANDLERS
301 
302 /* CORTEX-M7 core handlers */
303 void Reset_Handler                 ( void );
304 void NonMaskableInt_Handler        ( void );
305 void HardFault_Handler             ( void );
306 void MemoryManagement_Handler      ( void );
307 void BusFault_Handler              ( void );
308 void UsageFault_Handler            ( void );
309 void SVCall_Handler                ( void );
310 void DebugMonitor_Handler          ( void );
311 void PendSV_Handler                ( void );
312 void SysTick_Handler               ( void );
313 #endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */
314 
315 #if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
316 
317 /* Peripherals handlers */
318 void ACC_Handler                   ( void );
319 void AES_Handler                   ( void );
320 void AFEC0_Handler                 ( void );
321 void AFEC1_Handler                 ( void );
322 void CCF_Handler                   ( void );
323 void CCW_Handler                   ( void );
324 void DACC_Handler                  ( void );
325 void EFC_Handler                   ( void );
326 void FPU_Handler                   ( void );
327 void GMAC_Handler                  ( void );
328 void GMAC_Q1_Handler               ( void );
329 void GMAC_Q2_Handler               ( void );
330 void GMAC_Q3_Handler               ( void );
331 void GMAC_Q4_Handler               ( void );
332 void GMAC_Q5_Handler               ( void );
333 void ICM_Handler                   ( void );
334 void ISI_Handler                   ( void );
335 void IXC_Handler                   ( void );
336 void MCAN0_INT0_Handler            ( void );
337 void MCAN0_INT1_Handler            ( void );
338 void PIOA_Handler                  ( void );
339 void PIOB_Handler                  ( void );
340 void PIOD_Handler                  ( void );
341 void PMC_Handler                   ( void );
342 void PWM0_Handler                  ( void );
343 void PWM1_Handler                  ( void );
344 void QSPI_Handler                  ( void );
345 void RSTC_Handler                  ( void );
346 void RSWDT_Handler                 ( void );
347 void RTC_Handler                   ( void );
348 void RTT_Handler                   ( void );
349 void SSC_Handler                   ( void );
350 void SUPC_Handler                  ( void );
351 void TC0_Handler                   ( void );
352 void TC10_Handler                  ( void );
353 void TC11_Handler                  ( void );
354 void TC1_Handler                   ( void );
355 void TC2_Handler                   ( void );
356 void TC3_Handler                   ( void );
357 void TC4_Handler                   ( void );
358 void TC5_Handler                   ( void );
359 void TC6_Handler                   ( void );
360 void TC7_Handler                   ( void );
361 void TC8_Handler                   ( void );
362 void TC9_Handler                   ( void );
363 void TRNG_Handler                  ( void );
364 void TWIHS0_Handler                ( void );
365 void TWIHS1_Handler                ( void );
366 void UART0_Handler                 ( void );
367 void UART1_Handler                 ( void );
368 void UART2_Handler                 ( void );
369 void USART0_Handler                ( void );
370 void USART1_Handler                ( void );
371 void USBHS_Handler                 ( void );
372 void WDT_Handler                   ( void );
373 void XDMAC_Handler                 ( void );
374 #endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */
375 
376 
377 /* Defines for Deprecated Interrupt and Exceptions handler names */
378 #define MemManage_Handler         MemoryManagement_Handler        /**< \deprecated  Backward compatibility for ASF */
379 #define DebugMon_Handler          DebugMonitor_Handler            /**< \deprecated  Backward compatibility for ASF */
380 #define NMI_Handler               NonMaskableInt_Handler          /**< \deprecated  Backward compatibility for ASF */
381 #define SVC_Handler               SVCall_Handler                  /**< \deprecated  Backward compatibility for ASF */
382 
383 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
384 
385 
386 /*
387  * \brief Configuration of the CORTEX-M7 Processor and Core Peripherals
388  */
389 
390 #define __CM7_REV                 0x0101 /**< CM7 Core Revision                                                         */
391 #define __NVIC_PRIO_BITS               3 /**< Number of Bits used for Priority Levels                                   */
392 #define __Vendor_SysTickConfig         0 /**< Set to 1 if different SysTick Config is used                              */
393 #define __MPU_PRESENT                  1 /**< MPU present or not                                                        */
394 #define __VTOR_PRESENT                 1 /**< Vector Table Offset Register present or not                               */
395 #define __FPU_PRESENT                  1 /**< FPU present or not                                                        */
396 #define __FPU_DP                       1 /**< Double Precision FPU                                                      */
397 #define __ICACHE_PRESENT               1 /**< Instruction Cache present                                                 */
398 #define __DCACHE_PRESENT               1 /**< Data Cache present                                                        */
399 #define __ITCM_PRESENT                 1 /**< Instruction TCM present                                                   */
400 #define __DTCM_PRESENT                 1 /**< Data TCM present                                                          */
401 #define __DEBUG_LVL                    1
402 #define __TRACE_LVL                    1
403 #define __ARCH_ARM                     1
404 #define __ARCH_ARM_CORTEX_M            1
405 #define __DEVICE_IS_SAM                1
406 
407 /*
408  * \brief CMSIS includes
409  */
410 #include <core_cm7.h>
411 #if !defined DONT_USE_CMSIS_INIT
412 #include "system_same70.h"
413 #endif /* DONT_USE_CMSIS_INIT */
414 
415 /** @}  end of SAME70J19B_cmsis CMSIS Definitions */
416 
417 /** \defgroup SAME70J19B_api Peripheral Software API
418  *  @{
419  */
420 
421 /* ************************************************************************** */
422 /**  SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19B */
423 /* ************************************************************************** */
424 #include "component/acc.h"
425 #include "component/aes.h"
426 #include "component/afec.h"
427 #include "component/chipid.h"
428 #include "component/dacc.h"
429 #include "component/efc.h"
430 #include "component/gmac.h"
431 #include "component/gpbr.h"
432 #include "component/icm.h"
433 #include "component/isi.h"
434 #include "component/matrix.h"
435 #include "component/mcan.h"
436 #include "component/pio.h"
437 #include "component/pmc.h"
438 #include "component/pwm.h"
439 #include "component/qspi.h"
440 #include "component/rstc.h"
441 #include "component/rswdt.h"
442 #include "component/rtc.h"
443 #include "component/rtt.h"
444 #include "component/ssc.h"
445 #include "component/supc.h"
446 #include "component/tc.h"
447 #include "component/trng.h"
448 #include "component/twihs.h"
449 #include "component/uart.h"
450 #include "component/usart.h"
451 #include "component/usbhs.h"
452 #include "component/utmi.h"
453 #include "component/wdt.h"
454 #include "component/xdmac.h"
455 /** @}  end of Peripheral Software API */
456 
457 /** \defgroup SAME70J19B_reg Registers Access Definitions
458  *  @{
459  */
460 
461 /* ************************************************************************** */
462 /*   REGISTER ACCESS DEFINITIONS FOR SAME70J19B */
463 /* ************************************************************************** */
464 #include "instance/acc.h"
465 #include "instance/aes.h"
466 #include "instance/afec0.h"
467 #include "instance/afec1.h"
468 #include "instance/chipid.h"
469 #include "instance/dacc.h"
470 #include "instance/efc.h"
471 #include "instance/gmac.h"
472 #include "instance/gpbr.h"
473 #include "instance/icm.h"
474 #include "instance/isi.h"
475 #include "instance/matrix.h"
476 #include "instance/mcan0.h"
477 #include "instance/pioa.h"
478 #include "instance/piob.h"
479 #include "instance/piod.h"
480 #include "instance/pmc.h"
481 #include "instance/pwm0.h"
482 #include "instance/pwm1.h"
483 #include "instance/qspi.h"
484 #include "instance/rstc.h"
485 #include "instance/rswdt.h"
486 #include "instance/rtc.h"
487 #include "instance/rtt.h"
488 #include "instance/ssc.h"
489 #include "instance/supc.h"
490 #include "instance/tc0.h"
491 #include "instance/tc1.h"
492 #include "instance/tc2.h"
493 #include "instance/tc3.h"
494 #include "instance/trng.h"
495 #include "instance/twihs0.h"
496 #include "instance/twihs1.h"
497 #include "instance/uart0.h"
498 #include "instance/uart1.h"
499 #include "instance/uart2.h"
500 #include "instance/usart0.h"
501 #include "instance/usart1.h"
502 #include "instance/usbhs.h"
503 #include "instance/utmi.h"
504 #include "instance/wdt.h"
505 #include "instance/xdmac.h"
506 /** @}  end of Registers Access Definitions */
507 
508 /** \addtogroup SAME70J19B_id Peripheral Ids Definitions
509  *  @{
510  */
511 
512 /* ************************************************************************** */
513 /*  PERIPHERAL ID DEFINITIONS FOR SAME70J19B */
514 /* ************************************************************************** */
515 #define ID_SUPC         (  0) /**< \brief Supply Controller (SUPC) */
516 #define ID_RSTC         (  1) /**< \brief Reset Controller (RSTC) */
517 #define ID_RTC          (  2) /**< \brief Real-time Clock (RTC) */
518 #define ID_RTT          (  3) /**< \brief Real-time Timer (RTT) */
519 #define ID_WDT          (  4) /**< \brief Watchdog Timer (WDT) */
520 #define ID_PMC          (  5) /**< \brief Power Management Controller (PMC) */
521 #define ID_EFC          (  6) /**< \brief Embedded Flash Controller (EFC) */
522 #define ID_UART0        (  7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */
523 #define ID_UART1        (  8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */
524 #define ID_PIOA         ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */
525 #define ID_PIOB         ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */
526 #define ID_USART0       ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */
527 #define ID_USART1       ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */
528 #define ID_PIOD         ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */
529 #define ID_TWIHS0       ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */
530 #define ID_TWIHS1       ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */
531 #define ID_SSC          ( 22) /**< \brief Synchronous Serial Controller (SSC) */
532 #define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */
533 #define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */
534 #define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */
535 #define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */
536 #define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */
537 #define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */
538 #define ID_AFEC0        ( 29) /**< \brief Analog Front-End Controller (AFEC0) */
539 #define ID_DACC         ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */
540 #define ID_PWM0         ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */
541 #define ID_ICM          ( 32) /**< \brief Integrity Check Monitor (ICM) */
542 #define ID_ACC          ( 33) /**< \brief Analog Comparator Controller (ACC) */
543 #define ID_USBHS        ( 34) /**< \brief USB High-Speed Interface (USBHS) */
544 #define ID_MCAN0        ( 35) /**< \brief Controller Area Network (MCAN0) */
545 #define ID_GMAC         ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */
546 #define ID_AFEC1        ( 40) /**< \brief Analog Front-End Controller (AFEC1) */
547 #define ID_QSPI         ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */
548 #define ID_UART2        ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */
549 #define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */
550 #define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */
551 #define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */
552 #define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */
553 #define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */
554 #define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */
555 #define ID_AES          ( 56) /**< \brief Advanced Encryption Standard (AES) */
556 #define ID_TRNG         ( 57) /**< \brief True Random Number Generator (TRNG) */
557 #define ID_XDMAC        ( 58) /**< \brief Extensible DMA Controller (XDMAC) */
558 #define ID_ISI          ( 59) /**< \brief Image Sensor Interface (ISI) */
559 #define ID_PWM1         ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */
560 #define ID_RSWDT        ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */
561 
562 #define ID_PERIPH_COUNT ( 64) /**< \brief Number of peripheral IDs */
563 /** @}  end of Peripheral Ids Definitions */
564 
565 /** \addtogroup legacy_SAME70J19B_id Legacy Peripheral Ids Definitions
566  *  @{
567  */
568 
569 /* ************************************************************************** */
570 /*  LEGACY PERIPHERAL ID DEFINITIONS FOR SAME70J19B */
571 /* ************************************************************************** */
572 #define ID_TC0                   TC0_INSTANCE_ID_CHANNEL0
573 #define ID_TC1                   TC0_INSTANCE_ID_CHANNEL1
574 #define ID_TC2                   TC0_INSTANCE_ID_CHANNEL2
575 #define ID_TC3                   TC1_INSTANCE_ID_CHANNEL0
576 #define ID_TC4                   TC1_INSTANCE_ID_CHANNEL1
577 #define ID_TC5                   TC1_INSTANCE_ID_CHANNEL2
578 #define ID_TC6                   TC2_INSTANCE_ID_CHANNEL0
579 #define ID_TC7                   TC2_INSTANCE_ID_CHANNEL1
580 #define ID_TC8                   TC2_INSTANCE_ID_CHANNEL2
581 #define ID_TC9                   TC3_INSTANCE_ID_CHANNEL0
582 #define ID_TC10                  TC3_INSTANCE_ID_CHANNEL1
583 #define ID_TC11                  TC3_INSTANCE_ID_CHANNEL2
584 /** @}  end of Legacy Peripheral Ids Definitions */
585 
586 /** \addtogroup SAME70J19B_base Peripheral Base Address Definitions
587  *  @{
588  */
589 
590 /* ************************************************************************** */
591 /*   BASE ADDRESS DEFINITIONS FOR SAME70J19B */
592 /* ************************************************************************** */
593 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
594 #define ACC                    (0x40044000)                   /**< \brief (ACC       ) Base Address */
595 #define AES                    (0x4006C000)                   /**< \brief (AES       ) Base Address */
596 #define AFEC0                  (0x4003C000)                   /**< \brief (AFEC0     ) Base Address */
597 #define AFEC1                  (0x40064000)                   /**< \brief (AFEC1     ) Base Address */
598 #define CHIPID                 (0x400E0940)                   /**< \brief (CHIPID    ) Base Address */
599 #define DACC                   (0x40040000)                   /**< \brief (DACC      ) Base Address */
600 #define EFC                    (0x400E0C00)                   /**< \brief (EFC       ) Base Address */
601 #define GMAC                   (0x40050000)                   /**< \brief (GMAC      ) Base Address */
602 #define GPBR                   (0x400E1890)                   /**< \brief (GPBR      ) Base Address */
603 #define ICM                    (0x40048000)                   /**< \brief (ICM       ) Base Address */
604 #define ISI                    (0x4004C000)                   /**< \brief (ISI       ) Base Address */
605 #define MATRIX                 (0x40088000)                   /**< \brief (MATRIX    ) Base Address */
606 #define MCAN0                  (0x40030000)                   /**< \brief (MCAN0     ) Base Address */
607 #define PIOA                   (0x400E0E00)                   /**< \brief (PIOA      ) Base Address */
608 #define PIOB                   (0x400E1000)                   /**< \brief (PIOB      ) Base Address */
609 #define PIOD                   (0x400E1400)                   /**< \brief (PIOD      ) Base Address */
610 #define PMC                    (0x400E0600)                   /**< \brief (PMC       ) Base Address */
611 #define PWM0                   (0x40020000)                   /**< \brief (PWM0      ) Base Address */
612 #define PWM1                   (0x4005C000)                   /**< \brief (PWM1      ) Base Address */
613 #define QSPI                   (0x4007C000)                   /**< \brief (QSPI      ) Base Address */
614 #define RSTC                   (0x400E1800)                   /**< \brief (RSTC      ) Base Address */
615 #define RSWDT                  (0x400E1900)                   /**< \brief (RSWDT     ) Base Address */
616 #define RTC                    (0x400E1860)                   /**< \brief (RTC       ) Base Address */
617 #define RTT                    (0x400E1830)                   /**< \brief (RTT       ) Base Address */
618 #define SSC                    (0x40004000)                   /**< \brief (SSC       ) Base Address */
619 #define SUPC                   (0x400E1810)                   /**< \brief (SUPC      ) Base Address */
620 #define TC0                    (0x4000C000)                   /**< \brief (TC0       ) Base Address */
621 #define TC1                    (0x40010000)                   /**< \brief (TC1       ) Base Address */
622 #define TC2                    (0x40014000)                   /**< \brief (TC2       ) Base Address */
623 #define TC3                    (0x40054000)                   /**< \brief (TC3       ) Base Address */
624 #define TRNG                   (0x40070000)                   /**< \brief (TRNG      ) Base Address */
625 #define TWIHS0                 (0x40018000)                   /**< \brief (TWIHS0    ) Base Address */
626 #define TWIHS1                 (0x4001C000)                   /**< \brief (TWIHS1    ) Base Address */
627 #define UART0                  (0x400E0800)                   /**< \brief (UART0     ) Base Address */
628 #define UART1                  (0x400E0A00)                   /**< \brief (UART1     ) Base Address */
629 #define UART2                  (0x400E1A00)                   /**< \brief (UART2     ) Base Address */
630 #define USART0                 (0x40024000)                   /**< \brief (USART0    ) Base Address */
631 #define USART1                 (0x40028000)                   /**< \brief (USART1    ) Base Address */
632 #define USBHS                  (0x40038000)                   /**< \brief (USBHS     ) Base Address */
633 #define UTMI                   (0x400E0400)                   /**< \brief (UTMI      ) Base Address */
634 #define WDT                    (0x400E1850)                   /**< \brief (WDT       ) Base Address */
635 #define XDMAC                  (0x40078000)                   /**< \brief (XDMAC     ) Base Address */
636 
637 #else /* For C/C++ compiler */
638 
639 #define ACC                    ((Acc *)0x40044000U)           /**< \brief (ACC       ) Base Address */
640 #define ACC_INST_NUM           1                              /**< \brief (ACC       ) Number of instances */
641 #define ACC_INSTS              { ACC }                        /**< \brief (ACC       ) Instances List */
642 
643 #define AES                    ((Aes *)0x4006C000U)           /**< \brief (AES       ) Base Address */
644 #define AES_INST_NUM           1                              /**< \brief (AES       ) Number of instances */
645 #define AES_INSTS              { AES }                        /**< \brief (AES       ) Instances List */
646 
647 #define AFEC0                  ((Afec *)0x4003C000U)          /**< \brief (AFEC0     ) Base Address */
648 #define AFEC1                  ((Afec *)0x40064000U)          /**< \brief (AFEC1     ) Base Address */
649 #define AFEC_INST_NUM          2                              /**< \brief (AFEC      ) Number of instances */
650 #define AFEC_INSTS             { AFEC0, AFEC1 }               /**< \brief (AFEC      ) Instances List */
651 
652 #define CHIPID                 ((Chipid *)0x400E0940U)        /**< \brief (CHIPID    ) Base Address */
653 #define CHIPID_INST_NUM        1                              /**< \brief (CHIPID    ) Number of instances */
654 #define CHIPID_INSTS           { CHIPID }                     /**< \brief (CHIPID    ) Instances List */
655 
656 #define DACC                   ((Dacc *)0x40040000U)          /**< \brief (DACC      ) Base Address */
657 #define DACC_INST_NUM          1                              /**< \brief (DACC      ) Number of instances */
658 #define DACC_INSTS             { DACC }                       /**< \brief (DACC      ) Instances List */
659 
660 #define EFC                    ((Efc *)0x400E0C00U)           /**< \brief (EFC       ) Base Address */
661 #define EFC_INST_NUM           1                              /**< \brief (EFC       ) Number of instances */
662 #define EFC_INSTS              { EFC }                        /**< \brief (EFC       ) Instances List */
663 
664 #define GMAC                   ((Gmac *)0x40050000U)          /**< \brief (GMAC      ) Base Address */
665 #define GMAC_INST_NUM          1                              /**< \brief (GMAC      ) Number of instances */
666 #define GMAC_INSTS             { GMAC }                       /**< \brief (GMAC      ) Instances List */
667 
668 #define GPBR                   ((Gpbr *)0x400E1890U)          /**< \brief (GPBR      ) Base Address */
669 #define GPBR_INST_NUM          1                              /**< \brief (GPBR      ) Number of instances */
670 #define GPBR_INSTS             { GPBR }                       /**< \brief (GPBR      ) Instances List */
671 
672 #define ICM                    ((Icm *)0x40048000U)           /**< \brief (ICM       ) Base Address */
673 #define ICM_INST_NUM           1                              /**< \brief (ICM       ) Number of instances */
674 #define ICM_INSTS              { ICM }                        /**< \brief (ICM       ) Instances List */
675 
676 #define ISI                    ((Isi *)0x4004C000U)           /**< \brief (ISI       ) Base Address */
677 #define ISI_INST_NUM           1                              /**< \brief (ISI       ) Number of instances */
678 #define ISI_INSTS              { ISI }                        /**< \brief (ISI       ) Instances List */
679 
680 #define MATRIX                 ((Matrix *)0x40088000U)        /**< \brief (MATRIX    ) Base Address */
681 #define MATRIX_INST_NUM        1                              /**< \brief (MATRIX    ) Number of instances */
682 #define MATRIX_INSTS           { MATRIX }                     /**< \brief (MATRIX    ) Instances List */
683 
684 #define MCAN0                  ((Mcan *)0x40030000U)          /**< \brief (MCAN0     ) Base Address */
685 #define MCAN_INST_NUM          1                              /**< \brief (MCAN      ) Number of instances */
686 #define MCAN_INSTS             { MCAN0 }                      /**< \brief (MCAN      ) Instances List */
687 
688 #define PIOA                   ((Pio *)0x400E0E00U)           /**< \brief (PIOA      ) Base Address */
689 #define PIOB                   ((Pio *)0x400E1000U)           /**< \brief (PIOB      ) Base Address */
690 #define PIOD                   ((Pio *)0x400E1400U)           /**< \brief (PIOD      ) Base Address */
691 #define PIO_INST_NUM           3                              /**< \brief (PIO       ) Number of instances */
692 #define PIO_INSTS              { PIOA, PIOB, PIOD }           /**< \brief (PIO       ) Instances List */
693 
694 #define PMC                    ((Pmc *)0x400E0600U)           /**< \brief (PMC       ) Base Address */
695 #define PMC_INST_NUM           1                              /**< \brief (PMC       ) Number of instances */
696 #define PMC_INSTS              { PMC }                        /**< \brief (PMC       ) Instances List */
697 
698 #define PWM0                   ((Pwm *)0x40020000U)           /**< \brief (PWM0      ) Base Address */
699 #define PWM1                   ((Pwm *)0x4005C000U)           /**< \brief (PWM1      ) Base Address */
700 #define PWM_INST_NUM           2                              /**< \brief (PWM       ) Number of instances */
701 #define PWM_INSTS              { PWM0, PWM1 }                 /**< \brief (PWM       ) Instances List */
702 
703 #define QSPI                   ((Qspi *)0x4007C000U)          /**< \brief (QSPI      ) Base Address */
704 #define QSPI_INST_NUM          1                              /**< \brief (QSPI      ) Number of instances */
705 #define QSPI_INSTS             { QSPI }                       /**< \brief (QSPI      ) Instances List */
706 
707 #define RSTC                   ((Rstc *)0x400E1800U)          /**< \brief (RSTC      ) Base Address */
708 #define RSTC_INST_NUM          1                              /**< \brief (RSTC      ) Number of instances */
709 #define RSTC_INSTS             { RSTC }                       /**< \brief (RSTC      ) Instances List */
710 
711 #define RSWDT                  ((Rswdt *)0x400E1900U)         /**< \brief (RSWDT     ) Base Address */
712 #define RSWDT_INST_NUM         1                              /**< \brief (RSWDT     ) Number of instances */
713 #define RSWDT_INSTS            { RSWDT }                      /**< \brief (RSWDT     ) Instances List */
714 
715 #define RTC                    ((Rtc *)0x400E1860U)           /**< \brief (RTC       ) Base Address */
716 #define RTC_INST_NUM           1                              /**< \brief (RTC       ) Number of instances */
717 #define RTC_INSTS              { RTC }                        /**< \brief (RTC       ) Instances List */
718 
719 #define RTT                    ((Rtt *)0x400E1830U)           /**< \brief (RTT       ) Base Address */
720 #define RTT_INST_NUM           1                              /**< \brief (RTT       ) Number of instances */
721 #define RTT_INSTS              { RTT }                        /**< \brief (RTT       ) Instances List */
722 
723 #define SSC                    ((Ssc *)0x40004000U)           /**< \brief (SSC       ) Base Address */
724 #define SSC_INST_NUM           1                              /**< \brief (SSC       ) Number of instances */
725 #define SSC_INSTS              { SSC }                        /**< \brief (SSC       ) Instances List */
726 
727 #define SUPC                   ((Supc *)0x400E1810U)          /**< \brief (SUPC      ) Base Address */
728 #define SUPC_INST_NUM          1                              /**< \brief (SUPC      ) Number of instances */
729 #define SUPC_INSTS             { SUPC }                       /**< \brief (SUPC      ) Instances List */
730 
731 #define TC0                    ((Tc *)0x4000C000U)            /**< \brief (TC0       ) Base Address */
732 #define TC1                    ((Tc *)0x40010000U)            /**< \brief (TC1       ) Base Address */
733 #define TC2                    ((Tc *)0x40014000U)            /**< \brief (TC2       ) Base Address */
734 #define TC3                    ((Tc *)0x40054000U)            /**< \brief (TC3       ) Base Address */
735 #define TC_INST_NUM            4                              /**< \brief (TC        ) Number of instances */
736 #define TC_INSTS               { TC0, TC1, TC2, TC3 }         /**< \brief (TC        ) Instances List */
737 
738 #define TRNG                   ((Trng *)0x40070000U)          /**< \brief (TRNG      ) Base Address */
739 #define TRNG_INST_NUM          1                              /**< \brief (TRNG      ) Number of instances */
740 #define TRNG_INSTS             { TRNG }                       /**< \brief (TRNG      ) Instances List */
741 
742 #define TWIHS0                 ((Twihs *)0x40018000U)         /**< \brief (TWIHS0    ) Base Address */
743 #define TWIHS1                 ((Twihs *)0x4001C000U)         /**< \brief (TWIHS1    ) Base Address */
744 #define TWIHS_INST_NUM         2                              /**< \brief (TWIHS     ) Number of instances */
745 #define TWIHS_INSTS            { TWIHS0, TWIHS1 }             /**< \brief (TWIHS     ) Instances List */
746 
747 #define UART0                  ((Uart *)0x400E0800U)          /**< \brief (UART0     ) Base Address */
748 #define UART1                  ((Uart *)0x400E0A00U)          /**< \brief (UART1     ) Base Address */
749 #define UART2                  ((Uart *)0x400E1A00U)          /**< \brief (UART2     ) Base Address */
750 #define UART_INST_NUM          3                              /**< \brief (UART      ) Number of instances */
751 #define UART_INSTS             { UART0, UART1, UART2 }        /**< \brief (UART      ) Instances List */
752 
753 #define USART0                 ((Usart *)0x40024000U)         /**< \brief (USART0    ) Base Address */
754 #define USART1                 ((Usart *)0x40028000U)         /**< \brief (USART1    ) Base Address */
755 #define USART_INST_NUM         2                              /**< \brief (USART     ) Number of instances */
756 #define USART_INSTS            { USART0, USART1 }             /**< \brief (USART     ) Instances List */
757 
758 #define USBHS                  ((Usbhs *)0x40038000U)         /**< \brief (USBHS     ) Base Address */
759 #define USBHS_INST_NUM         1                              /**< \brief (USBHS     ) Number of instances */
760 #define USBHS_INSTS            { USBHS }                      /**< \brief (USBHS     ) Instances List */
761 
762 #define UTMI                   ((Utmi *)0x400E0400U)          /**< \brief (UTMI      ) Base Address */
763 #define UTMI_INST_NUM          1                              /**< \brief (UTMI      ) Number of instances */
764 #define UTMI_INSTS             { UTMI }                       /**< \brief (UTMI      ) Instances List */
765 
766 #define WDT                    ((Wdt *)0x400E1850U)           /**< \brief (WDT       ) Base Address */
767 #define WDT_INST_NUM           1                              /**< \brief (WDT       ) Number of instances */
768 #define WDT_INSTS              { WDT }                        /**< \brief (WDT       ) Instances List */
769 
770 #define XDMAC                  ((Xdmac *)0x40078000U)         /**< \brief (XDMAC     ) Base Address */
771 #define XDMAC_INST_NUM         1                              /**< \brief (XDMAC     ) Number of instances */
772 #define XDMAC_INSTS            { XDMAC }                      /**< \brief (XDMAC     ) Instances List */
773 
774 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
775 /** @}  end of Peripheral Base Address Definitions */
776 
777 /** \addtogroup SAME70J19B_pio Peripheral Pio Definitions
778  *  @{
779  */
780 
781 /* ************************************************************************** */
782 /*   PIO DEFINITIONS FOR SAME70J19B*/
783 /* ************************************************************************** */
784 #include "pio/same70j19b.h"
785 /** @}  end of Peripheral Pio Definitions */
786 
787 /* ************************************************************************** */
788 /*   MEMORY MAPPING DEFINITIONS FOR SAME70J19B*/
789 /* ************************************************************************** */
790 
791 #define PERIPHERALS_SIZE         _U_(0x20000000)       /* 524288kB Memory segment type: io */
792 #define SYSTEM_SIZE              _U_(0x10000000)       /* 262144kB Memory segment type: io */
793 #define QSPIMEM_SIZE             _U_(0x20000000)       /* 524288kB Memory segment type: other */
794 #define AXIMX_SIZE               _U_(0x00100000)       /* 1024kB Memory segment type: other */
795 #define ITCM_SIZE                _U_(0x00200000)       /* 2048kB Memory segment type: other */
796 #define IFLASH_SIZE              _U_(0x00080000)       /*  512kB Memory segment type: flash */
797 #define IFLASH_PAGE_SIZE         _U_(       512)
798 #define IFLASH_NB_OF_PAGES       _U_(      1024)
799 
800 #define IROM_SIZE                _U_(0x00004000)       /*   16kB Memory segment type: rom */
801 #define DTCM_SIZE                _U_(0x00020000)       /*  128kB Memory segment type: other */
802 #define IRAM_SIZE                _U_(0x00040000)       /*  256kB Memory segment type: ram */
803 
804 #define PERIPHERALS_ADDR         _U_(0x40000000)       /**< PERIPHERALS base address (type: io)*/
805 #define SYSTEM_ADDR              _U_(0xe0000000)       /**< SYSTEM base address (type: io)*/
806 #define QSPIMEM_ADDR             _U_(0x80000000)       /**< QSPIMEM base address (type: other)*/
807 #define AXIMX_ADDR               _U_(0xa0000000)       /**< AXIMX base address (type: other)*/
808 #define ITCM_ADDR                _U_(0x00000000)       /**< ITCM base address (type: other)*/
809 #define IFLASH_ADDR              _U_(0x00400000)       /**< IFLASH base address (type: flash)*/
810 #define IROM_ADDR                _U_(0x00800000)       /**< IROM base address (type: rom)*/
811 #define DTCM_ADDR                _U_(0x20000000)       /**< DTCM base address (type: other)*/
812 #define IRAM_ADDR                _U_(0x20400000)       /**< IRAM base address (type: ram)*/
813 
814 /* ************************************************************************** */
815 /**  DEVICE SIGNATURES FOR SAME70J19B */
816 /* ************************************************************************** */
817 #define JTAGID                   _UL_(0X05B3D03F)
818 #define CHIP_JTAGID              _UL_(0X05B3D03F)
819 #define CHIP_CIDR                _UL_(0XA10D0A01)
820 #define CHIP_EXID                _UL_(0X00000000)
821 
822 /* ************************************************************************** */
823 /**  ELECTRICAL DEFINITIONS FOR SAME70J19B */
824 /* ************************************************************************** */
825 #define CHIP_FREQ_SLCK_RC_MIN          _UL_(20000)
826 #define CHIP_FREQ_SLCK_RC              _UL_(32000)     /**< \brief Typical Slow Clock Internal RC frequency*/
827 #define CHIP_FREQ_SLCK_RC_MAX          _UL_(44000)
828 #define CHIP_FREQ_MAINCK_RC_4MHZ       _UL_(4000000)
829 #define CHIP_FREQ_MAINCK_RC_8MHZ       _UL_(8000000)
830 #define CHIP_FREQ_MAINCK_RC_12MHZ      _UL_(12000000)
831 #define CHIP_FREQ_CPU_MAX              _UL_(300000000)
832 #define CHIP_FREQ_XTAL_32K             _UL_(32768)
833 #define CHIP_FREQ_XTAL_12M             _UL_(12000000)
834 #define CHIP_FREQ_FWS_0                _UL_(23000000)  /**< \brief Maximum operating frequency when FWS is 0*/
835 #define CHIP_FREQ_FWS_1                _UL_(46000000)  /**< \brief Maximum operating frequency when FWS is 1*/
836 #define CHIP_FREQ_FWS_2                _UL_(69000000)  /**< \brief Maximum operating frequency when FWS is 2*/
837 #define CHIP_FREQ_FWS_3                _UL_(92000000)  /**< \brief Maximum operating frequency when FWS is 3*/
838 #define CHIP_FREQ_FWS_4                _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4*/
839 #define CHIP_FREQ_FWS_5                _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5*/
840 #define CHIP_FREQ_FWS_6                _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6*/
841 #define CHIP_FREQ_FWS_NUMBER           _UL_(7)         /**< \brief Number of FWS ranges*/
842 
843 
844 
845 #ifdef __cplusplus
846 }
847 #endif
848 
849 /** @}  end of SAME70J19B definitions */
850 
851 
852 #endif /* _SAME70J19B_H_ */
853