1 /** 2 * \file 3 * 4 * \brief Instance description for TC1 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:19:59Z */ 31 #ifndef _SAME70_TC1_INSTANCE_H_ 32 #define _SAME70_TC1_INSTANCE_H_ 33 34 /* ========== Register definition for TC1 peripheral ========== */ 35 #if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 36 37 #define REG_TC1_CCR0 (0x40010000) /**< (TC1) Channel Control Register (channel = 0) 0 */ 38 #define REG_TC1_CMR0 (0x40010004) /**< (TC1) Channel Mode Register (channel = 0) 0 */ 39 #define REG_TC1_SMMR0 (0x40010008) /**< (TC1) Stepper Motor Mode Register (channel = 0) 0 */ 40 #define REG_TC1_RAB0 (0x4001000C) /**< (TC1) Register AB (channel = 0) 0 */ 41 #define REG_TC1_CV0 (0x40010010) /**< (TC1) Counter Value (channel = 0) 0 */ 42 #define REG_TC1_RA0 (0x40010014) /**< (TC1) Register A (channel = 0) 0 */ 43 #define REG_TC1_RB0 (0x40010018) /**< (TC1) Register B (channel = 0) 0 */ 44 #define REG_TC1_RC0 (0x4001001C) /**< (TC1) Register C (channel = 0) 0 */ 45 #define REG_TC1_SR0 (0x40010020) /**< (TC1) Status Register (channel = 0) 0 */ 46 #define REG_TC1_IER0 (0x40010024) /**< (TC1) Interrupt Enable Register (channel = 0) 0 */ 47 #define REG_TC1_IDR0 (0x40010028) /**< (TC1) Interrupt Disable Register (channel = 0) 0 */ 48 #define REG_TC1_IMR0 (0x4001002C) /**< (TC1) Interrupt Mask Register (channel = 0) 0 */ 49 #define REG_TC1_EMR0 (0x40010030) /**< (TC1) Extended Mode Register (channel = 0) 0 */ 50 #define REG_TC1_CCR1 (0x40010040) /**< (TC1) Channel Control Register (channel = 0) 1 */ 51 #define REG_TC1_CMR1 (0x40010044) /**< (TC1) Channel Mode Register (channel = 0) 1 */ 52 #define REG_TC1_SMMR1 (0x40010048) /**< (TC1) Stepper Motor Mode Register (channel = 0) 1 */ 53 #define REG_TC1_RAB1 (0x4001004C) /**< (TC1) Register AB (channel = 0) 1 */ 54 #define REG_TC1_CV1 (0x40010050) /**< (TC1) Counter Value (channel = 0) 1 */ 55 #define REG_TC1_RA1 (0x40010054) /**< (TC1) Register A (channel = 0) 1 */ 56 #define REG_TC1_RB1 (0x40010058) /**< (TC1) Register B (channel = 0) 1 */ 57 #define REG_TC1_RC1 (0x4001005C) /**< (TC1) Register C (channel = 0) 1 */ 58 #define REG_TC1_SR1 (0x40010060) /**< (TC1) Status Register (channel = 0) 1 */ 59 #define REG_TC1_IER1 (0x40010064) /**< (TC1) Interrupt Enable Register (channel = 0) 1 */ 60 #define REG_TC1_IDR1 (0x40010068) /**< (TC1) Interrupt Disable Register (channel = 0) 1 */ 61 #define REG_TC1_IMR1 (0x4001006C) /**< (TC1) Interrupt Mask Register (channel = 0) 1 */ 62 #define REG_TC1_EMR1 (0x40010070) /**< (TC1) Extended Mode Register (channel = 0) 1 */ 63 #define REG_TC1_CCR2 (0x40010080) /**< (TC1) Channel Control Register (channel = 0) 2 */ 64 #define REG_TC1_CMR2 (0x40010084) /**< (TC1) Channel Mode Register (channel = 0) 2 */ 65 #define REG_TC1_SMMR2 (0x40010088) /**< (TC1) Stepper Motor Mode Register (channel = 0) 2 */ 66 #define REG_TC1_RAB2 (0x4001008C) /**< (TC1) Register AB (channel = 0) 2 */ 67 #define REG_TC1_CV2 (0x40010090) /**< (TC1) Counter Value (channel = 0) 2 */ 68 #define REG_TC1_RA2 (0x40010094) /**< (TC1) Register A (channel = 0) 2 */ 69 #define REG_TC1_RB2 (0x40010098) /**< (TC1) Register B (channel = 0) 2 */ 70 #define REG_TC1_RC2 (0x4001009C) /**< (TC1) Register C (channel = 0) 2 */ 71 #define REG_TC1_SR2 (0x400100A0) /**< (TC1) Status Register (channel = 0) 2 */ 72 #define REG_TC1_IER2 (0x400100A4) /**< (TC1) Interrupt Enable Register (channel = 0) 2 */ 73 #define REG_TC1_IDR2 (0x400100A8) /**< (TC1) Interrupt Disable Register (channel = 0) 2 */ 74 #define REG_TC1_IMR2 (0x400100AC) /**< (TC1) Interrupt Mask Register (channel = 0) 2 */ 75 #define REG_TC1_EMR2 (0x400100B0) /**< (TC1) Extended Mode Register (channel = 0) 2 */ 76 #define REG_TC1_BCR (0x400100C0) /**< (TC1) Block Control Register */ 77 #define REG_TC1_BMR (0x400100C4) /**< (TC1) Block Mode Register */ 78 #define REG_TC1_QIER (0x400100C8) /**< (TC1) QDEC Interrupt Enable Register */ 79 #define REG_TC1_QIDR (0x400100CC) /**< (TC1) QDEC Interrupt Disable Register */ 80 #define REG_TC1_QIMR (0x400100D0) /**< (TC1) QDEC Interrupt Mask Register */ 81 #define REG_TC1_QISR (0x400100D4) /**< (TC1) QDEC Interrupt Status Register */ 82 #define REG_TC1_FMR (0x400100D8) /**< (TC1) Fault Mode Register */ 83 #define REG_TC1_WPMR (0x400100E4) /**< (TC1) Write Protection Mode Register */ 84 85 #else 86 87 #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< (TC1) Channel Control Register (channel = 0) 0 */ 88 #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< (TC1) Channel Mode Register (channel = 0) 0 */ 89 #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 0 */ 90 #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< (TC1) Register AB (channel = 0) 0 */ 91 #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< (TC1) Counter Value (channel = 0) 0 */ 92 #define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< (TC1) Register A (channel = 0) 0 */ 93 #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< (TC1) Register B (channel = 0) 0 */ 94 #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< (TC1) Register C (channel = 0) 0 */ 95 #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< (TC1) Status Register (channel = 0) 0 */ 96 #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< (TC1) Interrupt Enable Register (channel = 0) 0 */ 97 #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< (TC1) Interrupt Disable Register (channel = 0) 0 */ 98 #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< (TC1) Interrupt Mask Register (channel = 0) 0 */ 99 #define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< (TC1) Extended Mode Register (channel = 0) 0 */ 100 #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< (TC1) Channel Control Register (channel = 0) 1 */ 101 #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< (TC1) Channel Mode Register (channel = 0) 1 */ 102 #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 1 */ 103 #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< (TC1) Register AB (channel = 0) 1 */ 104 #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< (TC1) Counter Value (channel = 0) 1 */ 105 #define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< (TC1) Register A (channel = 0) 1 */ 106 #define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< (TC1) Register B (channel = 0) 1 */ 107 #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< (TC1) Register C (channel = 0) 1 */ 108 #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< (TC1) Status Register (channel = 0) 1 */ 109 #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< (TC1) Interrupt Enable Register (channel = 0) 1 */ 110 #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< (TC1) Interrupt Disable Register (channel = 0) 1 */ 111 #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< (TC1) Interrupt Mask Register (channel = 0) 1 */ 112 #define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< (TC1) Extended Mode Register (channel = 0) 1 */ 113 #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< (TC1) Channel Control Register (channel = 0) 2 */ 114 #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< (TC1) Channel Mode Register (channel = 0) 2 */ 115 #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 2 */ 116 #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< (TC1) Register AB (channel = 0) 2 */ 117 #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< (TC1) Counter Value (channel = 0) 2 */ 118 #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< (TC1) Register A (channel = 0) 2 */ 119 #define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< (TC1) Register B (channel = 0) 2 */ 120 #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< (TC1) Register C (channel = 0) 2 */ 121 #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< (TC1) Status Register (channel = 0) 2 */ 122 #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< (TC1) Interrupt Enable Register (channel = 0) 2 */ 123 #define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< (TC1) Interrupt Disable Register (channel = 0) 2 */ 124 #define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< (TC1) Interrupt Mask Register (channel = 0) 2 */ 125 #define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< (TC1) Extended Mode Register (channel = 0) 2 */ 126 #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< (TC1) Block Control Register */ 127 #define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< (TC1) Block Mode Register */ 128 #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< (TC1) QDEC Interrupt Enable Register */ 129 #define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< (TC1) QDEC Interrupt Disable Register */ 130 #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< (TC1) QDEC Interrupt Mask Register */ 131 #define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< (TC1) QDEC Interrupt Status Register */ 132 #define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< (TC1) Fault Mode Register */ 133 #define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< (TC1) Write Protection Mode Register */ 134 135 #endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 /* ========== Instance Parameter definitions for TC1 peripheral ========== */ 138 #define TC1_DMAC_ID_RX 41 139 #define TC1_INSTANCE_ID_CHANNEL0 26 140 #define TC1_INSTANCE_ID_CHANNEL1 27 141 #define TC1_INSTANCE_ID_CHANNEL2 28 142 #define TC1_CLOCK_ID_CHANNEL0 26 143 #define TC1_CLOCK_ID_CHANNEL1 27 144 #define TC1_CLOCK_ID_CHANNEL2 28 145 #define TC1_TCCLKS_ 0 /* MCK */ 146 #define TC1_TCCLKS_TIMER_CLOCK1 1 /* PCK6 */ 147 #define TC1_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */ 148 #define TC1_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */ 149 #define TC1_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */ 150 #define TC1_TCCLKS_TIMER_CLOCK5 5 /* SLCK */ 151 #define TC1_TCCLKS_XC0 6 /* XC0 */ 152 #define TC1_TCCLKS_XC1 7 /* XC1 */ 153 #define TC1_TCCLKS_XC2 8 /* XC2 */ 154 #define TC1_NUM_INTERRUPT_LINES 3 155 #define TC1_TIMER_WIDTH 16 156 157 #endif /* _SAME70_TC1_INSTANCE_ */ 158
