1 /** 2 * \file 3 * 4 * \brief Component description for SSC 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:19:59Z */ 31 #ifndef _SAME70_SSC_COMPONENT_H_ 32 #define _SAME70_SSC_COMPONENT_H_ 33 #define _SAME70_SSC_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 Synchronous Serial Controller 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR SSC */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define SSC_6078 /**< (SSC) Module ID */ 46 #define REV_SSC Q /**< (SSC) Module revision */ 47 48 /* -------- SSC_CR : (SSC Offset: 0x00) (/W 32) Control Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t RXEN:1; /**< bit: 0 Receive Enable */ 54 uint32_t RXDIS:1; /**< bit: 1 Receive Disable */ 55 uint32_t :6; /**< bit: 2..7 Reserved */ 56 uint32_t TXEN:1; /**< bit: 8 Transmit Enable */ 57 uint32_t TXDIS:1; /**< bit: 9 Transmit Disable */ 58 uint32_t :5; /**< bit: 10..14 Reserved */ 59 uint32_t SWRST:1; /**< bit: 15 Software Reset */ 60 uint32_t :16; /**< bit: 16..31 Reserved */ 61 } bit; /**< Structure used for bit access */ 62 uint32_t reg; /**< Type used for register access */ 63 } SSC_CR_Type; 64 #endif 65 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 #define SSC_CR_OFFSET (0x00) /**< (SSC_CR) Control Register Offset */ 68 69 #define SSC_CR_RXEN_Pos 0 /**< (SSC_CR) Receive Enable Position */ 70 #define SSC_CR_RXEN_Msk (_U_(0x1) << SSC_CR_RXEN_Pos) /**< (SSC_CR) Receive Enable Mask */ 71 #define SSC_CR_RXEN SSC_CR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_RXEN_Msk instead */ 72 #define SSC_CR_RXDIS_Pos 1 /**< (SSC_CR) Receive Disable Position */ 73 #define SSC_CR_RXDIS_Msk (_U_(0x1) << SSC_CR_RXDIS_Pos) /**< (SSC_CR) Receive Disable Mask */ 74 #define SSC_CR_RXDIS SSC_CR_RXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_RXDIS_Msk instead */ 75 #define SSC_CR_TXEN_Pos 8 /**< (SSC_CR) Transmit Enable Position */ 76 #define SSC_CR_TXEN_Msk (_U_(0x1) << SSC_CR_TXEN_Pos) /**< (SSC_CR) Transmit Enable Mask */ 77 #define SSC_CR_TXEN SSC_CR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_TXEN_Msk instead */ 78 #define SSC_CR_TXDIS_Pos 9 /**< (SSC_CR) Transmit Disable Position */ 79 #define SSC_CR_TXDIS_Msk (_U_(0x1) << SSC_CR_TXDIS_Pos) /**< (SSC_CR) Transmit Disable Mask */ 80 #define SSC_CR_TXDIS SSC_CR_TXDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_TXDIS_Msk instead */ 81 #define SSC_CR_SWRST_Pos 15 /**< (SSC_CR) Software Reset Position */ 82 #define SSC_CR_SWRST_Msk (_U_(0x1) << SSC_CR_SWRST_Pos) /**< (SSC_CR) Software Reset Mask */ 83 #define SSC_CR_SWRST SSC_CR_SWRST_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_CR_SWRST_Msk instead */ 84 #define SSC_CR_MASK _U_(0x8303) /**< \deprecated (SSC_CR) Register MASK (Use SSC_CR_Msk instead) */ 85 #define SSC_CR_Msk _U_(0x8303) /**< (SSC_CR) Register Mask */ 86 87 88 /* -------- SSC_CMR : (SSC Offset: 0x04) (R/W 32) Clock Mode Register -------- */ 89 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 90 #if COMPONENT_TYPEDEF_STYLE == 'N' 91 typedef union { 92 struct { 93 uint32_t DIV:12; /**< bit: 0..11 Clock Divider */ 94 uint32_t :20; /**< bit: 12..31 Reserved */ 95 } bit; /**< Structure used for bit access */ 96 uint32_t reg; /**< Type used for register access */ 97 } SSC_CMR_Type; 98 #endif 99 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 100 101 #define SSC_CMR_OFFSET (0x04) /**< (SSC_CMR) Clock Mode Register Offset */ 102 103 #define SSC_CMR_DIV_Pos 0 /**< (SSC_CMR) Clock Divider Position */ 104 #define SSC_CMR_DIV_Msk (_U_(0xFFF) << SSC_CMR_DIV_Pos) /**< (SSC_CMR) Clock Divider Mask */ 105 #define SSC_CMR_DIV(value) (SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos)) 106 #define SSC_CMR_MASK _U_(0xFFF) /**< \deprecated (SSC_CMR) Register MASK (Use SSC_CMR_Msk instead) */ 107 #define SSC_CMR_Msk _U_(0xFFF) /**< (SSC_CMR) Register Mask */ 108 109 110 /* -------- SSC_RCMR : (SSC Offset: 0x10) (R/W 32) Receive Clock Mode Register -------- */ 111 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 112 #if COMPONENT_TYPEDEF_STYLE == 'N' 113 typedef union { 114 struct { 115 uint32_t CKS:2; /**< bit: 0..1 Receive Clock Selection */ 116 uint32_t CKO:3; /**< bit: 2..4 Receive Clock Output Mode Selection */ 117 uint32_t CKI:1; /**< bit: 5 Receive Clock Inversion */ 118 uint32_t CKG:2; /**< bit: 6..7 Receive Clock Gating Selection */ 119 uint32_t START:4; /**< bit: 8..11 Receive Start Selection */ 120 uint32_t STOP:1; /**< bit: 12 Receive Stop Selection */ 121 uint32_t :3; /**< bit: 13..15 Reserved */ 122 uint32_t STTDLY:8; /**< bit: 16..23 Receive Start Delay */ 123 uint32_t PERIOD:8; /**< bit: 24..31 Receive Period Divider Selection */ 124 } bit; /**< Structure used for bit access */ 125 uint32_t reg; /**< Type used for register access */ 126 } SSC_RCMR_Type; 127 #endif 128 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 129 130 #define SSC_RCMR_OFFSET (0x10) /**< (SSC_RCMR) Receive Clock Mode Register Offset */ 131 132 #define SSC_RCMR_CKS_Pos 0 /**< (SSC_RCMR) Receive Clock Selection Position */ 133 #define SSC_RCMR_CKS_Msk (_U_(0x3) << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Receive Clock Selection Mask */ 134 #define SSC_RCMR_CKS(value) (SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos)) 135 #define SSC_RCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_RCMR) Divided Clock */ 136 #define SSC_RCMR_CKS_TK_Val _U_(0x1) /**< (SSC_RCMR) TK Clock signal */ 137 #define SSC_RCMR_CKS_RK_Val _U_(0x2) /**< (SSC_RCMR) RK pin */ 138 #define SSC_RCMR_CKS_MCK (SSC_RCMR_CKS_MCK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) Divided Clock Position */ 139 #define SSC_RCMR_CKS_TK (SSC_RCMR_CKS_TK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) TK Clock signal Position */ 140 #define SSC_RCMR_CKS_RK (SSC_RCMR_CKS_RK_Val << SSC_RCMR_CKS_Pos) /**< (SSC_RCMR) RK pin Position */ 141 #define SSC_RCMR_CKO_Pos 2 /**< (SSC_RCMR) Receive Clock Output Mode Selection Position */ 142 #define SSC_RCMR_CKO_Msk (_U_(0x7) << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock Output Mode Selection Mask */ 143 #define SSC_RCMR_CKO(value) (SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos)) 144 #define SSC_RCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_RCMR) None, RK pin is an input */ 145 #define SSC_RCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ 146 #define SSC_RCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ 147 #define SSC_RCMR_CKO_NONE (SSC_RCMR_CKO_NONE_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) None, RK pin is an input Position */ 148 #define SSC_RCMR_CKO_CONTINUOUS (SSC_RCMR_CKO_CONTINUOUS_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Continuous Receive Clock, RK pin is an output Position */ 149 #define SSC_RCMR_CKO_TRANSFER (SSC_RCMR_CKO_TRANSFER_Val << SSC_RCMR_CKO_Pos) /**< (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output Position */ 150 #define SSC_RCMR_CKI_Pos 5 /**< (SSC_RCMR) Receive Clock Inversion Position */ 151 #define SSC_RCMR_CKI_Msk (_U_(0x1) << SSC_RCMR_CKI_Pos) /**< (SSC_RCMR) Receive Clock Inversion Mask */ 152 #define SSC_RCMR_CKI SSC_RCMR_CKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RCMR_CKI_Msk instead */ 153 #define SSC_RCMR_CKG_Pos 6 /**< (SSC_RCMR) Receive Clock Gating Selection Position */ 154 #define SSC_RCMR_CKG_Msk (_U_(0x3) << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock Gating Selection Mask */ 155 #define SSC_RCMR_CKG(value) (SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos)) 156 #define SSC_RCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) None */ 157 #define SSC_RCMR_CKG_EN_RF_LOW_Val _U_(0x1) /**< (SSC_RCMR) Receive Clock enabled only if RF Low */ 158 #define SSC_RCMR_CKG_EN_RF_HIGH_Val _U_(0x2) /**< (SSC_RCMR) Receive Clock enabled only if RF High */ 159 #define SSC_RCMR_CKG_CONTINUOUS (SSC_RCMR_CKG_CONTINUOUS_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) None Position */ 160 #define SSC_RCMR_CKG_EN_RF_LOW (SSC_RCMR_CKG_EN_RF_LOW_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF Low Position */ 161 #define SSC_RCMR_CKG_EN_RF_HIGH (SSC_RCMR_CKG_EN_RF_HIGH_Val << SSC_RCMR_CKG_Pos) /**< (SSC_RCMR) Receive Clock enabled only if RF High Position */ 162 #define SSC_RCMR_START_Pos 8 /**< (SSC_RCMR) Receive Start Selection Position */ 163 #define SSC_RCMR_START_Msk (_U_(0xF) << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Receive Start Selection Mask */ 164 #define SSC_RCMR_START(value) (SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos)) 165 #define SSC_RCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ 166 #define SSC_RCMR_START_TRANSMIT_Val _U_(0x1) /**< (SSC_RCMR) Transmit start */ 167 #define SSC_RCMR_START_RF_LOW_Val _U_(0x2) /**< (SSC_RCMR) Detection of a low level on RF signal */ 168 #define SSC_RCMR_START_RF_HIGH_Val _U_(0x3) /**< (SSC_RCMR) Detection of a high level on RF signal */ 169 #define SSC_RCMR_START_RF_FALLING_Val _U_(0x4) /**< (SSC_RCMR) Detection of a falling edge on RF signal */ 170 #define SSC_RCMR_START_RF_RISING_Val _U_(0x5) /**< (SSC_RCMR) Detection of a rising edge on RF signal */ 171 #define SSC_RCMR_START_RF_LEVEL_Val _U_(0x6) /**< (SSC_RCMR) Detection of any level change on RF signal */ 172 #define SSC_RCMR_START_RF_EDGE_Val _U_(0x7) /**< (SSC_RCMR) Detection of any edge on RF signal */ 173 #define SSC_RCMR_START_CMP_0_Val _U_(0x8) /**< (SSC_RCMR) Compare 0 */ 174 #define SSC_RCMR_START_CONTINUOUS (SSC_RCMR_START_CONTINUOUS_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Position */ 175 #define SSC_RCMR_START_TRANSMIT (SSC_RCMR_START_TRANSMIT_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Transmit start Position */ 176 #define SSC_RCMR_START_RF_LOW (SSC_RCMR_START_RF_LOW_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a low level on RF signal Position */ 177 #define SSC_RCMR_START_RF_HIGH (SSC_RCMR_START_RF_HIGH_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a high level on RF signal Position */ 178 #define SSC_RCMR_START_RF_FALLING (SSC_RCMR_START_RF_FALLING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a falling edge on RF signal Position */ 179 #define SSC_RCMR_START_RF_RISING (SSC_RCMR_START_RF_RISING_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of a rising edge on RF signal Position */ 180 #define SSC_RCMR_START_RF_LEVEL (SSC_RCMR_START_RF_LEVEL_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any level change on RF signal Position */ 181 #define SSC_RCMR_START_RF_EDGE (SSC_RCMR_START_RF_EDGE_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Detection of any edge on RF signal Position */ 182 #define SSC_RCMR_START_CMP_0 (SSC_RCMR_START_CMP_0_Val << SSC_RCMR_START_Pos) /**< (SSC_RCMR) Compare 0 Position */ 183 #define SSC_RCMR_STOP_Pos 12 /**< (SSC_RCMR) Receive Stop Selection Position */ 184 #define SSC_RCMR_STOP_Msk (_U_(0x1) << SSC_RCMR_STOP_Pos) /**< (SSC_RCMR) Receive Stop Selection Mask */ 185 #define SSC_RCMR_STOP SSC_RCMR_STOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RCMR_STOP_Msk instead */ 186 #define SSC_RCMR_STTDLY_Pos 16 /**< (SSC_RCMR) Receive Start Delay Position */ 187 #define SSC_RCMR_STTDLY_Msk (_U_(0xFF) << SSC_RCMR_STTDLY_Pos) /**< (SSC_RCMR) Receive Start Delay Mask */ 188 #define SSC_RCMR_STTDLY(value) (SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos)) 189 #define SSC_RCMR_PERIOD_Pos 24 /**< (SSC_RCMR) Receive Period Divider Selection Position */ 190 #define SSC_RCMR_PERIOD_Msk (_U_(0xFF) << SSC_RCMR_PERIOD_Pos) /**< (SSC_RCMR) Receive Period Divider Selection Mask */ 191 #define SSC_RCMR_PERIOD(value) (SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos)) 192 #define SSC_RCMR_MASK _U_(0xFFFF1FFF) /**< \deprecated (SSC_RCMR) Register MASK (Use SSC_RCMR_Msk instead) */ 193 #define SSC_RCMR_Msk _U_(0xFFFF1FFF) /**< (SSC_RCMR) Register Mask */ 194 195 196 /* -------- SSC_RFMR : (SSC Offset: 0x14) (R/W 32) Receive Frame Mode Register -------- */ 197 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 198 #if COMPONENT_TYPEDEF_STYLE == 'N' 199 typedef union { 200 struct { 201 uint32_t DATLEN:5; /**< bit: 0..4 Data Length */ 202 uint32_t LOOP:1; /**< bit: 5 Loop Mode */ 203 uint32_t :1; /**< bit: 6 Reserved */ 204 uint32_t MSBF:1; /**< bit: 7 Most Significant Bit First */ 205 uint32_t DATNB:4; /**< bit: 8..11 Data Number per Frame */ 206 uint32_t :4; /**< bit: 12..15 Reserved */ 207 uint32_t FSLEN:4; /**< bit: 16..19 Receive Frame Sync Length */ 208 uint32_t FSOS:3; /**< bit: 20..22 Receive Frame Sync Output Selection */ 209 uint32_t :1; /**< bit: 23 Reserved */ 210 uint32_t FSEDGE:1; /**< bit: 24 Frame Sync Edge Detection */ 211 uint32_t :3; /**< bit: 25..27 Reserved */ 212 uint32_t FSLEN_EXT:4; /**< bit: 28..31 FSLEN Field Extension */ 213 } bit; /**< Structure used for bit access */ 214 uint32_t reg; /**< Type used for register access */ 215 } SSC_RFMR_Type; 216 #endif 217 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 218 219 #define SSC_RFMR_OFFSET (0x14) /**< (SSC_RFMR) Receive Frame Mode Register Offset */ 220 221 #define SSC_RFMR_DATLEN_Pos 0 /**< (SSC_RFMR) Data Length Position */ 222 #define SSC_RFMR_DATLEN_Msk (_U_(0x1F) << SSC_RFMR_DATLEN_Pos) /**< (SSC_RFMR) Data Length Mask */ 223 #define SSC_RFMR_DATLEN(value) (SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos)) 224 #define SSC_RFMR_LOOP_Pos 5 /**< (SSC_RFMR) Loop Mode Position */ 225 #define SSC_RFMR_LOOP_Msk (_U_(0x1) << SSC_RFMR_LOOP_Pos) /**< (SSC_RFMR) Loop Mode Mask */ 226 #define SSC_RFMR_LOOP SSC_RFMR_LOOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RFMR_LOOP_Msk instead */ 227 #define SSC_RFMR_MSBF_Pos 7 /**< (SSC_RFMR) Most Significant Bit First Position */ 228 #define SSC_RFMR_MSBF_Msk (_U_(0x1) << SSC_RFMR_MSBF_Pos) /**< (SSC_RFMR) Most Significant Bit First Mask */ 229 #define SSC_RFMR_MSBF SSC_RFMR_MSBF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RFMR_MSBF_Msk instead */ 230 #define SSC_RFMR_DATNB_Pos 8 /**< (SSC_RFMR) Data Number per Frame Position */ 231 #define SSC_RFMR_DATNB_Msk (_U_(0xF) << SSC_RFMR_DATNB_Pos) /**< (SSC_RFMR) Data Number per Frame Mask */ 232 #define SSC_RFMR_DATNB(value) (SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos)) 233 #define SSC_RFMR_FSLEN_Pos 16 /**< (SSC_RFMR) Receive Frame Sync Length Position */ 234 #define SSC_RFMR_FSLEN_Msk (_U_(0xF) << SSC_RFMR_FSLEN_Pos) /**< (SSC_RFMR) Receive Frame Sync Length Mask */ 235 #define SSC_RFMR_FSLEN(value) (SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos)) 236 #define SSC_RFMR_FSOS_Pos 20 /**< (SSC_RFMR) Receive Frame Sync Output Selection Position */ 237 #define SSC_RFMR_FSOS_Msk (_U_(0x7) << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Receive Frame Sync Output Selection Mask */ 238 #define SSC_RFMR_FSOS(value) (SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos)) 239 #define SSC_RFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_RFMR) None, RF pin is an input */ 240 #define SSC_RFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Pulse, RF pin is an output */ 241 #define SSC_RFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_RFMR) Positive Pulse, RF pin is an output */ 242 #define SSC_RFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ 243 #define SSC_RFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output */ 244 #define SSC_RFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ 245 #define SSC_RFMR_FSOS_NONE (SSC_RFMR_FSOS_NONE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) None, RF pin is an input Position */ 246 #define SSC_RFMR_FSOS_NEGATIVE (SSC_RFMR_FSOS_NEGATIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Negative Pulse, RF pin is an output Position */ 247 #define SSC_RFMR_FSOS_POSITIVE (SSC_RFMR_FSOS_POSITIVE_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Positive Pulse, RF pin is an output Position */ 248 #define SSC_RFMR_FSOS_LOW (SSC_RFMR_FSOS_LOW_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven Low during data transfer, RF pin is an output Position */ 249 #define SSC_RFMR_FSOS_HIGH (SSC_RFMR_FSOS_HIGH_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Driven High during data transfer, RF pin is an output Position */ 250 #define SSC_RFMR_FSOS_TOGGLING (SSC_RFMR_FSOS_TOGGLING_Val << SSC_RFMR_FSOS_Pos) /**< (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output Position */ 251 #define SSC_RFMR_FSEDGE_Pos 24 /**< (SSC_RFMR) Frame Sync Edge Detection Position */ 252 #define SSC_RFMR_FSEDGE_Msk (_U_(0x1) << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Frame Sync Edge Detection Mask */ 253 #define SSC_RFMR_FSEDGE SSC_RFMR_FSEDGE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_RFMR_FSEDGE_Msk instead */ 254 #define SSC_RFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_RFMR) Positive Edge Detection */ 255 #define SSC_RFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_RFMR) Negative Edge Detection */ 256 #define SSC_RFMR_FSEDGE_POSITIVE (SSC_RFMR_FSEDGE_POSITIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Positive Edge Detection Position */ 257 #define SSC_RFMR_FSEDGE_NEGATIVE (SSC_RFMR_FSEDGE_NEGATIVE_Val << SSC_RFMR_FSEDGE_Pos) /**< (SSC_RFMR) Negative Edge Detection Position */ 258 #define SSC_RFMR_FSLEN_EXT_Pos 28 /**< (SSC_RFMR) FSLEN Field Extension Position */ 259 #define SSC_RFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_RFMR_FSLEN_EXT_Pos) /**< (SSC_RFMR) FSLEN Field Extension Mask */ 260 #define SSC_RFMR_FSLEN_EXT(value) (SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos)) 261 #define SSC_RFMR_MASK _U_(0xF17F0FBF) /**< \deprecated (SSC_RFMR) Register MASK (Use SSC_RFMR_Msk instead) */ 262 #define SSC_RFMR_Msk _U_(0xF17F0FBF) /**< (SSC_RFMR) Register Mask */ 263 264 265 /* -------- SSC_TCMR : (SSC Offset: 0x18) (R/W 32) Transmit Clock Mode Register -------- */ 266 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 267 #if COMPONENT_TYPEDEF_STYLE == 'N' 268 typedef union { 269 struct { 270 uint32_t CKS:2; /**< bit: 0..1 Transmit Clock Selection */ 271 uint32_t CKO:3; /**< bit: 2..4 Transmit Clock Output Mode Selection */ 272 uint32_t CKI:1; /**< bit: 5 Transmit Clock Inversion */ 273 uint32_t CKG:2; /**< bit: 6..7 Transmit Clock Gating Selection */ 274 uint32_t START:4; /**< bit: 8..11 Transmit Start Selection */ 275 uint32_t :4; /**< bit: 12..15 Reserved */ 276 uint32_t STTDLY:8; /**< bit: 16..23 Transmit Start Delay */ 277 uint32_t PERIOD:8; /**< bit: 24..31 Transmit Period Divider Selection */ 278 } bit; /**< Structure used for bit access */ 279 uint32_t reg; /**< Type used for register access */ 280 } SSC_TCMR_Type; 281 #endif 282 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 283 284 #define SSC_TCMR_OFFSET (0x18) /**< (SSC_TCMR) Transmit Clock Mode Register Offset */ 285 286 #define SSC_TCMR_CKS_Pos 0 /**< (SSC_TCMR) Transmit Clock Selection Position */ 287 #define SSC_TCMR_CKS_Msk (_U_(0x3) << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Transmit Clock Selection Mask */ 288 #define SSC_TCMR_CKS(value) (SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos)) 289 #define SSC_TCMR_CKS_MCK_Val _U_(0x0) /**< (SSC_TCMR) Divided Clock */ 290 #define SSC_TCMR_CKS_RK_Val _U_(0x1) /**< (SSC_TCMR) RK Clock signal */ 291 #define SSC_TCMR_CKS_TK_Val _U_(0x2) /**< (SSC_TCMR) TK pin */ 292 #define SSC_TCMR_CKS_MCK (SSC_TCMR_CKS_MCK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) Divided Clock Position */ 293 #define SSC_TCMR_CKS_RK (SSC_TCMR_CKS_RK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) RK Clock signal Position */ 294 #define SSC_TCMR_CKS_TK (SSC_TCMR_CKS_TK_Val << SSC_TCMR_CKS_Pos) /**< (SSC_TCMR) TK pin Position */ 295 #define SSC_TCMR_CKO_Pos 2 /**< (SSC_TCMR) Transmit Clock Output Mode Selection Position */ 296 #define SSC_TCMR_CKO_Msk (_U_(0x7) << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock Output Mode Selection Mask */ 297 #define SSC_TCMR_CKO(value) (SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos)) 298 #define SSC_TCMR_CKO_NONE_Val _U_(0x0) /**< (SSC_TCMR) None, TK pin is an input */ 299 #define SSC_TCMR_CKO_CONTINUOUS_Val _U_(0x1) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ 300 #define SSC_TCMR_CKO_TRANSFER_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ 301 #define SSC_TCMR_CKO_NONE (SSC_TCMR_CKO_NONE_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) None, TK pin is an input Position */ 302 #define SSC_TCMR_CKO_CONTINUOUS (SSC_TCMR_CKO_CONTINUOUS_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Continuous Transmit Clock, TK pin is an output Position */ 303 #define SSC_TCMR_CKO_TRANSFER (SSC_TCMR_CKO_TRANSFER_Val << SSC_TCMR_CKO_Pos) /**< (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output Position */ 304 #define SSC_TCMR_CKI_Pos 5 /**< (SSC_TCMR) Transmit Clock Inversion Position */ 305 #define SSC_TCMR_CKI_Msk (_U_(0x1) << SSC_TCMR_CKI_Pos) /**< (SSC_TCMR) Transmit Clock Inversion Mask */ 306 #define SSC_TCMR_CKI SSC_TCMR_CKI_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TCMR_CKI_Msk instead */ 307 #define SSC_TCMR_CKG_Pos 6 /**< (SSC_TCMR) Transmit Clock Gating Selection Position */ 308 #define SSC_TCMR_CKG_Msk (_U_(0x3) << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock Gating Selection Mask */ 309 #define SSC_TCMR_CKG(value) (SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos)) 310 #define SSC_TCMR_CKG_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) None */ 311 #define SSC_TCMR_CKG_EN_TF_LOW_Val _U_(0x1) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low */ 312 #define SSC_TCMR_CKG_EN_TF_HIGH_Val _U_(0x2) /**< (SSC_TCMR) Transmit Clock enabled only if TF High */ 313 #define SSC_TCMR_CKG_CONTINUOUS (SSC_TCMR_CKG_CONTINUOUS_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) None Position */ 314 #define SSC_TCMR_CKG_EN_TF_LOW (SSC_TCMR_CKG_EN_TF_LOW_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF Low Position */ 315 #define SSC_TCMR_CKG_EN_TF_HIGH (SSC_TCMR_CKG_EN_TF_HIGH_Val << SSC_TCMR_CKG_Pos) /**< (SSC_TCMR) Transmit Clock enabled only if TF High Position */ 316 #define SSC_TCMR_START_Pos 8 /**< (SSC_TCMR) Transmit Start Selection Position */ 317 #define SSC_TCMR_START_Msk (_U_(0xF) << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Transmit Start Selection Mask */ 318 #define SSC_TCMR_START(value) (SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos)) 319 #define SSC_TCMR_START_CONTINUOUS_Val _U_(0x0) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ 320 #define SSC_TCMR_START_RECEIVE_Val _U_(0x1) /**< (SSC_TCMR) Receive start */ 321 #define SSC_TCMR_START_TF_LOW_Val _U_(0x2) /**< (SSC_TCMR) Detection of a low level on TF signal */ 322 #define SSC_TCMR_START_TF_HIGH_Val _U_(0x3) /**< (SSC_TCMR) Detection of a high level on TF signal */ 323 #define SSC_TCMR_START_TF_FALLING_Val _U_(0x4) /**< (SSC_TCMR) Detection of a falling edge on TF signal */ 324 #define SSC_TCMR_START_TF_RISING_Val _U_(0x5) /**< (SSC_TCMR) Detection of a rising edge on TF signal */ 325 #define SSC_TCMR_START_TF_LEVEL_Val _U_(0x6) /**< (SSC_TCMR) Detection of any level change on TF signal */ 326 #define SSC_TCMR_START_TF_EDGE_Val _U_(0x7) /**< (SSC_TCMR) Detection of any edge on TF signal */ 327 #define SSC_TCMR_START_CONTINUOUS (SSC_TCMR_START_CONTINUOUS_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data Position */ 328 #define SSC_TCMR_START_RECEIVE (SSC_TCMR_START_RECEIVE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Receive start Position */ 329 #define SSC_TCMR_START_TF_LOW (SSC_TCMR_START_TF_LOW_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a low level on TF signal Position */ 330 #define SSC_TCMR_START_TF_HIGH (SSC_TCMR_START_TF_HIGH_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a high level on TF signal Position */ 331 #define SSC_TCMR_START_TF_FALLING (SSC_TCMR_START_TF_FALLING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a falling edge on TF signal Position */ 332 #define SSC_TCMR_START_TF_RISING (SSC_TCMR_START_TF_RISING_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of a rising edge on TF signal Position */ 333 #define SSC_TCMR_START_TF_LEVEL (SSC_TCMR_START_TF_LEVEL_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any level change on TF signal Position */ 334 #define SSC_TCMR_START_TF_EDGE (SSC_TCMR_START_TF_EDGE_Val << SSC_TCMR_START_Pos) /**< (SSC_TCMR) Detection of any edge on TF signal Position */ 335 #define SSC_TCMR_STTDLY_Pos 16 /**< (SSC_TCMR) Transmit Start Delay Position */ 336 #define SSC_TCMR_STTDLY_Msk (_U_(0xFF) << SSC_TCMR_STTDLY_Pos) /**< (SSC_TCMR) Transmit Start Delay Mask */ 337 #define SSC_TCMR_STTDLY(value) (SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos)) 338 #define SSC_TCMR_PERIOD_Pos 24 /**< (SSC_TCMR) Transmit Period Divider Selection Position */ 339 #define SSC_TCMR_PERIOD_Msk (_U_(0xFF) << SSC_TCMR_PERIOD_Pos) /**< (SSC_TCMR) Transmit Period Divider Selection Mask */ 340 #define SSC_TCMR_PERIOD(value) (SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos)) 341 #define SSC_TCMR_MASK _U_(0xFFFF0FFF) /**< \deprecated (SSC_TCMR) Register MASK (Use SSC_TCMR_Msk instead) */ 342 #define SSC_TCMR_Msk _U_(0xFFFF0FFF) /**< (SSC_TCMR) Register Mask */ 343 344 345 /* -------- SSC_TFMR : (SSC Offset: 0x1c) (R/W 32) Transmit Frame Mode Register -------- */ 346 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 347 #if COMPONENT_TYPEDEF_STYLE == 'N' 348 typedef union { 349 struct { 350 uint32_t DATLEN:5; /**< bit: 0..4 Data Length */ 351 uint32_t DATDEF:1; /**< bit: 5 Data Default Value */ 352 uint32_t :1; /**< bit: 6 Reserved */ 353 uint32_t MSBF:1; /**< bit: 7 Most Significant Bit First */ 354 uint32_t DATNB:4; /**< bit: 8..11 Data Number per Frame */ 355 uint32_t :4; /**< bit: 12..15 Reserved */ 356 uint32_t FSLEN:4; /**< bit: 16..19 Transmit Frame Sync Length */ 357 uint32_t FSOS:3; /**< bit: 20..22 Transmit Frame Sync Output Selection */ 358 uint32_t FSDEN:1; /**< bit: 23 Frame Sync Data Enable */ 359 uint32_t FSEDGE:1; /**< bit: 24 Frame Sync Edge Detection */ 360 uint32_t :3; /**< bit: 25..27 Reserved */ 361 uint32_t FSLEN_EXT:4; /**< bit: 28..31 FSLEN Field Extension */ 362 } bit; /**< Structure used for bit access */ 363 uint32_t reg; /**< Type used for register access */ 364 } SSC_TFMR_Type; 365 #endif 366 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 367 368 #define SSC_TFMR_OFFSET (0x1C) /**< (SSC_TFMR) Transmit Frame Mode Register Offset */ 369 370 #define SSC_TFMR_DATLEN_Pos 0 /**< (SSC_TFMR) Data Length Position */ 371 #define SSC_TFMR_DATLEN_Msk (_U_(0x1F) << SSC_TFMR_DATLEN_Pos) /**< (SSC_TFMR) Data Length Mask */ 372 #define SSC_TFMR_DATLEN(value) (SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos)) 373 #define SSC_TFMR_DATDEF_Pos 5 /**< (SSC_TFMR) Data Default Value Position */ 374 #define SSC_TFMR_DATDEF_Msk (_U_(0x1) << SSC_TFMR_DATDEF_Pos) /**< (SSC_TFMR) Data Default Value Mask */ 375 #define SSC_TFMR_DATDEF SSC_TFMR_DATDEF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_DATDEF_Msk instead */ 376 #define SSC_TFMR_MSBF_Pos 7 /**< (SSC_TFMR) Most Significant Bit First Position */ 377 #define SSC_TFMR_MSBF_Msk (_U_(0x1) << SSC_TFMR_MSBF_Pos) /**< (SSC_TFMR) Most Significant Bit First Mask */ 378 #define SSC_TFMR_MSBF SSC_TFMR_MSBF_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_MSBF_Msk instead */ 379 #define SSC_TFMR_DATNB_Pos 8 /**< (SSC_TFMR) Data Number per Frame Position */ 380 #define SSC_TFMR_DATNB_Msk (_U_(0xF) << SSC_TFMR_DATNB_Pos) /**< (SSC_TFMR) Data Number per Frame Mask */ 381 #define SSC_TFMR_DATNB(value) (SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos)) 382 #define SSC_TFMR_FSLEN_Pos 16 /**< (SSC_TFMR) Transmit Frame Sync Length Position */ 383 #define SSC_TFMR_FSLEN_Msk (_U_(0xF) << SSC_TFMR_FSLEN_Pos) /**< (SSC_TFMR) Transmit Frame Sync Length Mask */ 384 #define SSC_TFMR_FSLEN(value) (SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos)) 385 #define SSC_TFMR_FSOS_Pos 20 /**< (SSC_TFMR) Transmit Frame Sync Output Selection Position */ 386 #define SSC_TFMR_FSOS_Msk (_U_(0x7) << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Transmit Frame Sync Output Selection Mask */ 387 #define SSC_TFMR_FSOS(value) (SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos)) 388 #define SSC_TFMR_FSOS_NONE_Val _U_(0x0) /**< (SSC_TFMR) None, TF pin is an input */ 389 #define SSC_TFMR_FSOS_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Pulse, TF pin is an output */ 390 #define SSC_TFMR_FSOS_POSITIVE_Val _U_(0x2) /**< (SSC_TFMR) Positive Pulse, TF pin is an output */ 391 #define SSC_TFMR_FSOS_LOW_Val _U_(0x3) /**< (SSC_TFMR) Driven Low during data transfer */ 392 #define SSC_TFMR_FSOS_HIGH_Val _U_(0x4) /**< (SSC_TFMR) Driven High during data transfer */ 393 #define SSC_TFMR_FSOS_TOGGLING_Val _U_(0x5) /**< (SSC_TFMR) Toggling at each start of data transfer */ 394 #define SSC_TFMR_FSOS_NONE (SSC_TFMR_FSOS_NONE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) None, TF pin is an input Position */ 395 #define SSC_TFMR_FSOS_NEGATIVE (SSC_TFMR_FSOS_NEGATIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Negative Pulse, TF pin is an output Position */ 396 #define SSC_TFMR_FSOS_POSITIVE (SSC_TFMR_FSOS_POSITIVE_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Positive Pulse, TF pin is an output Position */ 397 #define SSC_TFMR_FSOS_LOW (SSC_TFMR_FSOS_LOW_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven Low during data transfer Position */ 398 #define SSC_TFMR_FSOS_HIGH (SSC_TFMR_FSOS_HIGH_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Driven High during data transfer Position */ 399 #define SSC_TFMR_FSOS_TOGGLING (SSC_TFMR_FSOS_TOGGLING_Val << SSC_TFMR_FSOS_Pos) /**< (SSC_TFMR) Toggling at each start of data transfer Position */ 400 #define SSC_TFMR_FSDEN_Pos 23 /**< (SSC_TFMR) Frame Sync Data Enable Position */ 401 #define SSC_TFMR_FSDEN_Msk (_U_(0x1) << SSC_TFMR_FSDEN_Pos) /**< (SSC_TFMR) Frame Sync Data Enable Mask */ 402 #define SSC_TFMR_FSDEN SSC_TFMR_FSDEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_FSDEN_Msk instead */ 403 #define SSC_TFMR_FSEDGE_Pos 24 /**< (SSC_TFMR) Frame Sync Edge Detection Position */ 404 #define SSC_TFMR_FSEDGE_Msk (_U_(0x1) << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Frame Sync Edge Detection Mask */ 405 #define SSC_TFMR_FSEDGE SSC_TFMR_FSEDGE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_TFMR_FSEDGE_Msk instead */ 406 #define SSC_TFMR_FSEDGE_POSITIVE_Val _U_(0x0) /**< (SSC_TFMR) Positive Edge Detection */ 407 #define SSC_TFMR_FSEDGE_NEGATIVE_Val _U_(0x1) /**< (SSC_TFMR) Negative Edge Detection */ 408 #define SSC_TFMR_FSEDGE_POSITIVE (SSC_TFMR_FSEDGE_POSITIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Positive Edge Detection Position */ 409 #define SSC_TFMR_FSEDGE_NEGATIVE (SSC_TFMR_FSEDGE_NEGATIVE_Val << SSC_TFMR_FSEDGE_Pos) /**< (SSC_TFMR) Negative Edge Detection Position */ 410 #define SSC_TFMR_FSLEN_EXT_Pos 28 /**< (SSC_TFMR) FSLEN Field Extension Position */ 411 #define SSC_TFMR_FSLEN_EXT_Msk (_U_(0xF) << SSC_TFMR_FSLEN_EXT_Pos) /**< (SSC_TFMR) FSLEN Field Extension Mask */ 412 #define SSC_TFMR_FSLEN_EXT(value) (SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos)) 413 #define SSC_TFMR_MASK _U_(0xF1FF0FBF) /**< \deprecated (SSC_TFMR) Register MASK (Use SSC_TFMR_Msk instead) */ 414 #define SSC_TFMR_Msk _U_(0xF1FF0FBF) /**< (SSC_TFMR) Register Mask */ 415 416 417 /* -------- SSC_RHR : (SSC Offset: 0x20) (R/ 32) Receive Holding Register -------- */ 418 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 419 #if COMPONENT_TYPEDEF_STYLE == 'N' 420 typedef union { 421 struct { 422 uint32_t RDAT:32; /**< bit: 0..31 Receive Data */ 423 } bit; /**< Structure used for bit access */ 424 uint32_t reg; /**< Type used for register access */ 425 } SSC_RHR_Type; 426 #endif 427 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 428 429 #define SSC_RHR_OFFSET (0x20) /**< (SSC_RHR) Receive Holding Register Offset */ 430 431 #define SSC_RHR_RDAT_Pos 0 /**< (SSC_RHR) Receive Data Position */ 432 #define SSC_RHR_RDAT_Msk (_U_(0xFFFFFFFF) << SSC_RHR_RDAT_Pos) /**< (SSC_RHR) Receive Data Mask */ 433 #define SSC_RHR_RDAT(value) (SSC_RHR_RDAT_Msk & ((value) << SSC_RHR_RDAT_Pos)) 434 #define SSC_RHR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SSC_RHR) Register MASK (Use SSC_RHR_Msk instead) */ 435 #define SSC_RHR_Msk _U_(0xFFFFFFFF) /**< (SSC_RHR) Register Mask */ 436 437 438 /* -------- SSC_THR : (SSC Offset: 0x24) (/W 32) Transmit Holding Register -------- */ 439 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 440 #if COMPONENT_TYPEDEF_STYLE == 'N' 441 typedef union { 442 struct { 443 uint32_t TDAT:32; /**< bit: 0..31 Transmit Data */ 444 } bit; /**< Structure used for bit access */ 445 uint32_t reg; /**< Type used for register access */ 446 } SSC_THR_Type; 447 #endif 448 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 449 450 #define SSC_THR_OFFSET (0x24) /**< (SSC_THR) Transmit Holding Register Offset */ 451 452 #define SSC_THR_TDAT_Pos 0 /**< (SSC_THR) Transmit Data Position */ 453 #define SSC_THR_TDAT_Msk (_U_(0xFFFFFFFF) << SSC_THR_TDAT_Pos) /**< (SSC_THR) Transmit Data Mask */ 454 #define SSC_THR_TDAT(value) (SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos)) 455 #define SSC_THR_MASK _U_(0xFFFFFFFF) /**< \deprecated (SSC_THR) Register MASK (Use SSC_THR_Msk instead) */ 456 #define SSC_THR_Msk _U_(0xFFFFFFFF) /**< (SSC_THR) Register Mask */ 457 458 459 /* -------- SSC_RSHR : (SSC Offset: 0x30) (R/ 32) Receive Sync. Holding Register -------- */ 460 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 461 #if COMPONENT_TYPEDEF_STYLE == 'N' 462 typedef union { 463 struct { 464 uint32_t RSDAT:16; /**< bit: 0..15 Receive Synchronization Data */ 465 uint32_t :16; /**< bit: 16..31 Reserved */ 466 } bit; /**< Structure used for bit access */ 467 uint32_t reg; /**< Type used for register access */ 468 } SSC_RSHR_Type; 469 #endif 470 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 471 472 #define SSC_RSHR_OFFSET (0x30) /**< (SSC_RSHR) Receive Sync. Holding Register Offset */ 473 474 #define SSC_RSHR_RSDAT_Pos 0 /**< (SSC_RSHR) Receive Synchronization Data Position */ 475 #define SSC_RSHR_RSDAT_Msk (_U_(0xFFFF) << SSC_RSHR_RSDAT_Pos) /**< (SSC_RSHR) Receive Synchronization Data Mask */ 476 #define SSC_RSHR_RSDAT(value) (SSC_RSHR_RSDAT_Msk & ((value) << SSC_RSHR_RSDAT_Pos)) 477 #define SSC_RSHR_MASK _U_(0xFFFF) /**< \deprecated (SSC_RSHR) Register MASK (Use SSC_RSHR_Msk instead) */ 478 #define SSC_RSHR_Msk _U_(0xFFFF) /**< (SSC_RSHR) Register Mask */ 479 480 481 /* -------- SSC_TSHR : (SSC Offset: 0x34) (R/W 32) Transmit Sync. Holding Register -------- */ 482 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 483 #if COMPONENT_TYPEDEF_STYLE == 'N' 484 typedef union { 485 struct { 486 uint32_t TSDAT:16; /**< bit: 0..15 Transmit Synchronization Data */ 487 uint32_t :16; /**< bit: 16..31 Reserved */ 488 } bit; /**< Structure used for bit access */ 489 uint32_t reg; /**< Type used for register access */ 490 } SSC_TSHR_Type; 491 #endif 492 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 493 494 #define SSC_TSHR_OFFSET (0x34) /**< (SSC_TSHR) Transmit Sync. Holding Register Offset */ 495 496 #define SSC_TSHR_TSDAT_Pos 0 /**< (SSC_TSHR) Transmit Synchronization Data Position */ 497 #define SSC_TSHR_TSDAT_Msk (_U_(0xFFFF) << SSC_TSHR_TSDAT_Pos) /**< (SSC_TSHR) Transmit Synchronization Data Mask */ 498 #define SSC_TSHR_TSDAT(value) (SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos)) 499 #define SSC_TSHR_MASK _U_(0xFFFF) /**< \deprecated (SSC_TSHR) Register MASK (Use SSC_TSHR_Msk instead) */ 500 #define SSC_TSHR_Msk _U_(0xFFFF) /**< (SSC_TSHR) Register Mask */ 501 502 503 /* -------- SSC_RC0R : (SSC Offset: 0x38) (R/W 32) Receive Compare 0 Register -------- */ 504 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 505 #if COMPONENT_TYPEDEF_STYLE == 'N' 506 typedef union { 507 struct { 508 uint32_t CP0:16; /**< bit: 0..15 Receive Compare Data 0 */ 509 uint32_t :16; /**< bit: 16..31 Reserved */ 510 } bit; /**< Structure used for bit access */ 511 uint32_t reg; /**< Type used for register access */ 512 } SSC_RC0R_Type; 513 #endif 514 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 515 516 #define SSC_RC0R_OFFSET (0x38) /**< (SSC_RC0R) Receive Compare 0 Register Offset */ 517 518 #define SSC_RC0R_CP0_Pos 0 /**< (SSC_RC0R) Receive Compare Data 0 Position */ 519 #define SSC_RC0R_CP0_Msk (_U_(0xFFFF) << SSC_RC0R_CP0_Pos) /**< (SSC_RC0R) Receive Compare Data 0 Mask */ 520 #define SSC_RC0R_CP0(value) (SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos)) 521 #define SSC_RC0R_MASK _U_(0xFFFF) /**< \deprecated (SSC_RC0R) Register MASK (Use SSC_RC0R_Msk instead) */ 522 #define SSC_RC0R_Msk _U_(0xFFFF) /**< (SSC_RC0R) Register Mask */ 523 524 525 /* -------- SSC_RC1R : (SSC Offset: 0x3c) (R/W 32) Receive Compare 1 Register -------- */ 526 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 527 #if COMPONENT_TYPEDEF_STYLE == 'N' 528 typedef union { 529 struct { 530 uint32_t CP1:16; /**< bit: 0..15 Receive Compare Data 1 */ 531 uint32_t :16; /**< bit: 16..31 Reserved */ 532 } bit; /**< Structure used for bit access */ 533 uint32_t reg; /**< Type used for register access */ 534 } SSC_RC1R_Type; 535 #endif 536 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 537 538 #define SSC_RC1R_OFFSET (0x3C) /**< (SSC_RC1R) Receive Compare 1 Register Offset */ 539 540 #define SSC_RC1R_CP1_Pos 0 /**< (SSC_RC1R) Receive Compare Data 1 Position */ 541 #define SSC_RC1R_CP1_Msk (_U_(0xFFFF) << SSC_RC1R_CP1_Pos) /**< (SSC_RC1R) Receive Compare Data 1 Mask */ 542 #define SSC_RC1R_CP1(value) (SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos)) 543 #define SSC_RC1R_MASK _U_(0xFFFF) /**< \deprecated (SSC_RC1R) Register MASK (Use SSC_RC1R_Msk instead) */ 544 #define SSC_RC1R_Msk _U_(0xFFFF) /**< (SSC_RC1R) Register Mask */ 545 546 547 /* -------- SSC_SR : (SSC Offset: 0x40) (R/ 32) Status Register -------- */ 548 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 549 #if COMPONENT_TYPEDEF_STYLE == 'N' 550 typedef union { 551 struct { 552 uint32_t TXRDY:1; /**< bit: 0 Transmit Ready */ 553 uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty */ 554 uint32_t :2; /**< bit: 2..3 Reserved */ 555 uint32_t RXRDY:1; /**< bit: 4 Receive Ready */ 556 uint32_t OVRUN:1; /**< bit: 5 Receive Overrun */ 557 uint32_t :2; /**< bit: 6..7 Reserved */ 558 uint32_t CP0:1; /**< bit: 8 Compare 0 */ 559 uint32_t CP1:1; /**< bit: 9 Compare 1 */ 560 uint32_t TXSYN:1; /**< bit: 10 Transmit Sync */ 561 uint32_t RXSYN:1; /**< bit: 11 Receive Sync */ 562 uint32_t :4; /**< bit: 12..15 Reserved */ 563 uint32_t TXEN:1; /**< bit: 16 Transmit Enable */ 564 uint32_t RXEN:1; /**< bit: 17 Receive Enable */ 565 uint32_t :14; /**< bit: 18..31 Reserved */ 566 } bit; /**< Structure used for bit access */ 567 struct { 568 uint32_t :8; /**< bit: 0..7 Reserved */ 569 uint32_t CP:2; /**< bit: 8..9 Compare x */ 570 uint32_t :22; /**< bit: 10..31 Reserved */ 571 } vec; /**< Structure used for vec access */ 572 uint32_t reg; /**< Type used for register access */ 573 } SSC_SR_Type; 574 #endif 575 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 576 577 #define SSC_SR_OFFSET (0x40) /**< (SSC_SR) Status Register Offset */ 578 579 #define SSC_SR_TXRDY_Pos 0 /**< (SSC_SR) Transmit Ready Position */ 580 #define SSC_SR_TXRDY_Msk (_U_(0x1) << SSC_SR_TXRDY_Pos) /**< (SSC_SR) Transmit Ready Mask */ 581 #define SSC_SR_TXRDY SSC_SR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXRDY_Msk instead */ 582 #define SSC_SR_TXEMPTY_Pos 1 /**< (SSC_SR) Transmit Empty Position */ 583 #define SSC_SR_TXEMPTY_Msk (_U_(0x1) << SSC_SR_TXEMPTY_Pos) /**< (SSC_SR) Transmit Empty Mask */ 584 #define SSC_SR_TXEMPTY SSC_SR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXEMPTY_Msk instead */ 585 #define SSC_SR_RXRDY_Pos 4 /**< (SSC_SR) Receive Ready Position */ 586 #define SSC_SR_RXRDY_Msk (_U_(0x1) << SSC_SR_RXRDY_Pos) /**< (SSC_SR) Receive Ready Mask */ 587 #define SSC_SR_RXRDY SSC_SR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_RXRDY_Msk instead */ 588 #define SSC_SR_OVRUN_Pos 5 /**< (SSC_SR) Receive Overrun Position */ 589 #define SSC_SR_OVRUN_Msk (_U_(0x1) << SSC_SR_OVRUN_Pos) /**< (SSC_SR) Receive Overrun Mask */ 590 #define SSC_SR_OVRUN SSC_SR_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_OVRUN_Msk instead */ 591 #define SSC_SR_CP0_Pos 8 /**< (SSC_SR) Compare 0 Position */ 592 #define SSC_SR_CP0_Msk (_U_(0x1) << SSC_SR_CP0_Pos) /**< (SSC_SR) Compare 0 Mask */ 593 #define SSC_SR_CP0 SSC_SR_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_CP0_Msk instead */ 594 #define SSC_SR_CP1_Pos 9 /**< (SSC_SR) Compare 1 Position */ 595 #define SSC_SR_CP1_Msk (_U_(0x1) << SSC_SR_CP1_Pos) /**< (SSC_SR) Compare 1 Mask */ 596 #define SSC_SR_CP1 SSC_SR_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_CP1_Msk instead */ 597 #define SSC_SR_TXSYN_Pos 10 /**< (SSC_SR) Transmit Sync Position */ 598 #define SSC_SR_TXSYN_Msk (_U_(0x1) << SSC_SR_TXSYN_Pos) /**< (SSC_SR) Transmit Sync Mask */ 599 #define SSC_SR_TXSYN SSC_SR_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXSYN_Msk instead */ 600 #define SSC_SR_RXSYN_Pos 11 /**< (SSC_SR) Receive Sync Position */ 601 #define SSC_SR_RXSYN_Msk (_U_(0x1) << SSC_SR_RXSYN_Pos) /**< (SSC_SR) Receive Sync Mask */ 602 #define SSC_SR_RXSYN SSC_SR_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_RXSYN_Msk instead */ 603 #define SSC_SR_TXEN_Pos 16 /**< (SSC_SR) Transmit Enable Position */ 604 #define SSC_SR_TXEN_Msk (_U_(0x1) << SSC_SR_TXEN_Pos) /**< (SSC_SR) Transmit Enable Mask */ 605 #define SSC_SR_TXEN SSC_SR_TXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_TXEN_Msk instead */ 606 #define SSC_SR_RXEN_Pos 17 /**< (SSC_SR) Receive Enable Position */ 607 #define SSC_SR_RXEN_Msk (_U_(0x1) << SSC_SR_RXEN_Pos) /**< (SSC_SR) Receive Enable Mask */ 608 #define SSC_SR_RXEN SSC_SR_RXEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_SR_RXEN_Msk instead */ 609 #define SSC_SR_MASK _U_(0x30F33) /**< \deprecated (SSC_SR) Register MASK (Use SSC_SR_Msk instead) */ 610 #define SSC_SR_Msk _U_(0x30F33) /**< (SSC_SR) Register Mask */ 611 612 #define SSC_SR_CP_Pos 8 /**< (SSC_SR Position) Compare x */ 613 #define SSC_SR_CP_Msk (_U_(0x3) << SSC_SR_CP_Pos) /**< (SSC_SR Mask) CP */ 614 #define SSC_SR_CP(value) (SSC_SR_CP_Msk & ((value) << SSC_SR_CP_Pos)) 615 616 /* -------- SSC_IER : (SSC Offset: 0x44) (/W 32) Interrupt Enable Register -------- */ 617 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 618 #if COMPONENT_TYPEDEF_STYLE == 'N' 619 typedef union { 620 struct { 621 uint32_t TXRDY:1; /**< bit: 0 Transmit Ready Interrupt Enable */ 622 uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty Interrupt Enable */ 623 uint32_t :2; /**< bit: 2..3 Reserved */ 624 uint32_t RXRDY:1; /**< bit: 4 Receive Ready Interrupt Enable */ 625 uint32_t OVRUN:1; /**< bit: 5 Receive Overrun Interrupt Enable */ 626 uint32_t :2; /**< bit: 6..7 Reserved */ 627 uint32_t CP0:1; /**< bit: 8 Compare 0 Interrupt Enable */ 628 uint32_t CP1:1; /**< bit: 9 Compare 1 Interrupt Enable */ 629 uint32_t TXSYN:1; /**< bit: 10 Tx Sync Interrupt Enable */ 630 uint32_t RXSYN:1; /**< bit: 11 Rx Sync Interrupt Enable */ 631 uint32_t :20; /**< bit: 12..31 Reserved */ 632 } bit; /**< Structure used for bit access */ 633 struct { 634 uint32_t :8; /**< bit: 0..7 Reserved */ 635 uint32_t CP:2; /**< bit: 8..9 Compare x Interrupt Enable */ 636 uint32_t :22; /**< bit: 10..31 Reserved */ 637 } vec; /**< Structure used for vec access */ 638 uint32_t reg; /**< Type used for register access */ 639 } SSC_IER_Type; 640 #endif 641 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 642 643 #define SSC_IER_OFFSET (0x44) /**< (SSC_IER) Interrupt Enable Register Offset */ 644 645 #define SSC_IER_TXRDY_Pos 0 /**< (SSC_IER) Transmit Ready Interrupt Enable Position */ 646 #define SSC_IER_TXRDY_Msk (_U_(0x1) << SSC_IER_TXRDY_Pos) /**< (SSC_IER) Transmit Ready Interrupt Enable Mask */ 647 #define SSC_IER_TXRDY SSC_IER_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_TXRDY_Msk instead */ 648 #define SSC_IER_TXEMPTY_Pos 1 /**< (SSC_IER) Transmit Empty Interrupt Enable Position */ 649 #define SSC_IER_TXEMPTY_Msk (_U_(0x1) << SSC_IER_TXEMPTY_Pos) /**< (SSC_IER) Transmit Empty Interrupt Enable Mask */ 650 #define SSC_IER_TXEMPTY SSC_IER_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_TXEMPTY_Msk instead */ 651 #define SSC_IER_RXRDY_Pos 4 /**< (SSC_IER) Receive Ready Interrupt Enable Position */ 652 #define SSC_IER_RXRDY_Msk (_U_(0x1) << SSC_IER_RXRDY_Pos) /**< (SSC_IER) Receive Ready Interrupt Enable Mask */ 653 #define SSC_IER_RXRDY SSC_IER_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_RXRDY_Msk instead */ 654 #define SSC_IER_OVRUN_Pos 5 /**< (SSC_IER) Receive Overrun Interrupt Enable Position */ 655 #define SSC_IER_OVRUN_Msk (_U_(0x1) << SSC_IER_OVRUN_Pos) /**< (SSC_IER) Receive Overrun Interrupt Enable Mask */ 656 #define SSC_IER_OVRUN SSC_IER_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_OVRUN_Msk instead */ 657 #define SSC_IER_CP0_Pos 8 /**< (SSC_IER) Compare 0 Interrupt Enable Position */ 658 #define SSC_IER_CP0_Msk (_U_(0x1) << SSC_IER_CP0_Pos) /**< (SSC_IER) Compare 0 Interrupt Enable Mask */ 659 #define SSC_IER_CP0 SSC_IER_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_CP0_Msk instead */ 660 #define SSC_IER_CP1_Pos 9 /**< (SSC_IER) Compare 1 Interrupt Enable Position */ 661 #define SSC_IER_CP1_Msk (_U_(0x1) << SSC_IER_CP1_Pos) /**< (SSC_IER) Compare 1 Interrupt Enable Mask */ 662 #define SSC_IER_CP1 SSC_IER_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_CP1_Msk instead */ 663 #define SSC_IER_TXSYN_Pos 10 /**< (SSC_IER) Tx Sync Interrupt Enable Position */ 664 #define SSC_IER_TXSYN_Msk (_U_(0x1) << SSC_IER_TXSYN_Pos) /**< (SSC_IER) Tx Sync Interrupt Enable Mask */ 665 #define SSC_IER_TXSYN SSC_IER_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_TXSYN_Msk instead */ 666 #define SSC_IER_RXSYN_Pos 11 /**< (SSC_IER) Rx Sync Interrupt Enable Position */ 667 #define SSC_IER_RXSYN_Msk (_U_(0x1) << SSC_IER_RXSYN_Pos) /**< (SSC_IER) Rx Sync Interrupt Enable Mask */ 668 #define SSC_IER_RXSYN SSC_IER_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IER_RXSYN_Msk instead */ 669 #define SSC_IER_MASK _U_(0xF33) /**< \deprecated (SSC_IER) Register MASK (Use SSC_IER_Msk instead) */ 670 #define SSC_IER_Msk _U_(0xF33) /**< (SSC_IER) Register Mask */ 671 672 #define SSC_IER_CP_Pos 8 /**< (SSC_IER Position) Compare x Interrupt Enable */ 673 #define SSC_IER_CP_Msk (_U_(0x3) << SSC_IER_CP_Pos) /**< (SSC_IER Mask) CP */ 674 #define SSC_IER_CP(value) (SSC_IER_CP_Msk & ((value) << SSC_IER_CP_Pos)) 675 676 /* -------- SSC_IDR : (SSC Offset: 0x48) (/W 32) Interrupt Disable Register -------- */ 677 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 678 #if COMPONENT_TYPEDEF_STYLE == 'N' 679 typedef union { 680 struct { 681 uint32_t TXRDY:1; /**< bit: 0 Transmit Ready Interrupt Disable */ 682 uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty Interrupt Disable */ 683 uint32_t :2; /**< bit: 2..3 Reserved */ 684 uint32_t RXRDY:1; /**< bit: 4 Receive Ready Interrupt Disable */ 685 uint32_t OVRUN:1; /**< bit: 5 Receive Overrun Interrupt Disable */ 686 uint32_t :2; /**< bit: 6..7 Reserved */ 687 uint32_t CP0:1; /**< bit: 8 Compare 0 Interrupt Disable */ 688 uint32_t CP1:1; /**< bit: 9 Compare 1 Interrupt Disable */ 689 uint32_t TXSYN:1; /**< bit: 10 Tx Sync Interrupt Enable */ 690 uint32_t RXSYN:1; /**< bit: 11 Rx Sync Interrupt Enable */ 691 uint32_t :20; /**< bit: 12..31 Reserved */ 692 } bit; /**< Structure used for bit access */ 693 struct { 694 uint32_t :8; /**< bit: 0..7 Reserved */ 695 uint32_t CP:2; /**< bit: 8..9 Compare x Interrupt Disable */ 696 uint32_t :22; /**< bit: 10..31 Reserved */ 697 } vec; /**< Structure used for vec access */ 698 uint32_t reg; /**< Type used for register access */ 699 } SSC_IDR_Type; 700 #endif 701 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 702 703 #define SSC_IDR_OFFSET (0x48) /**< (SSC_IDR) Interrupt Disable Register Offset */ 704 705 #define SSC_IDR_TXRDY_Pos 0 /**< (SSC_IDR) Transmit Ready Interrupt Disable Position */ 706 #define SSC_IDR_TXRDY_Msk (_U_(0x1) << SSC_IDR_TXRDY_Pos) /**< (SSC_IDR) Transmit Ready Interrupt Disable Mask */ 707 #define SSC_IDR_TXRDY SSC_IDR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_TXRDY_Msk instead */ 708 #define SSC_IDR_TXEMPTY_Pos 1 /**< (SSC_IDR) Transmit Empty Interrupt Disable Position */ 709 #define SSC_IDR_TXEMPTY_Msk (_U_(0x1) << SSC_IDR_TXEMPTY_Pos) /**< (SSC_IDR) Transmit Empty Interrupt Disable Mask */ 710 #define SSC_IDR_TXEMPTY SSC_IDR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_TXEMPTY_Msk instead */ 711 #define SSC_IDR_RXRDY_Pos 4 /**< (SSC_IDR) Receive Ready Interrupt Disable Position */ 712 #define SSC_IDR_RXRDY_Msk (_U_(0x1) << SSC_IDR_RXRDY_Pos) /**< (SSC_IDR) Receive Ready Interrupt Disable Mask */ 713 #define SSC_IDR_RXRDY SSC_IDR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_RXRDY_Msk instead */ 714 #define SSC_IDR_OVRUN_Pos 5 /**< (SSC_IDR) Receive Overrun Interrupt Disable Position */ 715 #define SSC_IDR_OVRUN_Msk (_U_(0x1) << SSC_IDR_OVRUN_Pos) /**< (SSC_IDR) Receive Overrun Interrupt Disable Mask */ 716 #define SSC_IDR_OVRUN SSC_IDR_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_OVRUN_Msk instead */ 717 #define SSC_IDR_CP0_Pos 8 /**< (SSC_IDR) Compare 0 Interrupt Disable Position */ 718 #define SSC_IDR_CP0_Msk (_U_(0x1) << SSC_IDR_CP0_Pos) /**< (SSC_IDR) Compare 0 Interrupt Disable Mask */ 719 #define SSC_IDR_CP0 SSC_IDR_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_CP0_Msk instead */ 720 #define SSC_IDR_CP1_Pos 9 /**< (SSC_IDR) Compare 1 Interrupt Disable Position */ 721 #define SSC_IDR_CP1_Msk (_U_(0x1) << SSC_IDR_CP1_Pos) /**< (SSC_IDR) Compare 1 Interrupt Disable Mask */ 722 #define SSC_IDR_CP1 SSC_IDR_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_CP1_Msk instead */ 723 #define SSC_IDR_TXSYN_Pos 10 /**< (SSC_IDR) Tx Sync Interrupt Enable Position */ 724 #define SSC_IDR_TXSYN_Msk (_U_(0x1) << SSC_IDR_TXSYN_Pos) /**< (SSC_IDR) Tx Sync Interrupt Enable Mask */ 725 #define SSC_IDR_TXSYN SSC_IDR_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_TXSYN_Msk instead */ 726 #define SSC_IDR_RXSYN_Pos 11 /**< (SSC_IDR) Rx Sync Interrupt Enable Position */ 727 #define SSC_IDR_RXSYN_Msk (_U_(0x1) << SSC_IDR_RXSYN_Pos) /**< (SSC_IDR) Rx Sync Interrupt Enable Mask */ 728 #define SSC_IDR_RXSYN SSC_IDR_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IDR_RXSYN_Msk instead */ 729 #define SSC_IDR_MASK _U_(0xF33) /**< \deprecated (SSC_IDR) Register MASK (Use SSC_IDR_Msk instead) */ 730 #define SSC_IDR_Msk _U_(0xF33) /**< (SSC_IDR) Register Mask */ 731 732 #define SSC_IDR_CP_Pos 8 /**< (SSC_IDR Position) Compare x Interrupt Disable */ 733 #define SSC_IDR_CP_Msk (_U_(0x3) << SSC_IDR_CP_Pos) /**< (SSC_IDR Mask) CP */ 734 #define SSC_IDR_CP(value) (SSC_IDR_CP_Msk & ((value) << SSC_IDR_CP_Pos)) 735 736 /* -------- SSC_IMR : (SSC Offset: 0x4c) (R/ 32) Interrupt Mask Register -------- */ 737 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 738 #if COMPONENT_TYPEDEF_STYLE == 'N' 739 typedef union { 740 struct { 741 uint32_t TXRDY:1; /**< bit: 0 Transmit Ready Interrupt Mask */ 742 uint32_t TXEMPTY:1; /**< bit: 1 Transmit Empty Interrupt Mask */ 743 uint32_t :2; /**< bit: 2..3 Reserved */ 744 uint32_t RXRDY:1; /**< bit: 4 Receive Ready Interrupt Mask */ 745 uint32_t OVRUN:1; /**< bit: 5 Receive Overrun Interrupt Mask */ 746 uint32_t :2; /**< bit: 6..7 Reserved */ 747 uint32_t CP0:1; /**< bit: 8 Compare 0 Interrupt Mask */ 748 uint32_t CP1:1; /**< bit: 9 Compare 1 Interrupt Mask */ 749 uint32_t TXSYN:1; /**< bit: 10 Tx Sync Interrupt Mask */ 750 uint32_t RXSYN:1; /**< bit: 11 Rx Sync Interrupt Mask */ 751 uint32_t :20; /**< bit: 12..31 Reserved */ 752 } bit; /**< Structure used for bit access */ 753 struct { 754 uint32_t :8; /**< bit: 0..7 Reserved */ 755 uint32_t CP:2; /**< bit: 8..9 Compare x Interrupt Mask */ 756 uint32_t :22; /**< bit: 10..31 Reserved */ 757 } vec; /**< Structure used for vec access */ 758 uint32_t reg; /**< Type used for register access */ 759 } SSC_IMR_Type; 760 #endif 761 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 762 763 #define SSC_IMR_OFFSET (0x4C) /**< (SSC_IMR) Interrupt Mask Register Offset */ 764 765 #define SSC_IMR_TXRDY_Pos 0 /**< (SSC_IMR) Transmit Ready Interrupt Mask Position */ 766 #define SSC_IMR_TXRDY_Msk (_U_(0x1) << SSC_IMR_TXRDY_Pos) /**< (SSC_IMR) Transmit Ready Interrupt Mask Mask */ 767 #define SSC_IMR_TXRDY SSC_IMR_TXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_TXRDY_Msk instead */ 768 #define SSC_IMR_TXEMPTY_Pos 1 /**< (SSC_IMR) Transmit Empty Interrupt Mask Position */ 769 #define SSC_IMR_TXEMPTY_Msk (_U_(0x1) << SSC_IMR_TXEMPTY_Pos) /**< (SSC_IMR) Transmit Empty Interrupt Mask Mask */ 770 #define SSC_IMR_TXEMPTY SSC_IMR_TXEMPTY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_TXEMPTY_Msk instead */ 771 #define SSC_IMR_RXRDY_Pos 4 /**< (SSC_IMR) Receive Ready Interrupt Mask Position */ 772 #define SSC_IMR_RXRDY_Msk (_U_(0x1) << SSC_IMR_RXRDY_Pos) /**< (SSC_IMR) Receive Ready Interrupt Mask Mask */ 773 #define SSC_IMR_RXRDY SSC_IMR_RXRDY_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_RXRDY_Msk instead */ 774 #define SSC_IMR_OVRUN_Pos 5 /**< (SSC_IMR) Receive Overrun Interrupt Mask Position */ 775 #define SSC_IMR_OVRUN_Msk (_U_(0x1) << SSC_IMR_OVRUN_Pos) /**< (SSC_IMR) Receive Overrun Interrupt Mask Mask */ 776 #define SSC_IMR_OVRUN SSC_IMR_OVRUN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_OVRUN_Msk instead */ 777 #define SSC_IMR_CP0_Pos 8 /**< (SSC_IMR) Compare 0 Interrupt Mask Position */ 778 #define SSC_IMR_CP0_Msk (_U_(0x1) << SSC_IMR_CP0_Pos) /**< (SSC_IMR) Compare 0 Interrupt Mask Mask */ 779 #define SSC_IMR_CP0 SSC_IMR_CP0_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_CP0_Msk instead */ 780 #define SSC_IMR_CP1_Pos 9 /**< (SSC_IMR) Compare 1 Interrupt Mask Position */ 781 #define SSC_IMR_CP1_Msk (_U_(0x1) << SSC_IMR_CP1_Pos) /**< (SSC_IMR) Compare 1 Interrupt Mask Mask */ 782 #define SSC_IMR_CP1 SSC_IMR_CP1_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_CP1_Msk instead */ 783 #define SSC_IMR_TXSYN_Pos 10 /**< (SSC_IMR) Tx Sync Interrupt Mask Position */ 784 #define SSC_IMR_TXSYN_Msk (_U_(0x1) << SSC_IMR_TXSYN_Pos) /**< (SSC_IMR) Tx Sync Interrupt Mask Mask */ 785 #define SSC_IMR_TXSYN SSC_IMR_TXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_TXSYN_Msk instead */ 786 #define SSC_IMR_RXSYN_Pos 11 /**< (SSC_IMR) Rx Sync Interrupt Mask Position */ 787 #define SSC_IMR_RXSYN_Msk (_U_(0x1) << SSC_IMR_RXSYN_Pos) /**< (SSC_IMR) Rx Sync Interrupt Mask Mask */ 788 #define SSC_IMR_RXSYN SSC_IMR_RXSYN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_IMR_RXSYN_Msk instead */ 789 #define SSC_IMR_MASK _U_(0xF33) /**< \deprecated (SSC_IMR) Register MASK (Use SSC_IMR_Msk instead) */ 790 #define SSC_IMR_Msk _U_(0xF33) /**< (SSC_IMR) Register Mask */ 791 792 #define SSC_IMR_CP_Pos 8 /**< (SSC_IMR Position) Compare x Interrupt Mask */ 793 #define SSC_IMR_CP_Msk (_U_(0x3) << SSC_IMR_CP_Pos) /**< (SSC_IMR Mask) CP */ 794 #define SSC_IMR_CP(value) (SSC_IMR_CP_Msk & ((value) << SSC_IMR_CP_Pos)) 795 796 /* -------- SSC_WPMR : (SSC Offset: 0xe4) (R/W 32) Write Protection Mode Register -------- */ 797 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 798 #if COMPONENT_TYPEDEF_STYLE == 'N' 799 typedef union { 800 struct { 801 uint32_t WPEN:1; /**< bit: 0 Write Protection Enable */ 802 uint32_t :7; /**< bit: 1..7 Reserved */ 803 uint32_t WPKEY:24; /**< bit: 8..31 Write Protection Key */ 804 } bit; /**< Structure used for bit access */ 805 uint32_t reg; /**< Type used for register access */ 806 } SSC_WPMR_Type; 807 #endif 808 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 809 810 #define SSC_WPMR_OFFSET (0xE4) /**< (SSC_WPMR) Write Protection Mode Register Offset */ 811 812 #define SSC_WPMR_WPEN_Pos 0 /**< (SSC_WPMR) Write Protection Enable Position */ 813 #define SSC_WPMR_WPEN_Msk (_U_(0x1) << SSC_WPMR_WPEN_Pos) /**< (SSC_WPMR) Write Protection Enable Mask */ 814 #define SSC_WPMR_WPEN SSC_WPMR_WPEN_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_WPMR_WPEN_Msk instead */ 815 #define SSC_WPMR_WPKEY_Pos 8 /**< (SSC_WPMR) Write Protection Key Position */ 816 #define SSC_WPMR_WPKEY_Msk (_U_(0xFFFFFF) << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Write Protection Key Mask */ 817 #define SSC_WPMR_WPKEY(value) (SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos)) 818 #define SSC_WPMR_WPKEY_PASSWD_Val _U_(0x535343) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ 819 #define SSC_WPMR_WPKEY_PASSWD (SSC_WPMR_WPKEY_PASSWD_Val << SSC_WPMR_WPKEY_Pos) /**< (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. Position */ 820 #define SSC_WPMR_MASK _U_(0xFFFFFF01) /**< \deprecated (SSC_WPMR) Register MASK (Use SSC_WPMR_Msk instead) */ 821 #define SSC_WPMR_Msk _U_(0xFFFFFF01) /**< (SSC_WPMR) Register Mask */ 822 823 824 /* -------- SSC_WPSR : (SSC Offset: 0xe8) (R/ 32) Write Protection Status Register -------- */ 825 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 826 #if COMPONENT_TYPEDEF_STYLE == 'N' 827 typedef union { 828 struct { 829 uint32_t WPVS:1; /**< bit: 0 Write Protection Violation Status */ 830 uint32_t :7; /**< bit: 1..7 Reserved */ 831 uint32_t WPVSRC:16; /**< bit: 8..23 Write Protect Violation Source */ 832 uint32_t :8; /**< bit: 24..31 Reserved */ 833 } bit; /**< Structure used for bit access */ 834 uint32_t reg; /**< Type used for register access */ 835 } SSC_WPSR_Type; 836 #endif 837 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 838 839 #define SSC_WPSR_OFFSET (0xE8) /**< (SSC_WPSR) Write Protection Status Register Offset */ 840 841 #define SSC_WPSR_WPVS_Pos 0 /**< (SSC_WPSR) Write Protection Violation Status Position */ 842 #define SSC_WPSR_WPVS_Msk (_U_(0x1) << SSC_WPSR_WPVS_Pos) /**< (SSC_WPSR) Write Protection Violation Status Mask */ 843 #define SSC_WPSR_WPVS SSC_WPSR_WPVS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use SSC_WPSR_WPVS_Msk instead */ 844 #define SSC_WPSR_WPVSRC_Pos 8 /**< (SSC_WPSR) Write Protect Violation Source Position */ 845 #define SSC_WPSR_WPVSRC_Msk (_U_(0xFFFF) << SSC_WPSR_WPVSRC_Pos) /**< (SSC_WPSR) Write Protect Violation Source Mask */ 846 #define SSC_WPSR_WPVSRC(value) (SSC_WPSR_WPVSRC_Msk & ((value) << SSC_WPSR_WPVSRC_Pos)) 847 #define SSC_WPSR_MASK _U_(0xFFFF01) /**< \deprecated (SSC_WPSR) Register MASK (Use SSC_WPSR_Msk instead) */ 848 #define SSC_WPSR_Msk _U_(0xFFFF01) /**< (SSC_WPSR) Register Mask */ 849 850 851 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 852 #if COMPONENT_TYPEDEF_STYLE == 'R' 853 /** \brief SSC hardware registers */ 854 typedef struct { 855 __O uint32_t SSC_CR; /**< (SSC Offset: 0x00) Control Register */ 856 __IO uint32_t SSC_CMR; /**< (SSC Offset: 0x04) Clock Mode Register */ 857 __I uint8_t Reserved1[8]; 858 __IO uint32_t SSC_RCMR; /**< (SSC Offset: 0x10) Receive Clock Mode Register */ 859 __IO uint32_t SSC_RFMR; /**< (SSC Offset: 0x14) Receive Frame Mode Register */ 860 __IO uint32_t SSC_TCMR; /**< (SSC Offset: 0x18) Transmit Clock Mode Register */ 861 __IO uint32_t SSC_TFMR; /**< (SSC Offset: 0x1C) Transmit Frame Mode Register */ 862 __I uint32_t SSC_RHR; /**< (SSC Offset: 0x20) Receive Holding Register */ 863 __O uint32_t SSC_THR; /**< (SSC Offset: 0x24) Transmit Holding Register */ 864 __I uint8_t Reserved2[8]; 865 __I uint32_t SSC_RSHR; /**< (SSC Offset: 0x30) Receive Sync. Holding Register */ 866 __IO uint32_t SSC_TSHR; /**< (SSC Offset: 0x34) Transmit Sync. Holding Register */ 867 __IO uint32_t SSC_RC0R; /**< (SSC Offset: 0x38) Receive Compare 0 Register */ 868 __IO uint32_t SSC_RC1R; /**< (SSC Offset: 0x3C) Receive Compare 1 Register */ 869 __I uint32_t SSC_SR; /**< (SSC Offset: 0x40) Status Register */ 870 __O uint32_t SSC_IER; /**< (SSC Offset: 0x44) Interrupt Enable Register */ 871 __O uint32_t SSC_IDR; /**< (SSC Offset: 0x48) Interrupt Disable Register */ 872 __I uint32_t SSC_IMR; /**< (SSC Offset: 0x4C) Interrupt Mask Register */ 873 __I uint8_t Reserved3[148]; 874 __IO uint32_t SSC_WPMR; /**< (SSC Offset: 0xE4) Write Protection Mode Register */ 875 __I uint32_t SSC_WPSR; /**< (SSC Offset: 0xE8) Write Protection Status Register */ 876 } Ssc; 877 878 #elif COMPONENT_TYPEDEF_STYLE == 'N' 879 /** \brief SSC hardware registers */ 880 typedef struct { 881 __O SSC_CR_Type SSC_CR; /**< Offset: 0x00 ( /W 32) Control Register */ 882 __IO SSC_CMR_Type SSC_CMR; /**< Offset: 0x04 (R/W 32) Clock Mode Register */ 883 __I uint8_t Reserved1[8]; 884 __IO SSC_RCMR_Type SSC_RCMR; /**< Offset: 0x10 (R/W 32) Receive Clock Mode Register */ 885 __IO SSC_RFMR_Type SSC_RFMR; /**< Offset: 0x14 (R/W 32) Receive Frame Mode Register */ 886 __IO SSC_TCMR_Type SSC_TCMR; /**< Offset: 0x18 (R/W 32) Transmit Clock Mode Register */ 887 __IO SSC_TFMR_Type SSC_TFMR; /**< Offset: 0x1C (R/W 32) Transmit Frame Mode Register */ 888 __I SSC_RHR_Type SSC_RHR; /**< Offset: 0x20 (R/ 32) Receive Holding Register */ 889 __O SSC_THR_Type SSC_THR; /**< Offset: 0x24 ( /W 32) Transmit Holding Register */ 890 __I uint8_t Reserved2[8]; 891 __I SSC_RSHR_Type SSC_RSHR; /**< Offset: 0x30 (R/ 32) Receive Sync. Holding Register */ 892 __IO SSC_TSHR_Type SSC_TSHR; /**< Offset: 0x34 (R/W 32) Transmit Sync. Holding Register */ 893 __IO SSC_RC0R_Type SSC_RC0R; /**< Offset: 0x38 (R/W 32) Receive Compare 0 Register */ 894 __IO SSC_RC1R_Type SSC_RC1R; /**< Offset: 0x3C (R/W 32) Receive Compare 1 Register */ 895 __I SSC_SR_Type SSC_SR; /**< Offset: 0x40 (R/ 32) Status Register */ 896 __O SSC_IER_Type SSC_IER; /**< Offset: 0x44 ( /W 32) Interrupt Enable Register */ 897 __O SSC_IDR_Type SSC_IDR; /**< Offset: 0x48 ( /W 32) Interrupt Disable Register */ 898 __I SSC_IMR_Type SSC_IMR; /**< Offset: 0x4C (R/ 32) Interrupt Mask Register */ 899 __I uint8_t Reserved3[148]; 900 __IO SSC_WPMR_Type SSC_WPMR; /**< Offset: 0xE4 (R/W 32) Write Protection Mode Register */ 901 __I SSC_WPSR_Type SSC_WPSR; /**< Offset: 0xE8 (R/ 32) Write Protection Status Register */ 902 } Ssc; 903 904 #else /* COMPONENT_TYPEDEF_STYLE */ 905 #error Unknown component typedef style 906 #endif /* COMPONENT_TYPEDEF_STYLE */ 907 908 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 909 /** @} end of Synchronous Serial Controller */ 910 911 #endif /* _SAME70_SSC_COMPONENT_H_ */ 912
