1 /** 2 * \file 3 * 4 * \brief Component description for CHIPID 5 * 6 * Copyright (c) 2019 Microchip Technology Inc. 7 * 8 * \license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \license_stop 27 * 28 */ 29 30 /* file generated from device description version 2019-01-18T21:19:59Z */ 31 #ifndef _SAME70_CHIPID_COMPONENT_H_ 32 #define _SAME70_CHIPID_COMPONENT_H_ 33 #define _SAME70_CHIPID_COMPONENT_ /**< \deprecated Backward compatibility for ASF */ 34 35 /** \addtogroup SAME_SAME70 Chip Identifier 36 * @{ 37 */ 38 /* ========================================================================== */ 39 /** SOFTWARE API DEFINITION FOR CHIPID */ 40 /* ========================================================================== */ 41 #ifndef COMPONENT_TYPEDEF_STYLE 42 #define COMPONENT_TYPEDEF_STYLE 'R' /**< Defines default style of typedefs for the component header files ('R' = RFO, 'N' = NTO)*/ 43 #endif 44 45 #define CHIPID_6417 /**< (CHIPID) Module ID */ 46 #define REV_CHIPID ZK /**< (CHIPID) Module revision */ 47 48 /* -------- CHIPID_CIDR : (CHIPID Offset: 0x00) (R/ 32) Chip ID Register -------- */ 49 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 50 #if COMPONENT_TYPEDEF_STYLE == 'N' 51 typedef union { 52 struct { 53 uint32_t VERSION:5; /**< bit: 0..4 Version of the Device */ 54 uint32_t EPROC:3; /**< bit: 5..7 Embedded Processor */ 55 uint32_t NVPSIZ:4; /**< bit: 8..11 Nonvolatile Program Memory Size */ 56 uint32_t NVPSIZ2:4; /**< bit: 12..15 Second Nonvolatile Program Memory Size */ 57 uint32_t SRAMSIZ:4; /**< bit: 16..19 Internal SRAM Size */ 58 uint32_t ARCH:8; /**< bit: 20..27 Architecture Identifier */ 59 uint32_t NVPTYP:3; /**< bit: 28..30 Nonvolatile Program Memory Type */ 60 uint32_t EXT:1; /**< bit: 31 Extension Flag */ 61 } bit; /**< Structure used for bit access */ 62 uint32_t reg; /**< Type used for register access */ 63 } CHIPID_CIDR_Type; 64 #endif 65 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 #define CHIPID_CIDR_OFFSET (0x00) /**< (CHIPID_CIDR) Chip ID Register Offset */ 68 69 #define CHIPID_CIDR_VERSION_Pos 0 /**< (CHIPID_CIDR) Version of the Device Position */ 70 #define CHIPID_CIDR_VERSION_Msk (_U_(0x1F) << CHIPID_CIDR_VERSION_Pos) /**< (CHIPID_CIDR) Version of the Device Mask */ 71 #define CHIPID_CIDR_VERSION(value) (CHIPID_CIDR_VERSION_Msk & ((value) << CHIPID_CIDR_VERSION_Pos)) 72 #define CHIPID_CIDR_EPROC_Pos 5 /**< (CHIPID_CIDR) Embedded Processor Position */ 73 #define CHIPID_CIDR_EPROC_Msk (_U_(0x7) << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Embedded Processor Mask */ 74 #define CHIPID_CIDR_EPROC(value) (CHIPID_CIDR_EPROC_Msk & ((value) << CHIPID_CIDR_EPROC_Pos)) 75 #define CHIPID_CIDR_EPROC_SAMx7_Val _U_(0x0) /**< (CHIPID_CIDR) Cortex-M7 */ 76 #define CHIPID_CIDR_EPROC_ARM946ES_Val _U_(0x1) /**< (CHIPID_CIDR) ARM946ES */ 77 #define CHIPID_CIDR_EPROC_ARM7TDMI_Val _U_(0x2) /**< (CHIPID_CIDR) ARM7TDMI */ 78 #define CHIPID_CIDR_EPROC_CM3_Val _U_(0x3) /**< (CHIPID_CIDR) Cortex-M3 */ 79 #define CHIPID_CIDR_EPROC_ARM920T_Val _U_(0x4) /**< (CHIPID_CIDR) ARM920T */ 80 #define CHIPID_CIDR_EPROC_ARM926EJS_Val _U_(0x5) /**< (CHIPID_CIDR) ARM926EJS */ 81 #define CHIPID_CIDR_EPROC_CA5_Val _U_(0x6) /**< (CHIPID_CIDR) Cortex-A5 */ 82 #define CHIPID_CIDR_EPROC_CM4_Val _U_(0x7) /**< (CHIPID_CIDR) Cortex-M4 */ 83 #define CHIPID_CIDR_EPROC_SAMx7 (CHIPID_CIDR_EPROC_SAMx7_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M7 Position */ 84 #define CHIPID_CIDR_EPROC_ARM946ES (CHIPID_CIDR_EPROC_ARM946ES_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM946ES Position */ 85 #define CHIPID_CIDR_EPROC_ARM7TDMI (CHIPID_CIDR_EPROC_ARM7TDMI_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM7TDMI Position */ 86 #define CHIPID_CIDR_EPROC_CM3 (CHIPID_CIDR_EPROC_CM3_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M3 Position */ 87 #define CHIPID_CIDR_EPROC_ARM920T (CHIPID_CIDR_EPROC_ARM920T_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM920T Position */ 88 #define CHIPID_CIDR_EPROC_ARM926EJS (CHIPID_CIDR_EPROC_ARM926EJS_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) ARM926EJS Position */ 89 #define CHIPID_CIDR_EPROC_CA5 (CHIPID_CIDR_EPROC_CA5_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-A5 Position */ 90 #define CHIPID_CIDR_EPROC_CM4 (CHIPID_CIDR_EPROC_CM4_Val << CHIPID_CIDR_EPROC_Pos) /**< (CHIPID_CIDR) Cortex-M4 Position */ 91 #define CHIPID_CIDR_NVPSIZ_Pos 8 /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Position */ 92 #define CHIPID_CIDR_NVPSIZ_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Size Mask */ 93 #define CHIPID_CIDR_NVPSIZ(value) (CHIPID_CIDR_NVPSIZ_Msk & ((value) << CHIPID_CIDR_NVPSIZ_Pos)) 94 #define CHIPID_CIDR_NVPSIZ_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */ 95 #define CHIPID_CIDR_NVPSIZ_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */ 96 #define CHIPID_CIDR_NVPSIZ_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */ 97 #define CHIPID_CIDR_NVPSIZ_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */ 98 #define CHIPID_CIDR_NVPSIZ_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */ 99 #define CHIPID_CIDR_NVPSIZ_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */ 100 #define CHIPID_CIDR_NVPSIZ_160K_Val _U_(0x8) /**< (CHIPID_CIDR) 160 Kbytes */ 101 #define CHIPID_CIDR_NVPSIZ_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */ 102 #define CHIPID_CIDR_NVPSIZ_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */ 103 #define CHIPID_CIDR_NVPSIZ_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */ 104 #define CHIPID_CIDR_NVPSIZ_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */ 105 #define CHIPID_CIDR_NVPSIZ_NONE (CHIPID_CIDR_NVPSIZ_NONE_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) None Position */ 106 #define CHIPID_CIDR_NVPSIZ_8K (CHIPID_CIDR_NVPSIZ_8K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ 107 #define CHIPID_CIDR_NVPSIZ_16K (CHIPID_CIDR_NVPSIZ_16K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ 108 #define CHIPID_CIDR_NVPSIZ_32K (CHIPID_CIDR_NVPSIZ_32K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ 109 #define CHIPID_CIDR_NVPSIZ_64K (CHIPID_CIDR_NVPSIZ_64K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ 110 #define CHIPID_CIDR_NVPSIZ_128K (CHIPID_CIDR_NVPSIZ_128K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ 111 #define CHIPID_CIDR_NVPSIZ_160K (CHIPID_CIDR_NVPSIZ_160K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */ 112 #define CHIPID_CIDR_NVPSIZ_256K (CHIPID_CIDR_NVPSIZ_256K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ 113 #define CHIPID_CIDR_NVPSIZ_512K (CHIPID_CIDR_NVPSIZ_512K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ 114 #define CHIPID_CIDR_NVPSIZ_1024K (CHIPID_CIDR_NVPSIZ_1024K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */ 115 #define CHIPID_CIDR_NVPSIZ_2048K (CHIPID_CIDR_NVPSIZ_2048K_Val << CHIPID_CIDR_NVPSIZ_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */ 116 #define CHIPID_CIDR_NVPSIZ2_Pos 12 /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Position */ 117 #define CHIPID_CIDR_NVPSIZ2_Msk (_U_(0xF) << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) Second Nonvolatile Program Memory Size Mask */ 118 #define CHIPID_CIDR_NVPSIZ2(value) (CHIPID_CIDR_NVPSIZ2_Msk & ((value) << CHIPID_CIDR_NVPSIZ2_Pos)) 119 #define CHIPID_CIDR_NVPSIZ2_NONE_Val _U_(0x0) /**< (CHIPID_CIDR) None */ 120 #define CHIPID_CIDR_NVPSIZ2_8K_Val _U_(0x1) /**< (CHIPID_CIDR) 8 Kbytes */ 121 #define CHIPID_CIDR_NVPSIZ2_16K_Val _U_(0x2) /**< (CHIPID_CIDR) 16 Kbytes */ 122 #define CHIPID_CIDR_NVPSIZ2_32K_Val _U_(0x3) /**< (CHIPID_CIDR) 32 Kbytes */ 123 #define CHIPID_CIDR_NVPSIZ2_64K_Val _U_(0x5) /**< (CHIPID_CIDR) 64 Kbytes */ 124 #define CHIPID_CIDR_NVPSIZ2_128K_Val _U_(0x7) /**< (CHIPID_CIDR) 128 Kbytes */ 125 #define CHIPID_CIDR_NVPSIZ2_256K_Val _U_(0x9) /**< (CHIPID_CIDR) 256 Kbytes */ 126 #define CHIPID_CIDR_NVPSIZ2_512K_Val _U_(0xA) /**< (CHIPID_CIDR) 512 Kbytes */ 127 #define CHIPID_CIDR_NVPSIZ2_1024K_Val _U_(0xC) /**< (CHIPID_CIDR) 1024 Kbytes */ 128 #define CHIPID_CIDR_NVPSIZ2_2048K_Val _U_(0xE) /**< (CHIPID_CIDR) 2048 Kbytes */ 129 #define CHIPID_CIDR_NVPSIZ2_NONE (CHIPID_CIDR_NVPSIZ2_NONE_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) None Position */ 130 #define CHIPID_CIDR_NVPSIZ2_8K (CHIPID_CIDR_NVPSIZ2_8K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ 131 #define CHIPID_CIDR_NVPSIZ2_16K (CHIPID_CIDR_NVPSIZ2_16K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ 132 #define CHIPID_CIDR_NVPSIZ2_32K (CHIPID_CIDR_NVPSIZ2_32K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ 133 #define CHIPID_CIDR_NVPSIZ2_64K (CHIPID_CIDR_NVPSIZ2_64K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ 134 #define CHIPID_CIDR_NVPSIZ2_128K (CHIPID_CIDR_NVPSIZ2_128K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ 135 #define CHIPID_CIDR_NVPSIZ2_256K (CHIPID_CIDR_NVPSIZ2_256K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ 136 #define CHIPID_CIDR_NVPSIZ2_512K (CHIPID_CIDR_NVPSIZ2_512K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ 137 #define CHIPID_CIDR_NVPSIZ2_1024K (CHIPID_CIDR_NVPSIZ2_1024K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 1024 Kbytes Position */ 138 #define CHIPID_CIDR_NVPSIZ2_2048K (CHIPID_CIDR_NVPSIZ2_2048K_Val << CHIPID_CIDR_NVPSIZ2_Pos) /**< (CHIPID_CIDR) 2048 Kbytes Position */ 139 #define CHIPID_CIDR_SRAMSIZ_Pos 16 /**< (CHIPID_CIDR) Internal SRAM Size Position */ 140 #define CHIPID_CIDR_SRAMSIZ_Msk (_U_(0xF) << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) Internal SRAM Size Mask */ 141 #define CHIPID_CIDR_SRAMSIZ(value) (CHIPID_CIDR_SRAMSIZ_Msk & ((value) << CHIPID_CIDR_SRAMSIZ_Pos)) 142 #define CHIPID_CIDR_SRAMSIZ_48K_Val _U_(0x0) /**< (CHIPID_CIDR) 48 Kbytes */ 143 #define CHIPID_CIDR_SRAMSIZ_192K_Val _U_(0x1) /**< (CHIPID_CIDR) 192 Kbytes */ 144 #define CHIPID_CIDR_SRAMSIZ_384K_Val _U_(0x2) /**< (CHIPID_CIDR) 384 Kbytes */ 145 #define CHIPID_CIDR_SRAMSIZ_6K_Val _U_(0x3) /**< (CHIPID_CIDR) 6 Kbytes */ 146 #define CHIPID_CIDR_SRAMSIZ_24K_Val _U_(0x4) /**< (CHIPID_CIDR) 24 Kbytes */ 147 #define CHIPID_CIDR_SRAMSIZ_4K_Val _U_(0x5) /**< (CHIPID_CIDR) 4 Kbytes */ 148 #define CHIPID_CIDR_SRAMSIZ_80K_Val _U_(0x6) /**< (CHIPID_CIDR) 80 Kbytes */ 149 #define CHIPID_CIDR_SRAMSIZ_160K_Val _U_(0x7) /**< (CHIPID_CIDR) 160 Kbytes */ 150 #define CHIPID_CIDR_SRAMSIZ_8K_Val _U_(0x8) /**< (CHIPID_CIDR) 8 Kbytes */ 151 #define CHIPID_CIDR_SRAMSIZ_16K_Val _U_(0x9) /**< (CHIPID_CIDR) 16 Kbytes */ 152 #define CHIPID_CIDR_SRAMSIZ_32K_Val _U_(0xA) /**< (CHIPID_CIDR) 32 Kbytes */ 153 #define CHIPID_CIDR_SRAMSIZ_64K_Val _U_(0xB) /**< (CHIPID_CIDR) 64 Kbytes */ 154 #define CHIPID_CIDR_SRAMSIZ_128K_Val _U_(0xC) /**< (CHIPID_CIDR) 128 Kbytes */ 155 #define CHIPID_CIDR_SRAMSIZ_256K_Val _U_(0xD) /**< (CHIPID_CIDR) 256 Kbytes */ 156 #define CHIPID_CIDR_SRAMSIZ_96K_Val _U_(0xE) /**< (CHIPID_CIDR) 96 Kbytes */ 157 #define CHIPID_CIDR_SRAMSIZ_512K_Val _U_(0xF) /**< (CHIPID_CIDR) 512 Kbytes */ 158 #define CHIPID_CIDR_SRAMSIZ_48K (CHIPID_CIDR_SRAMSIZ_48K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 48 Kbytes Position */ 159 #define CHIPID_CIDR_SRAMSIZ_192K (CHIPID_CIDR_SRAMSIZ_192K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 192 Kbytes Position */ 160 #define CHIPID_CIDR_SRAMSIZ_384K (CHIPID_CIDR_SRAMSIZ_384K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 384 Kbytes Position */ 161 #define CHIPID_CIDR_SRAMSIZ_6K (CHIPID_CIDR_SRAMSIZ_6K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 6 Kbytes Position */ 162 #define CHIPID_CIDR_SRAMSIZ_24K (CHIPID_CIDR_SRAMSIZ_24K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 24 Kbytes Position */ 163 #define CHIPID_CIDR_SRAMSIZ_4K (CHIPID_CIDR_SRAMSIZ_4K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 4 Kbytes Position */ 164 #define CHIPID_CIDR_SRAMSIZ_80K (CHIPID_CIDR_SRAMSIZ_80K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 80 Kbytes Position */ 165 #define CHIPID_CIDR_SRAMSIZ_160K (CHIPID_CIDR_SRAMSIZ_160K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 160 Kbytes Position */ 166 #define CHIPID_CIDR_SRAMSIZ_8K (CHIPID_CIDR_SRAMSIZ_8K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 8 Kbytes Position */ 167 #define CHIPID_CIDR_SRAMSIZ_16K (CHIPID_CIDR_SRAMSIZ_16K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 16 Kbytes Position */ 168 #define CHIPID_CIDR_SRAMSIZ_32K (CHIPID_CIDR_SRAMSIZ_32K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 32 Kbytes Position */ 169 #define CHIPID_CIDR_SRAMSIZ_64K (CHIPID_CIDR_SRAMSIZ_64K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 64 Kbytes Position */ 170 #define CHIPID_CIDR_SRAMSIZ_128K (CHIPID_CIDR_SRAMSIZ_128K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 128 Kbytes Position */ 171 #define CHIPID_CIDR_SRAMSIZ_256K (CHIPID_CIDR_SRAMSIZ_256K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 256 Kbytes Position */ 172 #define CHIPID_CIDR_SRAMSIZ_96K (CHIPID_CIDR_SRAMSIZ_96K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 96 Kbytes Position */ 173 #define CHIPID_CIDR_SRAMSIZ_512K (CHIPID_CIDR_SRAMSIZ_512K_Val << CHIPID_CIDR_SRAMSIZ_Pos) /**< (CHIPID_CIDR) 512 Kbytes Position */ 174 #define CHIPID_CIDR_ARCH_Pos 20 /**< (CHIPID_CIDR) Architecture Identifier Position */ 175 #define CHIPID_CIDR_ARCH_Msk (_U_(0xFF) << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) Architecture Identifier Mask */ 176 #define CHIPID_CIDR_ARCH(value) (CHIPID_CIDR_ARCH_Msk & ((value) << CHIPID_CIDR_ARCH_Pos)) 177 #define CHIPID_CIDR_ARCH_SAME70_Val _U_(0x10) /**< (CHIPID_CIDR) SAM E70 */ 178 #define CHIPID_CIDR_ARCH_SAMS70_Val _U_(0x11) /**< (CHIPID_CIDR) SAM S70 */ 179 #define CHIPID_CIDR_ARCH_SAMV71_Val _U_(0x12) /**< (CHIPID_CIDR) SAM V71 */ 180 #define CHIPID_CIDR_ARCH_SAMV70_Val _U_(0x13) /**< (CHIPID_CIDR) SAM V70 */ 181 #define CHIPID_CIDR_ARCH_SAME70 (CHIPID_CIDR_ARCH_SAME70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM E70 Position */ 182 #define CHIPID_CIDR_ARCH_SAMS70 (CHIPID_CIDR_ARCH_SAMS70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM S70 Position */ 183 #define CHIPID_CIDR_ARCH_SAMV71 (CHIPID_CIDR_ARCH_SAMV71_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V71 Position */ 184 #define CHIPID_CIDR_ARCH_SAMV70 (CHIPID_CIDR_ARCH_SAMV70_Val << CHIPID_CIDR_ARCH_Pos) /**< (CHIPID_CIDR) SAM V70 Position */ 185 #define CHIPID_CIDR_NVPTYP_Pos 28 /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Position */ 186 #define CHIPID_CIDR_NVPTYP_Msk (_U_(0x7) << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Nonvolatile Program Memory Type Mask */ 187 #define CHIPID_CIDR_NVPTYP(value) (CHIPID_CIDR_NVPTYP_Msk & ((value) << CHIPID_CIDR_NVPTYP_Pos)) 188 #define CHIPID_CIDR_NVPTYP_ROM_Val _U_(0x0) /**< (CHIPID_CIDR) ROM */ 189 #define CHIPID_CIDR_NVPTYP_ROMLESS_Val _U_(0x1) /**< (CHIPID_CIDR) ROMless or on-chip Flash */ 190 #define CHIPID_CIDR_NVPTYP_FLASH_Val _U_(0x2) /**< (CHIPID_CIDR) Embedded Flash Memory */ 191 #define CHIPID_CIDR_NVPTYP_ROM_FLASH_Val _U_(0x3) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ 192 #define CHIPID_CIDR_NVPTYP_SRAM_Val _U_(0x4) /**< (CHIPID_CIDR) SRAM emulating ROM */ 193 #define CHIPID_CIDR_NVPTYP_ROM (CHIPID_CIDR_NVPTYP_ROM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM Position */ 194 #define CHIPID_CIDR_NVPTYP_ROMLESS (CHIPID_CIDR_NVPTYP_ROMLESS_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROMless or on-chip Flash Position */ 195 #define CHIPID_CIDR_NVPTYP_FLASH (CHIPID_CIDR_NVPTYP_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) Embedded Flash Memory Position */ 196 #define CHIPID_CIDR_NVPTYP_ROM_FLASH (CHIPID_CIDR_NVPTYP_ROM_FLASH_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size Position */ 197 #define CHIPID_CIDR_NVPTYP_SRAM (CHIPID_CIDR_NVPTYP_SRAM_Val << CHIPID_CIDR_NVPTYP_Pos) /**< (CHIPID_CIDR) SRAM emulating ROM Position */ 198 #define CHIPID_CIDR_EXT_Pos 31 /**< (CHIPID_CIDR) Extension Flag Position */ 199 #define CHIPID_CIDR_EXT_Msk (_U_(0x1) << CHIPID_CIDR_EXT_Pos) /**< (CHIPID_CIDR) Extension Flag Mask */ 200 #define CHIPID_CIDR_EXT CHIPID_CIDR_EXT_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use CHIPID_CIDR_EXT_Msk instead */ 201 #define CHIPID_CIDR_MASK _U_(0xFFFFFFFF) /**< \deprecated (CHIPID_CIDR) Register MASK (Use CHIPID_CIDR_Msk instead) */ 202 #define CHIPID_CIDR_Msk _U_(0xFFFFFFFF) /**< (CHIPID_CIDR) Register Mask */ 203 204 205 /* -------- CHIPID_EXID : (CHIPID Offset: 0x04) (R/ 32) Chip ID Extension Register -------- */ 206 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 207 #if COMPONENT_TYPEDEF_STYLE == 'N' 208 typedef union { 209 struct { 210 uint32_t EXID:32; /**< bit: 0..31 Chip ID Extension */ 211 } bit; /**< Structure used for bit access */ 212 uint32_t reg; /**< Type used for register access */ 213 } CHIPID_EXID_Type; 214 #endif 215 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 216 217 #define CHIPID_EXID_OFFSET (0x04) /**< (CHIPID_EXID) Chip ID Extension Register Offset */ 218 219 #define CHIPID_EXID_EXID_Pos 0 /**< (CHIPID_EXID) Chip ID Extension Position */ 220 #define CHIPID_EXID_EXID_Msk (_U_(0xFFFFFFFF) << CHIPID_EXID_EXID_Pos) /**< (CHIPID_EXID) Chip ID Extension Mask */ 221 #define CHIPID_EXID_EXID(value) (CHIPID_EXID_EXID_Msk & ((value) << CHIPID_EXID_EXID_Pos)) 222 #define CHIPID_EXID_MASK _U_(0xFFFFFFFF) /**< \deprecated (CHIPID_EXID) Register MASK (Use CHIPID_EXID_Msk instead) */ 223 #define CHIPID_EXID_Msk _U_(0xFFFFFFFF) /**< (CHIPID_EXID) Register Mask */ 224 225 226 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 227 #if COMPONENT_TYPEDEF_STYLE == 'R' 228 /** \brief CHIPID hardware registers */ 229 typedef struct { 230 __I uint32_t CHIPID_CIDR; /**< (CHIPID Offset: 0x00) Chip ID Register */ 231 __I uint32_t CHIPID_EXID; /**< (CHIPID Offset: 0x04) Chip ID Extension Register */ 232 } Chipid; 233 234 #elif COMPONENT_TYPEDEF_STYLE == 'N' 235 /** \brief CHIPID hardware registers */ 236 typedef struct { 237 __I CHIPID_CIDR_Type CHIPID_CIDR; /**< Offset: 0x00 (R/ 32) Chip ID Register */ 238 __I CHIPID_EXID_Type CHIPID_EXID; /**< Offset: 0x04 (R/ 32) Chip ID Extension Register */ 239 } Chipid; 240 241 #else /* COMPONENT_TYPEDEF_STYLE */ 242 #error Unknown component typedef style 243 #endif /* COMPONENT_TYPEDEF_STYLE */ 244 245 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 246 /** @} end of Chip Identifier */ 247 248 #endif /* _SAME70_CHIPID_COMPONENT_H_ */ 249
